Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	11	119	91.54

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	11	119	91.54	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	29635952	1			T1	11		T2	20		T3	230
all_levels[1]	203599	1			T2	3		T3	70		T4	50
all_levels[2]	2241	1			T3	7		T4	4		T5	5
all_levels[3]	1071	1			T2	1		T3	1		T4	3
all_levels[4]	739	1			T4	4		T6	1		T99	1
all_levels[5]	503	1			T2	1		T3	1		T4	3
all_levels[6]	419	1			T4	2		T5	2		T99	1
all_levels[7]	347	1			T2	1		T3	2		T6	2
all_levels[8]	294	1			T2	1		T3	1		T5	1
all_levels[9]	215	1			T5	1		T42	1		T99	1
all_levels[10]	201	1			T3	1		T43	1		T118	1
all_levels[11]	192	1			T2	3		T42	1		T119	2
all_levels[12]	191	1			T42	2		T43	1		T37	1
all_levels[13]	147	1			T42	1		T39	1		T118	1
all_levels[14]	132	1			T118	2		T70	3		T120	1
all_levels[15]	123	1			T11	4		T39	2		T119	1
all_levels[16]	129	1			T43	1		T118	1		T19	1
all_levels[17]	91	1			T118	1		T119	1		T30	2
all_levels[18]	90	1			T118	1		T85	1		T29	1
all_levels[19]	94	1			T43	2		T50	1		T71	2
all_levels[20]	79	1			T85	1		T50	1		T121	1
all_levels[21]	74	1			T15	1		T51	1		T121	1
all_levels[22]	60	1			T42	1		T119	1		T33	1
all_levels[23]	70	1			T15	1		T30	3		T122	1
all_levels[24]	70	1			T43	1		T99	1		T119	1
all_levels[25]	69	1			T29	1		T30	1		T120	4
all_levels[26]	61	1			T123	1		T52	2		T124	1
all_levels[27]	36	1			T85	1		T29	2		T49	1
all_levels[28]	37	1			T43	1		T50	1		T121	1
all_levels[29]	36	1			T42	1		T85	2		T52	1
all_levels[30]	36	1			T50	1		T115	1		T125	1
all_levels[31]	36	1			T126	1		T127	2		T128	1
all_levels[32]	27	1			T14	1		T50	1		T122	1
all_levels[33]	35	1			T32	1		T33	1		T111	1
all_levels[34]	19	1			T52	1		T129	1		T130	1
all_levels[35]	25	1			T2	1		T131	1		T132	1
all_levels[36]	18	1			T131	1		T112	1		T133	1
all_levels[37]	40	1			T42	1		T32	1		T134	1
all_levels[38]	20	1			T135	1		T53	1		T111	1
all_levels[39]	24	1			T30	1		T136	1		T112	1
all_levels[40]	17	1			T126	2		T137	1		T138	1
all_levels[41]	22	1			T11	2		T85	1		T133	2
all_levels[42]	16	1			T85	1		T139	1		T140	1
all_levels[43]	14	1			T135	1		T129	1		T137	1
all_levels[44]	15	1			T52	1		T141	1		T106	1
all_levels[45]	21	1			T30	1		T142	1		T143	1
all_levels[46]	15	1			T32	1		T144	1		T145	1
all_levels[47]	13	1			T142	1		T146	1		T147	1
all_levels[48]	11	1			T148	1		T149	1		T150	1
all_levels[49]	16	1			T144	1		T143	1		T151	1
all_levels[50]	7	1			T152	1		T153	1		T154	1
all_levels[51]	8	1			T46	1		T125	1		T141	1
all_levels[52]	16	1			T52	2		T125	1		T155	1
all_levels[53]	7	1			T138	1		T156	1		T157	1
all_levels[54]	8	1			T11	1		T19	1		T155	2
all_levels[55]	8	1			T11	1		T19	1		T85	1
all_levels[56]	5	1			T158	1		T159	1		T160	1
all_levels[57]	11	1			T139	1		T161	1		T145	1
all_levels[58]	14	1			T2	1		T11	1		T112	1
all_levels[59]	5	1			T162	1		T163	2		T164	1
all_levels[60]	7	1			T135	1		T165	1		T60	1
all_levels[61]	6	1			T85	1		T166	1		T154	1
all_levels[62]	7	1			T85	1		T140	1		T167	1
all_levels[63]	8	1			T42	1		T19	1		T32	1
all_levels[64]	111	1			T4	1		T11	1		T14	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29843307

1

T1

2

T2

25

T3

313

auto[1]

4723

1

T1

9

T2

7

T4

58

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	11	119	91.54	11

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[32]]	[auto[1]]	0	1	1
[all_levels[43] , all_levels[44]]	[auto[1]]	--	--	2
[all_levels[50] , all_levels[51]]	[auto[1]]	--	--	2
[all_levels[53]]	[auto[1]]	0	1	1
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[60] , all_levels[61] , all_levels[62] , all_levels[63]]	[auto[1]]	--	--	4

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	29631689	1			T1	2		T2	15		T3	230
all_levels[0]	auto[1]	4263	1			T1	9		T2	5		T4	58
all_levels[1]	auto[0]	203516	1			T2	3		T3	70		T4	50
all_levels[1]	auto[1]	83	1			T101	1		T168	2		T131	1
all_levels[2]	auto[0]	2221	1			T3	7		T4	4		T5	5
all_levels[2]	auto[1]	20	1			T169	1		T170	2		T171	1
all_levels[3]	auto[0]	1047	1			T2	1		T3	1		T4	3
all_levels[3]	auto[1]	24	1			T49	2		T122	2		T172	2
all_levels[4]	auto[0]	725	1			T4	4		T6	1		T99	1
all_levels[4]	auto[1]	14	1			T169	1		T173	1		T174	1
all_levels[5]	auto[0]	486	1			T2	1		T3	1		T4	3
all_levels[5]	auto[1]	17	1			T37	1		T175	1		T176	1
all_levels[6]	auto[0]	399	1			T4	2		T5	2		T99	1
all_levels[6]	auto[1]	20	1			T37	2		T51	2		T128	1
all_levels[7]	auto[0]	332	1			T2	1		T3	2		T6	1
all_levels[7]	auto[1]	15	1			T6	1		T49	2		T148	1
all_levels[8]	auto[0]	273	1			T2	1		T3	1		T5	1
all_levels[8]	auto[1]	21	1			T39	1		T45	1		T177	5
all_levels[9]	auto[0]	208	1			T5	1		T42	1		T99	1
all_levels[9]	auto[1]	7	1			T52	1		T178	4		T147	1
all_levels[10]	auto[0]	188	1			T3	1		T43	1		T118	1
all_levels[10]	auto[1]	13	1			T121	1		T179	2		T162	1
all_levels[11]	auto[0]	177	1			T2	1		T42	1		T119	2
all_levels[11]	auto[1]	15	1			T2	2		T133	1		T180	3
all_levels[12]	auto[0]	183	1			T42	2		T43	1		T37	1
all_levels[12]	auto[1]	8	1			T181	1		T175	1		T182	2
all_levels[13]	auto[0]	141	1			T42	1		T39	1		T118	1
all_levels[13]	auto[1]	6	1			T134	2		T183	1		T184	2
all_levels[14]	auto[0]	122	1			T118	2		T70	1		T120	1
all_levels[14]	auto[1]	10	1			T70	2		T185	1		T56	1
all_levels[15]	auto[0]	102	1			T11	1		T39	1		T119	1
all_levels[15]	auto[1]	21	1			T11	3		T39	1		T186	1
all_levels[16]	auto[0]	118	1			T43	1		T118	1		T19	1
all_levels[16]	auto[1]	11	1			T187	1		T188	2		T189	3
all_levels[17]	auto[0]	82	1			T118	1		T119	1		T30	1
all_levels[17]	auto[1]	9	1			T30	1		T146	1		T190	1
all_levels[18]	auto[0]	84	1			T118	1		T85	1		T29	1
all_levels[18]	auto[1]	6	1			T191	3		T192	1		T193	1
all_levels[19]	auto[0]	84	1			T43	2		T50	1		T71	1
all_levels[19]	auto[1]	10	1			T71	1		T194	1		T195	1
all_levels[20]	auto[0]	74	1			T85	1		T50	1		T121	1
all_levels[20]	auto[1]	5	1			T170	2		T196	1		T197	1
all_levels[21]	auto[0]	66	1			T15	1		T51	1		T121	1
all_levels[21]	auto[1]	8	1			T198	2		T199	1		T200	2
all_levels[22]	auto[0]	57	1			T42	1		T119	1		T33	1
all_levels[22]	auto[1]	3	1			T201	1		T202	1		T203	1
all_levels[23]	auto[0]	64	1			T15	1		T30	1		T122	1
all_levels[23]	auto[1]	6	1			T30	2		T204	1		T205	1
all_levels[24]	auto[0]	64	1			T43	1		T99	1		T119	1
all_levels[24]	auto[1]	6	1			T133	1		T128	1		T206	1
all_levels[25]	auto[0]	53	1			T29	1		T30	1		T120	1
all_levels[25]	auto[1]	16	1			T120	3		T56	2		T207	2
all_levels[26]	auto[0]	49	1			T123	1		T52	2		T124	1
all_levels[26]	auto[1]	12	1			T181	1		T208	2		T209	1
all_levels[27]	auto[0]	35	1			T85	1		T29	2		T49	1
all_levels[27]	auto[1]	1	1			T175	1		-	-		-	-
all_levels[28]	auto[0]	33	1			T43	1		T50	1		T121	1
all_levels[28]	auto[1]	4	1			T210	1		T211	1		T212	2
all_levels[29]	auto[0]	35	1			T42	1		T85	2		T52	1
all_levels[29]	auto[1]	1	1			T213	1		-	-		-	-
all_levels[30]	auto[0]	32	1			T50	1		T115	1		T125	1
all_levels[30]	auto[1]	4	1			T214	1		T215	1		T216	1
all_levels[31]	auto[0]	35	1			T126	1		T127	2		T128	1
all_levels[31]	auto[1]	1	1			T205	1		-	-		-	-
all_levels[32]	auto[0]	27	1			T14	1		T50	1		T122	1
all_levels[33]	auto[0]	31	1			T32	1		T33	1		T111	1
all_levels[33]	auto[1]	4	1			T154	1		T217	3		-	-
all_levels[34]	auto[0]	16	1			T52	1		T129	1		T130	1
all_levels[34]	auto[1]	3	1			T218	3		-	-		-	-
all_levels[35]	auto[0]	24	1			T2	1		T131	1		T132	1
all_levels[35]	auto[1]	1	1			T219	1		-	-		-	-
all_levels[36]	auto[0]	14	1			T131	1		T112	1		T133	1
all_levels[36]	auto[1]	4	1			T220	1		T221	1		T222	1
all_levels[37]	auto[0]	36	1			T42	1		T32	1		T134	1
all_levels[37]	auto[1]	4	1			T211	1		T223	1		T224	2
all_levels[38]	auto[0]	19	1			T135	1		T53	1		T111	1
all_levels[38]	auto[1]	1	1			T225	1		-	-		-	-
all_levels[39]	auto[0]	23	1			T30	1		T136	1		T112	1
all_levels[39]	auto[1]	1	1			T226	1		-	-		-	-
all_levels[40]	auto[0]	16	1			T126	1		T137	1		T138	1
all_levels[40]	auto[1]	1	1			T126	1		-	-		-	-
all_levels[41]	auto[0]	20	1			T11	1		T85	1		T133	1
all_levels[41]	auto[1]	2	1			T11	1		T133	1		-	-
all_levels[42]	auto[0]	12	1			T85	1		T139	1		T140	1
all_levels[42]	auto[1]	4	1			T226	1		T227	2		T164	1
all_levels[43]	auto[0]	14	1			T135	1		T129	1		T137	1
all_levels[44]	auto[0]	15	1			T52	1		T141	1		T106	1
all_levels[45]	auto[0]	17	1			T30	1		T142	1		T143	1
all_levels[45]	auto[1]	4	1			T228	1		T229	2		T62	1
all_levels[46]	auto[0]	13	1			T32	1		T144	1		T145	1
all_levels[46]	auto[1]	2	1			T230	1		T231	1		-	-
all_levels[47]	auto[0]	11	1			T142	1		T146	1		T147	1
all_levels[47]	auto[1]	2	1			T232	2		-	-		-	-
all_levels[48]	auto[0]	10	1			T148	1		T149	1		T150	1
all_levels[48]	auto[1]	1	1			T233	1		-	-		-	-
all_levels[49]	auto[0]	12	1			T144	1		T143	1		T151	1
all_levels[49]	auto[1]	4	1			T234	3		T235	1		-	-
all_levels[50]	auto[0]	7	1			T152	1		T153	1		T154	1
all_levels[51]	auto[0]	8	1			T46	1		T125	1		T141	1
all_levels[52]	auto[0]	15	1			T52	1		T125	1		T155	1
all_levels[52]	auto[1]	1	1			T52	1		-	-		-	-
all_levels[53]	auto[0]	7	1			T138	1		T156	1		T157	1
all_levels[54]	auto[0]	7	1			T11	1		T19	1		T155	2
all_levels[54]	auto[1]	1	1			T236	1		-	-		-	-
all_levels[55]	auto[0]	7	1			T11	1		T19	1		T85	1
all_levels[55]	auto[1]	1	1			T237	1		-	-		-	-
all_levels[56]	auto[0]	5	1			T158	1		T159	1		T160	1
all_levels[57]	auto[0]	7	1			T139	1		T161	1		T145	1
all_levels[57]	auto[1]	4	1			T238	1		T239	3		-	-
all_levels[58]	auto[0]	12	1			T2	1		T11	1		T112	1
all_levels[58]	auto[1]	2	1			T240	2		-	-		-	-
all_levels[59]	auto[0]	4	1			T162	1		T163	1		T164	1
all_levels[59]	auto[1]	1	1			T163	1		-	-		-	-
all_levels[60]	auto[0]	7	1			T135	1		T165	1		T60	1
all_levels[61]	auto[0]	6	1			T85	1		T166	1		T154	1
all_levels[62]	auto[0]	7	1			T85	1		T140	1		T167	1
all_levels[63]	auto[0]	8	1			T42	1		T19	1		T32	1
all_levels[64]	auto[0]	96	1			T4	1		T11	1		T14	1
all_levels[64]	auto[1]	15	1			T171	2		T144	1		T56	1