Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 1 7 87.50


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 1 7 87.50 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 1 7 87.50


User Defined Bins for cp_watermark_lvl

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_levels[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 1388 1 T4 1 T6 5 T9 9
all_levels[1] 606 1 T28 1 T29 1 T110 4
all_levels[2] 489 1 T4 11 T41 2 T43 3
all_levels[3] 386 1 T38 10 T30 2 T110 1
all_levels[4] 212 1 T13 8 T29 10 T111 6
all_levels[5] 92 1 T30 1 T112 2 T113 6
all_levels[6] 61 1 T4 12 T13 10 T114 8

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%