Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	106185	1			T1	5		T2	18		T3	113
all_pins[1]	106185	1			T1	5		T2	18		T3	113
all_pins[2]	106185	1			T1	5		T2	18		T3	113
all_pins[3]	106185	1			T1	5		T2	18		T3	113
all_pins[4]	106185	1			T1	5		T2	18		T3	113
all_pins[5]	106185	1			T1	5		T2	18		T3	113
all_pins[6]	106185	1			T1	5		T2	18		T3	113
all_pins[7]	106185	1			T1	5		T2	18		T3	113
all_pins[8]	106185	1			T1	5		T2	18		T3	113

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	907701	1			T1	39		T2	139		T3	1009
values[0x1]	47964	1			T1	6		T2	23		T3	8
transitions[0x0=>0x1]	37517	1			T1	6		T2	19		T3	8
transitions[0x1=>0x0]	37318	1			T1	5		T2	18		T3	7

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	82566	1			T1	1		T2	9		T3	110
all_pins[0]	values[0x1]	23619	1			T1	4		T2	9		T3	3
all_pins[0]	transitions[0x0=>0x1]	23108	1			T1	4		T2	9		T3	3
all_pins[0]	transitions[0x1=>0x0]	1015	1			T4	4		T6	5		T28	1
all_pins[1]	values[0x0]	104659	1			T1	5		T2	18		T3	113
all_pins[1]	values[0x1]	1526	1			T4	5		T6	5		T41	2
all_pins[1]	transitions[0x0=>0x1]	1432	1			T4	5		T6	5		T41	2
all_pins[1]	transitions[0x1=>0x0]	2431	1			T1	2		T2	2		T3	4
all_pins[2]	values[0x0]	103660	1			T1	3		T2	16		T3	109
all_pins[2]	values[0x1]	2525	1			T1	2		T2	2		T3	4
all_pins[2]	transitions[0x0=>0x1]	2453	1			T1	2		T2	2		T3	4
all_pins[2]	transitions[0x1=>0x0]	231	1			T4	5		T6	1		T11	2
all_pins[3]	values[0x0]	105882	1			T1	5		T2	18		T3	113
all_pins[3]	values[0x1]	303	1			T4	5		T6	1		T11	2
all_pins[3]	transitions[0x0=>0x1]	257	1			T4	5		T6	1		T11	2
all_pins[3]	transitions[0x1=>0x0]	369	1			T4	9		T13	6		T29	1
all_pins[4]	values[0x0]	105770	1			T1	5		T2	18		T3	113
all_pins[4]	values[0x1]	415	1			T4	9		T13	6		T29	1
all_pins[4]	transitions[0x0=>0x1]	343	1			T4	6		T13	6		T29	1
all_pins[4]	transitions[0x1=>0x0]	171	1			T4	2		T30	3		T84	3
all_pins[5]	values[0x0]	105942	1			T1	5		T2	18		T3	113
all_pins[5]	values[0x1]	243	1			T4	5		T30	3		T84	4
all_pins[5]	transitions[0x0=>0x1]	195	1			T4	3		T30	1		T84	2
all_pins[5]	transitions[0x1=>0x0]	821	1			T3	1		T4	4		T6	2
all_pins[6]	values[0x0]	105316	1			T1	5		T2	18		T3	112
all_pins[6]	values[0x1]	869	1			T3	1		T4	6		T6	2
all_pins[6]	transitions[0x0=>0x1]	819	1			T3	1		T4	6		T6	2
all_pins[6]	transitions[0x1=>0x0]	268	1			T4	2		T15	1		T85	1
all_pins[7]	values[0x0]	105867	1			T1	5		T2	18		T3	113
all_pins[7]	values[0x1]	318	1			T4	2		T15	1		T85	1
all_pins[7]	transitions[0x0=>0x1]	159	1			T4	2		T85	1		T29	1
all_pins[7]	transitions[0x1=>0x0]	17987	1			T2	12		T4	102		T5	4
all_pins[8]	values[0x0]	88039	1			T1	5		T2	6		T3	113
all_pins[8]	values[0x1]	18146	1			T2	12		T4	102		T5	4
all_pins[8]	transitions[0x0=>0x1]	8751	1			T2	8		T4	64		T5	1
all_pins[8]	transitions[0x1=>0x0]	14025	1			T1	3		T2	4		T3	2