Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8774690	1			T1	6		T2	11		T3	282
all_levels[1]	1247583	1			T2	4		T3	2		T4	521
all_levels[2]	549949	1			T3	2		T4	518		T5	2
all_levels[3]	229928	1			T3	3		T4	511		T7	3
all_levels[4]	292833	1			T3	1		T4	518		T9	1205
all_levels[5]	295552	1			T3	2		T4	517		T6	2
all_levels[6]	210759	1			T2	2		T3	2		T4	518
all_levels[7]	257113	1			T4	519		T7	1		T9	1204
all_levels[8]	330157	1			T4	516		T7	2		T9	1204
all_levels[9]	213642	1			T4	519		T7	1		T9	1210
all_levels[10]	222763	1			T4	515		T9	1209		T42	1
all_levels[11]	195199	1			T4	519		T9	1313		T42	1
all_levels[12]	294215	1			T4	520		T9	1321		T100	2559
all_levels[13]	604965	1			T3	1		T4	518		T9	1390
all_levels[14]	435412	1			T4	521		T7	6		T9	1817
all_levels[15]	250409	1			T4	515		T9	1810		T42	2
all_levels[16]	490940	1			T3	1		T4	517		T6	2
all_levels[17]	201108	1			T4	522		T9	1812		T100	2548
all_levels[18]	239308	1			T4	516		T6	2		T9	1812
all_levels[19]	209506	1			T4	515		T9	1813		T100	2534
all_levels[20]	220121	1			T1	3		T4	518		T9	1814
all_levels[21]	203939	1			T2	3		T4	521		T9	1803
all_levels[22]	299417	1			T4	517		T6	2		T9	81140
all_levels[23]	243460	1			T4	519		T6	2		T9	1789
all_levels[24]	225501	1			T3	1		T4	516		T5	3
all_levels[25]	150682	1			T4	519		T9	1815		T100	2529
all_levels[26]	147240	1			T3	1		T4	516		T9	1814
all_levels[27]	397289	1			T4	518		T5	1		T6	3
all_levels[28]	184034	1			T4	517		T9	1797		T42	2
all_levels[29]	318474	1			T4	511		T9	1815		T100	2520
all_levels[30]	155142	1			T4	518		T9	1813		T100	2572
all_levels[31]	513983	1			T3	2		T4	1780		T9	5850
all_levels[32]	11242350	1			T2	13		T3	13		T4	26534

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29843307

1

T1

2

T2

25

T3

313

auto[1]

4356

1

T1

7

T2

8

T4

37

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8772148	1			T1	1		T2	7		T3	282
all_levels[0]	auto[1]	2542	1			T1	5		T2	4		T4	36
all_levels[1]	auto[0]	1247241	1			T2	4		T3	2		T4	521
all_levels[1]	auto[1]	342	1			T10	1		T43	3		T99	1
all_levels[2]	auto[0]	549913	1			T3	2		T4	518		T5	2
all_levels[2]	auto[1]	36	1			T124	1		T330	2		T213	1
all_levels[3]	auto[0]	229788	1			T3	3		T4	511		T7	3
all_levels[3]	auto[1]	140	1			T241	1		T70	4		T52	1
all_levels[4]	auto[0]	292812	1			T3	1		T4	518		T9	1205
all_levels[4]	auto[1]	21	1			T331	2		T175	1		T180	1
all_levels[5]	auto[0]	295513	1			T3	2		T4	517		T6	2
all_levels[5]	auto[1]	39	1			T11	3		T198	2		T139	3
all_levels[6]	auto[0]	210728	1			T2	2		T3	2		T4	518
all_levels[6]	auto[1]	31	1			T46	1		T331	2		T180	1
all_levels[7]	auto[0]	257021	1			T4	519		T7	1		T9	1204
all_levels[7]	auto[1]	92	1			T270	1		T259	5		T332	1
all_levels[8]	auto[0]	330134	1			T4	516		T7	2		T9	1204
all_levels[8]	auto[1]	23	1			T268	1		T333	1		T334	1
all_levels[9]	auto[0]	213614	1			T4	519		T7	1		T9	1210
all_levels[9]	auto[1]	28	1			T122	1		T84	1		T249	1
all_levels[10]	auto[0]	222749	1			T4	515		T9	1209		T42	1
all_levels[10]	auto[1]	14	1			T335	3		T336	1		T337	1
all_levels[11]	auto[0]	195166	1			T4	519		T9	1313		T42	1
all_levels[11]	auto[1]	33	1			T11	1		T258	2		T32	1
all_levels[12]	auto[0]	294183	1			T4	520		T9	1321		T100	2559
all_levels[12]	auto[1]	32	1			T257	2		T112	1		T186	2
all_levels[13]	auto[0]	604943	1			T3	1		T4	518		T9	1390
all_levels[13]	auto[1]	22	1			T101	2		T134	2		T256	1
all_levels[14]	auto[0]	435397	1			T4	521		T7	5		T9	1817
all_levels[14]	auto[1]	15	1			T7	1		T29	1		T168	2
all_levels[15]	auto[0]	250332	1			T4	515		T9	1810		T42	2
all_levels[15]	auto[1]	77	1			T30	2		T33	1		T271	1
all_levels[16]	auto[0]	490915	1			T3	1		T4	517		T6	1
all_levels[16]	auto[1]	25	1			T6	1		T52	1		T131	2
all_levels[17]	auto[0]	201089	1			T4	522		T9	1812		T100	2548
all_levels[17]	auto[1]	19	1			T180	2		T338	1		T57	1
all_levels[18]	auto[0]	239290	1			T4	516		T6	2		T9	1812
all_levels[18]	auto[1]	18	1			T302	2		T220	2		T339	1
all_levels[19]	auto[0]	209468	1			T4	515		T9	1813		T100	2534
all_levels[19]	auto[1]	38	1			T261	1		T135	1		T210	2
all_levels[20]	auto[0]	220101	1			T1	1		T4	518		T9	1814
all_levels[20]	auto[1]	20	1			T1	2		T261	1		T270	4
all_levels[21]	auto[0]	203923	1			T2	2		T4	521		T9	1803
all_levels[21]	auto[1]	16	1			T2	1		T84	1		T186	2
all_levels[22]	auto[0]	299388	1			T4	517		T6	2		T9	81140
all_levels[22]	auto[1]	29	1			T43	1		T247	1		T124	2
all_levels[23]	auto[0]	243443	1			T4	519		T6	2		T9	1789
all_levels[23]	auto[1]	17	1			T154	2		T226	1		T340	1
all_levels[24]	auto[0]	225485	1			T3	1		T4	516		T5	3
all_levels[24]	auto[1]	16	1			T295	1		T185	2		T173	1
all_levels[25]	auto[0]	150654	1			T4	519		T9	1815		T100	2529
all_levels[25]	auto[1]	28	1			T294	1		T33	2		T52	1
all_levels[26]	auto[0]	147217	1			T3	1		T4	516		T9	1814
all_levels[26]	auto[1]	23	1			T341	1		T342	5		T343	1
all_levels[27]	auto[0]	397251	1			T4	518		T5	1		T6	2
all_levels[27]	auto[1]	38	1			T6	1		T101	2		T261	2
all_levels[28]	auto[0]	184015	1			T4	517		T9	1797		T42	2
all_levels[28]	auto[1]	19	1			T46	2		T51	1		T170	2
all_levels[29]	auto[0]	318456	1			T4	511		T9	1815		T100	2520
all_levels[29]	auto[1]	18	1			T12	1		T198	1		T296	1
all_levels[30]	auto[0]	155127	1			T4	518		T9	1813		T100	2572
all_levels[30]	auto[1]	15	1			T141	1		T106	1		T344	3
all_levels[31]	auto[0]	513962	1			T3	2		T4	1780		T9	5850
all_levels[31]	auto[1]	21	1			T270	1		T103	3		T173	3
all_levels[32]	auto[0]	11241841	1			T2	10		T3	13		T4	26533
all_levels[32]	auto[1]	509	1			T2	3		T4	1		T9	1