Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	739	1			T4	7		T29	4		T30	19
all_values[1]	739	1			T4	7		T29	4		T30	19
all_values[2]	739	1			T4	7		T29	4		T30	19
all_values[3]	739	1			T4	7		T29	4		T30	19
all_values[4]	739	1			T4	7		T29	4		T30	19
all_values[5]	739	1			T4	7		T29	4		T30	19
all_values[6]	739	1			T4	7		T29	4		T30	19
all_values[7]	739	1			T4	7		T29	4		T30	19
all_values[8]	739	1			T4	7		T29	4		T30	19

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3486

1

T4

41

T29

13

T30

86

auto[1]

3165

1

T4

22

T29

23

T30

85

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2134

1

T4

25

T29

14

T30

49

auto[1]

4517

1

T4

38

T29

22

T30

122

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3933

1

T4

41

T29

24

T30

112

auto[1]

2718

1

T4

22

T29

12

T30

59

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	235	1			T4	3		T29	1		T30	5
all_values[0]	auto[0]	auto[1]	auto[1]	214	1			T4	1		T29	2		T30	9
all_values[0]	auto[1]	auto[0]	auto[1]	153	1			T4	2		T29	1		T30	4
all_values[0]	auto[1]	auto[1]	auto[1]	137	1			T4	1		T30	1		T84	1
all_values[1]	auto[0]	auto[0]	auto[0]	217	1			T4	4		T30	11		T84	3
all_values[1]	auto[0]	auto[1]	auto[0]	207	1			T4	2		T29	3		T30	2
all_values[1]	auto[1]	auto[0]	auto[1]	164	1			T30	2		T84	1		T52	4
all_values[1]	auto[1]	auto[1]	auto[1]	151	1			T4	1		T29	1		T30	4
all_values[2]	auto[0]	auto[0]	auto[0]	146	1			T4	3		T84	1		T52	1
all_values[2]	auto[0]	auto[0]	auto[1]	72	1			T4	1		T29	1		T30	5
all_values[2]	auto[0]	auto[1]	auto[0]	137	1			T30	3		T84	1		T52	3
all_values[2]	auto[0]	auto[1]	auto[1]	83	1			T4	1		T29	1		T30	2
all_values[2]	auto[1]	auto[0]	auto[1]	155	1			T4	1		T29	1		T30	7
all_values[2]	auto[1]	auto[1]	auto[1]	146	1			T4	1		T29	1		T30	2
all_values[3]	auto[0]	auto[0]	auto[0]	142	1			T30	4		T52	1		T111	2
all_values[3]	auto[0]	auto[0]	auto[1]	69	1			T4	1		T30	3		T52	3
all_values[3]	auto[0]	auto[1]	auto[0]	131	1			T4	2		T29	3		T30	2
all_values[3]	auto[0]	auto[1]	auto[1]	85	1			T30	3		T53	3		T115	1
all_values[3]	auto[1]	auto[0]	auto[1]	168	1			T4	3		T29	1		T30	4
all_values[3]	auto[1]	auto[1]	auto[1]	144	1			T4	1		T30	3		T84	3
all_values[4]	auto[0]	auto[0]	auto[0]	175	1			T29	1		T30	5		T84	4
all_values[4]	auto[0]	auto[0]	auto[1]	72	1			T4	1		T30	2		T52	1
all_values[4]	auto[0]	auto[1]	auto[0]	132	1			T30	1		T52	1		T53	4
all_values[4]	auto[0]	auto[1]	auto[1]	72	1			T4	1		T30	4		T84	1
all_values[4]	auto[1]	auto[0]	auto[1]	167	1			T4	3		T29	2		T30	2
all_values[4]	auto[1]	auto[1]	auto[1]	121	1			T4	2		T29	1		T30	5
all_values[5]	auto[0]	auto[0]	auto[0]	152	1			T4	4		T30	2		T52	3
all_values[5]	auto[0]	auto[0]	auto[1]	66	1			T29	1		T30	3		T52	1
all_values[5]	auto[0]	auto[1]	auto[0]	125	1			T29	2		T30	6		T84	2
all_values[5]	auto[0]	auto[1]	auto[1]	87	1			T4	1		T30	1		T84	2
all_values[5]	auto[1]	auto[0]	auto[1]	161	1			T4	1		T29	1		T30	4
all_values[5]	auto[1]	auto[1]	auto[1]	148	1			T4	1		T30	3		T84	3
all_values[6]	auto[0]	auto[0]	auto[0]	143	1			T4	2		T30	2		T84	2
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T30	1		T53	2		T115	1
all_values[6]	auto[0]	auto[1]	auto[0]	136	1			T4	3		T29	1		T30	2
all_values[6]	auto[0]	auto[1]	auto[1]	80	1			T4	1		T29	1		T30	5
all_values[6]	auto[1]	auto[0]	auto[1]	176	1			T29	1		T30	5		T52	1
all_values[6]	auto[1]	auto[1]	auto[1]	134	1			T4	1		T29	1		T30	4
all_values[7]	auto[0]	auto[0]	auto[0]	156	1			T4	4		T29	1		T30	3
all_values[7]	auto[0]	auto[0]	auto[1]	85	1			T30	3		T84	1		T53	2
all_values[7]	auto[0]	auto[1]	auto[0]	135	1			T4	1		T29	3		T30	6
all_values[7]	auto[0]	auto[1]	auto[1]	74	1			T30	2		T52	1		T53	1
all_values[7]	auto[1]	auto[0]	auto[1]	164	1			T4	2		T30	4		T84	2
all_values[7]	auto[1]	auto[1]	auto[1]	125	1			T30	1		T84	2		T116	1
all_values[8]	auto[0]	auto[0]	auto[1]	215	1			T4	4		T30	4		T84	2
all_values[8]	auto[0]	auto[1]	auto[1]	220	1			T4	1		T29	3		T30	11
all_values[8]	auto[1]	auto[0]	auto[1]	163	1			T4	2		T29	1		T30	1
all_values[8]	auto[1]	auto[1]	auto[1]	141	1			T30	3		T84	1		T52	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal