Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.53


Total test records in report: 1313
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T1257 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1325688776 Aug 04 04:25:03 PM PDT 24 Aug 04 04:25:03 PM PDT 24 16514702 ps
T1258 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1946667311 Aug 04 04:25:56 PM PDT 24 Aug 04 04:25:59 PM PDT 24 707925488 ps
T1259 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.988011820 Aug 04 04:24:40 PM PDT 24 Aug 04 04:24:41 PM PDT 24 118779895 ps
T1260 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2478774599 Aug 04 04:24:36 PM PDT 24 Aug 04 04:24:38 PM PDT 24 52480780 ps
T1261 /workspace/coverage/cover_reg_top/19.uart_intr_test.2943979449 Aug 04 04:24:57 PM PDT 24 Aug 04 04:24:58 PM PDT 24 15368493 ps
T1262 /workspace/coverage/cover_reg_top/23.uart_intr_test.3850924167 Aug 04 04:25:30 PM PDT 24 Aug 04 04:25:31 PM PDT 24 32405125 ps
T1263 /workspace/coverage/cover_reg_top/41.uart_intr_test.3812868210 Aug 04 04:25:01 PM PDT 24 Aug 04 04:25:02 PM PDT 24 25020063 ps
T1264 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.698004808 Aug 04 04:25:31 PM PDT 24 Aug 04 04:25:31 PM PDT 24 81538812 ps
T117 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1322625233 Aug 04 04:25:41 PM PDT 24 Aug 04 04:25:42 PM PDT 24 104220919 ps
T1265 /workspace/coverage/cover_reg_top/29.uart_intr_test.3539720590 Aug 04 04:24:56 PM PDT 24 Aug 04 04:24:57 PM PDT 24 14933597 ps
T1266 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2653355925 Aug 04 04:25:04 PM PDT 24 Aug 04 04:25:05 PM PDT 24 89499136 ps
T94 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1375566685 Aug 04 04:25:41 PM PDT 24 Aug 04 04:25:42 PM PDT 24 322540322 ps
T1267 /workspace/coverage/cover_reg_top/16.uart_tl_errors.3606938812 Aug 04 04:25:02 PM PDT 24 Aug 04 04:25:03 PM PDT 24 204534979 ps
T1268 /workspace/coverage/cover_reg_top/17.uart_csr_rw.3903380875 Aug 04 04:24:51 PM PDT 24 Aug 04 04:24:52 PM PDT 24 14463161 ps
T1269 /workspace/coverage/cover_reg_top/33.uart_intr_test.2246081171 Aug 04 04:25:31 PM PDT 24 Aug 04 04:25:31 PM PDT 24 24427147 ps
T1270 /workspace/coverage/cover_reg_top/44.uart_intr_test.3334256746 Aug 04 04:25:00 PM PDT 24 Aug 04 04:25:01 PM PDT 24 42831347 ps
T1271 /workspace/coverage/cover_reg_top/40.uart_intr_test.3382117413 Aug 04 04:25:19 PM PDT 24 Aug 04 04:25:19 PM PDT 24 24391338 ps
T1272 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2197167614 Aug 04 04:24:57 PM PDT 24 Aug 04 04:24:58 PM PDT 24 262716942 ps
T1273 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.961275321 Aug 04 04:25:33 PM PDT 24 Aug 04 04:25:34 PM PDT 24 62372453 ps
T1274 /workspace/coverage/cover_reg_top/48.uart_intr_test.625750235 Aug 04 04:25:03 PM PDT 24 Aug 04 04:25:04 PM PDT 24 17070189 ps
T1275 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2656844010 Aug 04 04:24:52 PM PDT 24 Aug 04 04:24:53 PM PDT 24 86258180 ps
T1276 /workspace/coverage/cover_reg_top/31.uart_intr_test.3053289983 Aug 04 04:25:51 PM PDT 24 Aug 04 04:25:52 PM PDT 24 53121837 ps
T1277 /workspace/coverage/cover_reg_top/47.uart_intr_test.40161385 Aug 04 04:25:56 PM PDT 24 Aug 04 04:25:57 PM PDT 24 47837571 ps
T1278 /workspace/coverage/cover_reg_top/17.uart_tl_errors.2904331262 Aug 04 04:24:48 PM PDT 24 Aug 04 04:24:51 PM PDT 24 462157433 ps
T1279 /workspace/coverage/cover_reg_top/32.uart_intr_test.1578490806 Aug 04 04:24:52 PM PDT 24 Aug 04 04:24:53 PM PDT 24 16515209 ps
T1280 /workspace/coverage/cover_reg_top/15.uart_intr_test.922802729 Aug 04 04:25:02 PM PDT 24 Aug 04 04:25:03 PM PDT 24 135518338 ps
T1281 /workspace/coverage/cover_reg_top/12.uart_intr_test.2971363879 Aug 04 04:25:02 PM PDT 24 Aug 04 04:25:03 PM PDT 24 115463883 ps
T1282 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3019489009 Aug 04 04:24:50 PM PDT 24 Aug 04 04:24:51 PM PDT 24 90407146 ps
T1283 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.407118539 Aug 04 04:24:59 PM PDT 24 Aug 04 04:25:00 PM PDT 24 18042331 ps
T1284 /workspace/coverage/cover_reg_top/18.uart_tl_errors.2378459567 Aug 04 04:25:35 PM PDT 24 Aug 04 04:25:37 PM PDT 24 402062358 ps
T1285 /workspace/coverage/cover_reg_top/7.uart_intr_test.370439369 Aug 04 04:24:40 PM PDT 24 Aug 04 04:24:40 PM PDT 24 13538556 ps
T1286 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3502417165 Aug 04 04:24:21 PM PDT 24 Aug 04 04:24:22 PM PDT 24 75967537 ps
T67 /workspace/coverage/cover_reg_top/5.uart_csr_rw.2852109060 Aug 04 04:24:35 PM PDT 24 Aug 04 04:24:36 PM PDT 24 30284862 ps
T1287 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.725310159 Aug 04 04:24:59 PM PDT 24 Aug 04 04:25:00 PM PDT 24 187003259 ps
T1288 /workspace/coverage/cover_reg_top/15.uart_tl_errors.1323281330 Aug 04 04:24:53 PM PDT 24 Aug 04 04:24:56 PM PDT 24 666134516 ps
T1289 /workspace/coverage/cover_reg_top/2.uart_intr_test.457484566 Aug 04 04:25:51 PM PDT 24 Aug 04 04:25:52 PM PDT 24 11614796 ps
T1290 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2106912302 Aug 04 04:25:57 PM PDT 24 Aug 04 04:25:58 PM PDT 24 53513349 ps
T1291 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2757374147 Aug 04 04:25:52 PM PDT 24 Aug 04 04:25:53 PM PDT 24 43295033 ps
T1292 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2157517131 Aug 04 04:25:30 PM PDT 24 Aug 04 04:25:31 PM PDT 24 20541513 ps
T1293 /workspace/coverage/cover_reg_top/37.uart_intr_test.1233329930 Aug 04 04:24:57 PM PDT 24 Aug 04 04:24:58 PM PDT 24 16957053 ps
T1294 /workspace/coverage/cover_reg_top/11.uart_tl_errors.3613832110 Aug 04 04:24:51 PM PDT 24 Aug 04 04:24:52 PM PDT 24 67903129 ps
T1295 /workspace/coverage/cover_reg_top/26.uart_intr_test.2285212264 Aug 04 04:25:35 PM PDT 24 Aug 04 04:25:35 PM PDT 24 67418627 ps
T1296 /workspace/coverage/cover_reg_top/14.uart_intr_test.2106198857 Aug 04 04:25:06 PM PDT 24 Aug 04 04:25:07 PM PDT 24 15417236 ps
T1297 /workspace/coverage/cover_reg_top/43.uart_intr_test.4019173542 Aug 04 04:24:57 PM PDT 24 Aug 04 04:24:58 PM PDT 24 15647461 ps
T1298 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3132413269 Aug 04 04:25:56 PM PDT 24 Aug 04 04:25:58 PM PDT 24 77850722 ps
T1299 /workspace/coverage/cover_reg_top/8.uart_csr_rw.1422048151 Aug 04 04:24:43 PM PDT 24 Aug 04 04:24:44 PM PDT 24 18423610 ps
T1300 /workspace/coverage/cover_reg_top/16.uart_intr_test.2337836364 Aug 04 04:25:01 PM PDT 24 Aug 04 04:25:01 PM PDT 24 38141740 ps
T1301 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2880613909 Aug 04 04:24:43 PM PDT 24 Aug 04 04:24:43 PM PDT 24 16770097 ps
T1302 /workspace/coverage/cover_reg_top/8.uart_tl_errors.3770968849 Aug 04 04:24:44 PM PDT 24 Aug 04 04:24:45 PM PDT 24 27090003 ps
T1303 /workspace/coverage/cover_reg_top/4.uart_tl_errors.3969380469 Aug 04 04:24:46 PM PDT 24 Aug 04 04:24:48 PM PDT 24 1154019465 ps
T1304 /workspace/coverage/cover_reg_top/27.uart_intr_test.1393576494 Aug 04 04:25:02 PM PDT 24 Aug 04 04:25:03 PM PDT 24 12291224 ps
T1305 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3057654213 Aug 04 04:24:36 PM PDT 24 Aug 04 04:24:37 PM PDT 24 27878823 ps
T1306 /workspace/coverage/cover_reg_top/12.uart_csr_rw.4103692706 Aug 04 04:24:53 PM PDT 24 Aug 04 04:24:53 PM PDT 24 52960266 ps
T1307 /workspace/coverage/cover_reg_top/7.uart_csr_rw.3441969752 Aug 04 04:24:46 PM PDT 24 Aug 04 04:24:47 PM PDT 24 13732929 ps
T1308 /workspace/coverage/cover_reg_top/4.uart_csr_rw.992937270 Aug 04 04:24:32 PM PDT 24 Aug 04 04:24:32 PM PDT 24 14151119 ps
T68 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2511360331 Aug 04 04:25:52 PM PDT 24 Aug 04 04:25:53 PM PDT 24 60219093 ps
T1309 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1087783340 Aug 04 04:24:36 PM PDT 24 Aug 04 04:24:37 PM PDT 24 148738262 ps
T1310 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.265705971 Aug 04 04:24:36 PM PDT 24 Aug 04 04:24:37 PM PDT 24 93865887 ps
T1311 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1217278343 Aug 04 04:24:46 PM PDT 24 Aug 04 04:24:47 PM PDT 24 67255810 ps
T69 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2145392986 Aug 04 04:24:55 PM PDT 24 Aug 04 04:24:56 PM PDT 24 27457705 ps
T1312 /workspace/coverage/cover_reg_top/38.uart_intr_test.1339436226 Aug 04 04:24:57 PM PDT 24 Aug 04 04:24:57 PM PDT 24 137553723 ps
T1313 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2977273663 Aug 04 04:25:01 PM PDT 24 Aug 04 04:25:02 PM PDT 24 64417826 ps
T91 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3710579725 Aug 04 04:24:57 PM PDT 24 Aug 04 04:24:58 PM PDT 24 277488082 ps

Test location /workspace/coverage/default/203.uart_fifo_reset.1998911850
Short name T2
Test name
Test status
Simulation time 62688596506 ps
CPU time 24.39 seconds
Started Aug 04 05:11:51 PM PDT 24
Finished Aug 04 05:12:16 PM PDT 24
Peak memory 199848 kb
Host smart-9d8b4e8d-e108-4377-97a9-c4342b1fe3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998911850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1998911850
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.544032197
Short name T29
Test name
Test status
Simulation time 196799717199 ps
CPU time 984.67 seconds
Started Aug 04 05:11:03 PM PDT 24
Finished Aug 04 05:27:28 PM PDT 24
Peak memory 232436 kb
Host smart-bad9cc9f-79a1-4b65-8aca-0386a178a37a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544032197 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.544032197
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3610880350
Short name T34
Test name
Test status
Simulation time 119943897658 ps
CPU time 1454.17 seconds
Started Aug 04 05:05:25 PM PDT 24
Finished Aug 04 05:29:39 PM PDT 24
Peak memory 232816 kb
Host smart-3880cca6-286e-496f-b561-dfb7b0b62015
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610880350 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3610880350
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2320209385
Short name T32
Test name
Test status
Simulation time 529729348866 ps
CPU time 785.04 seconds
Started Aug 04 05:07:41 PM PDT 24
Finished Aug 04 05:20:46 PM PDT 24
Peak memory 216496 kb
Host smart-ec4c3c16-5ff7-41f4-90d4-35745cfcc5c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320209385 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2320209385
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_stress_all.2182007980
Short name T4
Test name
Test status
Simulation time 271239901251 ps
CPU time 201.19 seconds
Started Aug 04 05:08:43 PM PDT 24
Finished Aug 04 05:12:05 PM PDT 24
Peak memory 199888 kb
Host smart-4ef7fa91-8c77-463f-9209-5f04c6042275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182007980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2182007980
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3706687518
Short name T53
Test name
Test status
Simulation time 141734960545 ps
CPU time 815.04 seconds
Started Aug 04 05:10:00 PM PDT 24
Finished Aug 04 05:23:35 PM PDT 24
Peak memory 224708 kb
Host smart-91e8523f-edae-4eb8-81d2-b035ef1b5ad2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706687518 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3706687518
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1631476599
Short name T33
Test name
Test status
Simulation time 165225229032 ps
CPU time 1574.17 seconds
Started Aug 04 05:08:33 PM PDT 24
Finished Aug 04 05:34:48 PM PDT 24
Peak memory 224996 kb
Host smart-67b7e66f-b34b-4f66-86cb-100e5db77f38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631476599 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1631476599
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1243296799
Short name T22
Test name
Test status
Simulation time 34788935 ps
CPU time 0.74 seconds
Started Aug 04 05:05:28 PM PDT 24
Finished Aug 04 05:05:29 PM PDT 24
Peak memory 218104 kb
Host smart-06fce5db-ff7c-481d-8352-0162ba6f26e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243296799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1243296799
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/18.uart_stress_all.1666524644
Short name T125
Test name
Test status
Simulation time 422946796683 ps
CPU time 700.2 seconds
Started Aug 04 05:07:41 PM PDT 24
Finished Aug 04 05:19:22 PM PDT 24
Peak memory 208100 kb
Host smart-f06896e2-5ffc-4f5b-8689-8fa78650d202
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666524644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1666524644
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.182988846
Short name T30
Test name
Test status
Simulation time 194622023613 ps
CPU time 1200.16 seconds
Started Aug 04 05:10:59 PM PDT 24
Finished Aug 04 05:30:59 PM PDT 24
Peak memory 224756 kb
Host smart-3762cf12-4a25-4fe8-8f45-75800fcbab73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182988846 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.182988846
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_stress_all.1093057375
Short name T140
Test name
Test status
Simulation time 864077401762 ps
CPU time 327.53 seconds
Started Aug 04 05:08:34 PM PDT 24
Finished Aug 04 05:14:02 PM PDT 24
Peak memory 200004 kb
Host smart-ee8f8a8b-7c4f-44b8-9ec3-474643d85dd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093057375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1093057375
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3909345955
Short name T12
Test name
Test status
Simulation time 112073534286 ps
CPU time 1234.95 seconds
Started Aug 04 05:10:53 PM PDT 24
Finished Aug 04 05:31:28 PM PDT 24
Peak memory 224652 kb
Host smart-0676f212-70e6-427c-817b-dac0181687c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909345955 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3909345955
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.455359798
Short name T52
Test name
Test status
Simulation time 313496184203 ps
CPU time 389.68 seconds
Started Aug 04 05:09:12 PM PDT 24
Finished Aug 04 05:15:42 PM PDT 24
Peak memory 216360 kb
Host smart-12f8d838-d099-482f-a6ef-a3ade140f232
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455359798 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.455359798
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1572964504
Short name T84
Test name
Test status
Simulation time 68278602807 ps
CPU time 912.4 seconds
Started Aug 04 05:09:08 PM PDT 24
Finished Aug 04 05:24:21 PM PDT 24
Peak memory 211808 kb
Host smart-beb8fb1a-58aa-4675-8763-47e129437d8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572964504 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1572964504
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1916894412
Short name T111
Test name
Test status
Simulation time 416882414252 ps
CPU time 1027.32 seconds
Started Aug 04 05:10:21 PM PDT 24
Finished Aug 04 05:27:28 PM PDT 24
Peak memory 232736 kb
Host smart-5e3aee67-e63b-4214-884e-e6f94aab9535
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916894412 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1916894412
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1712835905
Short name T96
Test name
Test status
Simulation time 96905512 ps
CPU time 1.21 seconds
Started Aug 04 04:24:46 PM PDT 24
Finished Aug 04 04:24:48 PM PDT 24
Peak memory 199656 kb
Host smart-7c6d6006-e8fe-4480-bbc5-825be85453f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712835905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1712835905
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/default/16.uart_alert_test.927733110
Short name T357
Test name
Test status
Simulation time 40563161 ps
CPU time 0.53 seconds
Started Aug 04 05:07:28 PM PDT 24
Finished Aug 04 05:07:28 PM PDT 24
Peak memory 195496 kb
Host smart-db7b027b-c0fe-4311-9f8c-cac9e8cf1e9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927733110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.927733110
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.454761036
Short name T63
Test name
Test status
Simulation time 48839200 ps
CPU time 0.63 seconds
Started Aug 04 04:24:56 PM PDT 24
Finished Aug 04 04:24:56 PM PDT 24
Peak memory 195632 kb
Host smart-614d7392-296a-402c-867e-a7985dd4da35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454761036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.454761036
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1019498851
Short name T51
Test name
Test status
Simulation time 73585595755 ps
CPU time 75.51 seconds
Started Aug 04 05:11:07 PM PDT 24
Finished Aug 04 05:12:23 PM PDT 24
Peak memory 199860 kb
Host smart-6fb2dc89-34a5-437b-805d-c8793b38f80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019498851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1019498851
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1175177136
Short name T220
Test name
Test status
Simulation time 182810240997 ps
CPU time 175.75 seconds
Started Aug 04 05:12:00 PM PDT 24
Finished Aug 04 05:14:56 PM PDT 24
Peak memory 199828 kb
Host smart-e61344b1-c062-4a08-af52-df06f85fb0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175177136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1175177136
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.413339702
Short name T56
Test name
Test status
Simulation time 660584266635 ps
CPU time 600.6 seconds
Started Aug 04 05:08:44 PM PDT 24
Finished Aug 04 05:18:45 PM PDT 24
Peak memory 224608 kb
Host smart-a42402a6-ae2c-43e5-b575-5ea626c18cda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413339702 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.413339702
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all.1560448049
Short name T146
Test name
Test status
Simulation time 141106422380 ps
CPU time 895.46 seconds
Started Aug 04 05:05:47 PM PDT 24
Finished Aug 04 05:20:42 PM PDT 24
Peak memory 199916 kb
Host smart-397f93d9-2553-44f6-bd5a-a623f2b9b8e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560448049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1560448049
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.302386689
Short name T99
Test name
Test status
Simulation time 24209666713 ps
CPU time 42.03 seconds
Started Aug 04 05:09:03 PM PDT 24
Finished Aug 04 05:09:45 PM PDT 24
Peak memory 199856 kb
Host smart-b6bc02fa-14c8-4c99-a733-c32c11cab231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302386689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.302386689
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.4063584009
Short name T139
Test name
Test status
Simulation time 136988643801 ps
CPU time 48.3 seconds
Started Aug 04 05:10:43 PM PDT 24
Finished Aug 04 05:11:32 PM PDT 24
Peak memory 199852 kb
Host smart-c9eb772c-cb85-40b0-8d26-b3a4ca49183b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063584009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.4063584009
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2617231198
Short name T215
Test name
Test status
Simulation time 305609823619 ps
CPU time 205.01 seconds
Started Aug 04 05:12:13 PM PDT 24
Finished Aug 04 05:15:38 PM PDT 24
Peak memory 199828 kb
Host smart-353494f3-cac3-4347-b856-b4c4a705935e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617231198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2617231198
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.429121656
Short name T19
Test name
Test status
Simulation time 233693026150 ps
CPU time 289.98 seconds
Started Aug 04 05:10:42 PM PDT 24
Finished Aug 04 05:15:33 PM PDT 24
Peak memory 216336 kb
Host smart-cf318a65-80af-45e6-84c0-9a3aa57a0563
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429121656 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.429121656
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.4109292125
Short name T180
Test name
Test status
Simulation time 40645469951 ps
CPU time 78.13 seconds
Started Aug 04 05:11:24 PM PDT 24
Finished Aug 04 05:12:42 PM PDT 24
Peak memory 199880 kb
Host smart-6a013b1e-13d8-4e36-a4b2-132538061245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109292125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.4109292125
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1186238758
Short name T154
Test name
Test status
Simulation time 87542152069 ps
CPU time 143.59 seconds
Started Aug 04 05:10:54 PM PDT 24
Finished Aug 04 05:13:18 PM PDT 24
Peak memory 199884 kb
Host smart-83974c03-29fd-4734-8fc9-3bb77227697e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186238758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1186238758
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2324990381
Short name T89
Test name
Test status
Simulation time 61909700 ps
CPU time 0.92 seconds
Started Aug 04 04:25:48 PM PDT 24
Finished Aug 04 04:25:49 PM PDT 24
Peak memory 199056 kb
Host smart-da8166d7-00dd-438f-a0b0-87714b8c4380
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324990381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2324990381
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.993759804
Short name T141
Test name
Test status
Simulation time 16843183200 ps
CPU time 24.4 seconds
Started Aug 04 05:11:21 PM PDT 24
Finished Aug 04 05:11:46 PM PDT 24
Peak memory 199816 kb
Host smart-711f2cd1-f2a2-40a7-84a4-7157d6d218bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993759804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.993759804
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2269674286
Short name T270
Test name
Test status
Simulation time 184882999859 ps
CPU time 51.94 seconds
Started Aug 04 05:12:20 PM PDT 24
Finished Aug 04 05:13:12 PM PDT 24
Peak memory 199840 kb
Host smart-0bc5bed9-bc2a-4855-a4aa-ad261a70b077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269674286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2269674286
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.393087589
Short name T138
Test name
Test status
Simulation time 14891545441 ps
CPU time 24.59 seconds
Started Aug 04 05:11:32 PM PDT 24
Finished Aug 04 05:11:57 PM PDT 24
Peak memory 199648 kb
Host smart-91a14f5e-e9c5-4af7-bab7-c4d4f8e9aeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393087589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.393087589
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3435440378
Short name T37
Test name
Test status
Simulation time 121626106536 ps
CPU time 24.34 seconds
Started Aug 04 05:10:51 PM PDT 24
Finished Aug 04 05:11:16 PM PDT 24
Peak memory 199792 kb
Host smart-ae6e32d8-0851-41c8-a3cd-375a7f433151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435440378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3435440378
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.443233112
Short name T102
Test name
Test status
Simulation time 72764603119 ps
CPU time 842.57 seconds
Started Aug 04 05:11:12 PM PDT 24
Finished Aug 04 05:25:15 PM PDT 24
Peak memory 224648 kb
Host smart-ae3ca368-e3f5-49d6-8a15-0df65a56e3cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443233112 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.443233112
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3019489009
Short name T1282
Test name
Test status
Simulation time 90407146 ps
CPU time 0.9 seconds
Started Aug 04 04:24:50 PM PDT 24
Finished Aug 04 04:24:51 PM PDT 24
Peak memory 198852 kb
Host smart-c0d74c9e-bf85-450e-9767-05b4da72b658
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019489009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3019489009
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3900610381
Short name T50
Test name
Test status
Simulation time 81227453459 ps
CPU time 40.98 seconds
Started Aug 04 05:07:49 PM PDT 24
Finished Aug 04 05:08:30 PM PDT 24
Peak memory 199904 kb
Host smart-05ce5f17-a8f0-46c7-af5e-eeb933435f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900610381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3900610381
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2858925039
Short name T172
Test name
Test status
Simulation time 28970032909 ps
CPU time 22.83 seconds
Started Aug 04 05:12:59 PM PDT 24
Finished Aug 04 05:13:22 PM PDT 24
Peak memory 199952 kb
Host smart-eabb1796-df38-4e7b-9ec9-65391400ec69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858925039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2858925039
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3787581548
Short name T160
Test name
Test status
Simulation time 158640569797 ps
CPU time 14.51 seconds
Started Aug 04 05:09:59 PM PDT 24
Finished Aug 04 05:10:14 PM PDT 24
Peak memory 199808 kb
Host smart-c8a2a3a3-6996-48b7-b9d9-0e61a482b1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787581548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3787581548
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1118154888
Short name T174
Test name
Test status
Simulation time 226195434649 ps
CPU time 71.49 seconds
Started Aug 04 05:11:23 PM PDT 24
Finished Aug 04 05:12:34 PM PDT 24
Peak memory 199760 kb
Host smart-2a7ea6d1-6e7d-4d24-8e63-5e0e7944d4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118154888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1118154888
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1975241075
Short name T164
Test name
Test status
Simulation time 246603599580 ps
CPU time 111.59 seconds
Started Aug 04 05:11:22 PM PDT 24
Finished Aug 04 05:13:13 PM PDT 24
Peak memory 199912 kb
Host smart-baf8cbb5-78fa-4f97-b4e8-06b4b4752f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975241075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1975241075
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.563650156
Short name T181
Test name
Test status
Simulation time 126325411154 ps
CPU time 312.01 seconds
Started Aug 04 05:11:24 PM PDT 24
Finished Aug 04 05:16:36 PM PDT 24
Peak memory 199856 kb
Host smart-f585aca5-c6cc-46b7-b58d-d859ecd41d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563650156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.563650156
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3887744026
Short name T133
Test name
Test status
Simulation time 27115317488 ps
CPU time 44.25 seconds
Started Aug 04 05:11:24 PM PDT 24
Finished Aug 04 05:12:08 PM PDT 24
Peak memory 199872 kb
Host smart-fec7881f-6885-4238-b1a0-fa33a403b397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887744026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3887744026
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_fifo_full.108404025
Short name T414
Test name
Test status
Simulation time 124336322574 ps
CPU time 94 seconds
Started Aug 04 05:07:02 PM PDT 24
Finished Aug 04 05:08:36 PM PDT 24
Peak memory 200080 kb
Host smart-f1de2aa3-3797-4a57-9b28-9966e5bea515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108404025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.108404025
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2094989163
Short name T228
Test name
Test status
Simulation time 44727685751 ps
CPU time 31.53 seconds
Started Aug 04 05:11:24 PM PDT 24
Finished Aug 04 05:11:56 PM PDT 24
Peak memory 199816 kb
Host smart-a0b9f244-40ce-4816-8d77-ebaae35c6877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094989163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2094989163
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1822314641
Short name T210
Test name
Test status
Simulation time 113477847896 ps
CPU time 117.74 seconds
Started Aug 04 05:11:32 PM PDT 24
Finished Aug 04 05:13:30 PM PDT 24
Peak memory 199816 kb
Host smart-161aebdc-f9c7-4f6f-b7cd-3d08267295f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822314641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1822314641
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.3712578250
Short name T192
Test name
Test status
Simulation time 9595359461 ps
CPU time 22.81 seconds
Started Aug 04 05:12:01 PM PDT 24
Finished Aug 04 05:12:24 PM PDT 24
Peak memory 199872 kb
Host smart-68f435b8-3368-4664-8d02-8796cf86527b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712578250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3712578250
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.4004361484
Short name T290
Test name
Test status
Simulation time 231759300663 ps
CPU time 25.91 seconds
Started Aug 04 05:08:20 PM PDT 24
Finished Aug 04 05:08:46 PM PDT 24
Peak memory 199856 kb
Host smart-838449d3-132e-4364-97b2-46aaeb020cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004361484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.4004361484
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.2285448725
Short name T60
Test name
Test status
Simulation time 242678055881 ps
CPU time 580.67 seconds
Started Aug 04 05:10:48 PM PDT 24
Finished Aug 04 05:20:29 PM PDT 24
Peak memory 226692 kb
Host smart-fb3b21a0-197d-48bc-9793-9edeaf0594fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285448725 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2285448725
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.274392010
Short name T177
Test name
Test status
Simulation time 10699904029 ps
CPU time 16.77 seconds
Started Aug 04 05:11:24 PM PDT 24
Finished Aug 04 05:11:41 PM PDT 24
Peak memory 199804 kb
Host smart-f7ef1d34-19ba-429a-a655-94bd67040186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274392010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.274392010
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.341866093
Short name T183
Test name
Test status
Simulation time 11799702056 ps
CPU time 19.94 seconds
Started Aug 04 05:11:27 PM PDT 24
Finished Aug 04 05:11:48 PM PDT 24
Peak memory 199788 kb
Host smart-1df9f762-bd7c-43b3-9e05-1d335e23eac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341866093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.341866093
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_stress_all.2438307163
Short name T232
Test name
Test status
Simulation time 385054944804 ps
CPU time 241.96 seconds
Started Aug 04 05:09:37 PM PDT 24
Finished Aug 04 05:13:39 PM PDT 24
Peak memory 208104 kb
Host smart-a8b191fd-b107-4efe-a606-fff58de66d60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438307163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2438307163
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2158968195
Short name T55
Test name
Test status
Simulation time 202686066493 ps
CPU time 450.37 seconds
Started Aug 04 05:06:06 PM PDT 24
Finished Aug 04 05:13:37 PM PDT 24
Peak memory 216428 kb
Host smart-56e3fd68-cf1d-4323-b53d-e528163c1346
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158968195 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2158968195
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3309134641
Short name T112
Test name
Test status
Simulation time 78225775570 ps
CPU time 81.53 seconds
Started Aug 04 05:11:24 PM PDT 24
Finished Aug 04 05:12:46 PM PDT 24
Peak memory 199788 kb
Host smart-ba2398c7-d63e-4d2f-94a6-a7426172b22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309134641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3309134641
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2884882822
Short name T233
Test name
Test status
Simulation time 42393325085 ps
CPU time 19.1 seconds
Started Aug 04 05:11:22 PM PDT 24
Finished Aug 04 05:11:41 PM PDT 24
Peak memory 199648 kb
Host smart-e6d455eb-e86e-4ba4-b3bd-1f61a106c88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884882822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2884882822
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3443736578
Short name T223
Test name
Test status
Simulation time 116616266818 ps
CPU time 380.76 seconds
Started Aug 04 05:11:23 PM PDT 24
Finished Aug 04 05:17:44 PM PDT 24
Peak memory 199840 kb
Host smart-c8bb2d81-e1f0-4908-be6e-79d6807d086a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443736578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3443736578
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all.3444525549
Short name T189
Test name
Test status
Simulation time 248528883964 ps
CPU time 160.28 seconds
Started Aug 04 05:07:06 PM PDT 24
Finished Aug 04 05:09:47 PM PDT 24
Peak memory 199924 kb
Host smart-d59679b0-547e-476e-9e9c-0a09a53360be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444525549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3444525549
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2997446365
Short name T203
Test name
Test status
Simulation time 56174226564 ps
CPU time 110.3 seconds
Started Aug 04 05:11:25 PM PDT 24
Finished Aug 04 05:13:15 PM PDT 24
Peak memory 199768 kb
Host smart-4ab5b57f-f695-4e7a-9af8-36deee26fb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997446365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2997446365
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3410872200
Short name T218
Test name
Test status
Simulation time 37404954624 ps
CPU time 69.88 seconds
Started Aug 04 05:11:23 PM PDT 24
Finished Aug 04 05:12:33 PM PDT 24
Peak memory 199920 kb
Host smart-f0c954e8-ae48-4bd9-9f00-4a34723437fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410872200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3410872200
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1935227249
Short name T170
Test name
Test status
Simulation time 7838027454 ps
CPU time 7.12 seconds
Started Aug 04 05:11:28 PM PDT 24
Finished Aug 04 05:11:35 PM PDT 24
Peak memory 199620 kb
Host smart-74dc7aad-f20c-4763-83ea-c142c0269cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935227249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1935227249
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2577086450
Short name T976
Test name
Test status
Simulation time 36892711109 ps
CPU time 59.14 seconds
Started Aug 04 05:11:32 PM PDT 24
Finished Aug 04 05:12:32 PM PDT 24
Peak memory 199836 kb
Host smart-a8c81020-a4da-4f26-acc6-e6d8588b70b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577086450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2577086450
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2621316775
Short name T240
Test name
Test status
Simulation time 64240199847 ps
CPU time 24.38 seconds
Started Aug 04 05:11:36 PM PDT 24
Finished Aug 04 05:12:01 PM PDT 24
Peak memory 199820 kb
Host smart-e4d7a5f4-d718-475a-91fd-b20e313c4ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621316775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2621316775
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.754611124
Short name T225
Test name
Test status
Simulation time 49470985254 ps
CPU time 18.9 seconds
Started Aug 04 05:11:39 PM PDT 24
Finished Aug 04 05:11:58 PM PDT 24
Peak memory 199920 kb
Host smart-fde572c8-41bf-4992-a8ca-d5e2582ea883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754611124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.754611124
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2540127020
Short name T219
Test name
Test status
Simulation time 139740796651 ps
CPU time 203.07 seconds
Started Aug 04 05:07:36 PM PDT 24
Finished Aug 04 05:11:00 PM PDT 24
Peak memory 199916 kb
Host smart-679cc0f8-ebf4-487d-b400-133955f5011c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540127020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2540127020
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_full.91051321
Short name T119
Test name
Test status
Simulation time 54915427137 ps
CPU time 57.38 seconds
Started Aug 04 05:07:50 PM PDT 24
Finished Aug 04 05:08:47 PM PDT 24
Peak memory 199824 kb
Host smart-6bf6096d-a97f-4d2c-9109-88743a46c08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91051321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.91051321
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2223908855
Short name T237
Test name
Test status
Simulation time 97784517023 ps
CPU time 132.71 seconds
Started Aug 04 05:12:08 PM PDT 24
Finished Aug 04 05:14:21 PM PDT 24
Peak memory 199852 kb
Host smart-640ad313-999f-49d7-8278-cc0d5d849ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223908855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2223908855
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.4190959025
Short name T226
Test name
Test status
Simulation time 125883026219 ps
CPU time 196.46 seconds
Started Aug 04 05:12:07 PM PDT 24
Finished Aug 04 05:15:24 PM PDT 24
Peak memory 199880 kb
Host smart-a6d5e110-b07b-4357-bf70-a99b2291bbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190959025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.4190959025
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.243484781
Short name T239
Test name
Test status
Simulation time 19806266952 ps
CPU time 15.75 seconds
Started Aug 04 05:12:08 PM PDT 24
Finished Aug 04 05:12:24 PM PDT 24
Peak memory 199808 kb
Host smart-4b418e56-b196-4714-9758-d361719ab85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243484781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.243484781
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1690061929
Short name T213
Test name
Test status
Simulation time 232440046224 ps
CPU time 22.35 seconds
Started Aug 04 05:12:13 PM PDT 24
Finished Aug 04 05:12:35 PM PDT 24
Peak memory 199864 kb
Host smart-bfc6e352-1452-4dc0-8415-d73c2ab407ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690061929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1690061929
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all.324538678
Short name T236
Test name
Test status
Simulation time 1038546219751 ps
CPU time 272.34 seconds
Started Aug 04 05:10:22 PM PDT 24
Finished Aug 04 05:14:54 PM PDT 24
Peak memory 199780 kb
Host smart-ef38887f-d9f4-4052-a44b-92a412e6ea90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324538678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.324538678
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3932051473
Short name T126
Test name
Test status
Simulation time 27520586390 ps
CPU time 27.84 seconds
Started Aug 04 05:10:51 PM PDT 24
Finished Aug 04 05:11:19 PM PDT 24
Peak memory 199800 kb
Host smart-b8206a9f-2808-4e09-b5fb-1b82a1a552bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932051473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3932051473
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.4088343226
Short name T163
Test name
Test status
Simulation time 151183527369 ps
CPU time 482.31 seconds
Started Aug 04 05:06:25 PM PDT 24
Finished Aug 04 05:14:27 PM PDT 24
Peak memory 216428 kb
Host smart-c95d9b43-cde8-4277-9798-5f062c115c7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088343226 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.4088343226
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.4174234385
Short name T235
Test name
Test status
Simulation time 153390380992 ps
CPU time 93.55 seconds
Started Aug 04 05:11:02 PM PDT 24
Finished Aug 04 05:12:36 PM PDT 24
Peak memory 199804 kb
Host smart-816bc50d-f3a0-476c-8751-fa9f2b467b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174234385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.4174234385
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2126820147
Short name T205
Test name
Test status
Simulation time 498095740028 ps
CPU time 1418.71 seconds
Started Aug 04 05:11:10 PM PDT 24
Finished Aug 04 05:34:48 PM PDT 24
Peak memory 232832 kb
Host smart-608e7fc8-57fa-48c9-a0f4-0de34286ee30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126820147 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2126820147
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3250929294
Short name T231
Test name
Test status
Simulation time 36963966772 ps
CPU time 36.37 seconds
Started Aug 04 05:11:06 PM PDT 24
Finished Aug 04 05:11:43 PM PDT 24
Peak memory 199880 kb
Host smart-c66f2900-9b7e-4cbe-9cd5-4eb90f5b6069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250929294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3250929294
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.825478636
Short name T175
Test name
Test status
Simulation time 8600149516 ps
CPU time 20.18 seconds
Started Aug 04 05:11:08 PM PDT 24
Finished Aug 04 05:11:28 PM PDT 24
Peak memory 199832 kb
Host smart-7a1523e3-9c37-4ed9-b9b7-fc60edc02daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825478636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.825478636
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2757374147
Short name T1291
Test name
Test status
Simulation time 43295033 ps
CPU time 0.65 seconds
Started Aug 04 04:25:52 PM PDT 24
Finished Aug 04 04:25:53 PM PDT 24
Peak memory 195192 kb
Host smart-0d4b4ac0-765f-411e-9d9b-181991348175
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757374147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2757374147
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2489046890
Short name T1188
Test name
Test status
Simulation time 3110702377 ps
CPU time 2.34 seconds
Started Aug 04 04:25:46 PM PDT 24
Finished Aug 04 04:25:49 PM PDT 24
Peak memory 198084 kb
Host smart-3c1e910e-1beb-4af4-a921-d65c0a6aaf19
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489046890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2489046890
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2600522372
Short name T65
Test name
Test status
Simulation time 64471119 ps
CPU time 0.63 seconds
Started Aug 04 04:24:12 PM PDT 24
Finished Aug 04 04:24:13 PM PDT 24
Peak memory 195480 kb
Host smart-58045a95-af34-4d9e-b3cc-f65b790886bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600522372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2600522372
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.961275321
Short name T1273
Test name
Test status
Simulation time 62372453 ps
CPU time 0.9 seconds
Started Aug 04 04:25:33 PM PDT 24
Finished Aug 04 04:25:34 PM PDT 24
Peak memory 198528 kb
Host smart-0e824422-5b76-496d-917a-69ece3332270
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961275321 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.961275321
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.4100391485
Short name T1245
Test name
Test status
Simulation time 48469247 ps
CPU time 0.56 seconds
Started Aug 04 04:25:34 PM PDT 24
Finished Aug 04 04:25:35 PM PDT 24
Peak memory 195492 kb
Host smart-c93a06f7-b805-4add-8cd3-6a4ef4705c7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100391485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.4100391485
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1562545440
Short name T1239
Test name
Test status
Simulation time 43470444 ps
CPU time 0.58 seconds
Started Aug 04 04:25:33 PM PDT 24
Finished Aug 04 04:25:34 PM PDT 24
Peak memory 193532 kb
Host smart-50144fae-1ee8-4283-ab92-37d4e4771a23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562545440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1562545440
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2157517131
Short name T1292
Test name
Test status
Simulation time 20541513 ps
CPU time 0.68 seconds
Started Aug 04 04:25:30 PM PDT 24
Finished Aug 04 04:25:31 PM PDT 24
Peak memory 193820 kb
Host smart-47a6a1f0-2200-4c48-9d3d-14fec3dd7e12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157517131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2157517131
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1852170540
Short name T1218
Test name
Test status
Simulation time 177142382 ps
CPU time 1.29 seconds
Started Aug 04 04:25:47 PM PDT 24
Finished Aug 04 04:25:49 PM PDT 24
Peak memory 200228 kb
Host smart-25610599-f6dc-47f9-afbe-cb53a7efe25b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852170540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1852170540
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1102693288
Short name T1223
Test name
Test status
Simulation time 33428617 ps
CPU time 0.7 seconds
Started Aug 04 04:24:21 PM PDT 24
Finished Aug 04 04:24:22 PM PDT 24
Peak memory 195332 kb
Host smart-99342b3d-e3bc-4864-b755-37e6d10828d9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102693288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1102693288
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3181406998
Short name T1243
Test name
Test status
Simulation time 93872638 ps
CPU time 1.52 seconds
Started Aug 04 04:25:33 PM PDT 24
Finished Aug 04 04:25:35 PM PDT 24
Peak memory 196236 kb
Host smart-5841785c-586d-4c2f-8991-36992fe7eae8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181406998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3181406998
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1748035920
Short name T1179
Test name
Test status
Simulation time 42286248 ps
CPU time 0.58 seconds
Started Aug 04 04:24:23 PM PDT 24
Finished Aug 04 04:24:23 PM PDT 24
Peak memory 195636 kb
Host smart-1efee4c4-c72f-4019-ae42-8fe1db2ce593
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748035920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1748035920
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.698004808
Short name T1264
Test name
Test status
Simulation time 81538812 ps
CPU time 0.69 seconds
Started Aug 04 04:25:31 PM PDT 24
Finished Aug 04 04:25:31 PM PDT 24
Peak memory 198032 kb
Host smart-7374adca-cdb4-4a04-8ce4-83a45886101a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698004808 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.698004808
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.762655584
Short name T73
Test name
Test status
Simulation time 19804518 ps
CPU time 0.64 seconds
Started Aug 04 04:24:21 PM PDT 24
Finished Aug 04 04:24:22 PM PDT 24
Peak memory 195752 kb
Host smart-d92c59f3-ed6a-42d4-a58b-d902d5d576bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762655584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.762655584
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1707843815
Short name T1238
Test name
Test status
Simulation time 33615788 ps
CPU time 0.57 seconds
Started Aug 04 04:25:45 PM PDT 24
Finished Aug 04 04:25:46 PM PDT 24
Peak memory 194328 kb
Host smart-6e2a112c-97bf-48bc-a7cc-90c2ac08c8ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707843815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1707843815
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3502417165
Short name T1286
Test name
Test status
Simulation time 75967537 ps
CPU time 0.75 seconds
Started Aug 04 04:24:21 PM PDT 24
Finished Aug 04 04:24:22 PM PDT 24
Peak memory 194824 kb
Host smart-6c1f7689-e507-4713-8f5d-0a5da856214c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502417165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3502417165
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3213645377
Short name T1189
Test name
Test status
Simulation time 128629354 ps
CPU time 1.12 seconds
Started Aug 04 04:25:33 PM PDT 24
Finished Aug 04 04:25:35 PM PDT 24
Peak memory 198632 kb
Host smart-2409e4f7-db74-4127-abd1-9fb25f4f7add
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213645377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3213645377
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2546137683
Short name T1221
Test name
Test status
Simulation time 148235888 ps
CPU time 0.9 seconds
Started Aug 04 04:25:45 PM PDT 24
Finished Aug 04 04:25:46 PM PDT 24
Peak memory 198864 kb
Host smart-16ac8c45-aeeb-4f49-b0b2-c24b4ea11f69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546137683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2546137683
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3189968871
Short name T1249
Test name
Test status
Simulation time 23445884 ps
CPU time 0.77 seconds
Started Aug 04 04:24:52 PM PDT 24
Finished Aug 04 04:24:53 PM PDT 24
Peak memory 199788 kb
Host smart-e3d60430-e6be-4838-af1b-01834b379440
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189968871 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3189968871
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3024705555
Short name T82
Test name
Test status
Simulation time 15798898 ps
CPU time 0.58 seconds
Started Aug 04 04:24:40 PM PDT 24
Finished Aug 04 04:24:40 PM PDT 24
Peak memory 195700 kb
Host smart-50ac176c-97ba-46b8-a485-4fd6c5154f7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024705555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3024705555
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.1240965688
Short name T1233
Test name
Test status
Simulation time 12168009 ps
CPU time 0.66 seconds
Started Aug 04 04:24:43 PM PDT 24
Finished Aug 04 04:24:44 PM PDT 24
Peak memory 194556 kb
Host smart-bbe091ec-8160-413a-93df-5917e6086741
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240965688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1240965688
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.988011820
Short name T1259
Test name
Test status
Simulation time 118779895 ps
CPU time 0.72 seconds
Started Aug 04 04:24:40 PM PDT 24
Finished Aug 04 04:24:41 PM PDT 24
Peak memory 197056 kb
Host smart-d67538ed-7203-4f7b-845b-e8617751eadb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988011820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.988011820
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2122903405
Short name T1180
Test name
Test status
Simulation time 92111962 ps
CPU time 1.33 seconds
Started Aug 04 04:24:37 PM PDT 24
Finished Aug 04 04:24:39 PM PDT 24
Peak memory 200284 kb
Host smart-4e4ed083-aa6c-48bb-80e7-d3d88cbaf2b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122903405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2122903405
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1217278343
Short name T1311
Test name
Test status
Simulation time 67255810 ps
CPU time 1.34 seconds
Started Aug 04 04:24:46 PM PDT 24
Finished Aug 04 04:24:47 PM PDT 24
Peak memory 199480 kb
Host smart-b73cd4e3-cbee-4f3e-90ca-01533009a4ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217278343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1217278343
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2656844010
Short name T1275
Test name
Test status
Simulation time 86258180 ps
CPU time 0.76 seconds
Started Aug 04 04:24:52 PM PDT 24
Finished Aug 04 04:24:53 PM PDT 24
Peak memory 198392 kb
Host smart-f1232f55-cbdf-41f8-9430-122010373f39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656844010 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2656844010
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3626421159
Short name T81
Test name
Test status
Simulation time 38004880 ps
CPU time 0.58 seconds
Started Aug 04 04:24:46 PM PDT 24
Finished Aug 04 04:24:47 PM PDT 24
Peak memory 195600 kb
Host smart-e41b4a90-ae88-4217-9cde-263022d3f7c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626421159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3626421159
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2565003660
Short name T1215
Test name
Test status
Simulation time 32510917 ps
CPU time 0.62 seconds
Started Aug 04 04:24:41 PM PDT 24
Finished Aug 04 04:24:42 PM PDT 24
Peak memory 194628 kb
Host smart-6d35df88-7c7c-4a4f-ab5b-a01c6030f0d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565003660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2565003660
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1768588510
Short name T1206
Test name
Test status
Simulation time 50378067 ps
CPU time 0.74 seconds
Started Aug 04 04:24:53 PM PDT 24
Finished Aug 04 04:24:54 PM PDT 24
Peak memory 196956 kb
Host smart-17f40855-b8d2-455b-ad8c-41205b76a830
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768588510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1768588510
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3613832110
Short name T1294
Test name
Test status
Simulation time 67903129 ps
CPU time 1.01 seconds
Started Aug 04 04:24:51 PM PDT 24
Finished Aug 04 04:24:52 PM PDT 24
Peak memory 200228 kb
Host smart-53c93f25-6087-46e2-ba7f-4ec5a1907dff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613832110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3613832110
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2669829392
Short name T1184
Test name
Test status
Simulation time 35980214 ps
CPU time 1.03 seconds
Started Aug 04 04:25:02 PM PDT 24
Finished Aug 04 04:25:03 PM PDT 24
Peak memory 200040 kb
Host smart-1f9ff867-4c35-42e2-88ab-2bc9a1303901
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669829392 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2669829392
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.4103692706
Short name T1306
Test name
Test status
Simulation time 52960266 ps
CPU time 0.62 seconds
Started Aug 04 04:24:53 PM PDT 24
Finished Aug 04 04:24:53 PM PDT 24
Peak memory 195692 kb
Host smart-9dd1e8c1-8b3b-410a-b0df-d32182008d46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103692706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.4103692706
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2971363879
Short name T1281
Test name
Test status
Simulation time 115463883 ps
CPU time 0.59 seconds
Started Aug 04 04:25:02 PM PDT 24
Finished Aug 04 04:25:03 PM PDT 24
Peak memory 194692 kb
Host smart-68f3a5aa-808e-48d1-bf73-42ed75fcf3e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971363879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2971363879
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.491007946
Short name T1255
Test name
Test status
Simulation time 23827157 ps
CPU time 0.74 seconds
Started Aug 04 04:24:55 PM PDT 24
Finished Aug 04 04:24:56 PM PDT 24
Peak memory 196020 kb
Host smart-7c4b7a16-7d5c-4ab2-85e3-5c6ea729e22b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491007946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr
_outstanding.491007946
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.329973597
Short name T1199
Test name
Test status
Simulation time 72044934 ps
CPU time 1.62 seconds
Started Aug 04 04:24:54 PM PDT 24
Finished Aug 04 04:24:56 PM PDT 24
Peak memory 200176 kb
Host smart-f515cece-cccd-4242-941c-e493e00a590a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329973597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.329973597
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3270121402
Short name T1251
Test name
Test status
Simulation time 155879205 ps
CPU time 0.97 seconds
Started Aug 04 04:24:42 PM PDT 24
Finished Aug 04 04:24:43 PM PDT 24
Peak memory 199396 kb
Host smart-8d5d75db-fa05-4175-9c99-3d3f02f4be3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270121402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3270121402
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.236766312
Short name T1197
Test name
Test status
Simulation time 17902969 ps
CPU time 0.7 seconds
Started Aug 04 04:24:51 PM PDT 24
Finished Aug 04 04:24:52 PM PDT 24
Peak memory 198040 kb
Host smart-4a62eb95-7f21-4fb7-af03-80b3dd2191fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236766312 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.236766312
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.4060366227
Short name T1204
Test name
Test status
Simulation time 14644465 ps
CPU time 0.59 seconds
Started Aug 04 04:25:09 PM PDT 24
Finished Aug 04 04:25:10 PM PDT 24
Peak memory 195576 kb
Host smart-d3e09e6a-d2d9-4453-8f27-e47f3ab7727c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060366227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.4060366227
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2555228387
Short name T1250
Test name
Test status
Simulation time 18938609 ps
CPU time 0.59 seconds
Started Aug 04 04:25:05 PM PDT 24
Finished Aug 04 04:25:05 PM PDT 24
Peak memory 194600 kb
Host smart-688a9e8b-f6c6-4d08-8c2b-ca9352ed93db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555228387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2555228387
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2977273663
Short name T1313
Test name
Test status
Simulation time 64417826 ps
CPU time 0.66 seconds
Started Aug 04 04:25:01 PM PDT 24
Finished Aug 04 04:25:02 PM PDT 24
Peak memory 195844 kb
Host smart-5986a956-a873-4340-9052-1a8d6d33e8d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977273663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2977273663
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3022481834
Short name T1225
Test name
Test status
Simulation time 37173485 ps
CPU time 1.83 seconds
Started Aug 04 04:24:53 PM PDT 24
Finished Aug 04 04:24:55 PM PDT 24
Peak memory 200304 kb
Host smart-50da5517-89b3-47b5-93fe-81c56f09c396
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022481834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3022481834
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3321467984
Short name T88
Test name
Test status
Simulation time 136626274 ps
CPU time 0.96 seconds
Started Aug 04 04:25:11 PM PDT 24
Finished Aug 04 04:25:12 PM PDT 24
Peak memory 199140 kb
Host smart-bbb910d4-646a-443e-b5bf-e2f68279955a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321467984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3321467984
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2937274453
Short name T1234
Test name
Test status
Simulation time 101592807 ps
CPU time 0.87 seconds
Started Aug 04 04:25:02 PM PDT 24
Finished Aug 04 04:25:03 PM PDT 24
Peak memory 200036 kb
Host smart-cf85bf1b-7199-43c4-8eea-9c7606ed01de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937274453 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2937274453
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2145392986
Short name T69
Test name
Test status
Simulation time 27457705 ps
CPU time 0.62 seconds
Started Aug 04 04:24:55 PM PDT 24
Finished Aug 04 04:24:56 PM PDT 24
Peak memory 195576 kb
Host smart-5b0508d6-4caf-4194-a387-bf6eb0e45346
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145392986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2145392986
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2106198857
Short name T1296
Test name
Test status
Simulation time 15417236 ps
CPU time 0.59 seconds
Started Aug 04 04:25:06 PM PDT 24
Finished Aug 04 04:25:07 PM PDT 24
Peak memory 194572 kb
Host smart-83b34454-9438-45f1-88f1-7d92fa4903ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106198857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2106198857
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3619964589
Short name T1213
Test name
Test status
Simulation time 39271159 ps
CPU time 0.69 seconds
Started Aug 04 04:25:03 PM PDT 24
Finished Aug 04 04:25:04 PM PDT 24
Peak memory 196748 kb
Host smart-13943d9e-77c9-4d1a-9b4a-a7b5f1fd4842
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619964589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3619964589
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.980015588
Short name T1196
Test name
Test status
Simulation time 271582414 ps
CPU time 2.19 seconds
Started Aug 04 04:25:05 PM PDT 24
Finished Aug 04 04:25:07 PM PDT 24
Peak memory 200244 kb
Host smart-c1fe6136-87a8-4882-b3ef-ed3f30a6e9fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980015588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.980015588
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.945215127
Short name T87
Test name
Test status
Simulation time 152557868 ps
CPU time 1.23 seconds
Started Aug 04 04:24:52 PM PDT 24
Finished Aug 04 04:24:53 PM PDT 24
Peak memory 199528 kb
Host smart-313741ce-1a97-4670-8dd2-bd625d0cb3cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945215127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.945215127
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2341534432
Short name T1252
Test name
Test status
Simulation time 72143856 ps
CPU time 0.74 seconds
Started Aug 04 04:24:52 PM PDT 24
Finished Aug 04 04:24:53 PM PDT 24
Peak memory 199028 kb
Host smart-d60ec512-9021-4d54-8921-0c378efa5db4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341534432 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2341534432
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.922802729
Short name T1280
Test name
Test status
Simulation time 135518338 ps
CPU time 0.57 seconds
Started Aug 04 04:25:02 PM PDT 24
Finished Aug 04 04:25:03 PM PDT 24
Peak memory 194596 kb
Host smart-a68d6325-ca34-4319-8bdb-b945d29c683d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922802729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.922802729
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2653355925
Short name T1266
Test name
Test status
Simulation time 89499136 ps
CPU time 0.72 seconds
Started Aug 04 04:25:04 PM PDT 24
Finished Aug 04 04:25:05 PM PDT 24
Peak memory 197080 kb
Host smart-6181fb05-0fbd-4f64-8cac-16742b256523
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653355925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2653355925
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1323281330
Short name T1288
Test name
Test status
Simulation time 666134516 ps
CPU time 2.34 seconds
Started Aug 04 04:24:53 PM PDT 24
Finished Aug 04 04:24:56 PM PDT 24
Peak memory 200300 kb
Host smart-6429ca16-8d53-43b4-be23-26d9e143a4cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323281330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1323281330
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2197167614
Short name T1272
Test name
Test status
Simulation time 262716942 ps
CPU time 1.29 seconds
Started Aug 04 04:24:57 PM PDT 24
Finished Aug 04 04:24:58 PM PDT 24
Peak memory 199468 kb
Host smart-a8e5c6ce-b2dd-4798-8764-85423a25d57b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197167614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2197167614
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3956193376
Short name T1190
Test name
Test status
Simulation time 27185321 ps
CPU time 0.83 seconds
Started Aug 04 04:24:52 PM PDT 24
Finished Aug 04 04:24:54 PM PDT 24
Peak memory 199000 kb
Host smart-52160b2b-8e1a-495c-ba26-79319f6bea14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956193376 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3956193376
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3106674682
Short name T74
Test name
Test status
Simulation time 15302215 ps
CPU time 0.63 seconds
Started Aug 04 04:25:02 PM PDT 24
Finished Aug 04 04:25:03 PM PDT 24
Peak memory 195888 kb
Host smart-cbae9e50-9693-48aa-b884-c6f20fc603d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106674682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3106674682
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2337836364
Short name T1300
Test name
Test status
Simulation time 38141740 ps
CPU time 0.55 seconds
Started Aug 04 04:25:01 PM PDT 24
Finished Aug 04 04:25:01 PM PDT 24
Peak memory 194604 kb
Host smart-7312ea67-45d7-4592-af35-4beb0dfc5a11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337836364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2337836364
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.407118539
Short name T1283
Test name
Test status
Simulation time 18042331 ps
CPU time 0.79 seconds
Started Aug 04 04:24:59 PM PDT 24
Finished Aug 04 04:25:00 PM PDT 24
Peak memory 196288 kb
Host smart-8843e9b0-72c3-44d5-9b97-eafce8839850
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407118539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.407118539
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3606938812
Short name T1267
Test name
Test status
Simulation time 204534979 ps
CPU time 1.34 seconds
Started Aug 04 04:25:02 PM PDT 24
Finished Aug 04 04:25:03 PM PDT 24
Peak memory 200308 kb
Host smart-adfdba85-9081-4bc3-9da9-668c170ca792
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606938812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3606938812
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.153945284
Short name T1235
Test name
Test status
Simulation time 68323696 ps
CPU time 0.67 seconds
Started Aug 04 04:25:05 PM PDT 24
Finished Aug 04 04:25:06 PM PDT 24
Peak memory 198204 kb
Host smart-6cfa209c-2a1e-47f6-8f95-9823e6515926
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153945284 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.153945284
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3903380875
Short name T1268
Test name
Test status
Simulation time 14463161 ps
CPU time 0.6 seconds
Started Aug 04 04:24:51 PM PDT 24
Finished Aug 04 04:24:52 PM PDT 24
Peak memory 196008 kb
Host smart-145daa90-614a-49f2-8010-e6141cb93ac5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903380875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3903380875
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.145907578
Short name T1195
Test name
Test status
Simulation time 39683619 ps
CPU time 0.59 seconds
Started Aug 04 04:24:58 PM PDT 24
Finished Aug 04 04:24:59 PM PDT 24
Peak memory 194604 kb
Host smart-ff189d15-f26e-440d-bd5f-dbb07d014ce3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145907578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.145907578
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2293752083
Short name T78
Test name
Test status
Simulation time 51488865 ps
CPU time 0.73 seconds
Started Aug 04 04:25:03 PM PDT 24
Finished Aug 04 04:25:04 PM PDT 24
Peak memory 197196 kb
Host smart-b4093a54-136b-435f-804c-dd5ec245bfff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293752083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2293752083
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2904331262
Short name T1278
Test name
Test status
Simulation time 462157433 ps
CPU time 2.18 seconds
Started Aug 04 04:24:48 PM PDT 24
Finished Aug 04 04:24:51 PM PDT 24
Peak memory 200296 kb
Host smart-e27baac4-8835-42b4-a2e6-48dc2ce5b4b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904331262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2904331262
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.725310159
Short name T1287
Test name
Test status
Simulation time 187003259 ps
CPU time 0.93 seconds
Started Aug 04 04:24:59 PM PDT 24
Finished Aug 04 04:25:00 PM PDT 24
Peak memory 199244 kb
Host smart-d3748709-63e3-47a3-bd06-11d62e5640db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725310159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.725310159
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2853908035
Short name T1226
Test name
Test status
Simulation time 84916006 ps
CPU time 1 seconds
Started Aug 04 04:24:58 PM PDT 24
Finished Aug 04 04:24:59 PM PDT 24
Peak memory 200084 kb
Host smart-aaf016a4-0cc3-4b25-b53f-7a2202012ff3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853908035 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2853908035
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3432706985
Short name T1224
Test name
Test status
Simulation time 15560896 ps
CPU time 0.63 seconds
Started Aug 04 04:25:01 PM PDT 24
Finished Aug 04 04:25:01 PM PDT 24
Peak memory 195712 kb
Host smart-ae91c0fe-1a54-467f-822b-671c1b857618
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432706985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3432706985
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3537608683
Short name T1185
Test name
Test status
Simulation time 35394765 ps
CPU time 0.51 seconds
Started Aug 04 04:24:57 PM PDT 24
Finished Aug 04 04:24:58 PM PDT 24
Peak memory 194584 kb
Host smart-12c307e2-9cad-4880-b954-e4b591328601
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537608683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3537608683
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3978225264
Short name T76
Test name
Test status
Simulation time 77242413 ps
CPU time 0.65 seconds
Started Aug 04 04:24:56 PM PDT 24
Finished Aug 04 04:24:57 PM PDT 24
Peak memory 196072 kb
Host smart-fe8e09df-d852-466b-aa14-ded9f09c0d61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978225264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3978225264
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2378459567
Short name T1284
Test name
Test status
Simulation time 402062358 ps
CPU time 1.94 seconds
Started Aug 04 04:25:35 PM PDT 24
Finished Aug 04 04:25:37 PM PDT 24
Peak memory 200184 kb
Host smart-e782f3f0-c6da-4697-9d48-b4eb1db11065
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378459567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2378459567
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.486279018
Short name T93
Test name
Test status
Simulation time 216356588 ps
CPU time 0.85 seconds
Started Aug 04 04:24:57 PM PDT 24
Finished Aug 04 04:24:58 PM PDT 24
Peak memory 199236 kb
Host smart-5c6a96d9-0936-4bef-93a1-4694b80523c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486279018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.486279018
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2106912302
Short name T1290
Test name
Test status
Simulation time 53513349 ps
CPU time 0.83 seconds
Started Aug 04 04:25:57 PM PDT 24
Finished Aug 04 04:25:58 PM PDT 24
Peak memory 200004 kb
Host smart-6989bfef-ec9a-46e5-81da-3920958fa5c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106912302 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2106912302
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1325688776
Short name T1257
Test name
Test status
Simulation time 16514702 ps
CPU time 0.65 seconds
Started Aug 04 04:25:03 PM PDT 24
Finished Aug 04 04:25:03 PM PDT 24
Peak memory 195716 kb
Host smart-61b5a5f8-0b3a-4b0d-8478-62a804c588af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325688776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1325688776
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2943979449
Short name T1261
Test name
Test status
Simulation time 15368493 ps
CPU time 0.57 seconds
Started Aug 04 04:24:57 PM PDT 24
Finished Aug 04 04:24:58 PM PDT 24
Peak memory 194528 kb
Host smart-d272ec3a-9cfc-493d-90f4-f7d2a1ae5366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943979449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2943979449
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2131905423
Short name T80
Test name
Test status
Simulation time 90245340 ps
CPU time 0.62 seconds
Started Aug 04 04:24:57 PM PDT 24
Finished Aug 04 04:24:58 PM PDT 24
Peak memory 195104 kb
Host smart-59732c0a-1400-41df-ba47-782e12fca4bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131905423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2131905423
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3755828298
Short name T1232
Test name
Test status
Simulation time 58320117 ps
CPU time 1.41 seconds
Started Aug 04 04:25:07 PM PDT 24
Finished Aug 04 04:25:09 PM PDT 24
Peak memory 200248 kb
Host smart-edfe3ade-7a7a-47fc-ae28-52ad4cdcb375
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755828298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3755828298
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3710579725
Short name T91
Test name
Test status
Simulation time 277488082 ps
CPU time 1.2 seconds
Started Aug 04 04:24:57 PM PDT 24
Finished Aug 04 04:24:58 PM PDT 24
Peak memory 199656 kb
Host smart-3c0589e2-d0d1-4657-a313-fd61271f5019
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710579725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3710579725
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.531714388
Short name T1212
Test name
Test status
Simulation time 25979568 ps
CPU time 0.75 seconds
Started Aug 04 04:25:56 PM PDT 24
Finished Aug 04 04:25:57 PM PDT 24
Peak memory 196952 kb
Host smart-04373409-41de-4718-89d0-de5b50842cf0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531714388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.531714388
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1946667311
Short name T1258
Test name
Test status
Simulation time 707925488 ps
CPU time 2.41 seconds
Started Aug 04 04:25:56 PM PDT 24
Finished Aug 04 04:25:59 PM PDT 24
Peak memory 197952 kb
Host smart-b55545cd-b8f5-4cb0-9be7-5588fceed0f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946667311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1946667311
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3317620476
Short name T1220
Test name
Test status
Simulation time 58887079 ps
CPU time 0.64 seconds
Started Aug 04 04:24:27 PM PDT 24
Finished Aug 04 04:24:28 PM PDT 24
Peak memory 195668 kb
Host smart-1f7eb85c-e7f4-49a2-a020-5f9753d67d5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317620476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3317620476
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1534849219
Short name T1202
Test name
Test status
Simulation time 93173583 ps
CPU time 0.76 seconds
Started Aug 04 04:25:36 PM PDT 24
Finished Aug 04 04:25:37 PM PDT 24
Peak memory 198464 kb
Host smart-4f523cdd-419b-42e0-a528-f61dcdd39657
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534849219 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1534849219
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1216163728
Short name T1253
Test name
Test status
Simulation time 14988187 ps
CPU time 0.58 seconds
Started Aug 04 04:25:56 PM PDT 24
Finished Aug 04 04:25:57 PM PDT 24
Peak memory 195656 kb
Host smart-34b44881-a1cb-4265-bc31-bc3c63f56d52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216163728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1216163728
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.457484566
Short name T1289
Test name
Test status
Simulation time 11614796 ps
CPU time 0.56 seconds
Started Aug 04 04:25:51 PM PDT 24
Finished Aug 04 04:25:52 PM PDT 24
Peak memory 194516 kb
Host smart-eba254e0-acf1-4564-911b-e6ccaaa2491b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457484566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.457484566
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2565255584
Short name T1230
Test name
Test status
Simulation time 164106231 ps
CPU time 0.62 seconds
Started Aug 04 04:25:52 PM PDT 24
Finished Aug 04 04:25:52 PM PDT 24
Peak memory 195636 kb
Host smart-4109cb02-4110-48e2-96a6-27feb0197147
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565255584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2565255584
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.1641242984
Short name T1193
Test name
Test status
Simulation time 22326751 ps
CPU time 1.14 seconds
Started Aug 04 04:25:52 PM PDT 24
Finished Aug 04 04:25:54 PM PDT 24
Peak memory 200184 kb
Host smart-e4c9dd8c-dfee-4f75-bf4d-d0d972ff2ec7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641242984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.1641242984
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1737835099
Short name T1211
Test name
Test status
Simulation time 314038089 ps
CPU time 1.27 seconds
Started Aug 04 04:25:58 PM PDT 24
Finished Aug 04 04:26:00 PM PDT 24
Peak memory 199668 kb
Host smart-59bb12f1-0ef1-4044-a069-6f4135408f01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737835099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1737835099
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1489931376
Short name T1203
Test name
Test status
Simulation time 43727206 ps
CPU time 0.64 seconds
Started Aug 04 04:25:03 PM PDT 24
Finished Aug 04 04:25:03 PM PDT 24
Peak memory 194568 kb
Host smart-0f5d4c8b-357f-4954-a3ce-58c79df64e45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489931376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1489931376
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1967212222
Short name T1208
Test name
Test status
Simulation time 30336553 ps
CPU time 0.59 seconds
Started Aug 04 04:25:04 PM PDT 24
Finished Aug 04 04:25:05 PM PDT 24
Peak memory 194568 kb
Host smart-695246f2-95df-409d-ae24-be4df490cd98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967212222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1967212222
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2219211986
Short name T1187
Test name
Test status
Simulation time 23554279 ps
CPU time 0.61 seconds
Started Aug 04 04:25:44 PM PDT 24
Finished Aug 04 04:25:45 PM PDT 24
Peak memory 194596 kb
Host smart-e9c3a2e2-d29b-4334-bac9-5a0c15e130ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219211986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2219211986
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3850924167
Short name T1262
Test name
Test status
Simulation time 32405125 ps
CPU time 0.59 seconds
Started Aug 04 04:25:30 PM PDT 24
Finished Aug 04 04:25:31 PM PDT 24
Peak memory 194636 kb
Host smart-23099d28-24e0-4088-ac31-7f9227766e7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850924167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3850924167
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2145289508
Short name T1198
Test name
Test status
Simulation time 25865226 ps
CPU time 0.6 seconds
Started Aug 04 04:25:01 PM PDT 24
Finished Aug 04 04:25:02 PM PDT 24
Peak memory 194660 kb
Host smart-c3103e79-2c3d-4896-a2b6-d0e2d8594f59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145289508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2145289508
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1990174583
Short name T1210
Test name
Test status
Simulation time 29711811 ps
CPU time 0.6 seconds
Started Aug 04 04:25:05 PM PDT 24
Finished Aug 04 04:25:05 PM PDT 24
Peak memory 194564 kb
Host smart-cef510f1-4b4c-48f4-9b7f-7990efbbfb9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990174583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1990174583
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2285212264
Short name T1295
Test name
Test status
Simulation time 67418627 ps
CPU time 0.6 seconds
Started Aug 04 04:25:35 PM PDT 24
Finished Aug 04 04:25:35 PM PDT 24
Peak memory 194604 kb
Host smart-8ed6a12c-4337-4c65-b8a9-1a52fadf4ec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285212264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2285212264
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1393576494
Short name T1304
Test name
Test status
Simulation time 12291224 ps
CPU time 0.57 seconds
Started Aug 04 04:25:02 PM PDT 24
Finished Aug 04 04:25:03 PM PDT 24
Peak memory 194920 kb
Host smart-70b331ee-70b5-43f6-9dfd-f0134c51cf9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393576494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1393576494
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2552772560
Short name T1194
Test name
Test status
Simulation time 135271184 ps
CPU time 0.58 seconds
Started Aug 04 04:25:02 PM PDT 24
Finished Aug 04 04:25:03 PM PDT 24
Peak memory 194604 kb
Host smart-43d9df84-70d1-4cb6-8905-cf04cff0cf90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552772560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2552772560
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3539720590
Short name T1265
Test name
Test status
Simulation time 14933597 ps
CPU time 0.57 seconds
Started Aug 04 04:24:56 PM PDT 24
Finished Aug 04 04:24:57 PM PDT 24
Peak memory 194984 kb
Host smart-a1efa112-d1cf-4016-8e18-bc658df3085d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539720590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3539720590
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.265705971
Short name T1310
Test name
Test status
Simulation time 93865887 ps
CPU time 0.81 seconds
Started Aug 04 04:24:36 PM PDT 24
Finished Aug 04 04:24:37 PM PDT 24
Peak memory 196420 kb
Host smart-42316293-3cbc-43de-9407-c534ca1caefd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265705971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.265705971
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1678866051
Short name T64
Test name
Test status
Simulation time 115635827 ps
CPU time 2.25 seconds
Started Aug 04 04:24:37 PM PDT 24
Finished Aug 04 04:24:39 PM PDT 24
Peak memory 197472 kb
Host smart-e70e035f-17a9-4dc7-a425-55f9a9dbbdfc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678866051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1678866051
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.654201782
Short name T66
Test name
Test status
Simulation time 17603127 ps
CPU time 0.62 seconds
Started Aug 04 04:24:35 PM PDT 24
Finished Aug 04 04:24:36 PM PDT 24
Peak memory 195664 kb
Host smart-ca50474a-b89d-4aaf-bf57-250b41702b01
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654201782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.654201782
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1603449158
Short name T1214
Test name
Test status
Simulation time 111221861 ps
CPU time 1.55 seconds
Started Aug 04 04:24:37 PM PDT 24
Finished Aug 04 04:24:38 PM PDT 24
Peak memory 200336 kb
Host smart-185fb669-1330-4550-b08c-5523a0c05adf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603449158 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1603449158
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3739724091
Short name T83
Test name
Test status
Simulation time 30404172 ps
CPU time 0.58 seconds
Started Aug 04 04:24:38 PM PDT 24
Finished Aug 04 04:24:39 PM PDT 24
Peak memory 195644 kb
Host smart-e054152a-6b52-474c-be27-2c9db6d9a169
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739724091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3739724091
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3406304910
Short name T1201
Test name
Test status
Simulation time 54928181 ps
CPU time 0.56 seconds
Started Aug 04 04:25:56 PM PDT 24
Finished Aug 04 04:25:57 PM PDT 24
Peak memory 194564 kb
Host smart-10b0ccb4-9414-42bf-951f-7f2bbf36c20b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406304910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3406304910
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3315381829
Short name T75
Test name
Test status
Simulation time 29877623 ps
CPU time 0.77 seconds
Started Aug 04 04:25:41 PM PDT 24
Finished Aug 04 04:25:42 PM PDT 24
Peak memory 194560 kb
Host smart-99481851-233c-4998-b045-d4769d66f4d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315381829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3315381829
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3813223553
Short name T1191
Test name
Test status
Simulation time 94932223 ps
CPU time 1.19 seconds
Started Aug 04 04:25:36 PM PDT 24
Finished Aug 04 04:25:38 PM PDT 24
Peak memory 199256 kb
Host smart-ab6273bd-9ee3-46b8-a11b-f0fe6248be85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813223553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3813223553
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3132413269
Short name T1298
Test name
Test status
Simulation time 77850722 ps
CPU time 1.2 seconds
Started Aug 04 04:25:56 PM PDT 24
Finished Aug 04 04:25:58 PM PDT 24
Peak memory 199544 kb
Host smart-3563eddf-b363-4be1-aef2-ba2d27896044
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132413269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3132413269
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1352308881
Short name T1219
Test name
Test status
Simulation time 12276144 ps
CPU time 0.57 seconds
Started Aug 04 04:25:08 PM PDT 24
Finished Aug 04 04:25:08 PM PDT 24
Peak memory 194532 kb
Host smart-bf7f46b0-b70b-47ca-807a-e103984ab532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352308881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1352308881
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3053289983
Short name T1276
Test name
Test status
Simulation time 53121837 ps
CPU time 0.58 seconds
Started Aug 04 04:25:51 PM PDT 24
Finished Aug 04 04:25:52 PM PDT 24
Peak memory 194596 kb
Host smart-5e224f4d-fbd7-432e-ae39-13ddfbd54990
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053289983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3053289983
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1578490806
Short name T1279
Test name
Test status
Simulation time 16515209 ps
CPU time 0.53 seconds
Started Aug 04 04:24:52 PM PDT 24
Finished Aug 04 04:24:53 PM PDT 24
Peak memory 194516 kb
Host smart-d0647601-5855-47cc-8418-78d09be1af8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578490806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1578490806
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2246081171
Short name T1269
Test name
Test status
Simulation time 24427147 ps
CPU time 0.61 seconds
Started Aug 04 04:25:31 PM PDT 24
Finished Aug 04 04:25:31 PM PDT 24
Peak memory 194684 kb
Host smart-2fe38346-82af-460f-a0be-f73b513ddaba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246081171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2246081171
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.4190588656
Short name T1241
Test name
Test status
Simulation time 11900720 ps
CPU time 0.58 seconds
Started Aug 04 04:25:03 PM PDT 24
Finished Aug 04 04:25:04 PM PDT 24
Peak memory 194568 kb
Host smart-9a23f086-79a7-4ce7-aa31-35cf9cf1f593
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190588656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.4190588656
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3484707173
Short name T1181
Test name
Test status
Simulation time 28605658 ps
CPU time 0.59 seconds
Started Aug 04 04:25:01 PM PDT 24
Finished Aug 04 04:25:02 PM PDT 24
Peak memory 194992 kb
Host smart-da83855a-4280-42e5-88f1-ca59b1c7453b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484707173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3484707173
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3361579675
Short name T1227
Test name
Test status
Simulation time 18213032 ps
CPU time 0.58 seconds
Started Aug 04 04:25:01 PM PDT 24
Finished Aug 04 04:25:01 PM PDT 24
Peak memory 194532 kb
Host smart-d6ee291a-aa28-43d9-9def-273036ee2881
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361579675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3361579675
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1233329930
Short name T1293
Test name
Test status
Simulation time 16957053 ps
CPU time 0.57 seconds
Started Aug 04 04:24:57 PM PDT 24
Finished Aug 04 04:24:58 PM PDT 24
Peak memory 194544 kb
Host smart-1e7764a3-87bc-4f17-b3e5-55b87a9706d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233329930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1233329930
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1339436226
Short name T1312
Test name
Test status
Simulation time 137553723 ps
CPU time 0.61 seconds
Started Aug 04 04:24:57 PM PDT 24
Finished Aug 04 04:24:57 PM PDT 24
Peak memory 194652 kb
Host smart-37f05a3b-5b1c-47be-a7a5-eb34e68e1349
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339436226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1339436226
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3017442103
Short name T1236
Test name
Test status
Simulation time 50329714 ps
CPU time 0.59 seconds
Started Aug 04 04:25:10 PM PDT 24
Finished Aug 04 04:25:11 PM PDT 24
Peak memory 194600 kb
Host smart-8363b378-098a-457c-b1ab-5fea84fa85a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017442103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3017442103
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2511360331
Short name T68
Test name
Test status
Simulation time 60219093 ps
CPU time 0.74 seconds
Started Aug 04 04:25:52 PM PDT 24
Finished Aug 04 04:25:53 PM PDT 24
Peak memory 196276 kb
Host smart-a4e2319d-b8e5-4013-91f8-dde9b88ccce3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511360331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2511360331
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3120169905
Short name T1192
Test name
Test status
Simulation time 66036831 ps
CPU time 1.42 seconds
Started Aug 04 04:24:31 PM PDT 24
Finished Aug 04 04:24:33 PM PDT 24
Peak memory 198256 kb
Host smart-c6723aac-29cd-4d29-9380-2132cbe53608
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120169905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3120169905
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1087783340
Short name T1309
Test name
Test status
Simulation time 148738262 ps
CPU time 0.6 seconds
Started Aug 04 04:24:36 PM PDT 24
Finished Aug 04 04:24:37 PM PDT 24
Peak memory 195612 kb
Host smart-6a736fc8-9906-4b74-a08f-ed614ce1689d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087783340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1087783340
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2011675255
Short name T1240
Test name
Test status
Simulation time 106258601 ps
CPU time 0.66 seconds
Started Aug 04 04:25:41 PM PDT 24
Finished Aug 04 04:25:42 PM PDT 24
Peak memory 196428 kb
Host smart-7b3fb4a5-ea25-48c1-ba20-644ecc287848
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011675255 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2011675255
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.992937270
Short name T1308
Test name
Test status
Simulation time 14151119 ps
CPU time 0.65 seconds
Started Aug 04 04:24:32 PM PDT 24
Finished Aug 04 04:24:32 PM PDT 24
Peak memory 195852 kb
Host smart-6e7d83f5-f2f9-484a-9b9c-7e7ca6892051
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992937270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.992937270
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.998634982
Short name T1216
Test name
Test status
Simulation time 15860516 ps
CPU time 0.62 seconds
Started Aug 04 04:24:34 PM PDT 24
Finished Aug 04 04:24:35 PM PDT 24
Peak memory 194636 kb
Host smart-fa63ec63-6ca7-47ba-b942-8f1ab8ca2a4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998634982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.998634982
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2073182251
Short name T1231
Test name
Test status
Simulation time 109865614 ps
CPU time 0.64 seconds
Started Aug 04 04:25:51 PM PDT 24
Finished Aug 04 04:25:52 PM PDT 24
Peak memory 195660 kb
Host smart-6acf058f-5441-4174-b5c4-c8caa4c0ec64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073182251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2073182251
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3969380469
Short name T1303
Test name
Test status
Simulation time 1154019465 ps
CPU time 2.3 seconds
Started Aug 04 04:24:46 PM PDT 24
Finished Aug 04 04:24:48 PM PDT 24
Peak memory 199816 kb
Host smart-9478bd60-e5fc-4075-aaf1-f90a0ebf1646
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969380469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3969380469
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1322625233
Short name T117
Test name
Test status
Simulation time 104220919 ps
CPU time 0.93 seconds
Started Aug 04 04:25:41 PM PDT 24
Finished Aug 04 04:25:42 PM PDT 24
Peak memory 197656 kb
Host smart-c088538b-325e-4d4e-85dc-212a775010fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322625233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1322625233
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3382117413
Short name T1271
Test name
Test status
Simulation time 24391338 ps
CPU time 0.58 seconds
Started Aug 04 04:25:19 PM PDT 24
Finished Aug 04 04:25:19 PM PDT 24
Peak memory 194680 kb
Host smart-e847f3ac-2271-489a-8bfa-7c985e81f972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382117413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3382117413
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3812868210
Short name T1263
Test name
Test status
Simulation time 25020063 ps
CPU time 0.59 seconds
Started Aug 04 04:25:01 PM PDT 24
Finished Aug 04 04:25:02 PM PDT 24
Peak memory 194620 kb
Host smart-a1b03259-5806-435c-ade6-0678ae885e65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812868210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3812868210
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1412439917
Short name T1254
Test name
Test status
Simulation time 40271096 ps
CPU time 0.57 seconds
Started Aug 04 04:25:39 PM PDT 24
Finished Aug 04 04:25:39 PM PDT 24
Peak memory 194572 kb
Host smart-62a64b2f-7076-446b-9701-547568558d25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412439917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1412439917
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.4019173542
Short name T1297
Test name
Test status
Simulation time 15647461 ps
CPU time 0.52 seconds
Started Aug 04 04:24:57 PM PDT 24
Finished Aug 04 04:24:58 PM PDT 24
Peak memory 194584 kb
Host smart-41121187-96a7-47aa-b14b-e585bde6cff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019173542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.4019173542
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3334256746
Short name T1270
Test name
Test status
Simulation time 42831347 ps
CPU time 0.58 seconds
Started Aug 04 04:25:00 PM PDT 24
Finished Aug 04 04:25:01 PM PDT 24
Peak memory 194984 kb
Host smart-4e373541-f398-4a05-805c-eb7c50cbbe12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334256746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3334256746
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.4292514111
Short name T1217
Test name
Test status
Simulation time 31781197 ps
CPU time 0.55 seconds
Started Aug 04 04:25:35 PM PDT 24
Finished Aug 04 04:25:35 PM PDT 24
Peak memory 194600 kb
Host smart-4ebd42c0-724b-4035-9085-40fb592f1c4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292514111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.4292514111
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1732300375
Short name T1229
Test name
Test status
Simulation time 33060231 ps
CPU time 0.57 seconds
Started Aug 04 04:25:04 PM PDT 24
Finished Aug 04 04:25:04 PM PDT 24
Peak memory 194560 kb
Host smart-5e7fa8fe-2270-45b2-b938-5e9482e0a061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732300375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1732300375
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.40161385
Short name T1277
Test name
Test status
Simulation time 47837571 ps
CPU time 0.6 seconds
Started Aug 04 04:25:56 PM PDT 24
Finished Aug 04 04:25:57 PM PDT 24
Peak memory 194564 kb
Host smart-403ab2c6-4d7b-4de7-b696-2be27bcf30f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40161385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.40161385
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.625750235
Short name T1274
Test name
Test status
Simulation time 17070189 ps
CPU time 0.58 seconds
Started Aug 04 04:25:03 PM PDT 24
Finished Aug 04 04:25:04 PM PDT 24
Peak memory 194560 kb
Host smart-6dd8df58-9384-4fa5-9856-22802ed82308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625750235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.625750235
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3234175257
Short name T1222
Test name
Test status
Simulation time 48501362 ps
CPU time 0.57 seconds
Started Aug 04 04:24:57 PM PDT 24
Finished Aug 04 04:24:58 PM PDT 24
Peak memory 194536 kb
Host smart-b93f75a3-012a-4865-a871-239a3d3423dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234175257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3234175257
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.401498142
Short name T1200
Test name
Test status
Simulation time 79183770 ps
CPU time 0.75 seconds
Started Aug 04 04:25:51 PM PDT 24
Finished Aug 04 04:25:52 PM PDT 24
Peak memory 199136 kb
Host smart-84b8c7d2-9054-472d-be37-64dd8e5f985e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401498142 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.401498142
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2852109060
Short name T67
Test name
Test status
Simulation time 30284862 ps
CPU time 0.61 seconds
Started Aug 04 04:24:35 PM PDT 24
Finished Aug 04 04:24:36 PM PDT 24
Peak memory 196000 kb
Host smart-b14cd745-79a8-445f-a749-bc3b3443a833
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852109060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2852109060
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3704888822
Short name T1248
Test name
Test status
Simulation time 42784934 ps
CPU time 0.57 seconds
Started Aug 04 04:24:36 PM PDT 24
Finished Aug 04 04:24:36 PM PDT 24
Peak memory 194984 kb
Host smart-f064983a-7806-4241-ab3f-5ea1bbfbede8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704888822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3704888822
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2758521204
Short name T1244
Test name
Test status
Simulation time 28495613 ps
CPU time 0.69 seconds
Started Aug 04 04:25:41 PM PDT 24
Finished Aug 04 04:25:42 PM PDT 24
Peak memory 195728 kb
Host smart-df18b536-b40b-4f23-9037-6af783246fe6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758521204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2758521204
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2752593281
Short name T1205
Test name
Test status
Simulation time 119562774 ps
CPU time 1.75 seconds
Started Aug 04 04:25:51 PM PDT 24
Finished Aug 04 04:25:53 PM PDT 24
Peak memory 200124 kb
Host smart-5692b3aa-6a0d-44e1-8bf2-d14d0a6ec4c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752593281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2752593281
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1375566685
Short name T94
Test name
Test status
Simulation time 322540322 ps
CPU time 1.24 seconds
Started Aug 04 04:25:41 PM PDT 24
Finished Aug 04 04:25:42 PM PDT 24
Peak memory 199052 kb
Host smart-9c1977fa-5012-4b53-bb4b-4636ba71d26f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375566685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1375566685
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2695530669
Short name T1242
Test name
Test status
Simulation time 223493762 ps
CPU time 0.74 seconds
Started Aug 04 04:24:48 PM PDT 24
Finished Aug 04 04:24:49 PM PDT 24
Peak memory 199392 kb
Host smart-c4910e79-b1ae-4f9e-a4f5-f0b8f213c21a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695530669 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2695530669
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2361816813
Short name T1228
Test name
Test status
Simulation time 11643022 ps
CPU time 0.6 seconds
Started Aug 04 04:25:51 PM PDT 24
Finished Aug 04 04:25:52 PM PDT 24
Peak memory 195564 kb
Host smart-0f616914-3e0e-489e-b6ec-4c8b7aa26165
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361816813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2361816813
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.24627611
Short name T1209
Test name
Test status
Simulation time 23050122 ps
CPU time 0.55 seconds
Started Aug 04 04:25:56 PM PDT 24
Finished Aug 04 04:25:57 PM PDT 24
Peak memory 194580 kb
Host smart-46c1da18-4d52-4fea-b8e7-f81a5c8a8f93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24627611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.24627611
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3057654213
Short name T1305
Test name
Test status
Simulation time 27878823 ps
CPU time 0.73 seconds
Started Aug 04 04:24:36 PM PDT 24
Finished Aug 04 04:24:37 PM PDT 24
Peak memory 197200 kb
Host smart-3a6fa6ef-b951-4274-b659-8252bc7daa93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057654213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3057654213
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1700860805
Short name T1186
Test name
Test status
Simulation time 206403508 ps
CPU time 2.09 seconds
Started Aug 04 04:25:51 PM PDT 24
Finished Aug 04 04:25:54 PM PDT 24
Peak memory 200164 kb
Host smart-dc5c57ca-9340-4023-b6eb-d841678b0463
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700860805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1700860805
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.410517918
Short name T86
Test name
Test status
Simulation time 53969445 ps
CPU time 0.93 seconds
Started Aug 04 04:25:52 PM PDT 24
Finished Aug 04 04:25:53 PM PDT 24
Peak memory 199076 kb
Host smart-76d9ef91-cef5-421f-a15b-250bb2d45df6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410517918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.410517918
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.436791912
Short name T1246
Test name
Test status
Simulation time 39571985 ps
CPU time 1.23 seconds
Started Aug 04 04:24:46 PM PDT 24
Finished Aug 04 04:24:47 PM PDT 24
Peak memory 199808 kb
Host smart-41d193da-f79e-478e-8d07-ad7e8260329a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436791912 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.436791912
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3441969752
Short name T1307
Test name
Test status
Simulation time 13732929 ps
CPU time 0.62 seconds
Started Aug 04 04:24:46 PM PDT 24
Finished Aug 04 04:24:47 PM PDT 24
Peak memory 195584 kb
Host smart-81c909f6-643c-4575-83ea-c8abc9120871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441969752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3441969752
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.370439369
Short name T1285
Test name
Test status
Simulation time 13538556 ps
CPU time 0.56 seconds
Started Aug 04 04:24:40 PM PDT 24
Finished Aug 04 04:24:40 PM PDT 24
Peak memory 194700 kb
Host smart-1fbbefd4-df8b-4d9d-ac6d-8684ad3331dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370439369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.370439369
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3672115358
Short name T77
Test name
Test status
Simulation time 16559150 ps
CPU time 0.78 seconds
Started Aug 04 04:24:53 PM PDT 24
Finished Aug 04 04:24:54 PM PDT 24
Peak memory 198068 kb
Host smart-d52b3833-bef2-4a0d-9650-0de630c18997
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672115358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3672115358
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1118479992
Short name T1182
Test name
Test status
Simulation time 133264269 ps
CPU time 1.48 seconds
Started Aug 04 04:24:44 PM PDT 24
Finished Aug 04 04:24:45 PM PDT 24
Peak memory 200260 kb
Host smart-cbf6ef70-2c18-4f33-83d3-ffe70b14c9eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118479992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1118479992
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.4102803342
Short name T95
Test name
Test status
Simulation time 1240272519 ps
CPU time 1.37 seconds
Started Aug 04 04:24:37 PM PDT 24
Finished Aug 04 04:24:38 PM PDT 24
Peak memory 199676 kb
Host smart-311d3032-1f33-4665-99eb-0179a1818dea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102803342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.4102803342
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2478774599
Short name T1260
Test name
Test status
Simulation time 52480780 ps
CPU time 1.37 seconds
Started Aug 04 04:24:36 PM PDT 24
Finished Aug 04 04:24:38 PM PDT 24
Peak memory 200148 kb
Host smart-3beb2321-152c-4733-a269-2525e190035c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478774599 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2478774599
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1422048151
Short name T1299
Test name
Test status
Simulation time 18423610 ps
CPU time 0.64 seconds
Started Aug 04 04:24:43 PM PDT 24
Finished Aug 04 04:24:44 PM PDT 24
Peak memory 195740 kb
Host smart-bd95af33-7d88-4cd1-a756-617db7c3b163
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422048151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1422048151
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3724665966
Short name T1247
Test name
Test status
Simulation time 63342823 ps
CPU time 0.57 seconds
Started Aug 04 04:24:38 PM PDT 24
Finished Aug 04 04:24:39 PM PDT 24
Peak memory 194652 kb
Host smart-c4366454-2b1e-49dd-8de9-7351e2d7fc36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724665966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3724665966
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3897336940
Short name T79
Test name
Test status
Simulation time 18492184 ps
CPU time 0.74 seconds
Started Aug 04 04:24:40 PM PDT 24
Finished Aug 04 04:24:41 PM PDT 24
Peak memory 197348 kb
Host smart-61002bd7-113f-4897-84e2-60e0e3becabd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897336940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3897336940
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3770968849
Short name T1302
Test name
Test status
Simulation time 27090003 ps
CPU time 1.39 seconds
Started Aug 04 04:24:44 PM PDT 24
Finished Aug 04 04:24:45 PM PDT 24
Peak memory 200260 kb
Host smart-0d04931e-d842-4dfe-bd0b-34e96f737e08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770968849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3770968849
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3337207894
Short name T92
Test name
Test status
Simulation time 63224174 ps
CPU time 0.9 seconds
Started Aug 04 04:24:40 PM PDT 24
Finished Aug 04 04:24:41 PM PDT 24
Peak memory 199148 kb
Host smart-89c8ad9a-a2fc-4084-b0b9-14d52f049e2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337207894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3337207894
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3444218242
Short name T1207
Test name
Test status
Simulation time 19797201 ps
CPU time 0.97 seconds
Started Aug 04 04:24:37 PM PDT 24
Finished Aug 04 04:24:38 PM PDT 24
Peak memory 200088 kb
Host smart-24c3e15c-61ad-48f6-84de-d5f4d9207c19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444218242 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3444218242
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.4034820322
Short name T1237
Test name
Test status
Simulation time 14338658 ps
CPU time 0.57 seconds
Started Aug 04 04:24:55 PM PDT 24
Finished Aug 04 04:24:56 PM PDT 24
Peak memory 195636 kb
Host smart-e17071ed-a6d9-44c2-b8f7-20922ce5845e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034820322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.4034820322
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3407410429
Short name T1183
Test name
Test status
Simulation time 47493747 ps
CPU time 0.61 seconds
Started Aug 04 04:24:43 PM PDT 24
Finished Aug 04 04:24:44 PM PDT 24
Peak memory 194588 kb
Host smart-b698db13-0bb9-435e-9ecd-4ebb4be0c0e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407410429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3407410429
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2880613909
Short name T1301
Test name
Test status
Simulation time 16770097 ps
CPU time 0.66 seconds
Started Aug 04 04:24:43 PM PDT 24
Finished Aug 04 04:24:43 PM PDT 24
Peak memory 196696 kb
Host smart-90e3d8e8-537c-499e-9744-770f5c7794a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880613909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2880613909
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1408799065
Short name T1256
Test name
Test status
Simulation time 34238535 ps
CPU time 1.78 seconds
Started Aug 04 04:24:38 PM PDT 24
Finished Aug 04 04:24:40 PM PDT 24
Peak memory 200360 kb
Host smart-253294da-562a-4324-9adb-fd8d5c0e8f7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408799065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1408799065
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1663021935
Short name T90
Test name
Test status
Simulation time 178092642 ps
CPU time 1 seconds
Started Aug 04 04:24:46 PM PDT 24
Finished Aug 04 04:24:47 PM PDT 24
Peak memory 199292 kb
Host smart-8196ae1c-d448-4093-978a-f132e2830674
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663021935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1663021935
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2451650866
Short name T1067
Test name
Test status
Simulation time 75492903 ps
CPU time 0.54 seconds
Started Aug 04 05:05:28 PM PDT 24
Finished Aug 04 05:05:28 PM PDT 24
Peak memory 195284 kb
Host smart-59e54973-0925-477c-bff0-cd559ad0ec59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451650866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2451650866
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.4233713313
Short name T153
Test name
Test status
Simulation time 244497629064 ps
CPU time 22.99 seconds
Started Aug 04 05:05:16 PM PDT 24
Finished Aug 04 05:05:39 PM PDT 24
Peak memory 199812 kb
Host smart-8ff30290-1ade-472d-b9fb-d0ba3abab9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233713313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.4233713313
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.921860554
Short name T1118
Test name
Test status
Simulation time 22105163391 ps
CPU time 15.64 seconds
Started Aug 04 05:05:21 PM PDT 24
Finished Aug 04 05:05:37 PM PDT 24
Peak memory 199568 kb
Host smart-4df186f4-8e01-44d4-849e-9bf80e88a5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921860554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.921860554
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1639328913
Short name T755
Test name
Test status
Simulation time 8742231485 ps
CPU time 20.01 seconds
Started Aug 04 05:05:20 PM PDT 24
Finished Aug 04 05:05:41 PM PDT 24
Peak memory 199824 kb
Host smart-9725164a-85df-4f3a-b5c7-6f5ff89c18e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639328913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1639328913
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2141731989
Short name T918
Test name
Test status
Simulation time 52082112017 ps
CPU time 23.39 seconds
Started Aug 04 05:05:20 PM PDT 24
Finished Aug 04 05:05:44 PM PDT 24
Peak memory 199924 kb
Host smart-3791a807-c4f1-4d23-be73-ef18c6c66031
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141731989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2141731989
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3669590971
Short name T1020
Test name
Test status
Simulation time 178002582630 ps
CPU time 758.48 seconds
Started Aug 04 05:05:24 PM PDT 24
Finished Aug 04 05:18:02 PM PDT 24
Peak memory 199836 kb
Host smart-e2e2389b-1c3d-483a-bbb9-8194c57ec014
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3669590971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3669590971
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.4274414668
Short name T669
Test name
Test status
Simulation time 6059156113 ps
CPU time 10.1 seconds
Started Aug 04 05:05:25 PM PDT 24
Finished Aug 04 05:05:35 PM PDT 24
Peak memory 198796 kb
Host smart-859c9ccb-8cbe-4448-8074-f46c0b5fa518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274414668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.4274414668
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.849697483
Short name T578
Test name
Test status
Simulation time 194361470823 ps
CPU time 32 seconds
Started Aug 04 05:05:19 PM PDT 24
Finished Aug 04 05:05:52 PM PDT 24
Peak memory 208196 kb
Host smart-d5c5122b-9ea2-4556-a18a-792baaf292ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849697483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.849697483
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2178547940
Short name T781
Test name
Test status
Simulation time 1115398358 ps
CPU time 61.56 seconds
Started Aug 04 05:05:24 PM PDT 24
Finished Aug 04 05:06:25 PM PDT 24
Peak memory 199860 kb
Host smart-77a5c1c2-89c2-498b-8772-185212177c7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2178547940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2178547940
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.650819375
Short name T369
Test name
Test status
Simulation time 7716580994 ps
CPU time 58.66 seconds
Started Aug 04 05:05:20 PM PDT 24
Finished Aug 04 05:06:19 PM PDT 24
Peak memory 198000 kb
Host smart-7b80225d-8fbc-4389-88e1-62622ffe966a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=650819375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.650819375
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.883881183
Short name T455
Test name
Test status
Simulation time 52894700924 ps
CPU time 46.92 seconds
Started Aug 04 05:05:25 PM PDT 24
Finished Aug 04 05:06:12 PM PDT 24
Peak memory 199792 kb
Host smart-9c6b3ea9-5a0a-4320-8b39-79f24bf543b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883881183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.883881183
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3906458921
Short name T1038
Test name
Test status
Simulation time 1551019628 ps
CPU time 2.88 seconds
Started Aug 04 05:05:22 PM PDT 24
Finished Aug 04 05:05:25 PM PDT 24
Peak memory 195528 kb
Host smart-de00fec4-8176-4f6e-8228-21056857a6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906458921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3906458921
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.3103753368
Short name T537
Test name
Test status
Simulation time 435790241 ps
CPU time 1.65 seconds
Started Aug 04 05:05:17 PM PDT 24
Finished Aug 04 05:05:18 PM PDT 24
Peak memory 199228 kb
Host smart-a7828eb6-1fed-41d1-b679-8baa1bcc1398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103753368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3103753368
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.435317487
Short name T711
Test name
Test status
Simulation time 319396863522 ps
CPU time 628.42 seconds
Started Aug 04 05:05:24 PM PDT 24
Finished Aug 04 05:15:52 PM PDT 24
Peak memory 199820 kb
Host smart-4a931158-5ce2-4fa6-903d-68fe8582c583
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435317487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.435317487
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2507667531
Short name T1058
Test name
Test status
Simulation time 8338563649 ps
CPU time 10.71 seconds
Started Aug 04 05:05:24 PM PDT 24
Finished Aug 04 05:05:35 PM PDT 24
Peak memory 199892 kb
Host smart-81efbb7a-75dc-4c85-aa7a-4e21935c3547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507667531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2507667531
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3932647177
Short name T1047
Test name
Test status
Simulation time 46026031025 ps
CPU time 19.44 seconds
Started Aug 04 05:05:15 PM PDT 24
Finished Aug 04 05:05:35 PM PDT 24
Peak memory 199932 kb
Host smart-4b098a8c-4a7c-430d-884f-6de28fe1100d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932647177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3932647177
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3982884304
Short name T763
Test name
Test status
Simulation time 18149052 ps
CPU time 0.55 seconds
Started Aug 04 05:05:36 PM PDT 24
Finished Aug 04 05:05:36 PM PDT 24
Peak memory 194256 kb
Host smart-0cc8f202-f005-4406-91b5-51c17f7313d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982884304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3982884304
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.4069763995
Short name T409
Test name
Test status
Simulation time 39448674771 ps
CPU time 35.22 seconds
Started Aug 04 05:05:27 PM PDT 24
Finished Aug 04 05:06:02 PM PDT 24
Peak memory 199836 kb
Host smart-9e3e6e9d-56b1-49aa-be1a-3bd97daafdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069763995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.4069763995
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.839550495
Short name T892
Test name
Test status
Simulation time 131349329025 ps
CPU time 19.41 seconds
Started Aug 04 05:05:28 PM PDT 24
Finished Aug 04 05:05:47 PM PDT 24
Peak memory 199332 kb
Host smart-2bb6b8cd-51eb-4d8a-96f8-00d550478c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839550495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.839550495
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3909782521
Short name T1016
Test name
Test status
Simulation time 40810148585 ps
CPU time 55.98 seconds
Started Aug 04 05:05:28 PM PDT 24
Finished Aug 04 05:06:24 PM PDT 24
Peak memory 199800 kb
Host smart-8d697957-e6d0-4880-bbcc-66babd9b2eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909782521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3909782521
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.2859126797
Short name T329
Test name
Test status
Simulation time 31572128323 ps
CPU time 55.79 seconds
Started Aug 04 05:05:33 PM PDT 24
Finished Aug 04 05:06:29 PM PDT 24
Peak memory 199876 kb
Host smart-704e3533-9669-4626-9e8c-8ed76768ec25
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859126797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2859126797
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1024482780
Short name T922
Test name
Test status
Simulation time 33455967859 ps
CPU time 143.73 seconds
Started Aug 04 05:05:34 PM PDT 24
Finished Aug 04 05:07:58 PM PDT 24
Peak memory 199852 kb
Host smart-7b97d0e1-15e6-4c73-86ac-a2f590be5b3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1024482780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1024482780
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3960682017
Short name T955
Test name
Test status
Simulation time 6826729778 ps
CPU time 5.55 seconds
Started Aug 04 05:05:34 PM PDT 24
Finished Aug 04 05:05:39 PM PDT 24
Peak memory 199368 kb
Host smart-6527db23-f5de-4a33-ba62-ddd92adca566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960682017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3960682017
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1944333189
Short name T1006
Test name
Test status
Simulation time 85539169033 ps
CPU time 72.96 seconds
Started Aug 04 05:05:33 PM PDT 24
Finished Aug 04 05:06:46 PM PDT 24
Peak memory 199968 kb
Host smart-134c25f6-83b6-4817-a426-a665a79d56a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944333189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1944333189
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.1375005248
Short name T371
Test name
Test status
Simulation time 9601710542 ps
CPU time 137.38 seconds
Started Aug 04 05:05:34 PM PDT 24
Finished Aug 04 05:07:52 PM PDT 24
Peak memory 199792 kb
Host smart-021fa0ee-1333-46a6-81d7-424b21ed826f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1375005248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1375005248
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2204734451
Short name T1045
Test name
Test status
Simulation time 5135360819 ps
CPU time 21.72 seconds
Started Aug 04 05:05:29 PM PDT 24
Finished Aug 04 05:05:51 PM PDT 24
Peak memory 197728 kb
Host smart-b1dc302a-5880-4e43-9c9f-4d06abcc0255
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2204734451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2204734451
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1044918089
Short name T155
Test name
Test status
Simulation time 43129936115 ps
CPU time 35.72 seconds
Started Aug 04 05:05:33 PM PDT 24
Finished Aug 04 05:06:09 PM PDT 24
Peak memory 199848 kb
Host smart-0237a4c6-e8e1-4d61-952c-1f8c3f9282e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044918089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1044918089
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3859493924
Short name T992
Test name
Test status
Simulation time 48097473355 ps
CPU time 36.02 seconds
Started Aug 04 05:05:32 PM PDT 24
Finished Aug 04 05:06:08 PM PDT 24
Peak memory 196192 kb
Host smart-d99fecd0-832e-4755-ac86-3b611f62c30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859493924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3859493924
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1213420243
Short name T97
Test name
Test status
Simulation time 252537964 ps
CPU time 0.82 seconds
Started Aug 04 05:05:34 PM PDT 24
Finished Aug 04 05:05:35 PM PDT 24
Peak memory 218240 kb
Host smart-0d6f2dc9-6c29-49b2-8200-3dd24ea1d7b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213420243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1213420243
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.4226201475
Short name T297
Test name
Test status
Simulation time 889405662 ps
CPU time 2.7 seconds
Started Aug 04 05:05:27 PM PDT 24
Finished Aug 04 05:05:30 PM PDT 24
Peak memory 198068 kb
Host smart-6ef01ad6-6195-4357-a39a-139ae0c58031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226201475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.4226201475
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3382697104
Short name T1042
Test name
Test status
Simulation time 177633342924 ps
CPU time 203.54 seconds
Started Aug 04 05:05:34 PM PDT 24
Finished Aug 04 05:08:58 PM PDT 24
Peak memory 199836 kb
Host smart-a12eef8d-6f27-4ca8-a652-254a2124e742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382697104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3382697104
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1208310362
Short name T785
Test name
Test status
Simulation time 83410560041 ps
CPU time 616.52 seconds
Started Aug 04 05:05:35 PM PDT 24
Finished Aug 04 05:15:52 PM PDT 24
Peak memory 215872 kb
Host smart-3b2cfad1-322e-4bd8-90b6-27e1240d0e84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208310362 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1208310362
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3484878820
Short name T573
Test name
Test status
Simulation time 3897032000 ps
CPU time 1.22 seconds
Started Aug 04 05:05:31 PM PDT 24
Finished Aug 04 05:05:32 PM PDT 24
Peak memory 199884 kb
Host smart-6a892c35-ffe1-42bc-b2d7-4e10c1eff1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484878820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3484878820
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.558913849
Short name T971
Test name
Test status
Simulation time 6721130187 ps
CPU time 12.13 seconds
Started Aug 04 05:05:28 PM PDT 24
Finished Aug 04 05:05:41 PM PDT 24
Peak memory 199844 kb
Host smart-690bb1fc-e599-4d6a-a0a5-d509003ab542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558913849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.558913849
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.1785445413
Short name T996
Test name
Test status
Simulation time 11391688 ps
CPU time 0.55 seconds
Started Aug 04 05:06:52 PM PDT 24
Finished Aug 04 05:06:53 PM PDT 24
Peak memory 195552 kb
Host smart-5e88712e-744f-4e09-b4e3-c812a347e2f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785445413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1785445413
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.41862023
Short name T1017
Test name
Test status
Simulation time 106696209840 ps
CPU time 84.3 seconds
Started Aug 04 05:06:39 PM PDT 24
Finished Aug 04 05:08:03 PM PDT 24
Peak memory 199844 kb
Host smart-cc51ec1a-6b22-4154-a74b-170283087854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41862023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.41862023
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.4154549903
Short name T1050
Test name
Test status
Simulation time 60122031240 ps
CPU time 16.19 seconds
Started Aug 04 05:06:40 PM PDT 24
Finished Aug 04 05:06:57 PM PDT 24
Peak memory 199728 kb
Host smart-4c819c43-2c24-4d01-97b3-e5c5a55b209b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154549903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.4154549903
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3667521793
Short name T477
Test name
Test status
Simulation time 67222704174 ps
CPU time 30.52 seconds
Started Aug 04 05:06:39 PM PDT 24
Finished Aug 04 05:07:10 PM PDT 24
Peak memory 199788 kb
Host smart-2ff7351b-7d5d-4cb4-9de7-788f9a7f1bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667521793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3667521793
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3596270041
Short name T967
Test name
Test status
Simulation time 15754527662 ps
CPU time 21.41 seconds
Started Aug 04 05:06:49 PM PDT 24
Finished Aug 04 05:07:11 PM PDT 24
Peak memory 197800 kb
Host smart-56200c48-56ad-46c4-997a-710371dc1280
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596270041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3596270041
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.607746336
Short name T273
Test name
Test status
Simulation time 149941634007 ps
CPU time 248.04 seconds
Started Aug 04 05:06:49 PM PDT 24
Finished Aug 04 05:10:58 PM PDT 24
Peak memory 199852 kb
Host smart-e70dfbde-9f7c-47df-a6ca-7711fab44c76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=607746336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.607746336
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.4177639586
Short name T598
Test name
Test status
Simulation time 2456850705 ps
CPU time 4.34 seconds
Started Aug 04 05:06:43 PM PDT 24
Finished Aug 04 05:06:47 PM PDT 24
Peak memory 197416 kb
Host smart-ae185b4e-c47e-4cb3-8dc9-5b055abf0e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177639586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.4177639586
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3953093645
Short name T334
Test name
Test status
Simulation time 30481442285 ps
CPU time 64.89 seconds
Started Aug 04 05:06:43 PM PDT 24
Finished Aug 04 05:07:48 PM PDT 24
Peak memory 199960 kb
Host smart-d3f3b297-de05-43fc-bad0-7e6bd15f3a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953093645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3953093645
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.910485418
Short name T283
Test name
Test status
Simulation time 15925919857 ps
CPU time 831.68 seconds
Started Aug 04 05:06:44 PM PDT 24
Finished Aug 04 05:20:36 PM PDT 24
Peak memory 199896 kb
Host smart-e67a73a7-5ab6-4851-8530-a998d3682df6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=910485418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.910485418
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.707308475
Short name T446
Test name
Test status
Simulation time 4546205055 ps
CPU time 39.38 seconds
Started Aug 04 05:06:43 PM PDT 24
Finished Aug 04 05:07:22 PM PDT 24
Peak memory 198564 kb
Host smart-f4f4dbb7-3291-46db-8039-ffb3e6788e4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=707308475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.707308475
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2507005899
Short name T142
Test name
Test status
Simulation time 40805905669 ps
CPU time 66.37 seconds
Started Aug 04 05:06:50 PM PDT 24
Finished Aug 04 05:07:56 PM PDT 24
Peak memory 199836 kb
Host smart-5f7a6aad-4405-482c-878f-bfc350446962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507005899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2507005899
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2905633592
Short name T428
Test name
Test status
Simulation time 4450193662 ps
CPU time 2.45 seconds
Started Aug 04 05:06:42 PM PDT 24
Finished Aug 04 05:06:45 PM PDT 24
Peak memory 196372 kb
Host smart-5e84413e-c23a-49c7-a9f6-84999a123442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905633592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2905633592
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1473951076
Short name T732
Test name
Test status
Simulation time 5688727565 ps
CPU time 13.4 seconds
Started Aug 04 05:06:38 PM PDT 24
Finished Aug 04 05:06:51 PM PDT 24
Peak memory 199796 kb
Host smart-9f587a5d-264d-4d40-ac8e-bffe1ecabd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473951076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1473951076
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2132673001
Short name T964
Test name
Test status
Simulation time 418357709519 ps
CPU time 53.75 seconds
Started Aug 04 05:06:51 PM PDT 24
Finished Aug 04 05:07:45 PM PDT 24
Peak memory 199776 kb
Host smart-0da12030-3f1e-4dbd-997f-b22c09459d1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132673001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2132673001
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1554022787
Short name T58
Test name
Test status
Simulation time 75306343782 ps
CPU time 830.45 seconds
Started Aug 04 05:06:49 PM PDT 24
Finished Aug 04 05:20:40 PM PDT 24
Peak memory 208172 kb
Host smart-67c26372-f5e4-4532-9f09-a041cb64e043
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554022787 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1554022787
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3691843148
Short name T8
Test name
Test status
Simulation time 6991478818 ps
CPU time 10.87 seconds
Started Aug 04 05:06:49 PM PDT 24
Finished Aug 04 05:07:00 PM PDT 24
Peak memory 199692 kb
Host smart-ef0d9e72-c7da-49b9-9959-f3dfdd8aa73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691843148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3691843148
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3147505504
Short name T506
Test name
Test status
Simulation time 174831355031 ps
CPU time 46.87 seconds
Started Aug 04 05:06:39 PM PDT 24
Finished Aug 04 05:07:26 PM PDT 24
Peak memory 199732 kb
Host smart-efc285ef-24e5-4e89-be56-20566be6f27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147505504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3147505504
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2537280071
Short name T753
Test name
Test status
Simulation time 65551424182 ps
CPU time 51.86 seconds
Started Aug 04 05:11:24 PM PDT 24
Finished Aug 04 05:12:16 PM PDT 24
Peak memory 199816 kb
Host smart-c63c47db-3d1c-4474-a7f0-bbd74230eba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537280071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2537280071
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3321208897
Short name T284
Test name
Test status
Simulation time 10049125340 ps
CPU time 11.68 seconds
Started Aug 04 05:11:22 PM PDT 24
Finished Aug 04 05:11:34 PM PDT 24
Peak memory 199416 kb
Host smart-be869055-e05e-4d27-a57a-d526ba12f0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321208897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3321208897
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3139887562
Short name T617
Test name
Test status
Simulation time 130906408551 ps
CPU time 59.87 seconds
Started Aug 04 05:11:23 PM PDT 24
Finished Aug 04 05:12:23 PM PDT 24
Peak memory 199528 kb
Host smart-745564ea-c972-4e5c-aaab-2c3a29a6d01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139887562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3139887562
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.4213521264
Short name T1030
Test name
Test status
Simulation time 18368315441 ps
CPU time 26.66 seconds
Started Aug 04 05:11:21 PM PDT 24
Finished Aug 04 05:11:48 PM PDT 24
Peak memory 199852 kb
Host smart-2c78f5fc-3a50-4899-9419-5b9c2de5681e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213521264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.4213521264
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3523393541
Short name T920
Test name
Test status
Simulation time 15511123429 ps
CPU time 13.33 seconds
Started Aug 04 05:11:26 PM PDT 24
Finished Aug 04 05:11:40 PM PDT 24
Peak memory 198692 kb
Host smart-43567e2d-c0c2-4c51-80c1-95e0f3547fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523393541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3523393541
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3113371908
Short name T198
Test name
Test status
Simulation time 84456971822 ps
CPU time 31.56 seconds
Started Aug 04 05:11:23 PM PDT 24
Finished Aug 04 05:11:54 PM PDT 24
Peak memory 199860 kb
Host smart-651bfb49-98c3-4daa-8259-de54e71476f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113371908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3113371908
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2328074470
Short name T949
Test name
Test status
Simulation time 15240014 ps
CPU time 0.55 seconds
Started Aug 04 05:06:54 PM PDT 24
Finished Aug 04 05:06:55 PM PDT 24
Peak memory 195244 kb
Host smart-2f75326f-3513-4614-877c-8dae691090ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328074470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2328074470
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3821727810
Short name T1054
Test name
Test status
Simulation time 30268578046 ps
CPU time 12.33 seconds
Started Aug 04 05:06:52 PM PDT 24
Finished Aug 04 05:07:05 PM PDT 24
Peak memory 199768 kb
Host smart-b53a3edd-d3ed-452e-a092-07178bdbb299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821727810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3821727810
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.756584381
Short name T653
Test name
Test status
Simulation time 162784543532 ps
CPU time 73.52 seconds
Started Aug 04 05:06:50 PM PDT 24
Finished Aug 04 05:08:04 PM PDT 24
Peak memory 199704 kb
Host smart-46c2e341-b8c9-42be-9885-5d0af4461d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756584381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.756584381
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2937161872
Short name T169
Test name
Test status
Simulation time 30136051416 ps
CPU time 40.2 seconds
Started Aug 04 05:06:52 PM PDT 24
Finished Aug 04 05:07:32 PM PDT 24
Peak memory 199832 kb
Host smart-310c085f-22cb-4670-a345-aef03abf383e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937161872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2937161872
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.2735414840
Short name T675
Test name
Test status
Simulation time 29031286304 ps
CPU time 18.66 seconds
Started Aug 04 05:06:58 PM PDT 24
Finished Aug 04 05:07:16 PM PDT 24
Peak memory 199904 kb
Host smart-1af565c7-eafd-420a-926c-8ad1746423e0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735414840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2735414840
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2422243881
Short name T265
Test name
Test status
Simulation time 94571494093 ps
CPU time 613.85 seconds
Started Aug 04 05:06:50 PM PDT 24
Finished Aug 04 05:17:04 PM PDT 24
Peak memory 199912 kb
Host smart-57cbb66a-addf-4a80-9d77-8762e31ee2ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2422243881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2422243881
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.3411697907
Short name T727
Test name
Test status
Simulation time 4229699009 ps
CPU time 8.47 seconds
Started Aug 04 05:06:52 PM PDT 24
Finished Aug 04 05:07:01 PM PDT 24
Peak memory 199620 kb
Host smart-3a505c59-9cb2-4fc9-89dc-e79221f16528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411697907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3411697907
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.1893451232
Short name T1159
Test name
Test status
Simulation time 17466082294 ps
CPU time 956.81 seconds
Started Aug 04 05:06:52 PM PDT 24
Finished Aug 04 05:22:49 PM PDT 24
Peak memory 199904 kb
Host smart-95b0944e-cbb8-41b0-a3db-332474a5e52e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893451232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1893451232
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.224583354
Short name T438
Test name
Test status
Simulation time 4086899412 ps
CPU time 34.22 seconds
Started Aug 04 05:06:49 PM PDT 24
Finished Aug 04 05:07:24 PM PDT 24
Peak memory 198232 kb
Host smart-71ed9353-e43f-4c22-9817-89bb091d2351
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=224583354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.224583354
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.4025930514
Short name T1086
Test name
Test status
Simulation time 75608524102 ps
CPU time 28.32 seconds
Started Aug 04 05:06:51 PM PDT 24
Finished Aug 04 05:07:19 PM PDT 24
Peak memory 199764 kb
Host smart-a625b8e9-4af5-487d-924d-3ce909630629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025930514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.4025930514
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1079914452
Short name T673
Test name
Test status
Simulation time 3728054092 ps
CPU time 6.8 seconds
Started Aug 04 05:06:51 PM PDT 24
Finished Aug 04 05:06:58 PM PDT 24
Peak memory 196364 kb
Host smart-0093d4d5-89b6-4f1c-bec9-a869322fe3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079914452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1079914452
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.371921501
Short name T758
Test name
Test status
Simulation time 735262496 ps
CPU time 1.78 seconds
Started Aug 04 05:06:46 PM PDT 24
Finished Aug 04 05:06:48 PM PDT 24
Peak memory 199460 kb
Host smart-3919781b-b746-4baa-9aae-a4ae24399c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371921501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.371921501
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2512618101
Short name T454
Test name
Test status
Simulation time 37867269189 ps
CPU time 25.07 seconds
Started Aug 04 05:06:56 PM PDT 24
Finished Aug 04 05:07:21 PM PDT 24
Peak memory 199916 kb
Host smart-ed376e6c-aee0-4b1e-8fef-028464850cd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512618101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2512618101
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1159638937
Short name T726
Test name
Test status
Simulation time 11438576123 ps
CPU time 102.57 seconds
Started Aug 04 05:06:51 PM PDT 24
Finished Aug 04 05:08:34 PM PDT 24
Peak memory 215972 kb
Host smart-2e8afc10-abe7-4478-8177-a128cdf19e0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159638937 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1159638937
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.3249649772
Short name T571
Test name
Test status
Simulation time 1901335868 ps
CPU time 2.28 seconds
Started Aug 04 05:06:50 PM PDT 24
Finished Aug 04 05:06:53 PM PDT 24
Peak memory 198268 kb
Host smart-0fd64fde-01fa-4793-99fb-938d3efba50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249649772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3249649772
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1423479091
Short name T830
Test name
Test status
Simulation time 10996155107 ps
CPU time 8.45 seconds
Started Aug 04 05:06:47 PM PDT 24
Finished Aug 04 05:06:55 PM PDT 24
Peak memory 196552 kb
Host smart-156926fe-5cf9-4919-a476-0699cc94a3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423479091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1423479091
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1417091456
Short name T737
Test name
Test status
Simulation time 61946479741 ps
CPU time 31.41 seconds
Started Aug 04 05:11:23 PM PDT 24
Finished Aug 04 05:11:54 PM PDT 24
Peak memory 199872 kb
Host smart-b5acc19d-912a-48d2-91f1-d39f42f4b056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417091456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1417091456
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.807297389
Short name T43
Test name
Test status
Simulation time 44599884107 ps
CPU time 23.75 seconds
Started Aug 04 05:11:16 PM PDT 24
Finished Aug 04 05:11:40 PM PDT 24
Peak memory 199916 kb
Host smart-3e98275f-ab0a-48e3-9b1a-5eb58488139b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807297389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.807297389
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1920594267
Short name T746
Test name
Test status
Simulation time 32447953271 ps
CPU time 13.68 seconds
Started Aug 04 05:11:24 PM PDT 24
Finished Aug 04 05:11:38 PM PDT 24
Peak memory 199868 kb
Host smart-f379365d-3d14-4568-b5f4-604e3134ee9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920594267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1920594267
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.84224555
Short name T948
Test name
Test status
Simulation time 63669012614 ps
CPU time 28.75 seconds
Started Aug 04 05:11:23 PM PDT 24
Finished Aug 04 05:11:52 PM PDT 24
Peak memory 199896 kb
Host smart-1404ec60-ef29-42a2-b4e3-72535948675e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84224555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.84224555
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1659408946
Short name T595
Test name
Test status
Simulation time 144084383298 ps
CPU time 50.97 seconds
Started Aug 04 05:11:24 PM PDT 24
Finished Aug 04 05:12:15 PM PDT 24
Peak memory 199848 kb
Host smart-1d249293-02a9-4304-8fb8-202b6afeb79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659408946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1659408946
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3623547486
Short name T1096
Test name
Test status
Simulation time 30064148 ps
CPU time 0.58 seconds
Started Aug 04 05:07:02 PM PDT 24
Finished Aug 04 05:07:03 PM PDT 24
Peak memory 195200 kb
Host smart-c9204f02-1e87-49fa-97e4-f3791cdd1683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623547486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3623547486
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1799680760
Short name T609
Test name
Test status
Simulation time 85338858501 ps
CPU time 49.31 seconds
Started Aug 04 05:06:55 PM PDT 24
Finished Aug 04 05:07:44 PM PDT 24
Peak memory 199800 kb
Host smart-8683f3a9-516e-4587-a1fb-ccaa2a7c07e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799680760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1799680760
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3563653483
Short name T712
Test name
Test status
Simulation time 31589490087 ps
CPU time 31.98 seconds
Started Aug 04 05:06:54 PM PDT 24
Finished Aug 04 05:07:26 PM PDT 24
Peak memory 199828 kb
Host smart-56ce8433-10c8-47a2-bb15-620201fcf107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563653483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3563653483
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.111851315
Short name T279
Test name
Test status
Simulation time 17240993755 ps
CPU time 14.27 seconds
Started Aug 04 05:06:53 PM PDT 24
Finished Aug 04 05:07:08 PM PDT 24
Peak memory 199892 kb
Host smart-f25f9707-56cb-47b3-a6b1-68fd9bfe56d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111851315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.111851315
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2169645865
Short name T511
Test name
Test status
Simulation time 10005270696 ps
CPU time 8.33 seconds
Started Aug 04 05:06:59 PM PDT 24
Finished Aug 04 05:07:08 PM PDT 24
Peak memory 199784 kb
Host smart-aba24023-dfe9-49ba-86d6-cad4c03b44f3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169645865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2169645865
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.747612054
Short name T1028
Test name
Test status
Simulation time 68707725619 ps
CPU time 235.97 seconds
Started Aug 04 05:07:01 PM PDT 24
Finished Aug 04 05:10:57 PM PDT 24
Peak memory 199720 kb
Host smart-62df8154-ee7f-47cd-b755-6f77528b2e48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=747612054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.747612054
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.246371954
Short name T1168
Test name
Test status
Simulation time 2499279365 ps
CPU time 4.29 seconds
Started Aug 04 05:06:59 PM PDT 24
Finished Aug 04 05:07:03 PM PDT 24
Peak memory 197132 kb
Host smart-8f7ee232-f0ff-427f-bc0c-a1d33a71580d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246371954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.246371954
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1668582067
Short name T600
Test name
Test status
Simulation time 101966424691 ps
CPU time 12.13 seconds
Started Aug 04 05:07:00 PM PDT 24
Finished Aug 04 05:07:12 PM PDT 24
Peak memory 196844 kb
Host smart-59378f6d-3046-47b0-a629-9d6fcb5590bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668582067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1668582067
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.418712189
Short name T1137
Test name
Test status
Simulation time 13398196633 ps
CPU time 659.04 seconds
Started Aug 04 05:07:00 PM PDT 24
Finished Aug 04 05:17:59 PM PDT 24
Peak memory 199896 kb
Host smart-63e97f7f-f189-4e6b-81bc-7a216d515530
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=418712189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.418712189
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.2171795256
Short name T914
Test name
Test status
Simulation time 1278084824 ps
CPU time 1.67 seconds
Started Aug 04 05:07:00 PM PDT 24
Finished Aug 04 05:07:02 PM PDT 24
Peak memory 196552 kb
Host smart-5d6431a9-d6a9-4dcc-9947-b007ccb374db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2171795256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2171795256
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3105341159
Short name T941
Test name
Test status
Simulation time 78375861326 ps
CPU time 64.93 seconds
Started Aug 04 05:06:58 PM PDT 24
Finished Aug 04 05:08:03 PM PDT 24
Peak memory 199912 kb
Host smart-f532cdfb-1c72-4c1b-b25d-1aa540c885dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105341159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3105341159
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2161395966
Short name T390
Test name
Test status
Simulation time 6456491315 ps
CPU time 9.29 seconds
Started Aug 04 05:06:58 PM PDT 24
Finished Aug 04 05:07:07 PM PDT 24
Peak memory 195924 kb
Host smart-05346718-de7a-4b0c-a6a8-dacbda708cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161395966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2161395966
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1147437270
Short name T999
Test name
Test status
Simulation time 6296444924 ps
CPU time 23.68 seconds
Started Aug 04 05:06:56 PM PDT 24
Finished Aug 04 05:07:20 PM PDT 24
Peak memory 199456 kb
Host smart-e50096d2-2a44-427c-b245-d9b0f64b37cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147437270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1147437270
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1432644260
Short name T299
Test name
Test status
Simulation time 193998115031 ps
CPU time 156.39 seconds
Started Aug 04 05:07:03 PM PDT 24
Finished Aug 04 05:09:39 PM PDT 24
Peak memory 200140 kb
Host smart-03fd8097-620f-413c-803d-d8c7ec3390e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432644260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1432644260
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.4271153280
Short name T853
Test name
Test status
Simulation time 57786169271 ps
CPU time 515.28 seconds
Started Aug 04 05:06:58 PM PDT 24
Finished Aug 04 05:15:34 PM PDT 24
Peak memory 224672 kb
Host smart-1abbc07c-e2a5-4005-8591-4a7452783a9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271153280 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.4271153280
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2438747345
Short name T945
Test name
Test status
Simulation time 4157747287 ps
CPU time 2.35 seconds
Started Aug 04 05:07:00 PM PDT 24
Finished Aug 04 05:07:02 PM PDT 24
Peak memory 199828 kb
Host smart-e02872d5-4c09-4063-8eeb-ebfd9f06dafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438747345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2438747345
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3672709947
Short name T775
Test name
Test status
Simulation time 83761324081 ps
CPU time 97.28 seconds
Started Aug 04 05:06:54 PM PDT 24
Finished Aug 04 05:08:31 PM PDT 24
Peak memory 199832 kb
Host smart-419bb86c-4944-4922-ba15-d12584edb8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672709947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3672709947
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.4282367569
Short name T664
Test name
Test status
Simulation time 45230117085 ps
CPU time 18.74 seconds
Started Aug 04 05:11:27 PM PDT 24
Finished Aug 04 05:11:45 PM PDT 24
Peak memory 199756 kb
Host smart-671cbbf8-7614-4784-b66f-11c94ae4cfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282367569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.4282367569
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2634973790
Short name T1089
Test name
Test status
Simulation time 35902792588 ps
CPU time 62.67 seconds
Started Aug 04 05:11:23 PM PDT 24
Finished Aug 04 05:12:26 PM PDT 24
Peak memory 199760 kb
Host smart-0e394c2b-1d29-4e86-99df-4863c079df4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634973790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2634973790
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3600410158
Short name T633
Test name
Test status
Simulation time 55435096410 ps
CPU time 82.73 seconds
Started Aug 04 05:11:22 PM PDT 24
Finished Aug 04 05:12:45 PM PDT 24
Peak memory 199868 kb
Host smart-516d2e89-8138-43f5-9839-ee00f567d3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600410158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3600410158
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.905427329
Short name T131
Test name
Test status
Simulation time 30823772052 ps
CPU time 24.98 seconds
Started Aug 04 05:11:25 PM PDT 24
Finished Aug 04 05:11:50 PM PDT 24
Peak memory 199860 kb
Host smart-2303d59c-7680-40e6-9551-cc05063cf6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905427329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.905427329
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.79260972
Short name T869
Test name
Test status
Simulation time 47067267126 ps
CPU time 44.3 seconds
Started Aug 04 05:11:21 PM PDT 24
Finished Aug 04 05:12:06 PM PDT 24
Peak memory 199828 kb
Host smart-98dc9aae-d141-4e43-b027-0ebfb6003b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79260972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.79260972
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1695399814
Short name T41
Test name
Test status
Simulation time 27096836241 ps
CPU time 19.43 seconds
Started Aug 04 05:11:22 PM PDT 24
Finished Aug 04 05:11:42 PM PDT 24
Peak memory 199448 kb
Host smart-4953254a-bb90-4d42-aabd-856a386f392e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695399814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1695399814
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.451093957
Short name T403
Test name
Test status
Simulation time 93331692400 ps
CPU time 43.63 seconds
Started Aug 04 05:11:24 PM PDT 24
Finished Aug 04 05:12:08 PM PDT 24
Peak memory 199752 kb
Host smart-db9c1fa0-ccea-43e3-a962-96371d87bf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451093957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.451093957
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1825841504
Short name T632
Test name
Test status
Simulation time 114367783160 ps
CPU time 151.63 seconds
Started Aug 04 05:11:23 PM PDT 24
Finished Aug 04 05:13:55 PM PDT 24
Peak memory 199808 kb
Host smart-af1e1cc9-770f-4e26-9257-b0d8ac8b66da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825841504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1825841504
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3599172506
Short name T851
Test name
Test status
Simulation time 123031445677 ps
CPU time 176.96 seconds
Started Aug 04 05:11:25 PM PDT 24
Finished Aug 04 05:14:22 PM PDT 24
Peak memory 199788 kb
Host smart-7c4ea6bd-8522-44d7-9274-3170ef3d370c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599172506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3599172506
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.167733252
Short name T340
Test name
Test status
Simulation time 131569472528 ps
CPU time 93.57 seconds
Started Aug 04 05:11:23 PM PDT 24
Finished Aug 04 05:12:56 PM PDT 24
Peak memory 199776 kb
Host smart-16c88917-f605-4fbb-a9bc-2f917a676e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167733252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.167733252
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2963289081
Short name T405
Test name
Test status
Simulation time 21132839 ps
CPU time 0.61 seconds
Started Aug 04 05:07:10 PM PDT 24
Finished Aug 04 05:07:11 PM PDT 24
Peak memory 194260 kb
Host smart-2883edf6-919c-4984-a700-bb0a1c1949ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963289081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2963289081
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3434369846
Short name T1099
Test name
Test status
Simulation time 100820473513 ps
CPU time 99.4 seconds
Started Aug 04 05:07:02 PM PDT 24
Finished Aug 04 05:08:42 PM PDT 24
Peak memory 199868 kb
Host smart-ae4cfbc7-d0c5-47d4-8ced-036e14aaba90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434369846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3434369846
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1080473986
Short name T661
Test name
Test status
Simulation time 22118321162 ps
CPU time 38.16 seconds
Started Aug 04 05:07:02 PM PDT 24
Finished Aug 04 05:07:40 PM PDT 24
Peak memory 199872 kb
Host smart-9f88d105-fda5-40f8-9e5a-8920c029bb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080473986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1080473986
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.4236419029
Short name T13
Test name
Test status
Simulation time 49258340858 ps
CPU time 77.57 seconds
Started Aug 04 05:07:07 PM PDT 24
Finished Aug 04 05:08:25 PM PDT 24
Peak memory 198872 kb
Host smart-11ed1a0a-0e6a-4cbe-b3bd-adfee9778092
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236419029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.4236419029
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.157323573
Short name T483
Test name
Test status
Simulation time 103547461981 ps
CPU time 414.2 seconds
Started Aug 04 05:07:09 PM PDT 24
Finished Aug 04 05:14:03 PM PDT 24
Peak memory 199804 kb
Host smart-37fcd62d-5ecf-4b07-a093-b45e5f8f921a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=157323573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.157323573
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.2601479689
Short name T505
Test name
Test status
Simulation time 2949177987 ps
CPU time 2.94 seconds
Started Aug 04 05:07:06 PM PDT 24
Finished Aug 04 05:07:09 PM PDT 24
Peak memory 197844 kb
Host smart-dba04ec3-3001-415e-8085-30444ee42f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601479689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2601479689
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.502445483
Short name T568
Test name
Test status
Simulation time 2205466559 ps
CPU time 3.53 seconds
Started Aug 04 05:07:06 PM PDT 24
Finished Aug 04 05:07:10 PM PDT 24
Peak memory 194420 kb
Host smart-b03c816f-4c27-4704-a98d-aff6e5a72e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502445483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.502445483
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2842882494
Short name T995
Test name
Test status
Simulation time 14112626212 ps
CPU time 787.49 seconds
Started Aug 04 05:07:09 PM PDT 24
Finished Aug 04 05:20:16 PM PDT 24
Peak memory 199808 kb
Host smart-783a8491-fa75-452d-b64e-cf3b4f8c9f40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2842882494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2842882494
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1806199251
Short name T1055
Test name
Test status
Simulation time 6340289677 ps
CPU time 15.54 seconds
Started Aug 04 05:07:07 PM PDT 24
Finished Aug 04 05:07:22 PM PDT 24
Peak memory 198680 kb
Host smart-8e3a98f8-6c18-4750-adb5-c8fab9009d83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1806199251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1806199251
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1852791355
Short name T903
Test name
Test status
Simulation time 103529301447 ps
CPU time 27.6 seconds
Started Aug 04 05:07:07 PM PDT 24
Finished Aug 04 05:07:34 PM PDT 24
Peak memory 199728 kb
Host smart-c6c2be76-de9f-4495-85df-47a079f09fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852791355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1852791355
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2320481212
Short name T651
Test name
Test status
Simulation time 33726039300 ps
CPU time 26.13 seconds
Started Aug 04 05:07:07 PM PDT 24
Finished Aug 04 05:07:33 PM PDT 24
Peak memory 195976 kb
Host smart-6ff503c1-7595-468c-b2e4-699ef71f27d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320481212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2320481212
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3984772685
Short name T378
Test name
Test status
Simulation time 314418768 ps
CPU time 1 seconds
Started Aug 04 05:07:05 PM PDT 24
Finished Aug 04 05:07:06 PM PDT 24
Peak memory 198140 kb
Host smart-636bf3bf-862a-4a77-a66e-e07880f0a613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984772685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3984772685
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1213470465
Short name T105
Test name
Test status
Simulation time 46215195365 ps
CPU time 237.42 seconds
Started Aug 04 05:07:06 PM PDT 24
Finished Aug 04 05:11:03 PM PDT 24
Peak memory 216492 kb
Host smart-0a27ad15-d903-436d-a432-f5087fb0fd4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213470465 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1213470465
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3764453771
Short name T699
Test name
Test status
Simulation time 12561852198 ps
CPU time 43.7 seconds
Started Aug 04 05:07:06 PM PDT 24
Finished Aug 04 05:07:50 PM PDT 24
Peak memory 199700 kb
Host smart-86399f48-6830-4de0-b193-9392f653cc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764453771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3764453771
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2993890304
Short name T921
Test name
Test status
Simulation time 67670481426 ps
CPU time 64.49 seconds
Started Aug 04 05:07:02 PM PDT 24
Finished Aug 04 05:08:06 PM PDT 24
Peak memory 199856 kb
Host smart-256e8592-0db4-4d0f-a8cf-c216e4d243b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993890304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2993890304
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1316554332
Short name T902
Test name
Test status
Simulation time 23796967473 ps
CPU time 34.65 seconds
Started Aug 04 05:11:26 PM PDT 24
Finished Aug 04 05:12:00 PM PDT 24
Peak memory 199880 kb
Host smart-3b475e6f-0080-47aa-9a4b-9a8b5cd17149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316554332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1316554332
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.309189621
Short name T337
Test name
Test status
Simulation time 22373051012 ps
CPU time 38.11 seconds
Started Aug 04 05:11:22 PM PDT 24
Finished Aug 04 05:12:01 PM PDT 24
Peak memory 199884 kb
Host smart-a6961b1f-b86c-4c5f-b6bc-05f70532eeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309189621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.309189621
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3468705395
Short name T986
Test name
Test status
Simulation time 46755622160 ps
CPU time 33.96 seconds
Started Aug 04 05:11:25 PM PDT 24
Finished Aug 04 05:11:59 PM PDT 24
Peak memory 199604 kb
Host smart-09792790-6e91-4f27-99a4-597ddaf01677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468705395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3468705395
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.809723986
Short name T610
Test name
Test status
Simulation time 10226912642 ps
CPU time 18.42 seconds
Started Aug 04 05:11:25 PM PDT 24
Finished Aug 04 05:11:43 PM PDT 24
Peak memory 199788 kb
Host smart-1dab0d21-6490-4236-a319-9a3d09919c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809723986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.809723986
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.4256237875
Short name T552
Test name
Test status
Simulation time 371324315877 ps
CPU time 39.77 seconds
Started Aug 04 05:11:27 PM PDT 24
Finished Aug 04 05:12:07 PM PDT 24
Peak memory 199892 kb
Host smart-18b3f96e-59c7-473f-8d22-0dfff86ba145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256237875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.4256237875
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2999724644
Short name T256
Test name
Test status
Simulation time 19957468347 ps
CPU time 40.95 seconds
Started Aug 04 05:11:27 PM PDT 24
Finished Aug 04 05:12:08 PM PDT 24
Peak memory 199776 kb
Host smart-9ea4379d-e947-4573-999a-c71e5b96b674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999724644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2999724644
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3913902244
Short name T734
Test name
Test status
Simulation time 40841877 ps
CPU time 0.57 seconds
Started Aug 04 05:07:13 PM PDT 24
Finished Aug 04 05:07:14 PM PDT 24
Peak memory 195504 kb
Host smart-3973d441-62a1-40e1-b204-0c5cb7eb282d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913902244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3913902244
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2240064599
Short name T377
Test name
Test status
Simulation time 34260050857 ps
CPU time 55.68 seconds
Started Aug 04 05:07:10 PM PDT 24
Finished Aug 04 05:08:06 PM PDT 24
Peak memory 199784 kb
Host smart-5a73270b-0209-457d-925e-c1422259301e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240064599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2240064599
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.987882857
Short name T816
Test name
Test status
Simulation time 11858746875 ps
CPU time 13.39 seconds
Started Aug 04 05:07:12 PM PDT 24
Finished Aug 04 05:07:26 PM PDT 24
Peak memory 199756 kb
Host smart-29ef3553-1eae-4d37-82a5-a62c56efd4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987882857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.987882857
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3725788739
Short name T190
Test name
Test status
Simulation time 94513989440 ps
CPU time 131.92 seconds
Started Aug 04 05:07:11 PM PDT 24
Finished Aug 04 05:09:23 PM PDT 24
Peak memory 199824 kb
Host smart-ff09f0d5-f418-4a1f-879e-e75658f1b82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725788739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3725788739
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.891822056
Short name T1060
Test name
Test status
Simulation time 8007455025 ps
CPU time 3.79 seconds
Started Aug 04 05:07:10 PM PDT 24
Finished Aug 04 05:07:14 PM PDT 24
Peak memory 199680 kb
Host smart-2c480ae8-1a29-4a91-810a-89def718c8d6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891822056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.891822056
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2740090571
Short name T665
Test name
Test status
Simulation time 164277487599 ps
CPU time 260.41 seconds
Started Aug 04 05:07:13 PM PDT 24
Finished Aug 04 05:11:34 PM PDT 24
Peak memory 199868 kb
Host smart-7d51182b-38a6-44b5-9dc4-0997786e8159
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2740090571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2740090571
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3042086821
Short name T368
Test name
Test status
Simulation time 4295253286 ps
CPU time 10.83 seconds
Started Aug 04 05:07:14 PM PDT 24
Finished Aug 04 05:07:24 PM PDT 24
Peak memory 199796 kb
Host smart-31975952-c51e-4f15-8536-fe9afd7c01cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042086821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3042086821
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.2459107109
Short name T1166
Test name
Test status
Simulation time 9822434494 ps
CPU time 15.99 seconds
Started Aug 04 05:07:13 PM PDT 24
Finished Aug 04 05:07:29 PM PDT 24
Peak memory 199888 kb
Host smart-7b9649bf-958b-4436-acbe-60937a850565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459107109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2459107109
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.273907892
Short name T570
Test name
Test status
Simulation time 9704687009 ps
CPU time 454.6 seconds
Started Aug 04 05:07:14 PM PDT 24
Finished Aug 04 05:14:49 PM PDT 24
Peak memory 199844 kb
Host smart-73b46153-dc9c-48d0-8cb7-746c664892d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=273907892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.273907892
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1683777947
Short name T372
Test name
Test status
Simulation time 6609672338 ps
CPU time 15.38 seconds
Started Aug 04 05:07:09 PM PDT 24
Finished Aug 04 05:07:25 PM PDT 24
Peak memory 197940 kb
Host smart-d411caba-daab-4103-a255-33800c37008c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1683777947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1683777947
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2625684313
Short name T289
Test name
Test status
Simulation time 46783059765 ps
CPU time 39.16 seconds
Started Aug 04 05:07:14 PM PDT 24
Finished Aug 04 05:07:53 PM PDT 24
Peak memory 200120 kb
Host smart-a69bbe0f-d094-4e53-8952-c9f10a92f25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625684313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2625684313
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3441114543
Short name T678
Test name
Test status
Simulation time 5992635711 ps
CPU time 3.06 seconds
Started Aug 04 05:07:14 PM PDT 24
Finished Aug 04 05:07:17 PM PDT 24
Peak memory 195940 kb
Host smart-d19b3b5e-883d-46ea-8ba9-325b18e925df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441114543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3441114543
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.4050329525
Short name T1012
Test name
Test status
Simulation time 294783164 ps
CPU time 1.23 seconds
Started Aug 04 05:07:09 PM PDT 24
Finished Aug 04 05:07:10 PM PDT 24
Peak memory 198924 kb
Host smart-d3634a6d-ab3b-4fae-8853-77b26904d8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050329525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.4050329525
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2601378199
Short name T1015
Test name
Test status
Simulation time 146713290548 ps
CPU time 275.2 seconds
Started Aug 04 05:07:13 PM PDT 24
Finished Aug 04 05:11:49 PM PDT 24
Peak memory 199800 kb
Host smart-f8f18b78-beef-4ca4-b19a-a6c238f98262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601378199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2601378199
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.4253719781
Short name T908
Test name
Test status
Simulation time 43892024810 ps
CPU time 426.06 seconds
Started Aug 04 05:07:16 PM PDT 24
Finished Aug 04 05:14:23 PM PDT 24
Peak memory 208860 kb
Host smart-9feca6bf-7e52-4545-a99e-59aa54e11d76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253719781 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.4253719781
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3380321039
Short name T72
Test name
Test status
Simulation time 6980399229 ps
CPU time 26.1 seconds
Started Aug 04 05:07:14 PM PDT 24
Finished Aug 04 05:07:40 PM PDT 24
Peak memory 199836 kb
Host smart-7893dea2-607f-4cdb-b8da-ccf07cd56309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380321039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3380321039
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.757485178
Short name T779
Test name
Test status
Simulation time 52038870529 ps
CPU time 41.75 seconds
Started Aug 04 05:07:12 PM PDT 24
Finished Aug 04 05:07:53 PM PDT 24
Peak memory 199852 kb
Host smart-2de6e12e-86bc-4be1-98ed-8de00cc5f8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757485178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.757485178
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1029875451
Short name T705
Test name
Test status
Simulation time 37084423379 ps
CPU time 16.54 seconds
Started Aug 04 05:11:30 PM PDT 24
Finished Aug 04 05:11:46 PM PDT 24
Peak memory 199920 kb
Host smart-764584c8-5fe0-4e50-954a-0b63692c0264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029875451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1029875451
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1950804360
Short name T963
Test name
Test status
Simulation time 119283365712 ps
CPU time 40.03 seconds
Started Aug 04 05:11:26 PM PDT 24
Finished Aug 04 05:12:06 PM PDT 24
Peak memory 199884 kb
Host smart-cfc8e556-4dc6-4459-a4d2-34bc6a428419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950804360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1950804360
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3791162402
Short name T187
Test name
Test status
Simulation time 56864611586 ps
CPU time 28.74 seconds
Started Aug 04 05:11:30 PM PDT 24
Finished Aug 04 05:11:59 PM PDT 24
Peak memory 199892 kb
Host smart-4c41c5d5-6698-4e1e-bf91-bc79091dcb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791162402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3791162402
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.719294468
Short name T800
Test name
Test status
Simulation time 55532792491 ps
CPU time 41.51 seconds
Started Aug 04 05:11:30 PM PDT 24
Finished Aug 04 05:12:12 PM PDT 24
Peak memory 199820 kb
Host smart-937a9959-96ee-4197-95cc-911d8d2ec0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719294468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.719294468
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2642589198
Short name T224
Test name
Test status
Simulation time 182381639656 ps
CPU time 71.85 seconds
Started Aug 04 05:11:29 PM PDT 24
Finished Aug 04 05:12:41 PM PDT 24
Peak memory 199816 kb
Host smart-72b17558-d6cd-430e-8d4d-0ff68577d275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642589198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2642589198
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.4095569746
Short name T1010
Test name
Test status
Simulation time 78889780359 ps
CPU time 37.05 seconds
Started Aug 04 05:11:30 PM PDT 24
Finished Aug 04 05:12:07 PM PDT 24
Peak memory 199860 kb
Host smart-50357e12-04b7-43d3-9195-8db94541208e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095569746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.4095569746
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.951918747
Short name T739
Test name
Test status
Simulation time 86651775481 ps
CPU time 100.42 seconds
Started Aug 04 05:11:28 PM PDT 24
Finished Aug 04 05:13:08 PM PDT 24
Peak memory 199912 kb
Host smart-320c00fa-cd3d-484f-8677-3a770372101d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951918747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.951918747
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2971620986
Short name T991
Test name
Test status
Simulation time 20176383 ps
CPU time 0.52 seconds
Started Aug 04 05:07:17 PM PDT 24
Finished Aug 04 05:07:18 PM PDT 24
Peak memory 195552 kb
Host smart-85b76dc8-6f38-474a-9dc3-6491fd474e31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971620986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2971620986
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.3061527594
Short name T643
Test name
Test status
Simulation time 36386899678 ps
CPU time 58.06 seconds
Started Aug 04 05:07:17 PM PDT 24
Finished Aug 04 05:08:15 PM PDT 24
Peak memory 199852 kb
Host smart-6ba3306e-b538-4754-8a86-11a855c70dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061527594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3061527594
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.96932305
Short name T1135
Test name
Test status
Simulation time 17556700312 ps
CPU time 28.21 seconds
Started Aug 04 05:07:17 PM PDT 24
Finished Aug 04 05:07:46 PM PDT 24
Peak memory 199284 kb
Host smart-6c846478-ed2a-4264-aab1-45a8ed35590f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96932305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.96932305
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.3946938645
Short name T603
Test name
Test status
Simulation time 25246248546 ps
CPU time 41.89 seconds
Started Aug 04 05:07:16 PM PDT 24
Finished Aug 04 05:07:58 PM PDT 24
Peak memory 199784 kb
Host smart-f59cbde9-d24b-4c3c-a012-0d6c4d46f80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946938645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3946938645
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1316029957
Short name T761
Test name
Test status
Simulation time 195979966807 ps
CPU time 72.95 seconds
Started Aug 04 05:07:14 PM PDT 24
Finished Aug 04 05:08:27 PM PDT 24
Peak memory 197036 kb
Host smart-d2209f16-6112-4d96-b90d-b0f81adc6e27
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316029957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1316029957
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2401248911
Short name T765
Test name
Test status
Simulation time 243383005566 ps
CPU time 179.96 seconds
Started Aug 04 05:07:18 PM PDT 24
Finished Aug 04 05:10:18 PM PDT 24
Peak memory 199700 kb
Host smart-a531d3a7-6f39-41fc-8d68-003734e62af9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2401248911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2401248911
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3768683774
Short name T1021
Test name
Test status
Simulation time 1130913944 ps
CPU time 1.76 seconds
Started Aug 04 05:07:17 PM PDT 24
Finished Aug 04 05:07:19 PM PDT 24
Peak memory 198552 kb
Host smart-a7a33a84-d60f-464b-859d-c9f98d68fc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768683774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3768683774
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.2956610462
Short name T583
Test name
Test status
Simulation time 26562753138 ps
CPU time 61.71 seconds
Started Aug 04 05:07:17 PM PDT 24
Finished Aug 04 05:08:19 PM PDT 24
Peak memory 198616 kb
Host smart-9e7fd43b-b332-42f0-8dce-590d89f5a091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956610462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2956610462
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2519202557
Short name T840
Test name
Test status
Simulation time 34179415220 ps
CPU time 95.14 seconds
Started Aug 04 05:07:18 PM PDT 24
Finished Aug 04 05:08:53 PM PDT 24
Peak memory 199864 kb
Host smart-edfa482d-bb5f-4854-b713-ff5c061c1041
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2519202557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2519202557
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3639143171
Short name T846
Test name
Test status
Simulation time 6283615620 ps
CPU time 61.58 seconds
Started Aug 04 05:07:13 PM PDT 24
Finished Aug 04 05:08:15 PM PDT 24
Peak memory 198984 kb
Host smart-87a98221-e38c-4dbe-9e63-1467105ec47d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3639143171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3639143171
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3616252400
Short name T161
Test name
Test status
Simulation time 36392579950 ps
CPU time 6.98 seconds
Started Aug 04 05:07:17 PM PDT 24
Finished Aug 04 05:07:24 PM PDT 24
Peak memory 199820 kb
Host smart-4b51cd7a-3ee7-450f-9264-04a8729174b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616252400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3616252400
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3825582698
Short name T860
Test name
Test status
Simulation time 577222327 ps
CPU time 1.59 seconds
Started Aug 04 05:07:18 PM PDT 24
Finished Aug 04 05:07:19 PM PDT 24
Peak memory 195440 kb
Host smart-ab3ef9d2-19d5-428b-b870-7c1acf7a2c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825582698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3825582698
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.368917337
Short name T946
Test name
Test status
Simulation time 495518283 ps
CPU time 1.1 seconds
Started Aug 04 05:07:13 PM PDT 24
Finished Aug 04 05:07:14 PM PDT 24
Peak memory 197916 kb
Host smart-3db474f0-e8e9-470e-85c1-97e6008b7d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368917337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.368917337
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3348494838
Short name T1132
Test name
Test status
Simulation time 277207148637 ps
CPU time 399.46 seconds
Started Aug 04 05:07:19 PM PDT 24
Finished Aug 04 05:13:58 PM PDT 24
Peak memory 199864 kb
Host smart-dd5f514a-acde-47b1-9f38-05496edeb977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348494838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3348494838
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3630851885
Short name T62
Test name
Test status
Simulation time 88987533546 ps
CPU time 1292.17 seconds
Started Aug 04 05:07:17 PM PDT 24
Finished Aug 04 05:28:49 PM PDT 24
Peak memory 216428 kb
Host smart-3bf16bc5-d7c7-469b-8124-013d2e0b263f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630851885 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3630851885
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1678171420
Short name T1122
Test name
Test status
Simulation time 1950641337 ps
CPU time 2.97 seconds
Started Aug 04 05:07:18 PM PDT 24
Finished Aug 04 05:07:21 PM PDT 24
Peak memory 198824 kb
Host smart-4251adbb-001a-40e9-8d97-9f1fc64cd042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678171420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1678171420
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.54949790
Short name T863
Test name
Test status
Simulation time 390990072136 ps
CPU time 41.65 seconds
Started Aug 04 05:07:14 PM PDT 24
Finished Aug 04 05:07:56 PM PDT 24
Peak memory 199864 kb
Host smart-c4392e53-52f7-414a-b90d-a4ae9b9fce40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54949790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.54949790
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.257784326
Short name T479
Test name
Test status
Simulation time 73210288375 ps
CPU time 113.16 seconds
Started Aug 04 05:11:31 PM PDT 24
Finished Aug 04 05:13:25 PM PDT 24
Peak memory 199836 kb
Host smart-5f167982-8bcc-4a31-8089-fd2a4f0a2c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257784326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.257784326
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2065729581
Short name T938
Test name
Test status
Simulation time 16527230201 ps
CPU time 25.66 seconds
Started Aug 04 05:11:32 PM PDT 24
Finished Aug 04 05:11:57 PM PDT 24
Peak memory 199768 kb
Host smart-05a3c8fd-8c84-439a-af70-0398068c2063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065729581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2065729581
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2999380502
Short name T500
Test name
Test status
Simulation time 137515503731 ps
CPU time 43.29 seconds
Started Aug 04 05:11:33 PM PDT 24
Finished Aug 04 05:12:17 PM PDT 24
Peak memory 200084 kb
Host smart-35dbdb61-4fd3-4dac-bd7f-e1648334095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999380502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2999380502
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3799033671
Short name T744
Test name
Test status
Simulation time 19105190083 ps
CPU time 9.54 seconds
Started Aug 04 05:11:34 PM PDT 24
Finished Aug 04 05:11:43 PM PDT 24
Peak memory 199720 kb
Host smart-7469e513-d3ab-4865-952a-77b11a90ee76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799033671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3799033671
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2002884107
Short name T782
Test name
Test status
Simulation time 95910658314 ps
CPU time 179.24 seconds
Started Aug 04 05:11:33 PM PDT 24
Finished Aug 04 05:14:32 PM PDT 24
Peak memory 199896 kb
Host smart-fc68086d-ed22-4bcc-9c4a-22d922f5caea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002884107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2002884107
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.13774926
Short name T1066
Test name
Test status
Simulation time 21313782590 ps
CPU time 17.41 seconds
Started Aug 04 05:11:30 PM PDT 24
Finished Aug 04 05:11:47 PM PDT 24
Peak memory 199844 kb
Host smart-43400900-e299-4ca2-9bbe-274cabb56705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13774926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.13774926
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2368881738
Short name T178
Test name
Test status
Simulation time 4885110698 ps
CPU time 4.44 seconds
Started Aug 04 05:11:33 PM PDT 24
Finished Aug 04 05:11:37 PM PDT 24
Peak memory 199816 kb
Host smart-0664076d-0562-428e-a9b4-050f9f9c49e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368881738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2368881738
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2335178002
Short name T659
Test name
Test status
Simulation time 43308711305 ps
CPU time 67.44 seconds
Started Aug 04 05:11:33 PM PDT 24
Finished Aug 04 05:12:41 PM PDT 24
Peak memory 200144 kb
Host smart-d33d44bc-f008-4386-8cd1-d013e409a9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335178002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2335178002
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_full.4241055657
Short name T1001
Test name
Test status
Simulation time 44644665612 ps
CPU time 71.91 seconds
Started Aug 04 05:07:20 PM PDT 24
Finished Aug 04 05:08:32 PM PDT 24
Peak memory 199784 kb
Host smart-fa577f4c-ee4b-41ec-b755-24a16253acf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241055657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.4241055657
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3352311286
Short name T1026
Test name
Test status
Simulation time 222778415929 ps
CPU time 48.33 seconds
Started Aug 04 05:07:21 PM PDT 24
Finished Aug 04 05:08:10 PM PDT 24
Peak memory 199788 kb
Host smart-8b3954bd-1bfa-4c6b-84b0-d2935020524d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352311286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3352311286
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2913950667
Short name T344
Test name
Test status
Simulation time 276895251564 ps
CPU time 30.78 seconds
Started Aug 04 05:07:20 PM PDT 24
Finished Aug 04 05:07:51 PM PDT 24
Peak memory 199836 kb
Host smart-5604b2c2-988b-4c95-8c52-34e3113c134b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913950667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2913950667
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.3011941935
Short name T1082
Test name
Test status
Simulation time 23817003614 ps
CPU time 10.81 seconds
Started Aug 04 05:07:25 PM PDT 24
Finished Aug 04 05:07:36 PM PDT 24
Peak memory 199060 kb
Host smart-cfa6a10b-4e0b-46a6-85de-5e3c79991993
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011941935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3011941935
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3367543933
Short name T901
Test name
Test status
Simulation time 135513395504 ps
CPU time 320.57 seconds
Started Aug 04 05:07:29 PM PDT 24
Finished Aug 04 05:12:50 PM PDT 24
Peak memory 199752 kb
Host smart-32ebb459-e9da-4700-96de-68832586653c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3367543933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3367543933
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.755368510
Short name T347
Test name
Test status
Simulation time 2112808087 ps
CPU time 2.49 seconds
Started Aug 04 05:07:27 PM PDT 24
Finished Aug 04 05:07:30 PM PDT 24
Peak memory 196028 kb
Host smart-3cd1c44c-f533-45c7-a23d-2a36d7d3a3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755368510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.755368510
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.3926889519
Short name T293
Test name
Test status
Simulation time 146814392323 ps
CPU time 28.68 seconds
Started Aug 04 05:07:27 PM PDT 24
Finished Aug 04 05:07:56 PM PDT 24
Peak memory 207548 kb
Host smart-e06ad674-1da6-45d7-a3a2-37849e5ba8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926889519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3926889519
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.1727222745
Short name T553
Test name
Test status
Simulation time 33302401338 ps
CPU time 116.48 seconds
Started Aug 04 05:07:24 PM PDT 24
Finished Aug 04 05:09:21 PM PDT 24
Peak memory 199756 kb
Host smart-f00a4e6a-a72f-4ff7-b816-aa3b0e151386
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1727222745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1727222745
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1220673994
Short name T351
Test name
Test status
Simulation time 6143733209 ps
CPU time 9.88 seconds
Started Aug 04 05:07:24 PM PDT 24
Finished Aug 04 05:07:34 PM PDT 24
Peak memory 199420 kb
Host smart-778bf797-917f-4f89-84af-5628207ef0e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1220673994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1220673994
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.455268240
Short name T531
Test name
Test status
Simulation time 66203079215 ps
CPU time 103.34 seconds
Started Aug 04 05:07:24 PM PDT 24
Finished Aug 04 05:09:07 PM PDT 24
Peak memory 199804 kb
Host smart-be137d80-9b55-4dba-a3da-46a3aff0c9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455268240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.455268240
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1114747786
Short name T363
Test name
Test status
Simulation time 2996677159 ps
CPU time 4.8 seconds
Started Aug 04 05:07:26 PM PDT 24
Finished Aug 04 05:07:31 PM PDT 24
Peak memory 195928 kb
Host smart-3c07310c-bc48-4255-b78a-ef0b01045429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114747786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1114747786
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.360297188
Short name T1043
Test name
Test status
Simulation time 452034442 ps
CPU time 3.18 seconds
Started Aug 04 05:07:20 PM PDT 24
Finished Aug 04 05:07:23 PM PDT 24
Peak memory 198060 kb
Host smart-4e9b192a-098f-4a87-b955-bd689c9f945d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360297188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.360297188
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2916147671
Short name T989
Test name
Test status
Simulation time 619541325017 ps
CPU time 119.91 seconds
Started Aug 04 05:07:29 PM PDT 24
Finished Aug 04 05:09:29 PM PDT 24
Peak memory 208164 kb
Host smart-6b1656e6-8ff4-4a62-8e7e-79ed6d5b2dd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916147671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2916147671
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1034951779
Short name T630
Test name
Test status
Simulation time 71712001580 ps
CPU time 952.16 seconds
Started Aug 04 05:07:28 PM PDT 24
Finished Aug 04 05:23:21 PM PDT 24
Peak memory 226204 kb
Host smart-9d3e3e4c-2df5-407c-95c8-613d42f191c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034951779 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1034951779
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.83701461
Short name T452
Test name
Test status
Simulation time 12537402590 ps
CPU time 11.98 seconds
Started Aug 04 05:07:23 PM PDT 24
Finished Aug 04 05:07:35 PM PDT 24
Peak memory 199744 kb
Host smart-6ada8738-183f-487f-8b88-25519083b0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83701461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.83701461
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.4182661396
Short name T813
Test name
Test status
Simulation time 14532214496 ps
CPU time 26.78 seconds
Started Aug 04 05:07:21 PM PDT 24
Finished Aug 04 05:07:48 PM PDT 24
Peak memory 199864 kb
Host smart-5dc41d5b-60de-49c6-a697-6c76b4efea87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182661396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.4182661396
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2566501835
Short name T759
Test name
Test status
Simulation time 207378843418 ps
CPU time 26.61 seconds
Started Aug 04 05:11:32 PM PDT 24
Finished Aug 04 05:11:59 PM PDT 24
Peak memory 199780 kb
Host smart-f126b1f5-be19-476d-a2f1-53d425b9a9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566501835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2566501835
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2683742831
Short name T644
Test name
Test status
Simulation time 31418231381 ps
CPU time 88.9 seconds
Started Aug 04 05:11:34 PM PDT 24
Finished Aug 04 05:13:03 PM PDT 24
Peak memory 199752 kb
Host smart-d3617650-2e51-4f08-821d-7014f211ef33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683742831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2683742831
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3408234497
Short name T807
Test name
Test status
Simulation time 18072794803 ps
CPU time 19.15 seconds
Started Aug 04 05:11:31 PM PDT 24
Finished Aug 04 05:11:50 PM PDT 24
Peak memory 199800 kb
Host smart-4e57a940-51d8-4886-a281-8ce2210bc4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408234497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3408234497
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.4157186901
Short name T28
Test name
Test status
Simulation time 47623955298 ps
CPU time 14.82 seconds
Started Aug 04 05:11:31 PM PDT 24
Finished Aug 04 05:11:46 PM PDT 24
Peak memory 199776 kb
Host smart-d546d17a-ad91-47c6-aeb1-51abe4d58fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157186901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.4157186901
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3164249624
Short name T729
Test name
Test status
Simulation time 44831859640 ps
CPU time 89.76 seconds
Started Aug 04 05:11:32 PM PDT 24
Finished Aug 04 05:13:02 PM PDT 24
Peak memory 199780 kb
Host smart-de43ef1a-8400-4a08-b90d-84dc1ac18c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164249624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3164249624
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1729523333
Short name T741
Test name
Test status
Simulation time 177801565200 ps
CPU time 87.86 seconds
Started Aug 04 05:11:35 PM PDT 24
Finished Aug 04 05:13:03 PM PDT 24
Peak memory 199728 kb
Host smart-897d1795-9e41-4e88-819f-a5556e8ec209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729523333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1729523333
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.4217320464
Short name T934
Test name
Test status
Simulation time 91580881487 ps
CPU time 31 seconds
Started Aug 04 05:11:35 PM PDT 24
Finished Aug 04 05:12:06 PM PDT 24
Peak memory 199852 kb
Host smart-972ee8ee-5145-4cf8-823c-8944a90df3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217320464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.4217320464
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.816111658
Short name T485
Test name
Test status
Simulation time 67528590885 ps
CPU time 10.42 seconds
Started Aug 04 05:11:35 PM PDT 24
Finished Aug 04 05:11:46 PM PDT 24
Peak memory 199876 kb
Host smart-e3726640-973a-4bfc-a87f-27967c068093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816111658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.816111658
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.407219988
Short name T690
Test name
Test status
Simulation time 27264273801 ps
CPU time 43.13 seconds
Started Aug 04 05:11:35 PM PDT 24
Finished Aug 04 05:12:18 PM PDT 24
Peak memory 199884 kb
Host smart-d39c70a1-ad61-4ccb-9f74-789f641573cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407219988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.407219988
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1252770357
Short name T456
Test name
Test status
Simulation time 46241591 ps
CPU time 0.55 seconds
Started Aug 04 05:07:36 PM PDT 24
Finished Aug 04 05:07:37 PM PDT 24
Peak memory 195232 kb
Host smart-782cde66-7767-4444-a320-b602ab6c5d86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252770357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1252770357
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.224296952
Short name T820
Test name
Test status
Simulation time 23415906553 ps
CPU time 34.77 seconds
Started Aug 04 05:07:38 PM PDT 24
Finished Aug 04 05:08:12 PM PDT 24
Peak memory 199836 kb
Host smart-a2dcca44-627d-4d40-b033-9e5d03b81e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224296952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.224296952
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.239733661
Short name T841
Test name
Test status
Simulation time 137959206159 ps
CPU time 56.97 seconds
Started Aug 04 05:07:29 PM PDT 24
Finished Aug 04 05:08:26 PM PDT 24
Peak memory 199820 kb
Host smart-c8101ed6-b1b7-48f1-a3a5-72db266ce019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239733661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.239733661
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3656071512
Short name T888
Test name
Test status
Simulation time 42578633548 ps
CPU time 20.02 seconds
Started Aug 04 05:07:28 PM PDT 24
Finished Aug 04 05:07:48 PM PDT 24
Peak memory 198688 kb
Host smart-fb2005a6-d447-4646-b890-a40b3e0bd33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656071512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3656071512
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.514562919
Short name T259
Test name
Test status
Simulation time 14105127953 ps
CPU time 14.5 seconds
Started Aug 04 05:07:36 PM PDT 24
Finished Aug 04 05:07:50 PM PDT 24
Peak memory 199624 kb
Host smart-3e7f58cb-5e83-4bc9-a8b1-bafdf6b58719
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514562919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.514562919
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.4293990824
Short name T408
Test name
Test status
Simulation time 107928168727 ps
CPU time 626.3 seconds
Started Aug 04 05:07:35 PM PDT 24
Finished Aug 04 05:18:01 PM PDT 24
Peak memory 199864 kb
Host smart-178bc033-f453-462a-a052-7760eeda7d1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4293990824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.4293990824
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.208848561
Short name T396
Test name
Test status
Simulation time 10615978243 ps
CPU time 3.54 seconds
Started Aug 04 05:07:32 PM PDT 24
Finished Aug 04 05:07:36 PM PDT 24
Peak memory 199884 kb
Host smart-b02970d2-2d5f-4b22-a5f8-77bdc17bcda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208848561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.208848561
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1941296114
Short name T787
Test name
Test status
Simulation time 74808210640 ps
CPU time 16.59 seconds
Started Aug 04 05:07:32 PM PDT 24
Finished Aug 04 05:07:49 PM PDT 24
Peak memory 194436 kb
Host smart-75131ab7-ad1e-4849-96a8-caa2ad71f361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941296114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1941296114
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.3245744489
Short name T700
Test name
Test status
Simulation time 15219666099 ps
CPU time 419.41 seconds
Started Aug 04 05:07:33 PM PDT 24
Finished Aug 04 05:14:33 PM PDT 24
Peak memory 199936 kb
Host smart-190623ac-4d6c-47c9-b26b-87d2a20c0276
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3245744489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3245744489
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3452312182
Short name T366
Test name
Test status
Simulation time 5162640778 ps
CPU time 10.33 seconds
Started Aug 04 05:07:33 PM PDT 24
Finished Aug 04 05:07:44 PM PDT 24
Peak memory 197992 kb
Host smart-905d4855-2427-4ce5-9ddf-e9945e96e157
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3452312182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3452312182
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.912448577
Short name T415
Test name
Test status
Simulation time 28784762566 ps
CPU time 41.87 seconds
Started Aug 04 05:07:32 PM PDT 24
Finished Aug 04 05:08:15 PM PDT 24
Peak memory 199780 kb
Host smart-70cb43ce-7c48-4aff-b18b-36069ed54480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912448577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.912448577
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.4261074111
Short name T1076
Test name
Test status
Simulation time 3639576271 ps
CPU time 3.42 seconds
Started Aug 04 05:07:33 PM PDT 24
Finished Aug 04 05:07:37 PM PDT 24
Peak memory 195608 kb
Host smart-e54f5d7c-b6a8-48cc-866e-80af901b3e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261074111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.4261074111
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.830837397
Short name T1174
Test name
Test status
Simulation time 6269660013 ps
CPU time 9.08 seconds
Started Aug 04 05:07:38 PM PDT 24
Finished Aug 04 05:07:48 PM PDT 24
Peak memory 199136 kb
Host smart-89aec399-3a83-483e-8650-7745be363145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830837397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.830837397
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.4113490477
Short name T1140
Test name
Test status
Simulation time 1090927112 ps
CPU time 2.68 seconds
Started Aug 04 05:07:32 PM PDT 24
Finished Aug 04 05:07:35 PM PDT 24
Peak memory 198932 kb
Host smart-d35dbce7-5706-4b2c-8c57-679ae74df676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113490477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.4113490477
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3159420576
Short name T243
Test name
Test status
Simulation time 101590806869 ps
CPU time 55.34 seconds
Started Aug 04 05:07:27 PM PDT 24
Finished Aug 04 05:08:23 PM PDT 24
Peak memory 199844 kb
Host smart-6039d3fe-7f2b-4ed2-b036-efb9a50bc862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159420576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3159420576
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.1447453793
Short name T828
Test name
Test status
Simulation time 137493654725 ps
CPU time 193.83 seconds
Started Aug 04 05:11:36 PM PDT 24
Finished Aug 04 05:14:50 PM PDT 24
Peak memory 199860 kb
Host smart-b885df0c-d69f-447c-b19c-43db37916860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447453793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1447453793
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3655614448
Short name T199
Test name
Test status
Simulation time 368197643715 ps
CPU time 56.99 seconds
Started Aug 04 05:11:40 PM PDT 24
Finished Aug 04 05:12:37 PM PDT 24
Peak memory 199912 kb
Host smart-eba3e790-29ab-47bc-8492-36bd9b75071b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655614448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3655614448
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3110322613
Short name T45
Test name
Test status
Simulation time 75834375145 ps
CPU time 28.16 seconds
Started Aug 04 05:11:39 PM PDT 24
Finished Aug 04 05:12:07 PM PDT 24
Peak memory 199916 kb
Host smart-432e6d43-7c1d-4b79-85ff-fc3c5288734a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110322613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3110322613
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2600015344
Short name T601
Test name
Test status
Simulation time 116950974844 ps
CPU time 31.58 seconds
Started Aug 04 05:11:39 PM PDT 24
Finished Aug 04 05:12:11 PM PDT 24
Peak memory 199844 kb
Host smart-5cd07745-eb69-42d4-b03d-ece325a0311a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600015344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2600015344
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2733210102
Short name T968
Test name
Test status
Simulation time 41362517227 ps
CPU time 154.3 seconds
Started Aug 04 05:11:38 PM PDT 24
Finished Aug 04 05:14:13 PM PDT 24
Peak memory 199908 kb
Host smart-75f71ebd-bd2a-4ea7-9a94-26df6f409a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733210102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2733210102
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.466971185
Short name T207
Test name
Test status
Simulation time 313324055930 ps
CPU time 80.03 seconds
Started Aug 04 05:11:40 PM PDT 24
Finished Aug 04 05:13:00 PM PDT 24
Peak memory 199852 kb
Host smart-7d299876-0666-48ce-9f7b-1593418f53b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466971185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.466971185
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2169553783
Short name T852
Test name
Test status
Simulation time 22404324014 ps
CPU time 34.27 seconds
Started Aug 04 05:11:39 PM PDT 24
Finished Aug 04 05:12:14 PM PDT 24
Peak memory 199752 kb
Host smart-d5132495-9709-4998-b29d-d6fbde690a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169553783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2169553783
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2183214540
Short name T211
Test name
Test status
Simulation time 205749175927 ps
CPU time 163.94 seconds
Started Aug 04 05:11:38 PM PDT 24
Finished Aug 04 05:14:22 PM PDT 24
Peak memory 199800 kb
Host smart-45478aab-a095-41d4-8e8b-88a0479d7344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183214540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2183214540
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.915301181
Short name T251
Test name
Test status
Simulation time 10379909378 ps
CPU time 20.58 seconds
Started Aug 04 05:11:43 PM PDT 24
Finished Aug 04 05:12:04 PM PDT 24
Peak memory 199892 kb
Host smart-71c1a9be-821a-4382-b6b1-9b6117aa225f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915301181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.915301181
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2403437395
Short name T457
Test name
Test status
Simulation time 43802691 ps
CPU time 0.55 seconds
Started Aug 04 05:07:57 PM PDT 24
Finished Aug 04 05:07:57 PM PDT 24
Peak memory 195580 kb
Host smart-ac9c63f8-7b8a-4ffa-92a8-dc6676f77618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403437395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2403437395
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2479231643
Short name T910
Test name
Test status
Simulation time 58410454279 ps
CPU time 96.06 seconds
Started Aug 04 05:07:37 PM PDT 24
Finished Aug 04 05:09:13 PM PDT 24
Peak memory 199856 kb
Host smart-892f79f6-4c9b-4761-af93-d3c08bcd670a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479231643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2479231643
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3350497017
Short name T246
Test name
Test status
Simulation time 44601683791 ps
CPU time 67.47 seconds
Started Aug 04 05:07:40 PM PDT 24
Finished Aug 04 05:08:48 PM PDT 24
Peak memory 199876 kb
Host smart-a6599bca-7a06-47bc-b3fb-e5d6bf85e61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350497017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3350497017
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_intr.2225224432
Short name T778
Test name
Test status
Simulation time 273991892429 ps
CPU time 106.59 seconds
Started Aug 04 05:07:36 PM PDT 24
Finished Aug 04 05:09:23 PM PDT 24
Peak memory 199804 kb
Host smart-402887b9-d4fc-4633-9e7b-4f1a015f23f3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225224432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2225224432
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1388871322
Short name T1112
Test name
Test status
Simulation time 145493123028 ps
CPU time 1151.66 seconds
Started Aug 04 05:07:43 PM PDT 24
Finished Aug 04 05:26:55 PM PDT 24
Peak memory 199808 kb
Host smart-976d516b-c6f8-4a11-a872-a99933f57ed2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388871322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1388871322
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1882821282
Short name T730
Test name
Test status
Simulation time 2433449781 ps
CPU time 3.78 seconds
Started Aug 04 05:07:41 PM PDT 24
Finished Aug 04 05:07:45 PM PDT 24
Peak memory 195720 kb
Host smart-517e19e2-e661-4342-b19b-a582420d6d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882821282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1882821282
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.309905059
Short name T850
Test name
Test status
Simulation time 14769933987 ps
CPU time 29.1 seconds
Started Aug 04 05:07:37 PM PDT 24
Finished Aug 04 05:08:06 PM PDT 24
Peak memory 198112 kb
Host smart-04a9baaf-f7b7-45f6-b58b-8024b100d7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309905059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.309905059
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.220832291
Short name T622
Test name
Test status
Simulation time 14468213010 ps
CPU time 449.12 seconds
Started Aug 04 05:07:42 PM PDT 24
Finished Aug 04 05:15:11 PM PDT 24
Peak memory 199916 kb
Host smart-dbcf0dc7-0a7d-48ad-a02d-f86d7b6a6bae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=220832291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.220832291
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1268719810
Short name T362
Test name
Test status
Simulation time 4995551140 ps
CPU time 44.06 seconds
Started Aug 04 05:07:37 PM PDT 24
Finished Aug 04 05:08:21 PM PDT 24
Peak memory 199100 kb
Host smart-b67d278e-c595-4a3c-83c4-b2a6fb325a29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1268719810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1268719810
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2927125079
Short name T489
Test name
Test status
Simulation time 144162636020 ps
CPU time 137.43 seconds
Started Aug 04 05:07:37 PM PDT 24
Finished Aug 04 05:09:54 PM PDT 24
Peak memory 199764 kb
Host smart-c79bb2d5-4b0e-4950-813b-e9abc0f42355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927125079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2927125079
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3898108946
Short name T718
Test name
Test status
Simulation time 682229917 ps
CPU time 1.61 seconds
Started Aug 04 05:07:38 PM PDT 24
Finished Aug 04 05:07:40 PM PDT 24
Peak memory 195444 kb
Host smart-815b47fa-229b-4f77-a358-d957fe53a85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898108946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3898108946
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1471926939
Short name T394
Test name
Test status
Simulation time 534127016 ps
CPU time 2.48 seconds
Started Aug 04 05:07:47 PM PDT 24
Finished Aug 04 05:07:50 PM PDT 24
Peak memory 198176 kb
Host smart-72fbe240-6643-4310-b21f-a34e9e4480e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471926939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1471926939
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1237637804
Short name T450
Test name
Test status
Simulation time 451852854 ps
CPU time 1.51 seconds
Started Aug 04 05:07:36 PM PDT 24
Finished Aug 04 05:07:38 PM PDT 24
Peak memory 197428 kb
Host smart-72e501bf-41fc-4dc8-9754-b2a2dcee52f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237637804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1237637804
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.238843811
Short name T314
Test name
Test status
Simulation time 23652855557 ps
CPU time 33.02 seconds
Started Aug 04 05:07:38 PM PDT 24
Finished Aug 04 05:08:11 PM PDT 24
Peak memory 199808 kb
Host smart-7faee455-9a73-4c2d-8fe3-5b0eaca60342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238843811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.238843811
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.603141195
Short name T165
Test name
Test status
Simulation time 119014348668 ps
CPU time 44.59 seconds
Started Aug 04 05:11:44 PM PDT 24
Finished Aug 04 05:12:28 PM PDT 24
Peak memory 199732 kb
Host smart-e2c4febd-2ee2-4c7c-a4ce-5ba169162b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603141195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.603141195
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1610744999
Short name T623
Test name
Test status
Simulation time 97405689545 ps
CPU time 12.56 seconds
Started Aug 04 05:11:43 PM PDT 24
Finished Aug 04 05:11:55 PM PDT 24
Peak memory 199864 kb
Host smart-29b492f2-aee5-4b77-a9ca-30a5a32546af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610744999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1610744999
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.463138387
Short name T1092
Test name
Test status
Simulation time 11923827186 ps
CPU time 6.46 seconds
Started Aug 04 05:11:43 PM PDT 24
Finished Aug 04 05:11:50 PM PDT 24
Peak memory 199856 kb
Host smart-871b0009-2b90-44c0-ba05-6c3bfa22c081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463138387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.463138387
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2821154295
Short name T1170
Test name
Test status
Simulation time 23859054263 ps
CPU time 12.4 seconds
Started Aug 04 05:11:45 PM PDT 24
Finished Aug 04 05:11:57 PM PDT 24
Peak memory 199748 kb
Host smart-345778e1-1d44-41fc-b617-f566182d4bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821154295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2821154295
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2438749611
Short name T791
Test name
Test status
Simulation time 16492684351 ps
CPU time 25.73 seconds
Started Aug 04 05:11:43 PM PDT 24
Finished Aug 04 05:12:09 PM PDT 24
Peak memory 199816 kb
Host smart-4b1baff4-bed1-4499-adbb-876d00f93c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438749611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2438749611
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3280221438
Short name T1101
Test name
Test status
Simulation time 160988292418 ps
CPU time 109.29 seconds
Started Aug 04 05:11:44 PM PDT 24
Finished Aug 04 05:13:33 PM PDT 24
Peak memory 199776 kb
Host smart-426bb270-9af0-4e79-9f35-d8d5f44f1512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280221438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3280221438
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3347628886
Short name T745
Test name
Test status
Simulation time 138147870277 ps
CPU time 229.04 seconds
Started Aug 04 05:11:49 PM PDT 24
Finished Aug 04 05:15:38 PM PDT 24
Peak memory 199904 kb
Host smart-04c930f3-69a0-401a-b239-77a1c1262b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347628886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3347628886
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.816573458
Short name T647
Test name
Test status
Simulation time 145455397861 ps
CPU time 66.25 seconds
Started Aug 04 05:11:47 PM PDT 24
Finished Aug 04 05:12:54 PM PDT 24
Peak memory 199788 kb
Host smart-f7f5a803-317a-4fda-971f-7207e6bc6272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816573458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.816573458
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3765295580
Short name T1169
Test name
Test status
Simulation time 51073642358 ps
CPU time 26.96 seconds
Started Aug 04 05:11:48 PM PDT 24
Finished Aug 04 05:12:15 PM PDT 24
Peak memory 199808 kb
Host smart-6b58f382-20c3-4b8d-812d-85f9b66f30d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765295580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3765295580
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1836040957
Short name T338
Test name
Test status
Simulation time 194060764162 ps
CPU time 82.76 seconds
Started Aug 04 05:11:48 PM PDT 24
Finished Aug 04 05:13:11 PM PDT 24
Peak memory 199860 kb
Host smart-7fc6c2e0-13b0-4a1c-bf08-cae926d61080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836040957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1836040957
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.4006486719
Short name T649
Test name
Test status
Simulation time 42338639 ps
CPU time 0.58 seconds
Started Aug 04 05:07:45 PM PDT 24
Finished Aug 04 05:07:46 PM PDT 24
Peak memory 195276 kb
Host smart-fad659f3-14f9-42da-b84a-ad0bed3c0396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006486719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.4006486719
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.4171942864
Short name T3
Test name
Test status
Simulation time 113487540288 ps
CPU time 189.79 seconds
Started Aug 04 05:07:40 PM PDT 24
Finished Aug 04 05:10:50 PM PDT 24
Peak memory 199848 kb
Host smart-4de3f0ac-a413-4db9-a276-9e2b6899df98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171942864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.4171942864
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.836925355
Short name T449
Test name
Test status
Simulation time 115271369827 ps
CPU time 42.58 seconds
Started Aug 04 05:07:41 PM PDT 24
Finished Aug 04 05:08:23 PM PDT 24
Peak memory 199840 kb
Host smart-a04677ad-fc5e-43a9-a39f-189171595d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836925355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.836925355
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2598853622
Short name T798
Test name
Test status
Simulation time 112751528898 ps
CPU time 43.78 seconds
Started Aug 04 05:07:43 PM PDT 24
Finished Aug 04 05:08:27 PM PDT 24
Peak memory 199544 kb
Host smart-15cd4039-1482-457a-a727-323934ba7606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598853622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2598853622
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.4099980355
Short name T1177
Test name
Test status
Simulation time 64970479860 ps
CPU time 15.72 seconds
Started Aug 04 05:07:41 PM PDT 24
Finished Aug 04 05:07:56 PM PDT 24
Peak memory 199564 kb
Host smart-a218176b-2dcb-4ba9-b224-d6888da25c57
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099980355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.4099980355
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1032027844
Short name T931
Test name
Test status
Simulation time 67757119701 ps
CPU time 174.47 seconds
Started Aug 04 05:07:44 PM PDT 24
Finished Aug 04 05:10:38 PM PDT 24
Peak memory 199876 kb
Host smart-0af9cc4c-52e1-4058-9780-d1a25bef4c10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1032027844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1032027844
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.918805759
Short name T1162
Test name
Test status
Simulation time 9015453280 ps
CPU time 2.69 seconds
Started Aug 04 05:07:44 PM PDT 24
Finished Aug 04 05:07:46 PM PDT 24
Peak memory 199524 kb
Host smart-6c72a4d6-da1f-4636-aa4b-c5537fe93050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918805759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.918805759
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2378551849
Short name T927
Test name
Test status
Simulation time 128226035558 ps
CPU time 67.62 seconds
Started Aug 04 05:07:45 PM PDT 24
Finished Aug 04 05:08:52 PM PDT 24
Peak memory 199944 kb
Host smart-d1221a2d-3942-40bf-8067-957bf7c80daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378551849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2378551849
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.2469568660
Short name T585
Test name
Test status
Simulation time 12003148341 ps
CPU time 66.19 seconds
Started Aug 04 05:07:45 PM PDT 24
Finished Aug 04 05:08:51 PM PDT 24
Peak memory 199796 kb
Host smart-bddfc56d-3224-45bf-9f48-3a3b3dccccf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2469568660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2469568660
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1166317216
Short name T48
Test name
Test status
Simulation time 3939045361 ps
CPU time 1.92 seconds
Started Aug 04 05:07:41 PM PDT 24
Finished Aug 04 05:07:43 PM PDT 24
Peak memory 198984 kb
Host smart-85078a1c-c8e6-4067-b6c8-0813014d3d8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1166317216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1166317216
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3754535312
Short name T1151
Test name
Test status
Simulation time 17504654616 ps
CPU time 12.72 seconds
Started Aug 04 05:07:44 PM PDT 24
Finished Aug 04 05:07:57 PM PDT 24
Peak memory 199856 kb
Host smart-f7f13629-c117-4b6a-b7c0-710b89b38958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754535312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3754535312
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.275822621
Short name T1074
Test name
Test status
Simulation time 39228037345 ps
CPU time 4.67 seconds
Started Aug 04 05:07:45 PM PDT 24
Finished Aug 04 05:07:49 PM PDT 24
Peak memory 195684 kb
Host smart-a5942e5d-4846-4b4a-9988-7a5e0f085116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275822621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.275822621
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.151710945
Short name T694
Test name
Test status
Simulation time 308155033 ps
CPU time 1.95 seconds
Started Aug 04 05:07:42 PM PDT 24
Finished Aug 04 05:07:44 PM PDT 24
Peak memory 198748 kb
Host smart-0ac2959d-649e-416c-8e64-ee189227837e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151710945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.151710945
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.3117835089
Short name T1139
Test name
Test status
Simulation time 4504963294 ps
CPU time 5.06 seconds
Started Aug 04 05:07:43 PM PDT 24
Finished Aug 04 05:07:49 PM PDT 24
Peak memory 199364 kb
Host smart-1e93e003-5e5d-43aa-b6da-4409a5a7a78e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117835089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3117835089
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.21760747
Short name T557
Test name
Test status
Simulation time 63240248073 ps
CPU time 356.53 seconds
Started Aug 04 05:07:45 PM PDT 24
Finished Aug 04 05:13:41 PM PDT 24
Peak memory 216420 kb
Host smart-4800bc62-505e-4112-a900-2dde97565cb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21760747 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.21760747
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.699549906
Short name T328
Test name
Test status
Simulation time 652429350 ps
CPU time 2.09 seconds
Started Aug 04 05:07:45 PM PDT 24
Finished Aug 04 05:07:47 PM PDT 24
Peak memory 199740 kb
Host smart-f651c9ae-2428-430f-999e-0ae74be6d0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699549906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.699549906
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3061204210
Short name T332
Test name
Test status
Simulation time 26972894917 ps
CPU time 22 seconds
Started Aug 04 05:07:41 PM PDT 24
Finished Aug 04 05:08:03 PM PDT 24
Peak memory 199924 kb
Host smart-0ac9039f-1dba-498e-a981-8afb0ff382ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061204210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3061204210
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.4164106961
Short name T541
Test name
Test status
Simulation time 56491767349 ps
CPU time 22.06 seconds
Started Aug 04 05:11:47 PM PDT 24
Finished Aug 04 05:12:09 PM PDT 24
Peak memory 199904 kb
Host smart-3f9237f9-fea5-4806-8673-e650e01c441c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164106961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.4164106961
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.809565975
Short name T517
Test name
Test status
Simulation time 133800043715 ps
CPU time 52.28 seconds
Started Aug 04 05:11:47 PM PDT 24
Finished Aug 04 05:12:39 PM PDT 24
Peak memory 199788 kb
Host smart-edf59242-7de1-4504-9f8c-7fb633f6092c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809565975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.809565975
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.148321635
Short name T1144
Test name
Test status
Simulation time 90108897402 ps
CPU time 145.86 seconds
Started Aug 04 05:11:48 PM PDT 24
Finished Aug 04 05:14:14 PM PDT 24
Peak memory 199768 kb
Host smart-be097a07-b2f8-4417-bab3-d92f492685b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148321635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.148321635
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.816579649
Short name T342
Test name
Test status
Simulation time 16566244318 ps
CPU time 33.61 seconds
Started Aug 04 05:11:49 PM PDT 24
Finished Aug 04 05:12:22 PM PDT 24
Peak memory 199916 kb
Host smart-47d6e912-4a66-432a-add9-73786b2a4ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816579649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.816579649
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2041475070
Short name T132
Test name
Test status
Simulation time 37629769558 ps
CPU time 27.54 seconds
Started Aug 04 05:11:47 PM PDT 24
Finished Aug 04 05:12:14 PM PDT 24
Peak memory 199760 kb
Host smart-eb208995-128f-482c-bc43-4c208ab69542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041475070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2041475070
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3900763363
Short name T49
Test name
Test status
Simulation time 113741935891 ps
CPU time 198.86 seconds
Started Aug 04 05:11:50 PM PDT 24
Finished Aug 04 05:15:09 PM PDT 24
Peak memory 199856 kb
Host smart-f5de236d-dbee-469c-aae8-7eb57d835e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900763363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3900763363
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2795135901
Short name T148
Test name
Test status
Simulation time 136152034933 ps
CPU time 52.4 seconds
Started Aug 04 05:11:47 PM PDT 24
Finished Aug 04 05:12:40 PM PDT 24
Peak memory 199844 kb
Host smart-1e973feb-1b58-4cc3-bb52-975010a4ed19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795135901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2795135901
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2219684966
Short name T550
Test name
Test status
Simulation time 31436048743 ps
CPU time 27.11 seconds
Started Aug 04 05:11:46 PM PDT 24
Finished Aug 04 05:12:13 PM PDT 24
Peak memory 199892 kb
Host smart-8c9ddcce-fffe-4127-8527-5ceec5285f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219684966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2219684966
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.4216518826
Short name T688
Test name
Test status
Simulation time 123362682892 ps
CPU time 145.64 seconds
Started Aug 04 05:11:48 PM PDT 24
Finished Aug 04 05:14:14 PM PDT 24
Peak memory 199476 kb
Host smart-ebb3d8ec-3ac1-40fd-aa1a-90b65f4bfb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216518826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.4216518826
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2316394709
Short name T532
Test name
Test status
Simulation time 62113739950 ps
CPU time 49.28 seconds
Started Aug 04 05:11:52 PM PDT 24
Finished Aug 04 05:12:42 PM PDT 24
Peak memory 199852 kb
Host smart-1126bf8d-0b5c-4585-9c8f-58bebbabb14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316394709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2316394709
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1663141759
Short name T25
Test name
Test status
Simulation time 16715464 ps
CPU time 0.55 seconds
Started Aug 04 05:05:47 PM PDT 24
Finished Aug 04 05:05:48 PM PDT 24
Peak memory 195216 kb
Host smart-25c4a06b-a7b9-4264-8d1c-1c2ee18ca425
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663141759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1663141759
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3878931655
Short name T926
Test name
Test status
Simulation time 119436428638 ps
CPU time 216.43 seconds
Started Aug 04 05:05:38 PM PDT 24
Finished Aug 04 05:09:14 PM PDT 24
Peak memory 199952 kb
Host smart-250f415e-fcd6-4177-84c3-b78ed18faee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878931655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3878931655
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.4197938720
Short name T833
Test name
Test status
Simulation time 52076958035 ps
CPU time 39.21 seconds
Started Aug 04 05:05:38 PM PDT 24
Finished Aug 04 05:06:17 PM PDT 24
Peak memory 199880 kb
Host smart-4c71ca76-7d1f-468b-9e14-7c1b94cbae39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197938720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.4197938720
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2815273034
Short name T70
Test name
Test status
Simulation time 8595495524 ps
CPU time 15.74 seconds
Started Aug 04 05:05:39 PM PDT 24
Finished Aug 04 05:05:55 PM PDT 24
Peak memory 199876 kb
Host smart-092f6f8a-d912-421d-b855-223cd8ab82e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815273034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2815273034
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2014516477
Short name T608
Test name
Test status
Simulation time 37962938908 ps
CPU time 72.84 seconds
Started Aug 04 05:05:41 PM PDT 24
Finished Aug 04 05:06:54 PM PDT 24
Peak memory 199852 kb
Host smart-addb4965-24ae-4dd8-b8b9-dec7cc601276
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014516477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2014516477
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2635456015
Short name T567
Test name
Test status
Simulation time 135178452701 ps
CPU time 838.79 seconds
Started Aug 04 05:05:47 PM PDT 24
Finished Aug 04 05:19:46 PM PDT 24
Peak memory 199876 kb
Host smart-17afbc39-0def-4038-b9c8-27a6302c6d69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2635456015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2635456015
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2852323266
Short name T983
Test name
Test status
Simulation time 4875279694 ps
CPU time 3.17 seconds
Started Aug 04 05:05:41 PM PDT 24
Finished Aug 04 05:05:45 PM PDT 24
Peak memory 198576 kb
Host smart-9e474c13-e7f1-46cc-93f7-3de4a3b3aa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852323266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2852323266
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1010819941
Short name T861
Test name
Test status
Simulation time 79534722574 ps
CPU time 44.59 seconds
Started Aug 04 05:05:41 PM PDT 24
Finished Aug 04 05:06:26 PM PDT 24
Peak memory 200104 kb
Host smart-318bd828-eb06-44e5-899e-8cc13f75926c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010819941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1010819941
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.4277986590
Short name T1117
Test name
Test status
Simulation time 6420851476 ps
CPU time 188.24 seconds
Started Aug 04 05:05:44 PM PDT 24
Finished Aug 04 05:08:52 PM PDT 24
Peak memory 199860 kb
Host smart-e15dc492-4680-4b18-9c84-885a51d282ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4277986590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.4277986590
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1477063499
Short name T471
Test name
Test status
Simulation time 5978816298 ps
CPU time 3.99 seconds
Started Aug 04 05:05:37 PM PDT 24
Finished Aug 04 05:05:41 PM PDT 24
Peak memory 199044 kb
Host smart-591613b7-8443-4538-9131-27e3c8b0d411
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1477063499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1477063499
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.98044328
Short name T849
Test name
Test status
Simulation time 154518070060 ps
CPU time 148.17 seconds
Started Aug 04 05:05:41 PM PDT 24
Finished Aug 04 05:08:09 PM PDT 24
Peak memory 199772 kb
Host smart-f9acdef0-aeab-4e50-89f6-a70a48c4e246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98044328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.98044328
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2023990637
Short name T318
Test name
Test status
Simulation time 26021213477 ps
CPU time 10.18 seconds
Started Aug 04 05:05:41 PM PDT 24
Finished Aug 04 05:05:51 PM PDT 24
Peak memory 196224 kb
Host smart-16babfbc-a244-4a60-b886-70ed1b70b648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023990637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2023990637
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2863186410
Short name T26
Test name
Test status
Simulation time 112442476 ps
CPU time 0.82 seconds
Started Aug 04 05:05:45 PM PDT 24
Finished Aug 04 05:05:46 PM PDT 24
Peak memory 218184 kb
Host smart-7102c720-d53c-4f9a-924f-5470631ff5c0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863186410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2863186410
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.140398443
Short name T702
Test name
Test status
Simulation time 672565984 ps
CPU time 2.7 seconds
Started Aug 04 05:05:36 PM PDT 24
Finished Aug 04 05:05:39 PM PDT 24
Peak memory 198312 kb
Host smart-88ec6d15-73ca-47bf-8d07-154b5678a67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140398443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.140398443
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1661875867
Short name T1039
Test name
Test status
Simulation time 54129743686 ps
CPU time 207.1 seconds
Started Aug 04 05:05:47 PM PDT 24
Finished Aug 04 05:09:14 PM PDT 24
Peak memory 208428 kb
Host smart-b2cdc4d6-a6d6-4353-963e-898b670ecd0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661875867 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1661875867
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3657554187
Short name T572
Test name
Test status
Simulation time 1850136450 ps
CPU time 2.97 seconds
Started Aug 04 05:05:41 PM PDT 24
Finished Aug 04 05:05:44 PM PDT 24
Peak memory 198252 kb
Host smart-383f3c01-5cb9-4323-ad84-f6fd636001c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657554187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3657554187
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1665387908
Short name T893
Test name
Test status
Simulation time 938459351 ps
CPU time 1.29 seconds
Started Aug 04 05:05:41 PM PDT 24
Finished Aug 04 05:05:42 PM PDT 24
Peak memory 197008 kb
Host smart-e8b199f8-94c4-41ed-9340-4adf25f801bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665387908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1665387908
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2298844155
Short name T447
Test name
Test status
Simulation time 39386816 ps
CPU time 0.54 seconds
Started Aug 04 05:07:53 PM PDT 24
Finished Aug 04 05:07:53 PM PDT 24
Peak memory 195212 kb
Host smart-f53b9dc7-cf69-4d71-a6dc-cd2f530e40d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298844155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2298844155
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3972061990
Short name T844
Test name
Test status
Simulation time 109709224989 ps
CPU time 14.58 seconds
Started Aug 04 05:07:49 PM PDT 24
Finished Aug 04 05:08:04 PM PDT 24
Peak memory 199904 kb
Host smart-36c88a5f-b833-47d0-9ab3-76a12aadb7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972061990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3972061990
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.1190622304
Short name T899
Test name
Test status
Simulation time 8844874767 ps
CPU time 4.35 seconds
Started Aug 04 05:07:49 PM PDT 24
Finished Aug 04 05:07:53 PM PDT 24
Peak memory 199884 kb
Host smart-8e45a6a5-8b96-47ed-92aa-5e7d2683296f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190622304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1190622304
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3271208727
Short name T1085
Test name
Test status
Simulation time 104238698807 ps
CPU time 649.83 seconds
Started Aug 04 05:07:56 PM PDT 24
Finished Aug 04 05:18:45 PM PDT 24
Peak memory 199712 kb
Host smart-0f99ce43-88e9-4e22-97f7-954bb938be5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3271208727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3271208727
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.918282328
Short name T803
Test name
Test status
Simulation time 5593504879 ps
CPU time 7.21 seconds
Started Aug 04 05:07:53 PM PDT 24
Finished Aug 04 05:08:01 PM PDT 24
Peak memory 199340 kb
Host smart-ee6304c0-9efc-48bd-87bb-18a8c8e6104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918282328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.918282328
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2736208924
Short name T619
Test name
Test status
Simulation time 86699533504 ps
CPU time 170.44 seconds
Started Aug 04 05:07:50 PM PDT 24
Finished Aug 04 05:10:41 PM PDT 24
Peak memory 208124 kb
Host smart-53891346-57e0-4eef-b3b9-b5f6db1bd323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736208924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2736208924
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.645738430
Short name T593
Test name
Test status
Simulation time 7445622650 ps
CPU time 453.2 seconds
Started Aug 04 05:07:56 PM PDT 24
Finished Aug 04 05:15:29 PM PDT 24
Peak memory 199908 kb
Host smart-3fcb26b1-a0b1-45f5-9450-b6afae53e371
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=645738430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.645738430
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2459706324
Short name T466
Test name
Test status
Simulation time 3829977929 ps
CPU time 6.61 seconds
Started Aug 04 05:07:51 PM PDT 24
Finished Aug 04 05:07:57 PM PDT 24
Peak memory 198020 kb
Host smart-c00faf2c-2aa8-4984-90b9-f9f330dac537
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2459706324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2459706324
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1710643984
Short name T341
Test name
Test status
Simulation time 364016825301 ps
CPU time 276.18 seconds
Started Aug 04 05:07:49 PM PDT 24
Finished Aug 04 05:12:25 PM PDT 24
Peak memory 199792 kb
Host smart-49f002d5-086d-4387-a1ef-a6866718afdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710643984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1710643984
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.331184560
Short name T291
Test name
Test status
Simulation time 3314147480 ps
CPU time 1.12 seconds
Started Aug 04 05:07:50 PM PDT 24
Finished Aug 04 05:07:51 PM PDT 24
Peak memory 195964 kb
Host smart-3238bfa7-73d7-4bdc-92ab-389a97c8c5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331184560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.331184560
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.900792803
Short name T464
Test name
Test status
Simulation time 505978144 ps
CPU time 2.55 seconds
Started Aug 04 05:07:46 PM PDT 24
Finished Aug 04 05:07:48 PM PDT 24
Peak memory 198116 kb
Host smart-72cc052f-7821-4772-bbe4-9aa65721f5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900792803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.900792803
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.3836199958
Short name T953
Test name
Test status
Simulation time 197333317223 ps
CPU time 306.67 seconds
Started Aug 04 05:07:53 PM PDT 24
Finished Aug 04 05:13:00 PM PDT 24
Peak memory 199856 kb
Host smart-1f20d492-4637-45f1-8e35-9f2f9119d67b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836199958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3836199958
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3902402952
Short name T733
Test name
Test status
Simulation time 1473371563352 ps
CPU time 1153.05 seconds
Started Aug 04 05:07:53 PM PDT 24
Finished Aug 04 05:27:06 PM PDT 24
Peak memory 224572 kb
Host smart-016848f2-7877-44c1-af22-9f7582c4fd7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902402952 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3902402952
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2809963115
Short name T1103
Test name
Test status
Simulation time 917957623 ps
CPU time 1.77 seconds
Started Aug 04 05:07:49 PM PDT 24
Finished Aug 04 05:07:51 PM PDT 24
Peak memory 199472 kb
Host smart-d22b86b4-7e2a-4f37-acf4-9044eb9b9e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809963115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2809963115
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3704643848
Short name T480
Test name
Test status
Simulation time 56103933867 ps
CPU time 84.34 seconds
Started Aug 04 05:07:44 PM PDT 24
Finished Aug 04 05:09:09 PM PDT 24
Peak memory 199808 kb
Host smart-80a5d48b-bb72-474c-bcb7-f28367747bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704643848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3704643848
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3920969896
Short name T216
Test name
Test status
Simulation time 22356334774 ps
CPU time 32.11 seconds
Started Aug 04 05:11:51 PM PDT 24
Finished Aug 04 05:12:23 PM PDT 24
Peak memory 199900 kb
Host smart-3566cc1a-7ee9-4e45-8b56-4d61f979f9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920969896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3920969896
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.323856742
Short name T294
Test name
Test status
Simulation time 7019001990 ps
CPU time 11 seconds
Started Aug 04 05:11:51 PM PDT 24
Finished Aug 04 05:12:02 PM PDT 24
Peak memory 199784 kb
Host smart-4709419e-75c0-4a38-a070-653a5b5b15c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323856742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.323856742
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2271945556
Short name T229
Test name
Test status
Simulation time 46218901916 ps
CPU time 65.52 seconds
Started Aug 04 05:11:49 PM PDT 24
Finished Aug 04 05:12:55 PM PDT 24
Peak memory 199824 kb
Host smart-4b99061f-df0a-4b5d-aa2f-4c3a55b9ec97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271945556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2271945556
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2547710814
Short name T197
Test name
Test status
Simulation time 148394216520 ps
CPU time 49.33 seconds
Started Aug 04 05:11:52 PM PDT 24
Finished Aug 04 05:12:41 PM PDT 24
Peak memory 200084 kb
Host smart-9b7f6f2b-53ad-4e3d-8d50-cda98085c04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547710814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2547710814
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.855566634
Short name T261
Test name
Test status
Simulation time 50705316794 ps
CPU time 21.4 seconds
Started Aug 04 05:11:51 PM PDT 24
Finished Aug 04 05:12:13 PM PDT 24
Peak memory 199896 kb
Host smart-ae2613f6-8a0c-429a-a496-ac26c2ff52ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855566634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.855566634
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3745114187
Short name T836
Test name
Test status
Simulation time 7892393080 ps
CPU time 5.7 seconds
Started Aug 04 05:11:52 PM PDT 24
Finished Aug 04 05:11:57 PM PDT 24
Peak memory 199464 kb
Host smart-3ad8b979-b5de-466a-a0ee-6bc64b7543da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745114187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3745114187
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.3927138085
Short name T667
Test name
Test status
Simulation time 57124153169 ps
CPU time 21.78 seconds
Started Aug 04 05:11:52 PM PDT 24
Finished Aug 04 05:12:14 PM PDT 24
Peak memory 199308 kb
Host smart-ce7d73d1-93bf-487f-99f2-3d42ba4f9721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927138085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3927138085
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3068407324
Short name T467
Test name
Test status
Simulation time 50538602877 ps
CPU time 73.87 seconds
Started Aug 04 05:11:56 PM PDT 24
Finished Aug 04 05:13:10 PM PDT 24
Peak memory 199864 kb
Host smart-ab959439-147e-4817-9730-d9fd94d11781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068407324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3068407324
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1825861508
Short name T616
Test name
Test status
Simulation time 88255841622 ps
CPU time 121.63 seconds
Started Aug 04 05:11:56 PM PDT 24
Finished Aug 04 05:13:57 PM PDT 24
Peak memory 199912 kb
Host smart-27e9baf1-89c1-41a8-b081-cde22570efa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825861508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1825861508
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3301444575
Short name T897
Test name
Test status
Simulation time 21467045 ps
CPU time 0.53 seconds
Started Aug 04 05:07:58 PM PDT 24
Finished Aug 04 05:07:59 PM PDT 24
Peak memory 194220 kb
Host smart-0be0e9f7-47f1-4ff8-8e64-66c104e479fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301444575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3301444575
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3563148399
Short name T434
Test name
Test status
Simulation time 49220336199 ps
CPU time 82.55 seconds
Started Aug 04 05:07:56 PM PDT 24
Finished Aug 04 05:09:19 PM PDT 24
Peak memory 199904 kb
Host smart-58398edf-9171-4980-9a4b-3c5b4d511426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563148399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3563148399
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2316707924
Short name T272
Test name
Test status
Simulation time 18038197149 ps
CPU time 20.18 seconds
Started Aug 04 05:07:52 PM PDT 24
Finished Aug 04 05:08:12 PM PDT 24
Peak memory 199228 kb
Host smart-3b3323a2-efb5-46a7-b0df-9effa9721170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316707924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2316707924
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1720056235
Short name T1077
Test name
Test status
Simulation time 44056444858 ps
CPU time 66.41 seconds
Started Aug 04 05:07:53 PM PDT 24
Finished Aug 04 05:08:59 PM PDT 24
Peak memory 199868 kb
Host smart-6352bb5c-7004-4bee-8942-7cd94b245a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720056235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1720056235
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2450121386
Short name T326
Test name
Test status
Simulation time 67299625625 ps
CPU time 25.74 seconds
Started Aug 04 05:07:54 PM PDT 24
Finished Aug 04 05:08:20 PM PDT 24
Peak memory 199836 kb
Host smart-e988ca2b-2705-4cef-9384-b6da6a4a90f1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450121386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2450121386
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.726253258
Short name T1123
Test name
Test status
Simulation time 103903588406 ps
CPU time 529.49 seconds
Started Aug 04 05:07:57 PM PDT 24
Finished Aug 04 05:16:47 PM PDT 24
Peak memory 199804 kb
Host smart-6b03a081-4747-4841-9fa0-22379a83d0a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=726253258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.726253258
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1788984824
Short name T435
Test name
Test status
Simulation time 8265355110 ps
CPU time 15.91 seconds
Started Aug 04 05:07:57 PM PDT 24
Finished Aug 04 05:08:13 PM PDT 24
Peak memory 198824 kb
Host smart-65d21708-6990-4e8f-825e-9a5191db0050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788984824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1788984824
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3577727040
Short name T254
Test name
Test status
Simulation time 153271116375 ps
CPU time 247.55 seconds
Started Aug 04 05:07:54 PM PDT 24
Finished Aug 04 05:12:01 PM PDT 24
Peak memory 199968 kb
Host smart-e3a12ac6-73d9-49d9-a1f7-82ebe9b7fc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577727040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3577727040
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.942704344
Short name T266
Test name
Test status
Simulation time 2707686846 ps
CPU time 140.08 seconds
Started Aug 04 05:07:58 PM PDT 24
Finished Aug 04 05:10:18 PM PDT 24
Peak memory 199832 kb
Host smart-72406fc0-d3ef-44a9-82b9-d39e1f9b0917
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=942704344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.942704344
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3561121056
Short name T722
Test name
Test status
Simulation time 2865759387 ps
CPU time 13.16 seconds
Started Aug 04 05:07:54 PM PDT 24
Finished Aug 04 05:08:07 PM PDT 24
Peak memory 198872 kb
Host smart-d3272556-3665-40cc-9ce1-cf1bf34db7f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561121056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3561121056
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1440422427
Short name T1070
Test name
Test status
Simulation time 248058710800 ps
CPU time 175.28 seconds
Started Aug 04 05:07:53 PM PDT 24
Finished Aug 04 05:10:49 PM PDT 24
Peak memory 199668 kb
Host smart-547a3957-6e00-45c8-9f6f-079845b82b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440422427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1440422427
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2172087373
Short name T970
Test name
Test status
Simulation time 3919723384 ps
CPU time 5.98 seconds
Started Aug 04 05:07:54 PM PDT 24
Finished Aug 04 05:08:00 PM PDT 24
Peak memory 196352 kb
Host smart-44b6d0f4-6f00-49e1-af71-923b38abf295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172087373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2172087373
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3510941268
Short name T311
Test name
Test status
Simulation time 738627226 ps
CPU time 5.25 seconds
Started Aug 04 05:07:55 PM PDT 24
Finished Aug 04 05:08:01 PM PDT 24
Peak memory 197972 kb
Host smart-8af7ed0e-7dd1-429a-bef3-b1d36939b390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510941268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3510941268
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.3531244309
Short name T271
Test name
Test status
Simulation time 143057831707 ps
CPU time 1277.75 seconds
Started Aug 04 05:07:58 PM PDT 24
Finished Aug 04 05:29:16 PM PDT 24
Peak memory 199900 kb
Host smart-19720653-3e70-4a0a-aeff-59491e188f2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531244309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3531244309
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1861494828
Short name T59
Test name
Test status
Simulation time 23763438802 ps
CPU time 197.68 seconds
Started Aug 04 05:08:04 PM PDT 24
Finished Aug 04 05:11:22 PM PDT 24
Peak memory 216240 kb
Host smart-ab262f20-ccf9-4761-9821-a2bc6a34bb59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861494828 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1861494828
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.758120105
Short name T1069
Test name
Test status
Simulation time 6668526606 ps
CPU time 20.07 seconds
Started Aug 04 05:07:58 PM PDT 24
Finished Aug 04 05:08:18 PM PDT 24
Peak memory 199904 kb
Host smart-819fd35b-9e17-4a6d-bce3-12f87bf15bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758120105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.758120105
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1420265525
Short name T307
Test name
Test status
Simulation time 110452340283 ps
CPU time 222.89 seconds
Started Aug 04 05:07:56 PM PDT 24
Finished Aug 04 05:11:39 PM PDT 24
Peak memory 199852 kb
Host smart-accd3be7-d52b-4a4d-b2c5-0c09580e49ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420265525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1420265525
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.4215872885
Short name T698
Test name
Test status
Simulation time 108755082074 ps
CPU time 196.79 seconds
Started Aug 04 05:11:56 PM PDT 24
Finished Aug 04 05:15:13 PM PDT 24
Peak memory 199912 kb
Host smart-11477c1c-21ec-499d-8849-267307e645bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215872885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.4215872885
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3790118261
Short name T944
Test name
Test status
Simulation time 104174593296 ps
CPU time 75.84 seconds
Started Aug 04 05:11:55 PM PDT 24
Finished Aug 04 05:13:11 PM PDT 24
Peak memory 199816 kb
Host smart-c9cc9fd6-b69d-4dc2-ae8f-76aa09e30923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790118261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3790118261
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2367133011
Short name T660
Test name
Test status
Simulation time 24904374636 ps
CPU time 45.81 seconds
Started Aug 04 05:11:56 PM PDT 24
Finished Aug 04 05:12:42 PM PDT 24
Peak memory 199840 kb
Host smart-45709bdc-0809-42aa-ab1c-5ac4325cdc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367133011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2367133011
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.3016675787
Short name T209
Test name
Test status
Simulation time 14948653432 ps
CPU time 48.09 seconds
Started Aug 04 05:11:54 PM PDT 24
Finished Aug 04 05:12:43 PM PDT 24
Peak memory 199812 kb
Host smart-c2b7e913-7376-4b17-8f35-9e2cb0ea42ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016675787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3016675787
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1599143053
Short name T46
Test name
Test status
Simulation time 34135162841 ps
CPU time 39.56 seconds
Started Aug 04 05:11:56 PM PDT 24
Finished Aug 04 05:12:36 PM PDT 24
Peak memory 199852 kb
Host smart-9c26246c-4cd7-4752-be3e-36196859a9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599143053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1599143053
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1193732851
Short name T179
Test name
Test status
Simulation time 40359892658 ps
CPU time 15.7 seconds
Started Aug 04 05:12:00 PM PDT 24
Finished Aug 04 05:12:16 PM PDT 24
Peak memory 199836 kb
Host smart-1acf9e3f-2e47-4990-ac3f-6086f228ee16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193732851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1193732851
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2990642175
Short name T646
Test name
Test status
Simulation time 87359800206 ps
CPU time 151.46 seconds
Started Aug 04 05:11:59 PM PDT 24
Finished Aug 04 05:14:31 PM PDT 24
Peak memory 199840 kb
Host smart-bec19a64-d56c-4df0-a124-b632d75bcc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990642175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2990642175
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.3232525499
Short name T594
Test name
Test status
Simulation time 139844872963 ps
CPU time 192.58 seconds
Started Aug 04 05:12:00 PM PDT 24
Finished Aug 04 05:15:12 PM PDT 24
Peak memory 199728 kb
Host smart-88fe4705-0172-4361-a7b7-c571225bb2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232525499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3232525499
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3407272570
Short name T1083
Test name
Test status
Simulation time 44240872 ps
CPU time 0.56 seconds
Started Aug 04 05:08:04 PM PDT 24
Finished Aug 04 05:08:04 PM PDT 24
Peak memory 195508 kb
Host smart-eec1d2ce-38a0-4dc9-8615-2be9c797d2d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407272570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3407272570
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3714576736
Short name T167
Test name
Test status
Simulation time 71707558918 ps
CPU time 15.83 seconds
Started Aug 04 05:07:57 PM PDT 24
Finished Aug 04 05:08:13 PM PDT 24
Peak memory 199848 kb
Host smart-4af82c5a-347b-4547-abf0-9d45f73aa187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714576736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3714576736
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2704961227
Short name T1004
Test name
Test status
Simulation time 30929551555 ps
CPU time 22.67 seconds
Started Aug 04 05:07:58 PM PDT 24
Finished Aug 04 05:08:20 PM PDT 24
Peak memory 199764 kb
Host smart-fbf8ef52-d864-496d-812d-627739a71833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704961227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2704961227
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3845534995
Short name T1093
Test name
Test status
Simulation time 15457237652 ps
CPU time 20.31 seconds
Started Aug 04 05:08:02 PM PDT 24
Finished Aug 04 05:08:23 PM PDT 24
Peak memory 199628 kb
Host smart-8df9b991-0b68-4528-a5ab-8e21a0bac0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845534995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3845534995
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3944671793
Short name T762
Test name
Test status
Simulation time 47653742276 ps
CPU time 21.86 seconds
Started Aug 04 05:08:01 PM PDT 24
Finished Aug 04 05:08:23 PM PDT 24
Peak memory 199056 kb
Host smart-952bd4ed-c5e9-4472-9ca5-075b491cd603
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944671793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3944671793
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.4063689119
Short name T365
Test name
Test status
Simulation time 63982057592 ps
CPU time 166.3 seconds
Started Aug 04 05:08:01 PM PDT 24
Finished Aug 04 05:10:47 PM PDT 24
Peak memory 199780 kb
Host smart-663609f4-bc62-4a9f-98d1-b2c7407aee24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4063689119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.4063689119
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1449852583
Short name T380
Test name
Test status
Simulation time 1355278029 ps
CPU time 2.7 seconds
Started Aug 04 05:08:00 PM PDT 24
Finished Aug 04 05:08:03 PM PDT 24
Peak memory 197564 kb
Host smart-95742d3a-a1f5-4d28-b246-f3f23a035a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449852583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1449852583
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.805648564
Short name T873
Test name
Test status
Simulation time 82818206964 ps
CPU time 134.72 seconds
Started Aug 04 05:08:02 PM PDT 24
Finished Aug 04 05:10:17 PM PDT 24
Peak memory 199332 kb
Host smart-b06e310a-f00a-4f24-a721-146d53e60bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805648564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.805648564
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.936926894
Short name T9
Test name
Test status
Simulation time 16068915699 ps
CPU time 406.61 seconds
Started Aug 04 05:08:02 PM PDT 24
Finished Aug 04 05:14:49 PM PDT 24
Peak memory 199836 kb
Host smart-6e6e9f66-4f6e-4170-804d-c81555f02635
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=936926894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.936926894
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1360325568
Short name T383
Test name
Test status
Simulation time 2642984829 ps
CPU time 4 seconds
Started Aug 04 05:08:02 PM PDT 24
Finished Aug 04 05:08:06 PM PDT 24
Peak memory 198960 kb
Host smart-51a80366-3f4d-4a8c-858c-322e064e3774
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1360325568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1360325568
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.770392651
Short name T545
Test name
Test status
Simulation time 60547579376 ps
CPU time 85.4 seconds
Started Aug 04 05:08:01 PM PDT 24
Finished Aug 04 05:09:26 PM PDT 24
Peak memory 199836 kb
Host smart-fbc83079-618c-43c5-b588-343cf46ac195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770392651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.770392651
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.334388378
Short name T1059
Test name
Test status
Simulation time 3439707488 ps
CPU time 2.02 seconds
Started Aug 04 05:08:01 PM PDT 24
Finished Aug 04 05:08:03 PM PDT 24
Peak memory 196216 kb
Host smart-2c307f2f-03cb-4dbf-a057-39574f84d7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334388378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.334388378
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.735145497
Short name T832
Test name
Test status
Simulation time 6098689703 ps
CPU time 7.15 seconds
Started Aug 04 05:07:57 PM PDT 24
Finished Aug 04 05:08:04 PM PDT 24
Peak memory 199128 kb
Host smart-0690f1c0-a168-4042-bebe-057d2a91257a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735145497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.735145497
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.1893330772
Short name T812
Test name
Test status
Simulation time 48273365931 ps
CPU time 44.86 seconds
Started Aug 04 05:08:04 PM PDT 24
Finished Aug 04 05:08:49 PM PDT 24
Peak memory 199808 kb
Host smart-6b06242f-3b6d-43da-8bf1-51ebd856484d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893330772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1893330772
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2684758891
Short name T430
Test name
Test status
Simulation time 84609552873 ps
CPU time 1228.36 seconds
Started Aug 04 05:08:05 PM PDT 24
Finished Aug 04 05:28:33 PM PDT 24
Peak memory 226404 kb
Host smart-856e4805-f924-4c5a-943e-bd4458987303
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684758891 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2684758891
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1833428800
Short name T274
Test name
Test status
Simulation time 1170437725 ps
CPU time 2.92 seconds
Started Aug 04 05:08:02 PM PDT 24
Finished Aug 04 05:08:05 PM PDT 24
Peak memory 198204 kb
Host smart-9bdf5633-8b9f-4002-8f06-d65e01f67aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833428800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1833428800
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2153114904
Short name T1025
Test name
Test status
Simulation time 116949415093 ps
CPU time 208.24 seconds
Started Aug 04 05:07:57 PM PDT 24
Finished Aug 04 05:11:25 PM PDT 24
Peak memory 199868 kb
Host smart-446c7746-3e0c-4c44-89c4-96d70b0b14f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153114904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2153114904
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.377518573
Short name T1051
Test name
Test status
Simulation time 105777669823 ps
CPU time 179 seconds
Started Aug 04 05:12:00 PM PDT 24
Finished Aug 04 05:14:59 PM PDT 24
Peak memory 199792 kb
Host smart-98abf63f-b6ef-4be1-aa9a-49927cf2fb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377518573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.377518573
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.62124251
Short name T422
Test name
Test status
Simulation time 19372730365 ps
CPU time 13.79 seconds
Started Aug 04 05:12:05 PM PDT 24
Finished Aug 04 05:12:19 PM PDT 24
Peak memory 199820 kb
Host smart-0df9a3fc-3d23-4766-a14b-cc3c2b96fa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62124251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.62124251
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3368151805
Short name T708
Test name
Test status
Simulation time 75723422373 ps
CPU time 33.63 seconds
Started Aug 04 05:12:04 PM PDT 24
Finished Aug 04 05:12:38 PM PDT 24
Peak memory 199876 kb
Host smart-9fd3c40b-55e4-4281-8e63-da34454cc28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368151805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3368151805
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3479960266
Short name T950
Test name
Test status
Simulation time 128804340899 ps
CPU time 105.28 seconds
Started Aug 04 05:12:04 PM PDT 24
Finished Aug 04 05:13:50 PM PDT 24
Peak memory 199844 kb
Host smart-cfc5662b-ae90-4919-9264-80fd51250ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479960266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3479960266
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2829295079
Short name T217
Test name
Test status
Simulation time 25132052775 ps
CPU time 24.72 seconds
Started Aug 04 05:12:05 PM PDT 24
Finished Aug 04 05:12:30 PM PDT 24
Peak memory 199836 kb
Host smart-64aaa2ec-99de-4781-8cb6-65834f4e0b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829295079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2829295079
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.459361916
Short name T940
Test name
Test status
Simulation time 22844624529 ps
CPU time 18.75 seconds
Started Aug 04 05:12:05 PM PDT 24
Finished Aug 04 05:12:24 PM PDT 24
Peak memory 199792 kb
Host smart-ea1a12fa-ba37-4d24-b708-eca6ae5dbc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459361916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.459361916
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2519389027
Short name T39
Test name
Test status
Simulation time 189486265432 ps
CPU time 72.42 seconds
Started Aug 04 05:12:08 PM PDT 24
Finished Aug 04 05:13:21 PM PDT 24
Peak memory 199768 kb
Host smart-d548da79-f2f8-478d-bb25-b41c45c65742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519389027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2519389027
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3175740437
Short name T1136
Test name
Test status
Simulation time 83747973634 ps
CPU time 39.97 seconds
Started Aug 04 05:12:09 PM PDT 24
Finished Aug 04 05:12:49 PM PDT 24
Peak memory 199772 kb
Host smart-e376a325-cc53-4ea2-a89a-7931c59c8dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175740437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3175740437
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3306605627
Short name T880
Test name
Test status
Simulation time 40239878825 ps
CPU time 25.59 seconds
Started Aug 04 05:12:08 PM PDT 24
Finished Aug 04 05:12:34 PM PDT 24
Peak memory 199856 kb
Host smart-1892e846-013d-48b4-a584-21c8eac55d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306605627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3306605627
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.175873366
Short name T584
Test name
Test status
Simulation time 35685006 ps
CPU time 0.56 seconds
Started Aug 04 05:08:11 PM PDT 24
Finished Aug 04 05:08:12 PM PDT 24
Peak memory 194248 kb
Host smart-3d342030-2f70-47e2-b57a-9e16970171ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175873366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.175873366
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.471820282
Short name T401
Test name
Test status
Simulation time 85683151393 ps
CPU time 34.51 seconds
Started Aug 04 05:08:07 PM PDT 24
Finished Aug 04 05:08:41 PM PDT 24
Peak memory 199728 kb
Host smart-b9e55866-3502-40f7-ac55-965286199b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471820282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.471820282
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1586831630
Short name T504
Test name
Test status
Simulation time 19829318789 ps
CPU time 28.2 seconds
Started Aug 04 05:08:08 PM PDT 24
Finished Aug 04 05:08:36 PM PDT 24
Peak memory 199724 kb
Host smart-b1a6ee89-9fd6-4271-8342-51269b94e676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586831630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1586831630
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1789715676
Short name T560
Test name
Test status
Simulation time 238187852571 ps
CPU time 49.99 seconds
Started Aug 04 05:08:11 PM PDT 24
Finished Aug 04 05:09:01 PM PDT 24
Peak memory 199828 kb
Host smart-6383d331-1bdc-4627-9386-15154b6f74bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789715676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1789715676
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.37827182
Short name T725
Test name
Test status
Simulation time 31414939525 ps
CPU time 26.57 seconds
Started Aug 04 05:08:08 PM PDT 24
Finished Aug 04 05:08:35 PM PDT 24
Peak memory 199856 kb
Host smart-b808a5c2-353f-412b-9d5a-75476e1e3e60
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37827182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.37827182
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1452486300
Short name T723
Test name
Test status
Simulation time 48486270969 ps
CPU time 78.67 seconds
Started Aug 04 05:08:09 PM PDT 24
Finished Aug 04 05:09:28 PM PDT 24
Peak memory 199832 kb
Host smart-c3ebb43b-1f07-43ea-8620-92ca2411bd14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1452486300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1452486300
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2138583332
Short name T358
Test name
Test status
Simulation time 3354511736 ps
CPU time 19.8 seconds
Started Aug 04 05:08:11 PM PDT 24
Finished Aug 04 05:08:31 PM PDT 24
Peak memory 199912 kb
Host smart-4e737c26-b60d-4e95-ae3a-74052e56a23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138583332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2138583332
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1671644336
Short name T1157
Test name
Test status
Simulation time 61358102635 ps
CPU time 53.48 seconds
Started Aug 04 05:08:08 PM PDT 24
Finished Aug 04 05:09:02 PM PDT 24
Peak memory 200036 kb
Host smart-e8e85e60-9734-4d1b-8c22-dce3878c39cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671644336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1671644336
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.687764839
Short name T475
Test name
Test status
Simulation time 26617955823 ps
CPU time 252.55 seconds
Started Aug 04 05:08:10 PM PDT 24
Finished Aug 04 05:12:23 PM PDT 24
Peak memory 199848 kb
Host smart-c7051180-4238-47f5-a9cc-92017fa113d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=687764839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.687764839
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.4159667455
Short name T799
Test name
Test status
Simulation time 2711400529 ps
CPU time 1.95 seconds
Started Aug 04 05:08:06 PM PDT 24
Finished Aug 04 05:08:08 PM PDT 24
Peak memory 198152 kb
Host smart-f78ebce4-b8cc-4428-b130-1635fc157c5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4159667455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.4159667455
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1063150625
Short name T756
Test name
Test status
Simulation time 20564966182 ps
CPU time 23.1 seconds
Started Aug 04 05:08:07 PM PDT 24
Finished Aug 04 05:08:30 PM PDT 24
Peak memory 199860 kb
Host smart-f5b250c5-1151-4d99-ab24-2ffc49fc7d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063150625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1063150625
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1588199793
Short name T292
Test name
Test status
Simulation time 3259596000 ps
CPU time 5.31 seconds
Started Aug 04 05:08:07 PM PDT 24
Finished Aug 04 05:08:12 PM PDT 24
Peak memory 196652 kb
Host smart-4349d51c-dae4-4cdd-995c-c8a232ded31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588199793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1588199793
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.3388941993
Short name T492
Test name
Test status
Simulation time 517029990 ps
CPU time 1.39 seconds
Started Aug 04 05:08:04 PM PDT 24
Finished Aug 04 05:08:05 PM PDT 24
Peak memory 199796 kb
Host smart-0192a699-621a-4ff0-9a8c-8e8f58840414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388941993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3388941993
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1045369686
Short name T1002
Test name
Test status
Simulation time 193809512106 ps
CPU time 115.21 seconds
Started Aug 04 05:08:13 PM PDT 24
Finished Aug 04 05:10:08 PM PDT 24
Peak memory 199888 kb
Host smart-b7fbec80-c14f-4ffa-aa0c-76b890a28611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045369686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1045369686
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3534830886
Short name T1064
Test name
Test status
Simulation time 7275072754 ps
CPU time 10.17 seconds
Started Aug 04 05:08:11 PM PDT 24
Finished Aug 04 05:08:21 PM PDT 24
Peak memory 199820 kb
Host smart-b547602f-12d7-46f2-8686-7f97aeaeffa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534830886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3534830886
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.4070682398
Short name T822
Test name
Test status
Simulation time 59853630391 ps
CPU time 20.45 seconds
Started Aug 04 05:08:04 PM PDT 24
Finished Aug 04 05:08:25 PM PDT 24
Peak memory 199776 kb
Host smart-24e8f13a-3ec0-4f1f-b6fe-144624d91790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070682398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.4070682398
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2231484627
Short name T182
Test name
Test status
Simulation time 130599764424 ps
CPU time 51.2 seconds
Started Aug 04 05:12:08 PM PDT 24
Finished Aug 04 05:12:59 PM PDT 24
Peak memory 199796 kb
Host smart-12ede3ee-6af4-44ed-a4da-9f0c75594e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231484627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2231484627
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3741455557
Short name T695
Test name
Test status
Simulation time 239066820373 ps
CPU time 81.96 seconds
Started Aug 04 05:12:09 PM PDT 24
Finished Aug 04 05:13:31 PM PDT 24
Peak memory 199800 kb
Host smart-3b9e941d-32a4-4f60-988a-3df488f8cb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741455557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3741455557
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1974991298
Short name T185
Test name
Test status
Simulation time 39983906328 ps
CPU time 42.61 seconds
Started Aug 04 05:12:08 PM PDT 24
Finished Aug 04 05:12:51 PM PDT 24
Peak memory 199844 kb
Host smart-a2d74339-3923-4f00-a7c9-e8c0adfdb421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974991298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1974991298
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1433195859
Short name T128
Test name
Test status
Simulation time 109800477885 ps
CPU time 143.3 seconds
Started Aug 04 05:12:07 PM PDT 24
Finished Aug 04 05:14:31 PM PDT 24
Peak memory 199876 kb
Host smart-50271a95-c93f-421e-8cf7-4f8d2e54487b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433195859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1433195859
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1426790236
Short name T202
Test name
Test status
Simulation time 33589595572 ps
CPU time 60.52 seconds
Started Aug 04 05:12:08 PM PDT 24
Finished Aug 04 05:13:08 PM PDT 24
Peak memory 199780 kb
Host smart-f7737b62-021a-4159-9ab4-f9adaebde00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426790236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1426790236
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.25678283
Short name T824
Test name
Test status
Simulation time 208715551460 ps
CPU time 22.66 seconds
Started Aug 04 05:12:12 PM PDT 24
Finished Aug 04 05:12:34 PM PDT 24
Peak memory 199920 kb
Host smart-25aedc55-21ba-447b-bd62-a6c66fdc91d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25678283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.25678283
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3918891881
Short name T147
Test name
Test status
Simulation time 82587005844 ps
CPU time 32.39 seconds
Started Aug 04 05:12:12 PM PDT 24
Finished Aug 04 05:12:45 PM PDT 24
Peak memory 199772 kb
Host smart-8453824e-5500-4f67-86b3-942ab05f3074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918891881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3918891881
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1398908190
Short name T973
Test name
Test status
Simulation time 13679945 ps
CPU time 0.58 seconds
Started Aug 04 05:08:15 PM PDT 24
Finished Aug 04 05:08:16 PM PDT 24
Peak memory 194664 kb
Host smart-8d6c24e3-72eb-46c9-b561-0c561abe2c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398908190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1398908190
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1000478016
Short name T42
Test name
Test status
Simulation time 84024761585 ps
CPU time 64.2 seconds
Started Aug 04 05:08:12 PM PDT 24
Finished Aug 04 05:09:17 PM PDT 24
Peak memory 199812 kb
Host smart-13d02ad7-0cdb-4167-a558-66992ac94449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000478016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1000478016
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.4125011393
Short name T796
Test name
Test status
Simulation time 53548022945 ps
CPU time 53.81 seconds
Started Aug 04 05:08:13 PM PDT 24
Finished Aug 04 05:09:07 PM PDT 24
Peak memory 199848 kb
Host smart-093a6711-bb36-44f4-a335-f880ab0b348c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125011393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.4125011393
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3807928997
Short name T555
Test name
Test status
Simulation time 152703117918 ps
CPU time 22.83 seconds
Started Aug 04 05:08:14 PM PDT 24
Finished Aug 04 05:08:37 PM PDT 24
Peak memory 199848 kb
Host smart-7360e44d-9410-418b-a31a-80b812a3c59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807928997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3807928997
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.1750069451
Short name T740
Test name
Test status
Simulation time 29658786435 ps
CPU time 13.22 seconds
Started Aug 04 05:08:17 PM PDT 24
Finished Aug 04 05:08:31 PM PDT 24
Peak memory 199824 kb
Host smart-604ff770-e07a-44a3-89a1-ca2d9b43ee49
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750069451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1750069451
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3097427362
Short name T777
Test name
Test status
Simulation time 166635988695 ps
CPU time 759.24 seconds
Started Aug 04 05:08:17 PM PDT 24
Finished Aug 04 05:20:57 PM PDT 24
Peak memory 199800 kb
Host smart-60e8f3f1-f140-4b7c-a2fc-b3b1dddcffd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3097427362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3097427362
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2116898675
Short name T353
Test name
Test status
Simulation time 1709919398 ps
CPU time 3.53 seconds
Started Aug 04 05:08:17 PM PDT 24
Finished Aug 04 05:08:20 PM PDT 24
Peak memory 197368 kb
Host smart-92b8c729-22d0-4444-a8b0-862ed6e6c248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116898675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2116898675
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.3529570800
Short name T731
Test name
Test status
Simulation time 52537462775 ps
CPU time 87.48 seconds
Started Aug 04 05:08:18 PM PDT 24
Finished Aug 04 05:09:45 PM PDT 24
Peak memory 199264 kb
Host smart-080828b4-2c8a-49cd-bc42-f73fb2c23594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529570800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3529570800
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.964448734
Short name T1116
Test name
Test status
Simulation time 17063775411 ps
CPU time 123.98 seconds
Started Aug 04 05:08:15 PM PDT 24
Finished Aug 04 05:10:19 PM PDT 24
Peak memory 199860 kb
Host smart-0eb8a229-3d3c-4ebc-a866-192650245520
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=964448734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.964448734
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1090303335
Short name T367
Test name
Test status
Simulation time 2012332130 ps
CPU time 5.98 seconds
Started Aug 04 05:08:14 PM PDT 24
Finished Aug 04 05:08:20 PM PDT 24
Peak memory 197828 kb
Host smart-3c6f7a41-ed6e-467d-8101-f96110abbe35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1090303335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1090303335
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.657044115
Short name T538
Test name
Test status
Simulation time 207507136180 ps
CPU time 101.61 seconds
Started Aug 04 05:08:17 PM PDT 24
Finished Aug 04 05:09:59 PM PDT 24
Peak memory 199748 kb
Host smart-a92997ae-6056-4336-adfd-9b9c8dfe2af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657044115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.657044115
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3352250729
Short name T107
Test name
Test status
Simulation time 2080170312 ps
CPU time 1.47 seconds
Started Aug 04 05:08:16 PM PDT 24
Finished Aug 04 05:08:18 PM PDT 24
Peak memory 195396 kb
Host smart-f005a56d-f85e-4b23-9b3b-2f1d3f7fe9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352250729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3352250729
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.301606818
Short name T795
Test name
Test status
Simulation time 931361261 ps
CPU time 3.48 seconds
Started Aug 04 05:08:13 PM PDT 24
Finished Aug 04 05:08:16 PM PDT 24
Peak memory 198896 kb
Host smart-92fa388b-e836-4aa1-8d38-e3e8abea0da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301606818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.301606818
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.4109141777
Short name T444
Test name
Test status
Simulation time 72221594372 ps
CPU time 879.39 seconds
Started Aug 04 05:08:19 PM PDT 24
Finished Aug 04 05:22:58 PM PDT 24
Peak memory 199788 kb
Host smart-a40494ac-cca2-4ceb-88c0-b125d802ecef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109141777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.4109141777
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.608446652
Short name T1108
Test name
Test status
Simulation time 58828244267 ps
CPU time 691.88 seconds
Started Aug 04 05:08:16 PM PDT 24
Finished Aug 04 05:19:48 PM PDT 24
Peak memory 216356 kb
Host smart-4a40e37a-c2ec-4a0b-9e21-481ac0d2591c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608446652 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.608446652
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2304436414
Short name T472
Test name
Test status
Simulation time 2838241878 ps
CPU time 2.09 seconds
Started Aug 04 05:08:16 PM PDT 24
Finished Aug 04 05:08:18 PM PDT 24
Peak memory 198720 kb
Host smart-cedb2ef7-652c-4fea-aeb4-6a53642ef6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304436414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2304436414
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.4106976403
Short name T392
Test name
Test status
Simulation time 35868310062 ps
CPU time 65.72 seconds
Started Aug 04 05:08:17 PM PDT 24
Finished Aug 04 05:09:23 PM PDT 24
Peak memory 199844 kb
Host smart-bab203f5-bf19-4c3c-91f8-128f32d4430f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106976403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.4106976403
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2656562479
Short name T101
Test name
Test status
Simulation time 25590573731 ps
CPU time 16.32 seconds
Started Aug 04 05:12:14 PM PDT 24
Finished Aug 04 05:12:30 PM PDT 24
Peak memory 199872 kb
Host smart-ba1ecfd0-4864-4c77-8c4b-23179af03c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656562479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2656562479
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1659433293
Short name T891
Test name
Test status
Simulation time 12739984514 ps
CPU time 18.94 seconds
Started Aug 04 05:12:11 PM PDT 24
Finished Aug 04 05:12:30 PM PDT 24
Peak memory 199776 kb
Host smart-ad137d81-4521-4f59-8ae8-6102e595127b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659433293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1659433293
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.1709736332
Short name T518
Test name
Test status
Simulation time 71569568508 ps
CPU time 128.76 seconds
Started Aug 04 05:12:12 PM PDT 24
Finished Aug 04 05:14:21 PM PDT 24
Peak memory 199836 kb
Host smart-92fed13a-71eb-4702-ac34-de51598f825b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709736332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1709736332
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1551635664
Short name T302
Test name
Test status
Simulation time 87566776237 ps
CPU time 149.73 seconds
Started Aug 04 05:12:12 PM PDT 24
Finished Aug 04 05:14:42 PM PDT 24
Peak memory 199904 kb
Host smart-11bcf81c-c6d5-489f-aad3-68d98db8aa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551635664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1551635664
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.389952776
Short name T650
Test name
Test status
Simulation time 73522141324 ps
CPU time 63.89 seconds
Started Aug 04 05:12:13 PM PDT 24
Finished Aug 04 05:13:17 PM PDT 24
Peak memory 199800 kb
Host smart-5a57a75f-4677-4ff4-8c43-7b1e565fc9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389952776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.389952776
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2516936139
Short name T122
Test name
Test status
Simulation time 43359566637 ps
CPU time 32.31 seconds
Started Aug 04 05:12:12 PM PDT 24
Finished Aug 04 05:12:45 PM PDT 24
Peak memory 199864 kb
Host smart-7d9bafbb-b666-4e60-9cbe-d46c2e4bac5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516936139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2516936139
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1372965321
Short name T191
Test name
Test status
Simulation time 21420258898 ps
CPU time 29.24 seconds
Started Aug 04 05:12:11 PM PDT 24
Finished Aug 04 05:12:40 PM PDT 24
Peak memory 199624 kb
Host smart-aacc6f58-c0ea-4e3b-93cc-bdbfe8a8d281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372965321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1372965321
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.591518487
Short name T829
Test name
Test status
Simulation time 103015694008 ps
CPU time 152.06 seconds
Started Aug 04 05:12:16 PM PDT 24
Finished Aug 04 05:14:48 PM PDT 24
Peak memory 200140 kb
Host smart-cc932e35-1380-4af6-b7c9-a63aebf3fd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591518487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.591518487
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3723549368
Short name T724
Test name
Test status
Simulation time 177431386581 ps
CPU time 29.98 seconds
Started Aug 04 05:12:20 PM PDT 24
Finished Aug 04 05:12:50 PM PDT 24
Peak memory 199756 kb
Host smart-6b75be5a-c69e-48f8-9e98-4ff4f7c52ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723549368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3723549368
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2422207740
Short name T709
Test name
Test status
Simulation time 21030549 ps
CPU time 0.57 seconds
Started Aug 04 05:08:21 PM PDT 24
Finished Aug 04 05:08:22 PM PDT 24
Peak memory 195188 kb
Host smart-6ef2dde2-f996-4396-a043-770d3a53926e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422207740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2422207740
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2985274764
Short name T136
Test name
Test status
Simulation time 61442540125 ps
CPU time 23.14 seconds
Started Aug 04 05:08:21 PM PDT 24
Finished Aug 04 05:08:44 PM PDT 24
Peak memory 199804 kb
Host smart-95b1dbd2-26cb-4cc2-b9c4-cf2ecb26147b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985274764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2985274764
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.947673498
Short name T110
Test name
Test status
Simulation time 102549686314 ps
CPU time 151.36 seconds
Started Aug 04 05:08:21 PM PDT 24
Finished Aug 04 05:10:53 PM PDT 24
Peak memory 199840 kb
Host smart-8cde32e9-6e68-46db-bb11-2ba1f1c3b500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947673498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.947673498
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2738706278
Short name T176
Test name
Test status
Simulation time 220864996270 ps
CPU time 58.05 seconds
Started Aug 04 05:08:20 PM PDT 24
Finished Aug 04 05:09:18 PM PDT 24
Peak memory 199816 kb
Host smart-f9143d47-b732-48c5-b6e7-34d7bd887268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738706278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2738706278
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.4015308659
Short name T1094
Test name
Test status
Simulation time 25415100439 ps
CPU time 37.06 seconds
Started Aug 04 05:08:22 PM PDT 24
Finished Aug 04 05:08:59 PM PDT 24
Peak memory 199884 kb
Host smart-37b56b99-fb7b-433a-8b9d-fdb5446759b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015308659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.4015308659
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.308356765
Short name T1164
Test name
Test status
Simulation time 100320747251 ps
CPU time 188.1 seconds
Started Aug 04 05:08:22 PM PDT 24
Finished Aug 04 05:11:30 PM PDT 24
Peak memory 199936 kb
Host smart-3a2fc882-3910-4650-9bbb-8ce9782d7ccf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=308356765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.308356765
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1415925026
Short name T1107
Test name
Test status
Simulation time 2665254637 ps
CPU time 2.99 seconds
Started Aug 04 05:08:21 PM PDT 24
Finished Aug 04 05:08:24 PM PDT 24
Peak memory 198248 kb
Host smart-183cd81d-da72-4507-950c-c6908bf0c77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415925026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1415925026
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.1055103932
Short name T961
Test name
Test status
Simulation time 84487232982 ps
CPU time 582.81 seconds
Started Aug 04 05:08:22 PM PDT 24
Finished Aug 04 05:18:05 PM PDT 24
Peak memory 199924 kb
Host smart-812a8028-bbca-4bc0-9ce2-e823707c0483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055103932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1055103932
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3143628670
Short name T805
Test name
Test status
Simulation time 12763319088 ps
CPU time 212.55 seconds
Started Aug 04 05:08:23 PM PDT 24
Finished Aug 04 05:11:56 PM PDT 24
Peak memory 199820 kb
Host smart-c33791a9-c8d4-4f78-b309-9a1afe8bc3a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3143628670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3143628670
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2546320747
Short name T1037
Test name
Test status
Simulation time 1377078147 ps
CPU time 6.05 seconds
Started Aug 04 05:08:20 PM PDT 24
Finished Aug 04 05:08:26 PM PDT 24
Peak memory 198016 kb
Host smart-30d6d819-ece0-4dc8-8c4f-e7e7954828ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2546320747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2546320747
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1094296112
Short name T1138
Test name
Test status
Simulation time 2565878041 ps
CPU time 4.8 seconds
Started Aug 04 05:08:20 PM PDT 24
Finished Aug 04 05:08:24 PM PDT 24
Peak memory 196428 kb
Host smart-a7649fc7-e307-4967-b0e1-c4adfb232f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094296112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1094296112
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.810802258
Short name T1057
Test name
Test status
Simulation time 5360211718 ps
CPU time 7.81 seconds
Started Aug 04 05:08:17 PM PDT 24
Finished Aug 04 05:08:25 PM PDT 24
Peak memory 199848 kb
Host smart-a1b525a4-a3da-476c-a6a3-c7c6c21a3474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810802258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.810802258
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1797722539
Short name T1105
Test name
Test status
Simulation time 177810940160 ps
CPU time 205.77 seconds
Started Aug 04 05:08:22 PM PDT 24
Finished Aug 04 05:11:48 PM PDT 24
Peak memory 199860 kb
Host smart-1b3e7191-6b62-43d5-a825-fec66474f520
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797722539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1797722539
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.2585097243
Short name T1078
Test name
Test status
Simulation time 85580688002 ps
CPU time 1596.1 seconds
Started Aug 04 05:08:20 PM PDT 24
Finished Aug 04 05:34:57 PM PDT 24
Peak memory 213124 kb
Host smart-799d253c-5da7-4935-97e1-064b1baed934
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585097243 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.2585097243
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.773677913
Short name T1141
Test name
Test status
Simulation time 1064429175 ps
CPU time 1.62 seconds
Started Aug 04 05:08:21 PM PDT 24
Finished Aug 04 05:08:23 PM PDT 24
Peak memory 198224 kb
Host smart-416b0a6a-d44e-4921-9fd4-f9e82dba24b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773677913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.773677913
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3440449947
Short name T400
Test name
Test status
Simulation time 41206502758 ps
CPU time 16.13 seconds
Started Aug 04 05:08:21 PM PDT 24
Finished Aug 04 05:08:38 PM PDT 24
Peak memory 197548 kb
Host smart-0b8cfccd-73a6-47a2-82d0-e6de644314cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440449947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3440449947
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2150213341
Short name T355
Test name
Test status
Simulation time 107852418360 ps
CPU time 143.56 seconds
Started Aug 04 05:12:16 PM PDT 24
Finished Aug 04 05:14:39 PM PDT 24
Peak memory 199688 kb
Host smart-f5b8216f-d82d-4600-98fd-256df3317a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150213341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2150213341
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.814324052
Short name T842
Test name
Test status
Simulation time 24129567454 ps
CPU time 39.76 seconds
Started Aug 04 05:12:15 PM PDT 24
Finished Aug 04 05:12:55 PM PDT 24
Peak memory 199756 kb
Host smart-9bba13b6-3fbf-444d-8186-9e2c76813a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814324052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.814324052
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2351083645
Short name T121
Test name
Test status
Simulation time 8527880674 ps
CPU time 16.24 seconds
Started Aug 04 05:12:16 PM PDT 24
Finished Aug 04 05:12:33 PM PDT 24
Peak memory 199904 kb
Host smart-12d68855-c2b4-40fc-bc28-430914b8ba1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351083645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2351083645
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.939443079
Short name T1090
Test name
Test status
Simulation time 50062778284 ps
CPU time 67.24 seconds
Started Aug 04 05:12:16 PM PDT 24
Finished Aug 04 05:13:23 PM PDT 24
Peak memory 199924 kb
Host smart-3db75d27-81e5-4c6c-87f9-8d7a72777859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939443079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.939443079
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1970278762
Short name T1147
Test name
Test status
Simulation time 62807698593 ps
CPU time 72.42 seconds
Started Aug 04 05:12:16 PM PDT 24
Finished Aug 04 05:13:29 PM PDT 24
Peak memory 199888 kb
Host smart-7a7fcfd4-dd97-420b-9eb9-cdb33113f519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970278762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1970278762
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1250480099
Short name T193
Test name
Test status
Simulation time 188201476395 ps
CPU time 83.88 seconds
Started Aug 04 05:12:17 PM PDT 24
Finished Aug 04 05:13:41 PM PDT 24
Peak memory 199820 kb
Host smart-630292ad-2e9b-4ecd-a3d6-876c91e70b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250480099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1250480099
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.311002914
Short name T825
Test name
Test status
Simulation time 55545032671 ps
CPU time 17.68 seconds
Started Aug 04 05:12:19 PM PDT 24
Finished Aug 04 05:12:37 PM PDT 24
Peak memory 199604 kb
Host smart-65e08195-d4f4-413e-b5a2-cedf92e8ed18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311002914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.311002914
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.375437258
Short name T566
Test name
Test status
Simulation time 14773941729 ps
CPU time 21.53 seconds
Started Aug 04 05:12:17 PM PDT 24
Finished Aug 04 05:12:39 PM PDT 24
Peak memory 199896 kb
Host smart-8dc5fcaf-7c7b-4a64-bb17-af017c9ec0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375437258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.375437258
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.218420432
Short name T330
Test name
Test status
Simulation time 115702103646 ps
CPU time 160.94 seconds
Started Aug 04 05:12:17 PM PDT 24
Finished Aug 04 05:14:58 PM PDT 24
Peak memory 199904 kb
Host smart-809a0c2d-6664-4f7c-a0d0-56ccf8959b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218420432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.218420432
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.74095270
Short name T208
Test name
Test status
Simulation time 126801995453 ps
CPU time 56.85 seconds
Started Aug 04 05:12:15 PM PDT 24
Finished Aug 04 05:13:12 PM PDT 24
Peak memory 199868 kb
Host smart-eae99dc2-03a2-4f14-9cc0-891d0a546b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74095270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.74095270
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1747808604
Short name T586
Test name
Test status
Simulation time 11063656 ps
CPU time 0.55 seconds
Started Aug 04 05:08:30 PM PDT 24
Finished Aug 04 05:08:30 PM PDT 24
Peak memory 195240 kb
Host smart-3ec9914e-3a2b-4202-86ca-ecbb9c072df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747808604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1747808604
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3472889602
Short name T317
Test name
Test status
Simulation time 69022576075 ps
CPU time 56.71 seconds
Started Aug 04 05:08:22 PM PDT 24
Finished Aug 04 05:09:19 PM PDT 24
Peak memory 199892 kb
Host smart-b2b85b43-d2ca-442d-9f70-a0b6e4104174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472889602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3472889602
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.912575775
Short name T426
Test name
Test status
Simulation time 97264460310 ps
CPU time 71.8 seconds
Started Aug 04 05:08:24 PM PDT 24
Finished Aug 04 05:09:35 PM PDT 24
Peak memory 199872 kb
Host smart-4ab36cdc-5a3f-4567-9b16-0d0b9df3d6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912575775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.912575775
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.930769502
Short name T200
Test name
Test status
Simulation time 45911727934 ps
CPU time 31.92 seconds
Started Aug 04 05:08:24 PM PDT 24
Finished Aug 04 05:08:56 PM PDT 24
Peak memory 199760 kb
Host smart-bc2e1053-e539-447a-bff7-49ed967451f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930769502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.930769502
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3443118877
Short name T590
Test name
Test status
Simulation time 8624275567 ps
CPU time 4.32 seconds
Started Aug 04 05:08:23 PM PDT 24
Finished Aug 04 05:08:27 PM PDT 24
Peak memory 198908 kb
Host smart-cfe10089-0949-4375-8644-5fedb06d239b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443118877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3443118877
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1773131093
Short name T569
Test name
Test status
Simulation time 108836049839 ps
CPU time 96.99 seconds
Started Aug 04 05:08:26 PM PDT 24
Finished Aug 04 05:10:03 PM PDT 24
Peak memory 199804 kb
Host smart-f4f73ce5-ff4c-4793-b08b-fa1a07a7c763
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1773131093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1773131093
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1520507681
Short name T325
Test name
Test status
Simulation time 7238149563 ps
CPU time 6.77 seconds
Started Aug 04 05:08:26 PM PDT 24
Finished Aug 04 05:08:33 PM PDT 24
Peak memory 198824 kb
Host smart-9bb04eb6-c726-445d-beb3-114df975639b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520507681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1520507681
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.4232072903
Short name T432
Test name
Test status
Simulation time 18708951978 ps
CPU time 30.96 seconds
Started Aug 04 05:08:23 PM PDT 24
Finished Aug 04 05:08:54 PM PDT 24
Peak memory 197988 kb
Host smart-7f213141-7074-466e-8d8e-deff369ea678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232072903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.4232072903
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3185452614
Short name T666
Test name
Test status
Simulation time 27045350939 ps
CPU time 1264.44 seconds
Started Aug 04 05:08:27 PM PDT 24
Finished Aug 04 05:29:32 PM PDT 24
Peak memory 199844 kb
Host smart-f410f7f7-2a6d-4c69-8978-c51f8e0bb43c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3185452614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3185452614
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2403630573
Short name T947
Test name
Test status
Simulation time 3176829169 ps
CPU time 22.99 seconds
Started Aug 04 05:08:22 PM PDT 24
Finished Aug 04 05:08:45 PM PDT 24
Peak memory 199752 kb
Host smart-e12889c4-7435-45da-8c7f-216d4b3183f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2403630573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2403630573
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.850157615
Short name T490
Test name
Test status
Simulation time 69796058141 ps
CPU time 35.2 seconds
Started Aug 04 05:08:26 PM PDT 24
Finished Aug 04 05:09:01 PM PDT 24
Peak memory 199748 kb
Host smart-9ae82d03-21a9-4e75-b1ce-507234346fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850157615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.850157615
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.4204833086
Short name T1171
Test name
Test status
Simulation time 1677016911 ps
CPU time 1.26 seconds
Started Aug 04 05:08:27 PM PDT 24
Finished Aug 04 05:08:28 PM PDT 24
Peak memory 195492 kb
Host smart-081a6442-a966-41f7-a208-90932c0cdab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204833086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.4204833086
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.985851863
Short name T411
Test name
Test status
Simulation time 6069378002 ps
CPU time 15.14 seconds
Started Aug 04 05:08:23 PM PDT 24
Finished Aug 04 05:08:38 PM PDT 24
Peak memory 199812 kb
Host smart-16264846-9ead-4fe8-8e87-d34af5fe7881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985851863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.985851863
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3067100024
Short name T221
Test name
Test status
Simulation time 88824330623 ps
CPU time 151.5 seconds
Started Aug 04 05:08:27 PM PDT 24
Finished Aug 04 05:10:58 PM PDT 24
Peak memory 199908 kb
Host smart-35e9c957-7a17-45bc-8c4e-db32160cd177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067100024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3067100024
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1464746789
Short name T104
Test name
Test status
Simulation time 61905226936 ps
CPU time 285.31 seconds
Started Aug 04 05:08:26 PM PDT 24
Finished Aug 04 05:13:12 PM PDT 24
Peak memory 216348 kb
Host smart-22df1fca-4bf2-4646-ae85-02d7290cba04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464746789 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1464746789
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.49083048
Short name T470
Test name
Test status
Simulation time 470801670 ps
CPU time 1.53 seconds
Started Aug 04 05:08:27 PM PDT 24
Finished Aug 04 05:08:28 PM PDT 24
Peak memory 198292 kb
Host smart-8c6a0fa1-2ffa-4cf6-9027-bb482a548e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49083048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.49083048
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1618768474
Short name T10
Test name
Test status
Simulation time 19234976760 ps
CPU time 28.83 seconds
Started Aug 04 05:08:23 PM PDT 24
Finished Aug 04 05:08:52 PM PDT 24
Peak memory 199908 kb
Host smart-370ba3bf-f37c-491e-855e-6ac305016f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618768474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1618768474
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.447989653
Short name T1009
Test name
Test status
Simulation time 206266309623 ps
CPU time 71.37 seconds
Started Aug 04 05:12:22 PM PDT 24
Finished Aug 04 05:13:34 PM PDT 24
Peak memory 199884 kb
Host smart-8bb77431-121c-41fd-89ab-3060425473f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447989653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.447989653
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3531393187
Short name T1126
Test name
Test status
Simulation time 17683189515 ps
CPU time 24.3 seconds
Started Aug 04 05:12:23 PM PDT 24
Finished Aug 04 05:12:47 PM PDT 24
Peak memory 199936 kb
Host smart-e421d10e-1018-4c94-ae79-6481f419f2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531393187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3531393187
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.447550060
Short name T11
Test name
Test status
Simulation time 7076164575 ps
CPU time 11.68 seconds
Started Aug 04 05:12:24 PM PDT 24
Finished Aug 04 05:12:36 PM PDT 24
Peak memory 199908 kb
Host smart-619d7425-52e6-461c-88d5-f9b33f285b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447550060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.447550060
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.814740704
Short name T1011
Test name
Test status
Simulation time 12727520123 ps
CPU time 11.57 seconds
Started Aug 04 05:12:20 PM PDT 24
Finished Aug 04 05:12:32 PM PDT 24
Peak memory 199836 kb
Host smart-410d0981-8c36-485f-8a01-616441277cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814740704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.814740704
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2157014530
Short name T867
Test name
Test status
Simulation time 86363944906 ps
CPU time 143.87 seconds
Started Aug 04 05:12:25 PM PDT 24
Finished Aug 04 05:14:49 PM PDT 24
Peak memory 199880 kb
Host smart-79bf3c0f-f6c5-4676-abb6-1aeedf304429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157014530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2157014530
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.287399714
Short name T238
Test name
Test status
Simulation time 90838577355 ps
CPU time 93.04 seconds
Started Aug 04 05:12:20 PM PDT 24
Finished Aug 04 05:13:54 PM PDT 24
Peak memory 199888 kb
Host smart-86403f91-e324-4536-82cf-6aebdacb3a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287399714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.287399714
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1158250188
Short name T168
Test name
Test status
Simulation time 29898080143 ps
CPU time 18.11 seconds
Started Aug 04 05:12:22 PM PDT 24
Finished Aug 04 05:12:40 PM PDT 24
Peak memory 199940 kb
Host smart-b6622464-6ff1-46c7-a7f0-f7ddb6fcd0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158250188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1158250188
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2229930274
Short name T227
Test name
Test status
Simulation time 47703108028 ps
CPU time 22.51 seconds
Started Aug 04 05:12:22 PM PDT 24
Finished Aug 04 05:12:45 PM PDT 24
Peak memory 199832 kb
Host smart-50b51c64-b9bf-4897-84d4-95f5745c0bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229930274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2229930274
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3170198809
Short name T1095
Test name
Test status
Simulation time 12924077 ps
CPU time 0.55 seconds
Started Aug 04 05:08:34 PM PDT 24
Finished Aug 04 05:08:34 PM PDT 24
Peak memory 195528 kb
Host smart-ba7a559b-bce8-49b0-8a6c-9eb0b32e8cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170198809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3170198809
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.579806593
Short name T158
Test name
Test status
Simulation time 38783803453 ps
CPU time 14.17 seconds
Started Aug 04 05:08:30 PM PDT 24
Finished Aug 04 05:08:44 PM PDT 24
Peak memory 199780 kb
Host smart-b8fcfc83-c0db-4e8d-ad8e-0335e90de69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579806593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.579806593
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1225204853
Short name T1033
Test name
Test status
Simulation time 21666179794 ps
CPU time 14.96 seconds
Started Aug 04 05:08:29 PM PDT 24
Finished Aug 04 05:08:44 PM PDT 24
Peak memory 199792 kb
Host smart-31b71701-fa27-4ca9-93c0-4594192b887e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225204853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1225204853
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.432961070
Short name T343
Test name
Test status
Simulation time 112526434337 ps
CPU time 163.67 seconds
Started Aug 04 05:08:29 PM PDT 24
Finished Aug 04 05:11:13 PM PDT 24
Peak memory 200144 kb
Host smart-ce44b8b7-a106-41bc-8dcf-73a62a746fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432961070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.432961070
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.3317130017
Short name T706
Test name
Test status
Simulation time 14969458659 ps
CPU time 27.41 seconds
Started Aug 04 05:08:38 PM PDT 24
Finished Aug 04 05:09:05 PM PDT 24
Peak memory 199764 kb
Host smart-12416734-f8fb-4f7e-a43b-205363d44f9b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317130017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3317130017
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2578606211
Short name T1155
Test name
Test status
Simulation time 102896249298 ps
CPU time 262.49 seconds
Started Aug 04 05:08:34 PM PDT 24
Finished Aug 04 05:12:56 PM PDT 24
Peak memory 199868 kb
Host smart-4d7afd84-b04e-4317-9424-1dd61a63db89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2578606211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2578606211
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2446425726
Short name T988
Test name
Test status
Simulation time 115444814 ps
CPU time 0.82 seconds
Started Aug 04 05:08:37 PM PDT 24
Finished Aug 04 05:08:38 PM PDT 24
Peak memory 197224 kb
Host smart-8aa1ea6c-cc72-4207-ac7e-97ac9fc8f390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446425726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2446425726
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.705463782
Short name T977
Test name
Test status
Simulation time 181445614923 ps
CPU time 108.64 seconds
Started Aug 04 05:08:30 PM PDT 24
Finished Aug 04 05:10:19 PM PDT 24
Peak memory 200040 kb
Host smart-84cdcd3e-7003-4e23-9d3e-9134008ac018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705463782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.705463782
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.4197288556
Short name T244
Test name
Test status
Simulation time 27673963409 ps
CPU time 1666.79 seconds
Started Aug 04 05:08:29 PM PDT 24
Finished Aug 04 05:36:16 PM PDT 24
Peak memory 199824 kb
Host smart-a1983b1d-c033-445d-a3d9-2b862f06a212
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4197288556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.4197288556
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.664034245
Short name T919
Test name
Test status
Simulation time 1284024647 ps
CPU time 1.14 seconds
Started Aug 04 05:08:29 PM PDT 24
Finished Aug 04 05:08:31 PM PDT 24
Peak memory 195436 kb
Host smart-f2497533-159a-487e-912e-70467660672c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=664034245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.664034245
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1990889821
Short name T790
Test name
Test status
Simulation time 13341322546 ps
CPU time 23.43 seconds
Started Aug 04 05:08:30 PM PDT 24
Finished Aug 04 05:08:53 PM PDT 24
Peak memory 199820 kb
Host smart-713a39a3-7d4b-42c6-8f37-8ab1143748c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990889821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1990889821
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1253668772
Short name T1022
Test name
Test status
Simulation time 2224456615 ps
CPU time 2.65 seconds
Started Aug 04 05:08:38 PM PDT 24
Finished Aug 04 05:08:41 PM PDT 24
Peak memory 195376 kb
Host smart-fab11e08-9290-42fb-b63c-da2d7c7b2a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253668772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1253668772
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2502417510
Short name T872
Test name
Test status
Simulation time 287422497 ps
CPU time 1.32 seconds
Started Aug 04 05:08:28 PM PDT 24
Finished Aug 04 05:08:29 PM PDT 24
Peak memory 197952 kb
Host smart-649430df-ce81-4b63-81d8-7e826fc51433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502417510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2502417510
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1169665913
Short name T1150
Test name
Test status
Simulation time 2236728444 ps
CPU time 2.31 seconds
Started Aug 04 05:08:38 PM PDT 24
Finished Aug 04 05:08:40 PM PDT 24
Peak memory 198564 kb
Host smart-81b7a2b7-b96c-4964-8400-492bad1b6dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169665913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1169665913
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1787241048
Short name T1160
Test name
Test status
Simulation time 86646572798 ps
CPU time 38.29 seconds
Started Aug 04 05:08:30 PM PDT 24
Finished Aug 04 05:09:08 PM PDT 24
Peak memory 199864 kb
Host smart-9c091d5e-cab2-4c94-8b77-8351cf62911b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787241048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1787241048
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1992873941
Short name T696
Test name
Test status
Simulation time 20059673498 ps
CPU time 15.85 seconds
Started Aug 04 05:12:21 PM PDT 24
Finished Aug 04 05:12:37 PM PDT 24
Peak memory 199836 kb
Host smart-f67af192-3747-42d8-83be-c9b2496b9990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992873941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1992873941
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.998475096
Short name T1036
Test name
Test status
Simulation time 34608189853 ps
CPU time 23.16 seconds
Started Aug 04 05:12:21 PM PDT 24
Finished Aug 04 05:12:44 PM PDT 24
Peak memory 199848 kb
Host smart-d666992e-41b1-4e5d-b218-6a405ba40ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998475096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.998475096
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.204870150
Short name T513
Test name
Test status
Simulation time 19161851501 ps
CPU time 28.86 seconds
Started Aug 04 05:12:25 PM PDT 24
Finished Aug 04 05:12:54 PM PDT 24
Peak memory 199860 kb
Host smart-87ae974b-7dd4-4a1a-a331-b2bd83e8ca85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204870150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.204870150
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.893507336
Short name T375
Test name
Test status
Simulation time 90646494101 ps
CPU time 126.66 seconds
Started Aug 04 05:12:21 PM PDT 24
Finished Aug 04 05:14:28 PM PDT 24
Peak memory 199840 kb
Host smart-e3d42a8f-dff1-4516-81fd-6f3a66a02bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893507336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.893507336
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3427187616
Short name T184
Test name
Test status
Simulation time 24907269820 ps
CPU time 34.83 seconds
Started Aug 04 05:12:21 PM PDT 24
Finished Aug 04 05:12:56 PM PDT 24
Peak memory 199700 kb
Host smart-b0d83eba-b1d9-4420-bb52-72c94f4185f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427187616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3427187616
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1949169732
Short name T634
Test name
Test status
Simulation time 194965909448 ps
CPU time 157.39 seconds
Started Aug 04 05:12:25 PM PDT 24
Finished Aug 04 05:15:03 PM PDT 24
Peak memory 199796 kb
Host smart-7f8c196a-d243-414c-b58a-2d0625dd91a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949169732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1949169732
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3787645565
Short name T1073
Test name
Test status
Simulation time 147624218703 ps
CPU time 40.24 seconds
Started Aug 04 05:12:20 PM PDT 24
Finished Aug 04 05:13:00 PM PDT 24
Peak memory 199632 kb
Host smart-103a9ebd-5501-464b-b133-2134ee5d25f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787645565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3787645565
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.4151810638
Short name T764
Test name
Test status
Simulation time 111592241129 ps
CPU time 80.23 seconds
Started Aug 04 05:12:21 PM PDT 24
Finished Aug 04 05:13:42 PM PDT 24
Peak memory 199820 kb
Host smart-2498c0cb-3a1f-4996-bc12-3f7749b6eebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151810638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.4151810638
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1840181153
Short name T905
Test name
Test status
Simulation time 144384405926 ps
CPU time 100.72 seconds
Started Aug 04 05:12:21 PM PDT 24
Finished Aug 04 05:14:02 PM PDT 24
Peak memory 199728 kb
Host smart-750c4b4f-d902-446e-9c99-4912416bc0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840181153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1840181153
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.207492529
Short name T143
Test name
Test status
Simulation time 23049541870 ps
CPU time 38.33 seconds
Started Aug 04 05:12:20 PM PDT 24
Finished Aug 04 05:12:59 PM PDT 24
Peak memory 199808 kb
Host smart-ba08ecba-ec48-43db-aad5-96725c5937d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207492529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.207492529
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3601946304
Short name T542
Test name
Test status
Simulation time 23820807 ps
CPU time 0.56 seconds
Started Aug 04 05:08:38 PM PDT 24
Finished Aug 04 05:08:39 PM PDT 24
Peak memory 195296 kb
Host smart-3960310e-c4e1-4b88-8503-699bcb7eab38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601946304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3601946304
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3764095939
Short name T135
Test name
Test status
Simulation time 46732266354 ps
CPU time 21.05 seconds
Started Aug 04 05:08:32 PM PDT 24
Finished Aug 04 05:08:54 PM PDT 24
Peak memory 199896 kb
Host smart-07a05282-0b4b-478c-8859-afb2eaf3d951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764095939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3764095939
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.76920858
Short name T300
Test name
Test status
Simulation time 153530400911 ps
CPU time 222.67 seconds
Started Aug 04 05:08:32 PM PDT 24
Finished Aug 04 05:12:15 PM PDT 24
Peak memory 199860 kb
Host smart-38eaf2dc-5e88-4389-ad5f-66a220bda556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76920858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.76920858
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.187690902
Short name T331
Test name
Test status
Simulation time 15214868087 ps
CPU time 27.96 seconds
Started Aug 04 05:08:33 PM PDT 24
Finished Aug 04 05:09:01 PM PDT 24
Peak memory 199816 kb
Host smart-78b10b16-9c69-4bc2-98e6-1d1503c39b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187690902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.187690902
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.2347048179
Short name T837
Test name
Test status
Simulation time 28688464054 ps
CPU time 49.17 seconds
Started Aug 04 05:08:34 PM PDT 24
Finished Aug 04 05:09:23 PM PDT 24
Peak memory 199548 kb
Host smart-c47f9f7a-8396-42b8-b6a3-bf68fafe0bab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347048179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2347048179
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3641588574
Short name T1024
Test name
Test status
Simulation time 76137949833 ps
CPU time 250.7 seconds
Started Aug 04 05:08:36 PM PDT 24
Finished Aug 04 05:12:47 PM PDT 24
Peak memory 199872 kb
Host smart-d25b1ff0-a1f9-4a71-9be3-f3d875cd1c13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3641588574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3641588574
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3279119118
Short name T361
Test name
Test status
Simulation time 3966839788 ps
CPU time 6.48 seconds
Started Aug 04 05:08:37 PM PDT 24
Finished Aug 04 05:08:43 PM PDT 24
Peak memory 197876 kb
Host smart-6bb85ee7-5dc3-4412-ae0e-96f23231c777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279119118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3279119118
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.300179823
Short name T743
Test name
Test status
Simulation time 33362794898 ps
CPU time 35.32 seconds
Started Aug 04 05:08:35 PM PDT 24
Finished Aug 04 05:09:11 PM PDT 24
Peak memory 199952 kb
Host smart-d18a73db-4c0a-4f9f-a06b-3a22d7f2ab68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300179823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.300179823
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1466110917
Short name T100
Test name
Test status
Simulation time 14788357984 ps
CPU time 876.4 seconds
Started Aug 04 05:08:36 PM PDT 24
Finished Aug 04 05:23:13 PM PDT 24
Peak memory 199800 kb
Host smart-430dc831-d0bb-407e-83f1-024050d8644f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1466110917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1466110917
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.4036829277
Short name T324
Test name
Test status
Simulation time 1789679272 ps
CPU time 9.09 seconds
Started Aug 04 05:08:34 PM PDT 24
Finished Aug 04 05:08:43 PM PDT 24
Peak memory 198068 kb
Host smart-73a809c5-e805-4915-a403-ce6a7cce4c74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036829277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.4036829277
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3738199472
Short name T668
Test name
Test status
Simulation time 177031277516 ps
CPU time 19.72 seconds
Started Aug 04 05:08:37 PM PDT 24
Finished Aug 04 05:08:57 PM PDT 24
Peak memory 199876 kb
Host smart-22cf348e-8a55-436e-aa8b-95d284115a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738199472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3738199472
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1812467183
Short name T384
Test name
Test status
Simulation time 639737388 ps
CPU time 1.66 seconds
Started Aug 04 05:08:36 PM PDT 24
Finished Aug 04 05:08:38 PM PDT 24
Peak memory 195404 kb
Host smart-d98afb02-d3a8-4e91-9749-575749e24e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812467183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1812467183
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2771332653
Short name T303
Test name
Test status
Simulation time 5839713359 ps
CPU time 8.88 seconds
Started Aug 04 05:08:32 PM PDT 24
Finished Aug 04 05:08:41 PM PDT 24
Peak memory 199504 kb
Host smart-80ce4bf6-f747-400e-a704-16a0fd1ce32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771332653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2771332653
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.892127375
Short name T1153
Test name
Test status
Simulation time 189008098832 ps
CPU time 282.48 seconds
Started Aug 04 05:08:36 PM PDT 24
Finished Aug 04 05:13:19 PM PDT 24
Peak memory 208236 kb
Host smart-e0aba8d3-270b-4561-a511-0bb4510e486a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892127375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.892127375
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1900629566
Short name T847
Test name
Test status
Simulation time 34516293985 ps
CPU time 551.85 seconds
Started Aug 04 05:08:35 PM PDT 24
Finished Aug 04 05:17:47 PM PDT 24
Peak memory 216168 kb
Host smart-e6367d6f-bd13-4772-975b-c32ae315e394
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900629566 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1900629566
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1496377123
Short name T1167
Test name
Test status
Simulation time 7151071867 ps
CPU time 8.89 seconds
Started Aug 04 05:08:35 PM PDT 24
Finished Aug 04 05:08:44 PM PDT 24
Peak memory 199416 kb
Host smart-73c37722-f8e0-4758-9469-93f55cb3806c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496377123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1496377123
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.4162547416
Short name T939
Test name
Test status
Simulation time 209941701624 ps
CPU time 93.39 seconds
Started Aug 04 05:08:34 PM PDT 24
Finished Aug 04 05:10:07 PM PDT 24
Peak memory 199840 kb
Host smart-31bc9c4f-5f76-4797-9e5d-4fa7fbb70b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162547416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.4162547416
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1991726294
Short name T1084
Test name
Test status
Simulation time 101094574056 ps
CPU time 41.73 seconds
Started Aug 04 05:12:24 PM PDT 24
Finished Aug 04 05:13:06 PM PDT 24
Peak memory 199696 kb
Host smart-6a23f0d2-2f2c-4ec1-acde-c504e3091a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991726294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1991726294
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.4240247379
Short name T916
Test name
Test status
Simulation time 55472290414 ps
CPU time 49.35 seconds
Started Aug 04 05:12:26 PM PDT 24
Finished Aug 04 05:13:15 PM PDT 24
Peak memory 199808 kb
Host smart-c64e94a5-e7b3-4443-b95e-3a76b0a12973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240247379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.4240247379
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.201867271
Short name T533
Test name
Test status
Simulation time 79145449929 ps
CPU time 30.9 seconds
Started Aug 04 05:12:26 PM PDT 24
Finished Aug 04 05:12:57 PM PDT 24
Peak memory 200084 kb
Host smart-c2c7afe0-d5af-41f1-8fc0-28ac9a124bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201867271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.201867271
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.582316577
Short name T648
Test name
Test status
Simulation time 72810939947 ps
CPU time 31.61 seconds
Started Aug 04 05:12:27 PM PDT 24
Finished Aug 04 05:12:58 PM PDT 24
Peak memory 199792 kb
Host smart-18e74a11-e770-47a6-8018-9eaeb082a45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582316577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.582316577
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.98370653
Short name T680
Test name
Test status
Simulation time 12564817100 ps
CPU time 22.1 seconds
Started Aug 04 05:12:25 PM PDT 24
Finished Aug 04 05:12:48 PM PDT 24
Peak memory 199820 kb
Host smart-c6878965-2c7f-43a6-b7dc-b4510025bc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98370653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.98370653
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.415420142
Short name T522
Test name
Test status
Simulation time 148780208996 ps
CPU time 67.72 seconds
Started Aug 04 05:12:25 PM PDT 24
Finished Aug 04 05:13:33 PM PDT 24
Peak memory 199872 kb
Host smart-11314c31-95ba-4f7b-a3e5-bb6ff8c33b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415420142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.415420142
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.4162973078
Short name T909
Test name
Test status
Simulation time 93617329325 ps
CPU time 88.22 seconds
Started Aug 04 05:12:25 PM PDT 24
Finished Aug 04 05:13:53 PM PDT 24
Peak memory 199860 kb
Host smart-f7d48a8d-a8a0-4477-a411-f47f8e92185d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162973078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.4162973078
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2229927754
Short name T493
Test name
Test status
Simulation time 167035641231 ps
CPU time 256.62 seconds
Started Aug 04 05:12:23 PM PDT 24
Finished Aug 04 05:16:40 PM PDT 24
Peak memory 199788 kb
Host smart-b1e341c5-cfcb-4010-b75e-30c7e6352ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229927754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2229927754
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2316164335
Short name T71
Test name
Test status
Simulation time 38935637612 ps
CPU time 31.62 seconds
Started Aug 04 05:12:26 PM PDT 24
Finished Aug 04 05:12:58 PM PDT 24
Peak memory 199872 kb
Host smart-0ca0dbdf-de28-4c0f-84e4-d1a570ccf48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316164335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2316164335
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1605871381
Short name T1161
Test name
Test status
Simulation time 55623716361 ps
CPU time 81.28 seconds
Started Aug 04 05:12:25 PM PDT 24
Finished Aug 04 05:13:46 PM PDT 24
Peak memory 199836 kb
Host smart-06a74cea-e7ae-4e9b-952d-a38519d2eb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605871381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1605871381
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.4128994589
Short name T521
Test name
Test status
Simulation time 14809991 ps
CPU time 0.54 seconds
Started Aug 04 05:08:43 PM PDT 24
Finished Aug 04 05:08:43 PM PDT 24
Peak memory 195268 kb
Host smart-b459af8c-a52d-4c9f-96a6-e5c923b0be87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128994589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.4128994589
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.930311657
Short name T313
Test name
Test status
Simulation time 34828109588 ps
CPU time 56.04 seconds
Started Aug 04 05:08:38 PM PDT 24
Finished Aug 04 05:09:35 PM PDT 24
Peak memory 199884 kb
Host smart-ea261942-6337-4523-a885-7ed7b951dff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930311657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.930311657
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1071815068
Short name T1062
Test name
Test status
Simulation time 31790831351 ps
CPU time 23.01 seconds
Started Aug 04 05:08:36 PM PDT 24
Finished Aug 04 05:08:59 PM PDT 24
Peak memory 199824 kb
Host smart-f2810f12-3e5d-4458-97c7-24763be6cfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071815068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1071815068
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3103880631
Short name T707
Test name
Test status
Simulation time 69177597926 ps
CPU time 25.79 seconds
Started Aug 04 05:08:41 PM PDT 24
Finished Aug 04 05:09:07 PM PDT 24
Peak memory 199544 kb
Host smart-ec9060f2-bbb0-428b-b18f-af69094924bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103880631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3103880631
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.3212485489
Short name T549
Test name
Test status
Simulation time 212321725681 ps
CPU time 80.63 seconds
Started Aug 04 05:08:40 PM PDT 24
Finished Aug 04 05:10:01 PM PDT 24
Peak memory 199196 kb
Host smart-f2f20baf-7fda-4ebe-b914-e14cdd0099f5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212485489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3212485489
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2751721383
Short name T935
Test name
Test status
Simulation time 103923093654 ps
CPU time 585.53 seconds
Started Aug 04 05:08:43 PM PDT 24
Finished Aug 04 05:18:28 PM PDT 24
Peak memory 199916 kb
Host smart-17d85b2a-fde1-450b-a8cc-1746e8ab5e4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2751721383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2751721383
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.4064601397
Short name T774
Test name
Test status
Simulation time 6569478974 ps
CPU time 14.5 seconds
Started Aug 04 05:08:43 PM PDT 24
Finished Aug 04 05:08:58 PM PDT 24
Peak memory 199456 kb
Host smart-31b6080f-76bb-4b6d-8a96-e000c8fdd42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064601397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.4064601397
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.1881931104
Short name T994
Test name
Test status
Simulation time 162276823740 ps
CPU time 81.15 seconds
Started Aug 04 05:08:40 PM PDT 24
Finished Aug 04 05:10:02 PM PDT 24
Peak memory 209280 kb
Host smart-2f531f27-122b-4e9a-a0f3-bcafef018c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881931104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1881931104
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.1964507982
Short name T581
Test name
Test status
Simulation time 22756255991 ps
CPU time 1291.98 seconds
Started Aug 04 05:08:43 PM PDT 24
Finished Aug 04 05:30:15 PM PDT 24
Peak memory 199844 kb
Host smart-b8e732ca-9e9f-458f-bc98-97bc20b01e87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1964507982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1964507982
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2137142010
Short name T520
Test name
Test status
Simulation time 3885380571 ps
CPU time 2.92 seconds
Started Aug 04 05:08:39 PM PDT 24
Finished Aug 04 05:08:42 PM PDT 24
Peak memory 198064 kb
Host smart-4f6066a8-077a-4dd1-afcf-6d23be767277
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2137142010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2137142010
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.282229122
Short name T704
Test name
Test status
Simulation time 54198683691 ps
CPU time 41.35 seconds
Started Aug 04 05:08:41 PM PDT 24
Finished Aug 04 05:09:22 PM PDT 24
Peak memory 199864 kb
Host smart-777dd21a-7508-45e2-bbd2-1b9f700c5982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282229122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.282229122
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.4142980946
Short name T47
Test name
Test status
Simulation time 3463262145 ps
CPU time 1.78 seconds
Started Aug 04 05:08:40 PM PDT 24
Finished Aug 04 05:08:41 PM PDT 24
Peak memory 196500 kb
Host smart-e0a4f3c4-438a-49a0-9b93-bcca01794a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142980946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.4142980946
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.77213338
Short name T407
Test name
Test status
Simulation time 11093994628 ps
CPU time 59.96 seconds
Started Aug 04 05:08:36 PM PDT 24
Finished Aug 04 05:09:36 PM PDT 24
Peak memory 199816 kb
Host smart-71a01af7-417a-4ef5-9e31-e480e0e4704d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77213338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.77213338
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2533016934
Short name T502
Test name
Test status
Simulation time 381138036 ps
CPU time 1.09 seconds
Started Aug 04 05:08:43 PM PDT 24
Finished Aug 04 05:08:45 PM PDT 24
Peak memory 198744 kb
Host smart-7b9d5bcd-fb65-4f94-a6bc-1e3ef0b9343e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533016934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2533016934
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.44241878
Short name T398
Test name
Test status
Simulation time 26090821054 ps
CPU time 36.72 seconds
Started Aug 04 05:08:36 PM PDT 24
Finished Aug 04 05:09:13 PM PDT 24
Peak memory 199764 kb
Host smart-dd5a1654-bc3a-4ec2-b8b6-0bfb50690339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44241878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.44241878
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2299046826
Short name T768
Test name
Test status
Simulation time 33165846152 ps
CPU time 13.24 seconds
Started Aug 04 05:12:29 PM PDT 24
Finished Aug 04 05:12:42 PM PDT 24
Peak memory 199736 kb
Host smart-edf70ee2-ca16-4a6c-9f4f-f16d75f3f385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299046826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2299046826
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.3278610469
Short name T1149
Test name
Test status
Simulation time 62874806589 ps
CPU time 13.82 seconds
Started Aug 04 05:12:30 PM PDT 24
Finished Aug 04 05:12:44 PM PDT 24
Peak memory 199936 kb
Host smart-f06ee3a4-c477-437d-84c7-84efe1b7f5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278610469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3278610469
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.4275223038
Short name T663
Test name
Test status
Simulation time 177688466360 ps
CPU time 139.82 seconds
Started Aug 04 05:12:29 PM PDT 24
Finished Aug 04 05:14:49 PM PDT 24
Peak memory 199836 kb
Host smart-3b1159fa-d59a-418e-a633-941c18756dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275223038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.4275223038
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3383779724
Short name T129
Test name
Test status
Simulation time 179372150530 ps
CPU time 45.95 seconds
Started Aug 04 05:12:30 PM PDT 24
Finished Aug 04 05:13:16 PM PDT 24
Peak memory 199804 kb
Host smart-2431ce33-05b2-4fd8-b974-d483b6143ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383779724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3383779724
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2449681310
Short name T206
Test name
Test status
Simulation time 23056613412 ps
CPU time 60.34 seconds
Started Aug 04 05:12:30 PM PDT 24
Finished Aug 04 05:13:30 PM PDT 24
Peak memory 199808 kb
Host smart-65fc0395-aa71-4a26-984e-926f443a22be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449681310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2449681310
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2099025302
Short name T1131
Test name
Test status
Simulation time 20903650336 ps
CPU time 34.68 seconds
Started Aug 04 05:12:31 PM PDT 24
Finished Aug 04 05:13:06 PM PDT 24
Peak memory 199852 kb
Host smart-851c9e4c-66f1-49f5-a3c2-7ab7fd043b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099025302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2099025302
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2303573318
Short name T515
Test name
Test status
Simulation time 36839706789 ps
CPU time 34.02 seconds
Started Aug 04 05:12:29 PM PDT 24
Finished Aug 04 05:13:04 PM PDT 24
Peak memory 199848 kb
Host smart-907db82f-2908-4d2f-91bc-be79cffeec4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303573318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2303573318
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3602414719
Short name T171
Test name
Test status
Simulation time 108994208898 ps
CPU time 68.44 seconds
Started Aug 04 05:12:29 PM PDT 24
Finished Aug 04 05:13:37 PM PDT 24
Peak memory 199808 kb
Host smart-6ad74727-96aa-4dfe-b41f-9e7e43255528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602414719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3602414719
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.452912579
Short name T738
Test name
Test status
Simulation time 118039028088 ps
CPU time 40.94 seconds
Started Aug 04 05:12:29 PM PDT 24
Finished Aug 04 05:13:10 PM PDT 24
Peak memory 199824 kb
Host smart-b6e2feeb-2f3a-431c-9cae-6027ddbced54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452912579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.452912579
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.1088288372
Short name T876
Test name
Test status
Simulation time 18307908580 ps
CPU time 13.68 seconds
Started Aug 04 05:12:29 PM PDT 24
Finished Aug 04 05:12:43 PM PDT 24
Peak memory 199828 kb
Host smart-89d5b35d-9852-48da-ae7f-64f497471fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088288372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1088288372
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3991978264
Short name T24
Test name
Test status
Simulation time 12288535 ps
CPU time 0.53 seconds
Started Aug 04 05:05:56 PM PDT 24
Finished Aug 04 05:05:56 PM PDT 24
Peak memory 195268 kb
Host smart-ca26977b-0181-4e00-a796-b66e5781915b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991978264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3991978264
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2794911764
Short name T519
Test name
Test status
Simulation time 50435048920 ps
CPU time 45.12 seconds
Started Aug 04 05:05:49 PM PDT 24
Finished Aug 04 05:06:34 PM PDT 24
Peak memory 199840 kb
Host smart-03676925-4572-4a20-95d5-7e628fbc953c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794911764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2794911764
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.806315189
Short name T280
Test name
Test status
Simulation time 38180910705 ps
CPU time 17.53 seconds
Started Aug 04 05:05:53 PM PDT 24
Finished Aug 04 05:06:10 PM PDT 24
Peak memory 199872 kb
Host smart-32b76174-a23f-48c0-922f-ba3ef6f135c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806315189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.806315189
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2591353298
Short name T859
Test name
Test status
Simulation time 28773818215 ps
CPU time 25.3 seconds
Started Aug 04 05:05:51 PM PDT 24
Finished Aug 04 05:06:16 PM PDT 24
Peak memory 199796 kb
Host smart-91924220-563d-459b-8ec5-045eb879483d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591353298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2591353298
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2001927189
Short name T487
Test name
Test status
Simulation time 351201245433 ps
CPU time 244.39 seconds
Started Aug 04 05:05:48 PM PDT 24
Finished Aug 04 05:09:53 PM PDT 24
Peak memory 199816 kb
Host smart-6f6f9dcb-5177-4407-88ec-ec2aaaab4290
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001927189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2001927189
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3297716022
Short name T393
Test name
Test status
Simulation time 116701885456 ps
CPU time 759.76 seconds
Started Aug 04 05:05:53 PM PDT 24
Finished Aug 04 05:18:33 PM PDT 24
Peak memory 199768 kb
Host smart-bcd5b8ce-b0b2-41d1-8a78-d07b98bfcb87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3297716022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3297716022
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2870883367
Short name T469
Test name
Test status
Simulation time 7098996598 ps
CPU time 5.18 seconds
Started Aug 04 05:05:54 PM PDT 24
Finished Aug 04 05:05:59 PM PDT 24
Peak memory 199468 kb
Host smart-609ef1a1-d084-485f-b036-f5b572c5919a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870883367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2870883367
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3595255702
Short name T1124
Test name
Test status
Simulation time 62555772429 ps
CPU time 92.38 seconds
Started Aug 04 05:05:51 PM PDT 24
Finished Aug 04 05:07:24 PM PDT 24
Peak memory 198960 kb
Host smart-b893726a-6b23-477b-a402-0c1dcdceb4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595255702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3595255702
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1152247026
Short name T327
Test name
Test status
Simulation time 6775944255 ps
CPU time 152.43 seconds
Started Aug 04 05:05:56 PM PDT 24
Finished Aug 04 05:08:28 PM PDT 24
Peak memory 199832 kb
Host smart-acfaf7f7-0a14-4bd7-be6e-38a9f10c1fd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1152247026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1152247026
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2041548065
Short name T543
Test name
Test status
Simulation time 4549108948 ps
CPU time 10.17 seconds
Started Aug 04 05:05:50 PM PDT 24
Finished Aug 04 05:06:00 PM PDT 24
Peak memory 197624 kb
Host smart-9a3e5313-6483-4484-b719-0e2a454c8797
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2041548065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2041548065
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3377707814
Short name T682
Test name
Test status
Simulation time 34631376424 ps
CPU time 31.78 seconds
Started Aug 04 05:05:53 PM PDT 24
Finished Aug 04 05:06:25 PM PDT 24
Peak memory 199840 kb
Host smart-c01cafab-4f6e-4b8d-843b-708ca24bd17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377707814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3377707814
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.4128556086
Short name T614
Test name
Test status
Simulation time 3470643261 ps
CPU time 1.15 seconds
Started Aug 04 05:05:49 PM PDT 24
Finished Aug 04 05:05:50 PM PDT 24
Peak memory 196172 kb
Host smart-247244c1-35af-4c1f-8987-1f677eb71fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128556086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.4128556086
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.30215131
Short name T27
Test name
Test status
Simulation time 200043523 ps
CPU time 0.85 seconds
Started Aug 04 05:05:54 PM PDT 24
Finished Aug 04 05:05:55 PM PDT 24
Peak memory 218148 kb
Host smart-678b2b62-af71-4521-81af-a6bf095b3693
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30215131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.30215131
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3282558317
Short name T882
Test name
Test status
Simulation time 6011580181 ps
CPU time 9.06 seconds
Started Aug 04 05:05:46 PM PDT 24
Finished Aug 04 05:05:55 PM PDT 24
Peak memory 199612 kb
Host smart-3cfff802-369d-4c93-a90e-52f4b337b428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282558317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3282558317
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2162631629
Short name T1134
Test name
Test status
Simulation time 38678267970 ps
CPU time 127.94 seconds
Started Aug 04 05:05:53 PM PDT 24
Finished Aug 04 05:08:01 PM PDT 24
Peak memory 199924 kb
Host smart-a736f55b-5a9e-4939-88e3-0d592e127141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162631629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2162631629
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.772454580
Short name T17
Test name
Test status
Simulation time 67201720474 ps
CPU time 441.76 seconds
Started Aug 04 05:05:54 PM PDT 24
Finished Aug 04 05:13:16 PM PDT 24
Peak memory 216152 kb
Host smart-45175257-4f2a-4354-b28c-79ab2c1b9408
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772454580 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.772454580
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.188846348
Short name T1115
Test name
Test status
Simulation time 1337570697 ps
CPU time 5.06 seconds
Started Aug 04 05:05:53 PM PDT 24
Finished Aug 04 05:05:58 PM PDT 24
Peak memory 199624 kb
Host smart-abbbc5f0-547e-42f1-bd7c-d0b0ed7c75e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188846348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.188846348
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.279573124
Short name T1052
Test name
Test status
Simulation time 66902523741 ps
CPU time 203.12 seconds
Started Aug 04 05:05:51 PM PDT 24
Finished Aug 04 05:09:14 PM PDT 24
Peak memory 199816 kb
Host smart-7ac6e045-23f1-45c3-a3ba-12ffeabe2105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279573124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.279573124
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3142691994
Short name T985
Test name
Test status
Simulation time 11154703 ps
CPU time 0.56 seconds
Started Aug 04 05:08:52 PM PDT 24
Finished Aug 04 05:08:52 PM PDT 24
Peak memory 195260 kb
Host smart-9c55e288-f470-4ad0-821b-d14d214f0247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142691994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3142691994
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1029006756
Short name T618
Test name
Test status
Simulation time 28019915093 ps
CPU time 17.49 seconds
Started Aug 04 05:08:48 PM PDT 24
Finished Aug 04 05:09:06 PM PDT 24
Peak memory 199852 kb
Host smart-02d3361d-19ba-4f9b-8f33-0b4939008fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029006756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1029006756
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.749374684
Short name T320
Test name
Test status
Simulation time 107260272090 ps
CPU time 172.97 seconds
Started Aug 04 05:08:48 PM PDT 24
Finished Aug 04 05:11:41 PM PDT 24
Peak memory 199836 kb
Host smart-185e81cc-45cb-4ad7-88c7-97fe5bd88e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749374684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.749374684
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3350176590
Short name T497
Test name
Test status
Simulation time 9216044250 ps
CPU time 15.94 seconds
Started Aug 04 05:08:47 PM PDT 24
Finished Aug 04 05:09:03 PM PDT 24
Peak memory 199796 kb
Host smart-c38faa1b-b569-49cf-8e74-e5564f3d72f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350176590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3350176590
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3203040383
Short name T582
Test name
Test status
Simulation time 287345163963 ps
CPU time 110.9 seconds
Started Aug 04 05:08:47 PM PDT 24
Finished Aug 04 05:10:38 PM PDT 24
Peak memory 199668 kb
Host smart-6fe696ca-5c9c-4b57-8bc5-b442b8f22445
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203040383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3203040383
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2850615152
Short name T990
Test name
Test status
Simulation time 112115131195 ps
CPU time 847.63 seconds
Started Aug 04 05:08:51 PM PDT 24
Finished Aug 04 05:22:59 PM PDT 24
Peak memory 199776 kb
Host smart-19d9817d-429c-4fe6-bc96-a46ba95ceb63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2850615152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2850615152
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3250999394
Short name T389
Test name
Test status
Simulation time 3151445039 ps
CPU time 6.61 seconds
Started Aug 04 05:08:50 PM PDT 24
Finished Aug 04 05:08:57 PM PDT 24
Peak memory 198964 kb
Host smart-1c9aee6e-c063-46d3-998a-82139805efa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250999394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3250999394
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.903831398
Short name T44
Test name
Test status
Simulation time 341335132101 ps
CPU time 62.16 seconds
Started Aug 04 05:08:51 PM PDT 24
Finished Aug 04 05:09:53 PM PDT 24
Peak memory 198424 kb
Host smart-6d119b4f-75e4-4cfd-af72-e326902c1035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903831398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.903831398
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2065260036
Short name T818
Test name
Test status
Simulation time 2238988295 ps
CPU time 34.26 seconds
Started Aug 04 05:08:53 PM PDT 24
Finished Aug 04 05:09:27 PM PDT 24
Peak memory 199772 kb
Host smart-e95f2995-583a-4273-b87e-595bb98d79c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2065260036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2065260036
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1841965394
Short name T792
Test name
Test status
Simulation time 6437684633 ps
CPU time 52.77 seconds
Started Aug 04 05:08:48 PM PDT 24
Finished Aug 04 05:09:40 PM PDT 24
Peak memory 198552 kb
Host smart-499ef04d-e1f8-4e1b-8afb-037df4b6c02c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1841965394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1841965394
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3806202649
Short name T14
Test name
Test status
Simulation time 7135622113 ps
CPU time 13.13 seconds
Started Aug 04 05:08:48 PM PDT 24
Finished Aug 04 05:09:01 PM PDT 24
Peak memory 199808 kb
Host smart-1ec6430f-c631-4882-8583-56f8b8e80673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806202649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3806202649
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2074342475
Short name T858
Test name
Test status
Simulation time 3829594413 ps
CPU time 1.75 seconds
Started Aug 04 05:08:48 PM PDT 24
Finished Aug 04 05:08:50 PM PDT 24
Peak memory 196020 kb
Host smart-9de96bcc-0517-474c-a0ba-512bf17eda50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074342475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2074342475
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.683930101
Short name T715
Test name
Test status
Simulation time 464161672 ps
CPU time 1.39 seconds
Started Aug 04 05:08:51 PM PDT 24
Finished Aug 04 05:08:53 PM PDT 24
Peak memory 199336 kb
Host smart-702a7cc1-b382-4381-9334-a1a3ce046180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683930101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.683930101
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.681193043
Short name T607
Test name
Test status
Simulation time 285280714927 ps
CPU time 733.47 seconds
Started Aug 04 05:08:52 PM PDT 24
Finished Aug 04 05:21:05 PM PDT 24
Peak memory 199832 kb
Host smart-d611ef29-917f-4a7a-a533-c728e380f16f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681193043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.681193043
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.2579476646
Short name T751
Test name
Test status
Simulation time 67098773048 ps
CPU time 465.41 seconds
Started Aug 04 05:08:51 PM PDT 24
Finished Aug 04 05:16:37 PM PDT 24
Peak memory 225408 kb
Host smart-3f295e65-ac1c-428f-8d8b-901c9d983926
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579476646 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.2579476646
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2580148313
Short name T1156
Test name
Test status
Simulation time 6802510032 ps
CPU time 24.8 seconds
Started Aug 04 05:08:51 PM PDT 24
Finished Aug 04 05:09:16 PM PDT 24
Peak memory 199820 kb
Host smart-27e0bbdf-4de1-4fb9-ab98-6dd8a0e4a7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580148313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2580148313
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.4084138849
Short name T503
Test name
Test status
Simulation time 97724708311 ps
CPU time 81.9 seconds
Started Aug 04 05:08:48 PM PDT 24
Finished Aug 04 05:10:10 PM PDT 24
Peak memory 199884 kb
Host smart-1415f138-1e1f-47c4-9fa7-25874c8b0834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084138849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.4084138849
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3690457150
Short name T716
Test name
Test status
Simulation time 15134518 ps
CPU time 0.57 seconds
Started Aug 04 05:08:55 PM PDT 24
Finished Aug 04 05:08:56 PM PDT 24
Peak memory 195296 kb
Host smart-d149c6da-24cc-448a-ae36-6e4b03ac5edc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690457150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3690457150
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1564772643
Short name T692
Test name
Test status
Simulation time 141556559061 ps
CPU time 253.04 seconds
Started Aug 04 05:08:51 PM PDT 24
Finished Aug 04 05:13:04 PM PDT 24
Peak memory 199896 kb
Host smart-54b24ea2-4ccf-476b-a105-787ea9ac5347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564772643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1564772643
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1961634522
Short name T626
Test name
Test status
Simulation time 53361581282 ps
CPU time 81.33 seconds
Started Aug 04 05:08:53 PM PDT 24
Finished Aug 04 05:10:15 PM PDT 24
Peak memory 199812 kb
Host smart-3fe47e5f-eda5-463c-81ba-91e3d5412b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961634522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1961634522
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2090434271
Short name T819
Test name
Test status
Simulation time 18409491740 ps
CPU time 19.85 seconds
Started Aug 04 05:08:54 PM PDT 24
Finished Aug 04 05:09:14 PM PDT 24
Peak memory 199800 kb
Host smart-b28c93d7-aca7-470a-a88a-d4b14b5148ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090434271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2090434271
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2242852815
Short name T670
Test name
Test status
Simulation time 298490975403 ps
CPU time 492.99 seconds
Started Aug 04 05:08:56 PM PDT 24
Finished Aug 04 05:17:09 PM PDT 24
Peak memory 199868 kb
Host smart-53b42f90-6a00-4cd9-b732-69b89c697f0d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242852815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2242852815
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2465200881
Short name T376
Test name
Test status
Simulation time 61905069189 ps
CPU time 526.52 seconds
Started Aug 04 05:08:57 PM PDT 24
Finished Aug 04 05:17:44 PM PDT 24
Peak memory 199872 kb
Host smart-e1c35a94-5d2d-4771-ab6a-046f68ea307d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2465200881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2465200881
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2261448926
Short name T691
Test name
Test status
Simulation time 9135714362 ps
CPU time 10.54 seconds
Started Aug 04 05:08:56 PM PDT 24
Finished Aug 04 05:09:06 PM PDT 24
Peak memory 199860 kb
Host smart-7b19d236-775a-4fca-b5a7-644bfa4eedc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261448926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2261448926
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.2937636852
Short name T676
Test name
Test status
Simulation time 145692144278 ps
CPU time 45.03 seconds
Started Aug 04 05:08:56 PM PDT 24
Finished Aug 04 05:09:41 PM PDT 24
Peak memory 208232 kb
Host smart-70b39d24-ad3c-4af0-b196-0cd4dd1e8531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937636852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2937636852
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1292587125
Short name T286
Test name
Test status
Simulation time 12629040639 ps
CPU time 441.31 seconds
Started Aug 04 05:08:56 PM PDT 24
Finished Aug 04 05:16:17 PM PDT 24
Peak memory 199860 kb
Host smart-888d487f-041f-4551-87ba-efa0c2f48873
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1292587125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1292587125
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2937022818
Short name T742
Test name
Test status
Simulation time 4651487049 ps
CPU time 11.16 seconds
Started Aug 04 05:08:55 PM PDT 24
Finished Aug 04 05:09:06 PM PDT 24
Peak memory 197864 kb
Host smart-bcf4d368-b0ae-4088-a291-3334824147d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2937022818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2937022818
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.978942185
Short name T624
Test name
Test status
Simulation time 450579434900 ps
CPU time 41.15 seconds
Started Aug 04 05:08:55 PM PDT 24
Finished Aug 04 05:09:36 PM PDT 24
Peak memory 199820 kb
Host smart-bbf4f881-e2ec-4917-9eca-2d88c3bd70e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978942185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.978942185
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2880328770
Short name T1063
Test name
Test status
Simulation time 2812065667 ps
CPU time 1.69 seconds
Started Aug 04 05:08:55 PM PDT 24
Finished Aug 04 05:08:57 PM PDT 24
Peak memory 196384 kb
Host smart-71b9249b-0401-40d4-a560-bc53ba979eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880328770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2880328770
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.100985507
Short name T360
Test name
Test status
Simulation time 626825151 ps
CPU time 2.7 seconds
Started Aug 04 05:09:38 PM PDT 24
Finished Aug 04 05:09:41 PM PDT 24
Peak memory 199652 kb
Host smart-4f743cec-19c0-47f2-ac9e-d5b60c5f9b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100985507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.100985507
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3177519685
Short name T188
Test name
Test status
Simulation time 85111457395 ps
CPU time 243.99 seconds
Started Aug 04 05:08:57 PM PDT 24
Finished Aug 04 05:13:01 PM PDT 24
Peak memory 199796 kb
Host smart-16f0ebbc-ab83-400d-a298-f4f5cdedb27d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177519685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3177519685
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1441947782
Short name T864
Test name
Test status
Simulation time 216133083924 ps
CPU time 814.5 seconds
Started Aug 04 05:08:55 PM PDT 24
Finished Aug 04 05:22:29 PM PDT 24
Peak memory 224712 kb
Host smart-2be4b149-f9db-4397-a940-b204b13e9531
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441947782 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1441947782
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.433989618
Short name T379
Test name
Test status
Simulation time 695008056 ps
CPU time 1.45 seconds
Started Aug 04 05:08:54 PM PDT 24
Finished Aug 04 05:08:56 PM PDT 24
Peak memory 198656 kb
Host smart-443653c8-8c84-4cff-add4-b3d2cc9cb8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433989618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.433989618
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3570989460
Short name T1005
Test name
Test status
Simulation time 28636833338 ps
CPU time 25.9 seconds
Started Aug 04 05:08:52 PM PDT 24
Finished Aug 04 05:09:18 PM PDT 24
Peak memory 199812 kb
Host smart-d199bcee-559f-45e8-a620-eeacfe390072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570989460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3570989460
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2407231201
Short name T23
Test name
Test status
Simulation time 14986024 ps
CPU time 0.55 seconds
Started Aug 04 05:09:07 PM PDT 24
Finished Aug 04 05:09:08 PM PDT 24
Peak memory 195216 kb
Host smart-1cfb3283-8206-4ef9-943d-0c7b1608287b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407231201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2407231201
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.997678287
Short name T255
Test name
Test status
Simulation time 8336280603 ps
CPU time 14.48 seconds
Started Aug 04 05:08:59 PM PDT 24
Finished Aug 04 05:09:13 PM PDT 24
Peak memory 199812 kb
Host smart-8abca41d-cdf9-4676-9703-718ea9d56f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997678287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.997678287
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.856001282
Short name T267
Test name
Test status
Simulation time 121897005427 ps
CPU time 147.08 seconds
Started Aug 04 05:09:06 PM PDT 24
Finished Aug 04 05:11:34 PM PDT 24
Peak memory 199792 kb
Host smart-178b3fcc-ca1c-409f-9095-4d306e49a490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856001282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.856001282
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3249502046
Short name T6
Test name
Test status
Simulation time 42538525707 ps
CPU time 78.16 seconds
Started Aug 04 05:09:00 PM PDT 24
Finished Aug 04 05:10:18 PM PDT 24
Peak memory 199792 kb
Host smart-08187b53-6cce-4ae3-8685-8711125f6892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249502046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3249502046
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.176968231
Short name T834
Test name
Test status
Simulation time 39431427116 ps
CPU time 12.9 seconds
Started Aug 04 05:08:59 PM PDT 24
Finished Aug 04 05:09:12 PM PDT 24
Peak memory 199404 kb
Host smart-9a1903fd-3a72-434f-9ce6-f9a065ebeeb2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176968231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.176968231
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.4236528059
Short name T356
Test name
Test status
Simulation time 50649439909 ps
CPU time 311.47 seconds
Started Aug 04 05:08:59 PM PDT 24
Finished Aug 04 05:14:11 PM PDT 24
Peak memory 199868 kb
Host smart-43363e77-8375-48bd-9890-2b21d530321c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4236528059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.4236528059
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.150477695
Short name T18
Test name
Test status
Simulation time 3228219103 ps
CPU time 3.07 seconds
Started Aug 04 05:08:58 PM PDT 24
Finished Aug 04 05:09:01 PM PDT 24
Peak memory 196352 kb
Host smart-1aa708be-8af3-400b-b9a7-bf5a5d3a3379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150477695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.150477695
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3259970620
Short name T249
Test name
Test status
Simulation time 42510470258 ps
CPU time 74.28 seconds
Started Aug 04 05:08:59 PM PDT 24
Finished Aug 04 05:10:13 PM PDT 24
Peak memory 199948 kb
Host smart-6567c35f-8cae-4122-8488-487d4c5f02fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259970620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3259970620
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1535426019
Short name T431
Test name
Test status
Simulation time 21028506752 ps
CPU time 139.81 seconds
Started Aug 04 05:08:59 PM PDT 24
Finished Aug 04 05:11:19 PM PDT 24
Peak memory 199824 kb
Host smart-57bb3776-eeb3-4497-b0fa-aed719eabe29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1535426019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1535426019
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1518489719
Short name T736
Test name
Test status
Simulation time 5157761577 ps
CPU time 42.56 seconds
Started Aug 04 05:09:00 PM PDT 24
Finished Aug 04 05:09:43 PM PDT 24
Peak memory 197944 kb
Host smart-b865f9d5-a051-47fc-89fd-03500f39b841
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1518489719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1518489719
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1563736251
Short name T687
Test name
Test status
Simulation time 38308771064 ps
CPU time 63.85 seconds
Started Aug 04 05:09:07 PM PDT 24
Finished Aug 04 05:10:10 PM PDT 24
Peak memory 199792 kb
Host smart-2661e2d8-5906-4b86-bc52-91c62909f7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563736251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1563736251
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1981691826
Short name T512
Test name
Test status
Simulation time 7125436668 ps
CPU time 3.07 seconds
Started Aug 04 05:09:00 PM PDT 24
Finished Aug 04 05:09:03 PM PDT 24
Peak memory 196320 kb
Host smart-cefac1d4-da66-416d-954a-acc1308252a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981691826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1981691826
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1218099501
Short name T523
Test name
Test status
Simulation time 461084043 ps
CPU time 1.72 seconds
Started Aug 04 05:08:55 PM PDT 24
Finished Aug 04 05:08:57 PM PDT 24
Peak memory 198864 kb
Host smart-0eabb090-2082-4d3e-a4cd-1c3d7efa9d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218099501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1218099501
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.2114093268
Short name T257
Test name
Test status
Simulation time 235054082909 ps
CPU time 937.87 seconds
Started Aug 04 05:09:03 PM PDT 24
Finished Aug 04 05:24:41 PM PDT 24
Peak memory 199860 kb
Host smart-2f87558d-300c-4ff7-a36e-33c060925b74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114093268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2114093268
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3531193849
Short name T1163
Test name
Test status
Simulation time 46000515670 ps
CPU time 270.47 seconds
Started Aug 04 05:09:00 PM PDT 24
Finished Aug 04 05:13:30 PM PDT 24
Peak memory 216388 kb
Host smart-aeab2ee7-f436-40fe-ae1f-3a4da8557166
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531193849 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3531193849
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3662467378
Short name T321
Test name
Test status
Simulation time 6481249436 ps
CPU time 22.89 seconds
Started Aug 04 05:09:06 PM PDT 24
Finished Aug 04 05:09:29 PM PDT 24
Peak memory 199696 kb
Host smart-62ad57bc-12db-4bab-8428-61724a184a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662467378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3662467378
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3466883833
Short name T917
Test name
Test status
Simulation time 78570457655 ps
CPU time 8.73 seconds
Started Aug 04 05:08:56 PM PDT 24
Finished Aug 04 05:09:05 PM PDT 24
Peak memory 199844 kb
Host smart-0a2a2640-11a3-4ac7-b7fb-2d191b35711d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466883833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3466883833
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2671555999
Short name T894
Test name
Test status
Simulation time 11558837 ps
CPU time 0.52 seconds
Started Aug 04 05:09:07 PM PDT 24
Finished Aug 04 05:09:08 PM PDT 24
Peak memory 195292 kb
Host smart-6705188b-e7e1-4743-bb45-99b231da2deb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671555999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2671555999
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2425847758
Short name T448
Test name
Test status
Simulation time 108677578121 ps
CPU time 135.51 seconds
Started Aug 04 05:09:07 PM PDT 24
Finished Aug 04 05:11:23 PM PDT 24
Peak memory 199772 kb
Host smart-3508f5d9-56fc-413b-ab24-f99db96872ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425847758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2425847758
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.346890781
Short name T374
Test name
Test status
Simulation time 46372611829 ps
CPU time 66.53 seconds
Started Aug 04 05:09:05 PM PDT 24
Finished Aug 04 05:10:11 PM PDT 24
Peak memory 199876 kb
Host smart-25fd515c-3015-401d-a03b-f48b2c266e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346890781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.346890781
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_intr.4224355084
Short name T114
Test name
Test status
Simulation time 24691617086 ps
CPU time 5.16 seconds
Started Aug 04 05:09:05 PM PDT 24
Finished Aug 04 05:09:10 PM PDT 24
Peak memory 196868 kb
Host smart-d7edc6fd-8982-401b-a3c3-07a439f37d65
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224355084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.4224355084
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2425340058
Short name T386
Test name
Test status
Simulation time 82484008947 ps
CPU time 417.46 seconds
Started Aug 04 05:09:09 PM PDT 24
Finished Aug 04 05:16:07 PM PDT 24
Peak memory 199748 kb
Host smart-6c6878fa-1eea-43de-abdf-fad0f85d2a44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2425340058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2425340058
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2287359467
Short name T838
Test name
Test status
Simulation time 4821459021 ps
CPU time 9.71 seconds
Started Aug 04 05:09:08 PM PDT 24
Finished Aug 04 05:09:18 PM PDT 24
Peak memory 198548 kb
Host smart-3ac398b1-5908-44a1-ac92-12d0de33a879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287359467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2287359467
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2762657199
Short name T1032
Test name
Test status
Simulation time 78403367507 ps
CPU time 236.01 seconds
Started Aug 04 05:09:04 PM PDT 24
Finished Aug 04 05:13:00 PM PDT 24
Peak memory 208280 kb
Host smart-eb525b9d-3c00-474c-9fec-03819edcac8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762657199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2762657199
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.4215846139
Short name T802
Test name
Test status
Simulation time 13668522082 ps
CPU time 189.87 seconds
Started Aug 04 05:09:08 PM PDT 24
Finished Aug 04 05:12:18 PM PDT 24
Peak memory 199856 kb
Host smart-b5a64677-e7b2-4c94-a324-11dd3d63c74b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4215846139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.4215846139
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1487012004
Short name T855
Test name
Test status
Simulation time 2123079882 ps
CPU time 8.64 seconds
Started Aug 04 05:09:05 PM PDT 24
Finished Aug 04 05:09:14 PM PDT 24
Peak memory 198080 kb
Host smart-b6511e09-311c-4416-b8b0-9ff742b54805
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1487012004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1487012004
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3585692686
Short name T1154
Test name
Test status
Simulation time 82018844378 ps
CPU time 35.38 seconds
Started Aug 04 05:09:04 PM PDT 24
Finished Aug 04 05:09:39 PM PDT 24
Peak memory 199840 kb
Host smart-469743c3-23d1-462b-bb91-bd2cd67729b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585692686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3585692686
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.222590256
Short name T576
Test name
Test status
Simulation time 3677593186 ps
CPU time 6.5 seconds
Started Aug 04 05:09:07 PM PDT 24
Finished Aug 04 05:09:13 PM PDT 24
Peak memory 196172 kb
Host smart-d357aeb0-fb7e-467e-b9b1-4664334617e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222590256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.222590256
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2729769264
Short name T427
Test name
Test status
Simulation time 307765152 ps
CPU time 1.53 seconds
Started Aug 04 05:09:04 PM PDT 24
Finished Aug 04 05:09:06 PM PDT 24
Peak memory 198932 kb
Host smart-c9c98ce5-a115-4305-9ffb-31b5cc73d44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729769264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2729769264
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.1565726167
Short name T681
Test name
Test status
Simulation time 147243113486 ps
CPU time 532.2 seconds
Started Aug 04 05:09:10 PM PDT 24
Finished Aug 04 05:18:02 PM PDT 24
Peak memory 199860 kb
Host smart-4c7f7e83-6ef7-494f-8558-114a5f9aa05d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565726167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1565726167
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.827903302
Short name T1178
Test name
Test status
Simulation time 1699028789 ps
CPU time 1.93 seconds
Started Aug 04 05:09:04 PM PDT 24
Finished Aug 04 05:09:06 PM PDT 24
Peak memory 198044 kb
Host smart-4006c50d-069f-460e-8cfb-a5c453e91c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827903302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.827903302
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1310825380
Short name T419
Test name
Test status
Simulation time 79707319464 ps
CPU time 34.4 seconds
Started Aug 04 05:09:05 PM PDT 24
Finished Aug 04 05:09:40 PM PDT 24
Peak memory 199304 kb
Host smart-18f791a1-4932-46b9-ad41-1bc35f582063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310825380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1310825380
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.4070484207
Short name T929
Test name
Test status
Simulation time 14565956 ps
CPU time 0.61 seconds
Started Aug 04 05:09:11 PM PDT 24
Finished Aug 04 05:09:12 PM PDT 24
Peak memory 195212 kb
Host smart-08c4049f-0ba8-4fcb-8bba-f608b6cf4663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070484207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.4070484207
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1839185403
Short name T749
Test name
Test status
Simulation time 78571430453 ps
CPU time 145.03 seconds
Started Aug 04 05:09:09 PM PDT 24
Finished Aug 04 05:11:35 PM PDT 24
Peak memory 199852 kb
Host smart-dbbf8a46-e58b-4e0b-9ecd-bc15c0e2b06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839185403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1839185403
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3787817147
Short name T865
Test name
Test status
Simulation time 108245429245 ps
CPU time 19.09 seconds
Started Aug 04 05:09:11 PM PDT 24
Finished Aug 04 05:09:30 PM PDT 24
Peak memory 199848 kb
Host smart-c14622b7-ee40-4ebe-aa3e-9af90d0a7761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787817147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3787817147
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2030640382
Short name T268
Test name
Test status
Simulation time 18210094691 ps
CPU time 13.31 seconds
Started Aug 04 05:09:08 PM PDT 24
Finished Aug 04 05:09:21 PM PDT 24
Peak memory 199908 kb
Host smart-5e4244b8-aec2-4e88-8c5f-654b687ac3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030640382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2030640382
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1550439134
Short name T958
Test name
Test status
Simulation time 363846790957 ps
CPU time 149.14 seconds
Started Aug 04 05:09:13 PM PDT 24
Finished Aug 04 05:11:42 PM PDT 24
Peak memory 198832 kb
Host smart-2c992e72-a78e-4ed1-928a-e756112cf1c0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550439134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1550439134
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3413351268
Short name T565
Test name
Test status
Simulation time 174931719662 ps
CPU time 438.42 seconds
Started Aug 04 05:09:12 PM PDT 24
Finished Aug 04 05:16:30 PM PDT 24
Peak memory 199856 kb
Host smart-e4e40f0f-f479-41d3-93c3-17bb8856669e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3413351268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3413351268
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1809354406
Short name T1165
Test name
Test status
Simulation time 8217699247 ps
CPU time 5.64 seconds
Started Aug 04 05:09:12 PM PDT 24
Finished Aug 04 05:09:18 PM PDT 24
Peak memory 199916 kb
Host smart-28ca5439-4d6a-4d49-8441-87854072fa1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809354406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1809354406
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.918538038
Short name T592
Test name
Test status
Simulation time 317461891737 ps
CPU time 47.59 seconds
Started Aug 04 05:09:11 PM PDT 24
Finished Aug 04 05:09:59 PM PDT 24
Peak memory 208196 kb
Host smart-7172b29c-c572-47e7-a011-bcf326ec50fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918538038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.918538038
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.196591422
Short name T943
Test name
Test status
Simulation time 12842240168 ps
CPU time 617.21 seconds
Started Aug 04 05:09:12 PM PDT 24
Finished Aug 04 05:19:30 PM PDT 24
Peak memory 199856 kb
Host smart-269f358b-72fa-4ae3-b638-41c26d2e1afa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=196591422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.196591422
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.943565622
Short name T482
Test name
Test status
Simulation time 4062432826 ps
CPU time 9.67 seconds
Started Aug 04 05:09:08 PM PDT 24
Finished Aug 04 05:09:18 PM PDT 24
Peak memory 198256 kb
Host smart-ae447212-aae8-4d65-84b7-88fe09d81f47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943565622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.943565622
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1019660295
Short name T253
Test name
Test status
Simulation time 71437932691 ps
CPU time 58.88 seconds
Started Aug 04 05:09:13 PM PDT 24
Finished Aug 04 05:10:12 PM PDT 24
Peak memory 199928 kb
Host smart-eff0cbd5-d9bd-4bd4-ac16-a07643d57f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019660295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1019660295
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3201925275
Short name T425
Test name
Test status
Simulation time 580868170 ps
CPU time 1.53 seconds
Started Aug 04 05:09:12 PM PDT 24
Finished Aug 04 05:09:14 PM PDT 24
Peak memory 195504 kb
Host smart-b550516f-66d6-49cf-9543-3c7b1ff5862a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201925275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3201925275
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.4079922281
Short name T693
Test name
Test status
Simulation time 6059353902 ps
CPU time 12.52 seconds
Started Aug 04 05:09:09 PM PDT 24
Finished Aug 04 05:09:22 PM PDT 24
Peak memory 199752 kb
Host smart-2bd044e7-770e-4d5b-9fc5-8622d611a332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079922281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.4079922281
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2991070662
Short name T979
Test name
Test status
Simulation time 111455777675 ps
CPU time 110.92 seconds
Started Aug 04 05:09:10 PM PDT 24
Finished Aug 04 05:11:01 PM PDT 24
Peak memory 199864 kb
Host smart-3906e919-768b-44e0-ad33-71a9fa4a6f8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991070662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2991070662
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.70171608
Short name T16
Test name
Test status
Simulation time 1053477362 ps
CPU time 1.96 seconds
Started Aug 04 05:09:11 PM PDT 24
Finished Aug 04 05:09:13 PM PDT 24
Peak memory 198676 kb
Host smart-a4d22156-d990-4638-be56-6a4e8b07acfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70171608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.70171608
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1031526970
Short name T719
Test name
Test status
Simulation time 120658039818 ps
CPU time 98.57 seconds
Started Aug 04 05:09:09 PM PDT 24
Finished Aug 04 05:10:48 PM PDT 24
Peak memory 199820 kb
Host smart-b9c03490-b645-43e1-a6dd-e512f40ff660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031526970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1031526970
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1173522385
Short name T1145
Test name
Test status
Simulation time 20694266 ps
CPU time 0.53 seconds
Started Aug 04 05:09:16 PM PDT 24
Finished Aug 04 05:09:17 PM PDT 24
Peak memory 194676 kb
Host smart-9a8406f5-7760-4656-bbb3-86fd7e14a535
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173522385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1173522385
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.829200010
Short name T269
Test name
Test status
Simulation time 97415048915 ps
CPU time 206.1 seconds
Started Aug 04 05:09:13 PM PDT 24
Finished Aug 04 05:12:40 PM PDT 24
Peak memory 199888 kb
Host smart-09c63431-065b-4a59-9d89-b11389f70e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829200010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.829200010
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1659335304
Short name T151
Test name
Test status
Simulation time 181942821993 ps
CPU time 188.55 seconds
Started Aug 04 05:09:11 PM PDT 24
Finished Aug 04 05:12:20 PM PDT 24
Peak memory 199944 kb
Host smart-f7d3c4ea-2b68-4a70-af30-e39d5cc50913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659335304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1659335304
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.4208977820
Short name T1048
Test name
Test status
Simulation time 64199699861 ps
CPU time 64.09 seconds
Started Aug 04 05:09:18 PM PDT 24
Finished Aug 04 05:10:22 PM PDT 24
Peak memory 199828 kb
Host smart-a0aaf039-b6ff-4aad-8378-d5edd314a26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208977820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.4208977820
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2097631952
Short name T641
Test name
Test status
Simulation time 44640436021 ps
CPU time 66.36 seconds
Started Aug 04 05:09:17 PM PDT 24
Finished Aug 04 05:10:23 PM PDT 24
Peak memory 199864 kb
Host smart-54f9bffd-c836-40b0-9bbb-b4e3daa88710
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097631952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2097631952
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2411878680
Short name T36
Test name
Test status
Simulation time 76376300083 ps
CPU time 311.23 seconds
Started Aug 04 05:09:16 PM PDT 24
Finished Aug 04 05:14:28 PM PDT 24
Peak memory 199916 kb
Host smart-01646f91-1617-46f9-a155-54d5cebc6f61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2411878680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2411878680
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3152914544
Short name T345
Test name
Test status
Simulation time 1310824184 ps
CPU time 2.62 seconds
Started Aug 04 05:09:16 PM PDT 24
Finished Aug 04 05:09:19 PM PDT 24
Peak memory 196056 kb
Host smart-cde922b9-8fa5-490a-ba9c-3bb1965eebc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152914544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3152914544
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.3900389753
Short name T287
Test name
Test status
Simulation time 154574477371 ps
CPU time 136.3 seconds
Started Aug 04 05:09:18 PM PDT 24
Finished Aug 04 05:11:34 PM PDT 24
Peak memory 200164 kb
Host smart-5ab5394b-4771-45d5-a210-80658d2eefcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900389753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3900389753
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2582874436
Short name T509
Test name
Test status
Simulation time 5367849894 ps
CPU time 317.93 seconds
Started Aug 04 05:09:16 PM PDT 24
Finished Aug 04 05:14:34 PM PDT 24
Peak memory 199784 kb
Host smart-4b8fa494-04ee-49d3-b95e-96f9f19fd8c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2582874436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2582874436
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2567542908
Short name T441
Test name
Test status
Simulation time 6139806954 ps
CPU time 57.63 seconds
Started Aug 04 05:09:18 PM PDT 24
Finished Aug 04 05:10:15 PM PDT 24
Peak memory 197928 kb
Host smart-a7264529-7356-4a58-a80b-326aebc47892
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2567542908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2567542908
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.878540169
Short name T85
Test name
Test status
Simulation time 73649604620 ps
CPU time 30.18 seconds
Started Aug 04 05:09:17 PM PDT 24
Finished Aug 04 05:09:47 PM PDT 24
Peak memory 199904 kb
Host smart-b5d63b23-7974-4678-8c66-d1cb5f37f7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878540169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.878540169
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.520178471
Short name T399
Test name
Test status
Simulation time 33852394672 ps
CPU time 11.95 seconds
Started Aug 04 05:09:17 PM PDT 24
Finished Aug 04 05:09:29 PM PDT 24
Peak memory 196732 kb
Host smart-5cf1d3a5-13ab-4f90-a535-63d2ff6b49f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520178471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.520178471
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.4172714173
Short name T637
Test name
Test status
Simulation time 670650864 ps
CPU time 2.93 seconds
Started Aug 04 05:09:13 PM PDT 24
Finished Aug 04 05:09:16 PM PDT 24
Peak memory 199632 kb
Host smart-99236200-e9ab-461c-9913-1533f02c4547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172714173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.4172714173
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.1660827425
Short name T546
Test name
Test status
Simulation time 489636850611 ps
CPU time 78.88 seconds
Started Aug 04 05:09:19 PM PDT 24
Finished Aug 04 05:10:38 PM PDT 24
Peak memory 199728 kb
Host smart-d21b9c3f-7d1b-45b6-8a79-6b17082a602e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660827425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1660827425
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3057297717
Short name T539
Test name
Test status
Simulation time 58460084058 ps
CPU time 820.62 seconds
Started Aug 04 05:09:18 PM PDT 24
Finished Aug 04 05:22:59 PM PDT 24
Peak memory 216432 kb
Host smart-f46968ea-cb44-49bd-813a-b5e8b0022fc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057297717 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3057297717
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3497659633
Short name T924
Test name
Test status
Simulation time 7375752050 ps
CPU time 13.76 seconds
Started Aug 04 05:09:17 PM PDT 24
Finished Aug 04 05:09:31 PM PDT 24
Peak memory 199832 kb
Host smart-03b44659-acbc-4b85-bcb8-da567161708f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497659633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3497659633
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3915036521
Short name T488
Test name
Test status
Simulation time 32827968554 ps
CPU time 11.77 seconds
Started Aug 04 05:09:11 PM PDT 24
Finished Aug 04 05:09:23 PM PDT 24
Peak memory 197640 kb
Host smart-c8eb9266-7183-42b2-adc8-66531b7d0bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915036521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3915036521
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3133160773
Short name T416
Test name
Test status
Simulation time 48309345 ps
CPU time 0.56 seconds
Started Aug 04 05:09:25 PM PDT 24
Finished Aug 04 05:09:25 PM PDT 24
Peak memory 195196 kb
Host smart-69378c09-574e-4215-b89d-e1a457bcd2d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133160773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3133160773
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1922612485
Short name T535
Test name
Test status
Simulation time 42085811253 ps
CPU time 39.69 seconds
Started Aug 04 05:09:21 PM PDT 24
Finished Aug 04 05:10:00 PM PDT 24
Peak memory 199884 kb
Host smart-d4f123eb-20dd-4cf7-8eff-276f698d7fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922612485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1922612485
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.841169676
Short name T322
Test name
Test status
Simulation time 74330316291 ps
CPU time 110.29 seconds
Started Aug 04 05:09:20 PM PDT 24
Finished Aug 04 05:11:11 PM PDT 24
Peak memory 199856 kb
Host smart-62ca8bf9-849d-4ea9-810e-d21df975ad8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841169676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.841169676
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.644861228
Short name T1143
Test name
Test status
Simulation time 124261356313 ps
CPU time 50.12 seconds
Started Aug 04 05:09:20 PM PDT 24
Finished Aug 04 05:10:11 PM PDT 24
Peak memory 199828 kb
Host smart-dc28240c-f5f6-4689-b63b-0afa8500d7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644861228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.644861228
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.4211278582
Short name T907
Test name
Test status
Simulation time 32999606567 ps
CPU time 41.71 seconds
Started Aug 04 05:09:21 PM PDT 24
Finished Aug 04 05:10:03 PM PDT 24
Peak memory 198152 kb
Host smart-95b7a22d-3de2-4668-b2fa-a7ebd1c88042
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211278582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.4211278582
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1562224147
Short name T597
Test name
Test status
Simulation time 194477791639 ps
CPU time 332.52 seconds
Started Aug 04 05:09:24 PM PDT 24
Finished Aug 04 05:14:57 PM PDT 24
Peak memory 199748 kb
Host smart-68beb9f0-db0a-41d9-acc3-2919a7300601
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1562224147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1562224147
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3646784373
Short name T406
Test name
Test status
Simulation time 9247180017 ps
CPU time 10.25 seconds
Started Aug 04 05:09:20 PM PDT 24
Finished Aug 04 05:09:30 PM PDT 24
Peak memory 198008 kb
Host smart-24324df5-5565-46ea-99b2-1745acd2be0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646784373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3646784373
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.805114345
Short name T333
Test name
Test status
Simulation time 83149672644 ps
CPU time 148.04 seconds
Started Aug 04 05:09:20 PM PDT 24
Finished Aug 04 05:11:49 PM PDT 24
Peak memory 199328 kb
Host smart-4dc163c8-f316-454b-8a5d-a00546988d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805114345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.805114345
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.616262792
Short name T516
Test name
Test status
Simulation time 13999124712 ps
CPU time 113.75 seconds
Started Aug 04 05:09:25 PM PDT 24
Finished Aug 04 05:11:19 PM PDT 24
Peak memory 199820 kb
Host smart-5a9a72bb-e4c2-4603-83c2-499e76bb8768
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616262792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.616262792
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.4028079895
Short name T848
Test name
Test status
Simulation time 5616228515 ps
CPU time 11.47 seconds
Started Aug 04 05:09:20 PM PDT 24
Finished Aug 04 05:09:32 PM PDT 24
Peak memory 198928 kb
Host smart-287be580-92f8-426f-b808-355629b46adc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4028079895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.4028079895
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.4014456259
Short name T821
Test name
Test status
Simulation time 25409452030 ps
CPU time 12.01 seconds
Started Aug 04 05:09:20 PM PDT 24
Finished Aug 04 05:09:32 PM PDT 24
Peak memory 199152 kb
Host smart-0b7b6795-1dd0-4ff5-8ab5-0cf8bc627b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014456259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.4014456259
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1792656478
Short name T639
Test name
Test status
Simulation time 25366127476 ps
CPU time 30.76 seconds
Started Aug 04 05:09:18 PM PDT 24
Finished Aug 04 05:09:49 PM PDT 24
Peak memory 196132 kb
Host smart-e4c6295d-0ff7-41c1-a6bb-216152fcfb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792656478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1792656478
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1052098887
Short name T498
Test name
Test status
Simulation time 505520532 ps
CPU time 2.79 seconds
Started Aug 04 05:09:16 PM PDT 24
Finished Aug 04 05:09:19 PM PDT 24
Peak memory 199548 kb
Host smart-eafad265-2f64-4a2f-98ed-b299d4494aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052098887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1052098887
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.3114810095
Short name T402
Test name
Test status
Simulation time 46406687146 ps
CPU time 73.64 seconds
Started Aug 04 05:09:24 PM PDT 24
Finished Aug 04 05:10:38 PM PDT 24
Peak memory 200188 kb
Host smart-4272c74d-b038-4acd-afe4-f8186815c2c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114810095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3114810095
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3542807055
Short name T589
Test name
Test status
Simulation time 35826998441 ps
CPU time 389.14 seconds
Started Aug 04 05:09:23 PM PDT 24
Finished Aug 04 05:15:53 PM PDT 24
Peak memory 216464 kb
Host smart-99042b5a-0887-4697-9508-5e2429b8bc67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542807055 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3542807055
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2716189494
Short name T1061
Test name
Test status
Simulation time 2665457771 ps
CPU time 1.79 seconds
Started Aug 04 05:09:19 PM PDT 24
Finished Aug 04 05:09:21 PM PDT 24
Peak memory 199436 kb
Host smart-9979c718-4fd6-4b31-8570-ca3a302531d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716189494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2716189494
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.4086859361
Short name T843
Test name
Test status
Simulation time 24872204342 ps
CPU time 20.8 seconds
Started Aug 04 05:09:16 PM PDT 24
Finished Aug 04 05:09:37 PM PDT 24
Peak memory 199696 kb
Host smart-eea034ca-61f7-4fac-9148-29e7c43f4992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086859361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.4086859361
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1548581311
Short name T1029
Test name
Test status
Simulation time 21299899 ps
CPU time 0.54 seconds
Started Aug 04 05:09:31 PM PDT 24
Finished Aug 04 05:09:32 PM PDT 24
Peak memory 195296 kb
Host smart-38abf9cb-1247-4729-8e5a-32d04127c82a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548581311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1548581311
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.803055704
Short name T1091
Test name
Test status
Simulation time 254635194510 ps
CPU time 27.06 seconds
Started Aug 04 05:09:29 PM PDT 24
Finished Aug 04 05:09:56 PM PDT 24
Peak memory 199836 kb
Host smart-9009d203-5e2a-4fec-a78b-a3ff1ca9f396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803055704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.803055704
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.4124184102
Short name T1146
Test name
Test status
Simulation time 174683634210 ps
CPU time 150.07 seconds
Started Aug 04 05:09:29 PM PDT 24
Finished Aug 04 05:12:00 PM PDT 24
Peak memory 199888 kb
Host smart-6cb5fae5-0209-4b30-abe9-8a72b17d32cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124184102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.4124184102
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2848291472
Short name T420
Test name
Test status
Simulation time 53661504943 ps
CPU time 75.97 seconds
Started Aug 04 05:09:30 PM PDT 24
Finished Aug 04 05:10:46 PM PDT 24
Peak memory 199792 kb
Host smart-ef946092-072b-4583-9492-b4963b4a1ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848291472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2848291472
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.873603478
Short name T1044
Test name
Test status
Simulation time 288613746410 ps
CPU time 176.03 seconds
Started Aug 04 05:09:28 PM PDT 24
Finished Aug 04 05:12:24 PM PDT 24
Peak memory 199844 kb
Host smart-53aed61c-d733-440a-923a-b3e32b5925aa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873603478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.873603478
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3704009686
Short name T638
Test name
Test status
Simulation time 42486099384 ps
CPU time 70.12 seconds
Started Aug 04 05:09:34 PM PDT 24
Finished Aug 04 05:10:44 PM PDT 24
Peak memory 199840 kb
Host smart-da4a3502-3960-454d-8635-7f4dff750e21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3704009686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3704009686
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2067856172
Short name T499
Test name
Test status
Simulation time 268857517 ps
CPU time 0.79 seconds
Started Aug 04 05:09:32 PM PDT 24
Finished Aug 04 05:09:33 PM PDT 24
Peak memory 197244 kb
Host smart-ca7bd922-eb8f-4238-bb37-0a5f9cdcec6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067856172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2067856172
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2453873674
Short name T881
Test name
Test status
Simulation time 225235151392 ps
CPU time 114.44 seconds
Started Aug 04 05:09:28 PM PDT 24
Finished Aug 04 05:11:22 PM PDT 24
Peak memory 208236 kb
Host smart-a678f9cc-6f96-4396-b8a7-707fb1bc4ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453873674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2453873674
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.4053126608
Short name T878
Test name
Test status
Simulation time 9243403021 ps
CPU time 77.93 seconds
Started Aug 04 05:09:34 PM PDT 24
Finished Aug 04 05:10:52 PM PDT 24
Peak memory 199836 kb
Host smart-b5ad6a5d-bfb2-4c86-a86f-df6658e7a428
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4053126608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.4053126608
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3576406249
Short name T982
Test name
Test status
Simulation time 7313603673 ps
CPU time 13.88 seconds
Started Aug 04 05:09:28 PM PDT 24
Finished Aug 04 05:09:42 PM PDT 24
Peak memory 199188 kb
Host smart-71bf6cab-687f-4bdd-890c-f9f284d64979
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3576406249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3576406249
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.4191153434
Short name T710
Test name
Test status
Simulation time 11279944028 ps
CPU time 6.24 seconds
Started Aug 04 05:09:28 PM PDT 24
Finished Aug 04 05:09:35 PM PDT 24
Peak memory 199620 kb
Host smart-7e4edf41-ad05-409a-9d45-73455827f2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191153434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.4191153434
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3393256727
Short name T957
Test name
Test status
Simulation time 43671227126 ps
CPU time 16.96 seconds
Started Aug 04 05:09:29 PM PDT 24
Finished Aug 04 05:09:46 PM PDT 24
Peak memory 195768 kb
Host smart-c5e0f547-8e98-41ff-a456-7f615c77d301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393256727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3393256727
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.4032414826
Short name T463
Test name
Test status
Simulation time 11057191976 ps
CPU time 35.61 seconds
Started Aug 04 05:09:24 PM PDT 24
Finished Aug 04 05:10:00 PM PDT 24
Peak memory 199760 kb
Host smart-67caeafc-e9b2-4b47-80ec-4757f2e78334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032414826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.4032414826
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3331475266
Short name T116
Test name
Test status
Simulation time 73275575891 ps
CPU time 481.18 seconds
Started Aug 04 05:09:32 PM PDT 24
Finished Aug 04 05:17:33 PM PDT 24
Peak memory 199860 kb
Host smart-87042f9f-d692-4844-a299-cb94e5c9e60c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331475266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3331475266
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.426772489
Short name T395
Test name
Test status
Simulation time 38974410898 ps
CPU time 478.5 seconds
Started Aug 04 05:09:34 PM PDT 24
Finished Aug 04 05:17:32 PM PDT 24
Peak memory 224676 kb
Host smart-2f79a7a1-0714-48cd-aa3d-49fb7efe1255
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426772489 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.426772489
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.2803102562
Short name T465
Test name
Test status
Simulation time 6163966359 ps
CPU time 28.83 seconds
Started Aug 04 05:09:32 PM PDT 24
Finished Aug 04 05:10:01 PM PDT 24
Peak memory 199880 kb
Host smart-5dca6a6a-2b33-4481-9f7c-d76e181871f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803102562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2803102562
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3539041828
Short name T972
Test name
Test status
Simulation time 26980580066 ps
CPU time 11.87 seconds
Started Aug 04 05:09:24 PM PDT 24
Finished Aug 04 05:09:36 PM PDT 24
Peak memory 199872 kb
Host smart-7d414247-2696-4665-9081-fdf3cb97049c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539041828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3539041828
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.463236954
Short name T575
Test name
Test status
Simulation time 33917840 ps
CPU time 0.55 seconds
Started Aug 04 05:09:44 PM PDT 24
Finished Aug 04 05:09:44 PM PDT 24
Peak memory 195304 kb
Host smart-3837738d-5560-4c29-99d1-748f9270e3c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463236954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.463236954
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.85744348
Short name T412
Test name
Test status
Simulation time 8780007660 ps
CPU time 16.61 seconds
Started Aug 04 05:09:33 PM PDT 24
Finished Aug 04 05:09:50 PM PDT 24
Peak memory 199880 kb
Host smart-941e8db2-d39d-4934-8d78-106fd5dd7b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85744348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.85744348
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.853849718
Short name T285
Test name
Test status
Simulation time 115321716729 ps
CPU time 251.05 seconds
Started Aug 04 05:09:32 PM PDT 24
Finished Aug 04 05:13:43 PM PDT 24
Peak memory 199868 kb
Host smart-fd0804f0-5bcc-417e-bcce-8699310ecd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853849718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.853849718
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2011392231
Short name T974
Test name
Test status
Simulation time 14257965870 ps
CPU time 13.88 seconds
Started Aug 04 05:09:33 PM PDT 24
Finished Aug 04 05:09:47 PM PDT 24
Peak memory 199788 kb
Host smart-104be786-bde1-44bb-b397-aa24a7fcc5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011392231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2011392231
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.1542755911
Short name T442
Test name
Test status
Simulation time 299427595793 ps
CPU time 217.31 seconds
Started Aug 04 05:09:37 PM PDT 24
Finished Aug 04 05:13:14 PM PDT 24
Peak memory 199820 kb
Host smart-ce83b833-e677-4df7-a0fc-25931786ab74
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542755911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1542755911
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.2299930509
Short name T767
Test name
Test status
Simulation time 42444304581 ps
CPU time 154.46 seconds
Started Aug 04 05:09:37 PM PDT 24
Finished Aug 04 05:12:11 PM PDT 24
Peak memory 199868 kb
Host smart-c576e17f-3645-4303-b11d-a0e790a159f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2299930509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2299930509
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1922828873
Short name T962
Test name
Test status
Simulation time 11995467656 ps
CPU time 18.94 seconds
Started Aug 04 05:09:36 PM PDT 24
Finished Aug 04 05:09:55 PM PDT 24
Peak memory 199736 kb
Host smart-3a6f31b9-c45d-45c1-9b82-672828380f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922828873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1922828873
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3103090511
Short name T752
Test name
Test status
Simulation time 319276948469 ps
CPU time 31.26 seconds
Started Aug 04 05:09:36 PM PDT 24
Finished Aug 04 05:10:08 PM PDT 24
Peak memory 208252 kb
Host smart-64a54d6e-e12f-45b2-8d95-c1f681cccd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103090511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3103090511
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1824910068
Short name T264
Test name
Test status
Simulation time 8374637041 ps
CPU time 58.48 seconds
Started Aug 04 05:09:38 PM PDT 24
Finished Aug 04 05:10:36 PM PDT 24
Peak memory 199904 kb
Host smart-5f00eae7-9fc5-4d5e-be74-688c637d5975
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1824910068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1824910068
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2980204159
Short name T769
Test name
Test status
Simulation time 4323835829 ps
CPU time 5.93 seconds
Started Aug 04 05:09:38 PM PDT 24
Finished Aug 04 05:09:44 PM PDT 24
Peak memory 198196 kb
Host smart-4c9cc8a9-cef4-4f8b-94b8-3657eb80ba98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2980204159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2980204159
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1497517967
Short name T421
Test name
Test status
Simulation time 11311412744 ps
CPU time 35.45 seconds
Started Aug 04 05:09:36 PM PDT 24
Finished Aug 04 05:10:11 PM PDT 24
Peak memory 199856 kb
Host smart-4cb8f0c3-0f89-4174-8233-aaba999d839a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497517967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1497517967
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.281109741
Short name T108
Test name
Test status
Simulation time 3018566759 ps
CPU time 1.74 seconds
Started Aug 04 05:09:38 PM PDT 24
Finished Aug 04 05:09:39 PM PDT 24
Peak memory 195764 kb
Host smart-251e9100-2f0a-4cc1-bed2-df650148cf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281109741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.281109741
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3314542122
Short name T773
Test name
Test status
Simulation time 340189841 ps
CPU time 1.02 seconds
Started Aug 04 05:09:34 PM PDT 24
Finished Aug 04 05:09:35 PM PDT 24
Peak memory 198256 kb
Host smart-0c1b4d43-1148-44e8-8cc0-f0121cae9c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314542122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3314542122
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.393418483
Short name T1081
Test name
Test status
Simulation time 104436459423 ps
CPU time 671.98 seconds
Started Aug 04 05:09:36 PM PDT 24
Finished Aug 04 05:20:48 PM PDT 24
Peak memory 216476 kb
Host smart-0c99a8c8-7dbb-47f3-b6f1-b78c9fc301c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393418483 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.393418483
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.191915422
Short name T547
Test name
Test status
Simulation time 8297965637 ps
CPU time 10.7 seconds
Started Aug 04 05:09:37 PM PDT 24
Finished Aug 04 05:09:48 PM PDT 24
Peak memory 199716 kb
Host smart-96f19223-3176-4217-b762-843121995a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191915422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.191915422
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2299392056
Short name T1056
Test name
Test status
Simulation time 112979434205 ps
CPU time 50.21 seconds
Started Aug 04 05:09:32 PM PDT 24
Finished Aug 04 05:10:22 PM PDT 24
Peak memory 199848 kb
Host smart-3c9cbaf9-65d3-4205-9c30-681a9f4f6140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299392056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2299392056
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.3311846003
Short name T364
Test name
Test status
Simulation time 21187705 ps
CPU time 0.56 seconds
Started Aug 04 05:09:42 PM PDT 24
Finished Aug 04 05:09:43 PM PDT 24
Peak memory 195200 kb
Host smart-47e48fb2-9cfe-4ddb-985a-a68154594f33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311846003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3311846003
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.3110926439
Short name T703
Test name
Test status
Simulation time 51295574763 ps
CPU time 84.87 seconds
Started Aug 04 05:09:42 PM PDT 24
Finished Aug 04 05:11:07 PM PDT 24
Peak memory 199304 kb
Host smart-c18fe837-cff8-491b-8e64-9054d458bd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110926439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3110926439
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3543039388
Short name T747
Test name
Test status
Simulation time 27660274550 ps
CPU time 50.17 seconds
Started Aug 04 05:09:41 PM PDT 24
Finished Aug 04 05:10:32 PM PDT 24
Peak memory 199808 kb
Host smart-1d6ce3c3-e1bd-4e60-b1e1-d2ae54304bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543039388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3543039388
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.223790834
Short name T530
Test name
Test status
Simulation time 27885071898 ps
CPU time 11.09 seconds
Started Aug 04 05:09:41 PM PDT 24
Finished Aug 04 05:09:52 PM PDT 24
Peak memory 199896 kb
Host smart-8d68940b-afd7-4833-99dc-4f4d4134d274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223790834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.223790834
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3840871938
Short name T895
Test name
Test status
Simulation time 16495934705 ps
CPU time 6.7 seconds
Started Aug 04 05:09:41 PM PDT 24
Finished Aug 04 05:09:48 PM PDT 24
Peak memory 196612 kb
Host smart-9e3960bc-190c-45c2-ae8e-4b7f0058c761
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840871938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3840871938
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.77453290
Short name T433
Test name
Test status
Simulation time 298206754352 ps
CPU time 349.23 seconds
Started Aug 04 05:09:41 PM PDT 24
Finished Aug 04 05:15:31 PM PDT 24
Peak memory 199768 kb
Host smart-b7948bc2-a29c-43cf-bdaa-dbdf7026f761
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77453290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.77453290
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2195262186
Short name T381
Test name
Test status
Simulation time 102662360 ps
CPU time 0.76 seconds
Started Aug 04 05:09:43 PM PDT 24
Finished Aug 04 05:09:44 PM PDT 24
Peak memory 195788 kb
Host smart-c9c4d540-ae33-47e6-b0c8-48b31a118851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195262186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2195262186
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2122065776
Short name T242
Test name
Test status
Simulation time 490372682637 ps
CPU time 56.78 seconds
Started Aug 04 05:09:42 PM PDT 24
Finished Aug 04 05:10:39 PM PDT 24
Peak memory 208236 kb
Host smart-5872883e-bbfe-473b-954f-9e5151f7517f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122065776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2122065776
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1136686980
Short name T263
Test name
Test status
Simulation time 17642368486 ps
CPU time 447.79 seconds
Started Aug 04 05:09:44 PM PDT 24
Finished Aug 04 05:17:12 PM PDT 24
Peak memory 199848 kb
Host smart-8dea5883-3848-443d-a4eb-2096a66e81b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1136686980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1136686980
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.4271352924
Short name T563
Test name
Test status
Simulation time 1925452614 ps
CPU time 3.14 seconds
Started Aug 04 05:09:42 PM PDT 24
Finished Aug 04 05:09:45 PM PDT 24
Peak memory 198020 kb
Host smart-70c6d6b7-365c-43e8-9b3e-be3d2189b016
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4271352924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.4271352924
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1518415152
Short name T486
Test name
Test status
Simulation time 161113698481 ps
CPU time 117.53 seconds
Started Aug 04 05:09:44 PM PDT 24
Finished Aug 04 05:11:42 PM PDT 24
Peak memory 199920 kb
Host smart-1fcbeb5c-b6b2-496b-96e5-f123f060c6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518415152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1518415152
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3946749358
Short name T397
Test name
Test status
Simulation time 1404798059 ps
CPU time 1.14 seconds
Started Aug 04 05:09:41 PM PDT 24
Finished Aug 04 05:09:43 PM PDT 24
Peak memory 195364 kb
Host smart-c4803141-a606-4923-98b1-706c7c8ef89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946749358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3946749358
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1860952759
Short name T548
Test name
Test status
Simulation time 5549918043 ps
CPU time 10.02 seconds
Started Aug 04 05:09:43 PM PDT 24
Finished Aug 04 05:09:53 PM PDT 24
Peak memory 199776 kb
Host smart-15a7f987-67c2-4533-8683-0cb0ba934a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860952759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1860952759
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3028532795
Short name T886
Test name
Test status
Simulation time 402196840947 ps
CPU time 195.3 seconds
Started Aug 04 05:09:41 PM PDT 24
Finished Aug 04 05:12:56 PM PDT 24
Peak memory 199852 kb
Host smart-d94a1d70-1f97-4908-99ce-28193af67440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028532795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3028532795
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.4200153510
Short name T495
Test name
Test status
Simulation time 59659735221 ps
CPU time 191.98 seconds
Started Aug 04 05:09:41 PM PDT 24
Finished Aug 04 05:12:53 PM PDT 24
Peak memory 215896 kb
Host smart-21389fac-d15f-424f-8310-461ef3dda83c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200153510 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.4200153510
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2914216538
Short name T559
Test name
Test status
Simulation time 997592906 ps
CPU time 2.76 seconds
Started Aug 04 05:09:43 PM PDT 24
Finished Aug 04 05:09:46 PM PDT 24
Peak memory 198732 kb
Host smart-90bbe240-b742-46f4-99e0-78d7fe461df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914216538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2914216538
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.3107146194
Short name T352
Test name
Test status
Simulation time 168929405 ps
CPU time 0.84 seconds
Started Aug 04 05:09:42 PM PDT 24
Finished Aug 04 05:09:43 PM PDT 24
Peak memory 196684 kb
Host smart-ba2d722a-1d73-40d6-a52c-372a088c8715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107146194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3107146194
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.393880322
Short name T524
Test name
Test status
Simulation time 125469196 ps
CPU time 0.59 seconds
Started Aug 04 05:06:07 PM PDT 24
Finished Aug 04 05:06:08 PM PDT 24
Peak memory 195224 kb
Host smart-ee52c41e-46c9-423d-b8db-d507d73b403e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393880322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.393880322
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3140392905
Short name T5
Test name
Test status
Simulation time 18254560270 ps
CPU time 24.25 seconds
Started Aug 04 05:05:57 PM PDT 24
Finished Aug 04 05:06:22 PM PDT 24
Peak memory 199812 kb
Host smart-eb67a4bb-bd0a-40a4-99e3-9d6701f9c037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140392905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3140392905
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.631832680
Short name T654
Test name
Test status
Simulation time 45912038194 ps
CPU time 43.6 seconds
Started Aug 04 05:05:56 PM PDT 24
Finished Aug 04 05:06:39 PM PDT 24
Peak memory 199792 kb
Host smart-067fd15d-fb13-430b-bc10-f507a9cca6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631832680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.631832680
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2053824474
Short name T130
Test name
Test status
Simulation time 86847352459 ps
CPU time 128.43 seconds
Started Aug 04 05:05:56 PM PDT 24
Finished Aug 04 05:08:05 PM PDT 24
Peak memory 199792 kb
Host smart-3ae2a2d3-be24-454f-9345-c688bb513f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053824474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2053824474
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.141877402
Short name T461
Test name
Test status
Simulation time 47235915152 ps
CPU time 44.49 seconds
Started Aug 04 05:05:58 PM PDT 24
Finished Aug 04 05:06:42 PM PDT 24
Peak memory 199764 kb
Host smart-03d0f687-7ab0-4127-a089-539a704f65c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141877402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.141877402
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.104671659
Short name T984
Test name
Test status
Simulation time 201160994382 ps
CPU time 223.27 seconds
Started Aug 04 05:06:05 PM PDT 24
Finished Aug 04 05:09:49 PM PDT 24
Peak memory 199860 kb
Host smart-3c9a3a4f-9da7-43e8-a0be-2787235c295d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104671659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.104671659
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2936815776
Short name T423
Test name
Test status
Simulation time 7656974072 ps
CPU time 5.02 seconds
Started Aug 04 05:06:02 PM PDT 24
Finished Aug 04 05:06:07 PM PDT 24
Peak memory 199800 kb
Host smart-6d8c6163-343b-4d8c-b296-a13d6a9eb0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936815776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2936815776
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3583658985
Short name T507
Test name
Test status
Simulation time 57393594396 ps
CPU time 20.24 seconds
Started Aug 04 05:06:02 PM PDT 24
Finished Aug 04 05:06:23 PM PDT 24
Peak memory 198452 kb
Host smart-14ad1b31-7957-4c14-a246-d5e43d184224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583658985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3583658985
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.4016549695
Short name T528
Test name
Test status
Simulation time 14838970661 ps
CPU time 847.73 seconds
Started Aug 04 05:06:01 PM PDT 24
Finished Aug 04 05:20:09 PM PDT 24
Peak memory 200088 kb
Host smart-980c8117-ee66-44f0-9c21-d7f13faa7b83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4016549695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.4016549695
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1014960650
Short name T478
Test name
Test status
Simulation time 2244346218 ps
CPU time 2.9 seconds
Started Aug 04 05:05:56 PM PDT 24
Finished Aug 04 05:05:59 PM PDT 24
Peak memory 197808 kb
Host smart-27817794-58b8-4c61-baa1-197780300b37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1014960650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1014960650
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1831988553
Short name T556
Test name
Test status
Simulation time 28704037122 ps
CPU time 24.37 seconds
Started Aug 04 05:06:01 PM PDT 24
Finished Aug 04 05:06:25 PM PDT 24
Peak memory 199884 kb
Host smart-9ed32e73-87c6-4107-8893-ca7fddcc3f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831988553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1831988553
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3732612688
Short name T20
Test name
Test status
Simulation time 4749811125 ps
CPU time 2.58 seconds
Started Aug 04 05:06:03 PM PDT 24
Finished Aug 04 05:06:06 PM PDT 24
Peak memory 195972 kb
Host smart-94a421a0-b9fd-4ac8-ad89-8f5c21c5fb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732612688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3732612688
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2005437984
Short name T98
Test name
Test status
Simulation time 61024324 ps
CPU time 0.85 seconds
Started Aug 04 05:06:05 PM PDT 24
Finished Aug 04 05:06:06 PM PDT 24
Peak memory 218172 kb
Host smart-81579602-7daf-4925-a23b-80364989f89b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005437984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2005437984
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1979883564
Short name T315
Test name
Test status
Simulation time 105890374 ps
CPU time 0.83 seconds
Started Aug 04 05:05:53 PM PDT 24
Finished Aug 04 05:05:53 PM PDT 24
Peak memory 197792 kb
Host smart-b3d982e2-48dd-41a0-bc3f-544ba9098ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979883564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1979883564
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.726154157
Short name T683
Test name
Test status
Simulation time 65118867042 ps
CPU time 1971.23 seconds
Started Aug 04 05:06:08 PM PDT 24
Finished Aug 04 05:38:59 PM PDT 24
Peak memory 208180 kb
Host smart-b6cf3656-0fb0-4f6b-a18d-840c37c70ce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726154157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.726154157
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3045613055
Short name T561
Test name
Test status
Simulation time 920446793 ps
CPU time 2.41 seconds
Started Aug 04 05:06:00 PM PDT 24
Finished Aug 04 05:06:02 PM PDT 24
Peak memory 198516 kb
Host smart-5476b1d3-39ca-4c8b-8174-2cdeaf9536f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045613055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3045613055
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3614253710
Short name T241
Test name
Test status
Simulation time 81734039550 ps
CPU time 52.6 seconds
Started Aug 04 05:05:53 PM PDT 24
Finished Aug 04 05:06:46 PM PDT 24
Peak memory 199852 kb
Host smart-f1b42cf6-a6dd-4a7e-8191-dd2805b765b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614253710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3614253710
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.696770187
Short name T1035
Test name
Test status
Simulation time 41385473 ps
CPU time 0.6 seconds
Started Aug 04 05:09:46 PM PDT 24
Finished Aug 04 05:09:47 PM PDT 24
Peak memory 195556 kb
Host smart-30554532-2e35-4c0f-82fb-ea0779bdfe99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696770187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.696770187
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2557995804
Short name T496
Test name
Test status
Simulation time 288115934416 ps
CPU time 76.32 seconds
Started Aug 04 05:09:44 PM PDT 24
Finished Aug 04 05:11:01 PM PDT 24
Peak memory 199856 kb
Host smart-7df4490a-0e2d-4bc6-b7c8-3d911b3a77c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557995804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2557995804
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2691719528
Short name T250
Test name
Test status
Simulation time 80252031887 ps
CPU time 42.8 seconds
Started Aug 04 05:09:47 PM PDT 24
Finished Aug 04 05:10:29 PM PDT 24
Peak memory 199828 kb
Host smart-eb9baf5e-6f95-4b85-8fc5-2ae087fdc610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691719528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2691719528
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.781352382
Short name T162
Test name
Test status
Simulation time 36107857206 ps
CPU time 23.26 seconds
Started Aug 04 05:09:48 PM PDT 24
Finished Aug 04 05:10:11 PM PDT 24
Peak memory 199748 kb
Host smart-439dd59e-8a22-46c2-a630-2d8fbc6b2d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781352382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.781352382
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1305938371
Short name T418
Test name
Test status
Simulation time 39462197647 ps
CPU time 16.64 seconds
Started Aug 04 05:09:45 PM PDT 24
Finished Aug 04 05:10:02 PM PDT 24
Peak memory 199660 kb
Host smart-b3ff5779-f425-4695-8b59-bdc405ab6290
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305938371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1305938371
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3781987145
Short name T877
Test name
Test status
Simulation time 125292077855 ps
CPU time 334 seconds
Started Aug 04 05:09:46 PM PDT 24
Finished Aug 04 05:15:20 PM PDT 24
Peak memory 199848 kb
Host smart-ffdc45d7-698c-479c-adf1-0685985657ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3781987145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3781987145
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3151345459
Short name T510
Test name
Test status
Simulation time 9834513457 ps
CPU time 9.13 seconds
Started Aug 04 05:09:46 PM PDT 24
Finished Aug 04 05:09:56 PM PDT 24
Peak memory 199748 kb
Host smart-3d74068a-b3bf-4f81-bc19-363491218bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151345459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3151345459
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1551548599
Short name T458
Test name
Test status
Simulation time 149833524851 ps
CPU time 66.21 seconds
Started Aug 04 05:09:46 PM PDT 24
Finished Aug 04 05:10:52 PM PDT 24
Peak memory 199884 kb
Host smart-f243bc83-65ca-42c3-b6a2-dcbe1ed33ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551548599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1551548599
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.895662712
Short name T993
Test name
Test status
Simulation time 9334846833 ps
CPU time 536.4 seconds
Started Aug 04 05:09:47 PM PDT 24
Finished Aug 04 05:18:43 PM PDT 24
Peak memory 199892 kb
Host smart-55c0d0bd-94b2-474a-aad7-6215f2636545
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=895662712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.895662712
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3586700240
Short name T349
Test name
Test status
Simulation time 2650246860 ps
CPU time 7.41 seconds
Started Aug 04 05:09:47 PM PDT 24
Finished Aug 04 05:09:55 PM PDT 24
Peak memory 198028 kb
Host smart-8cba4f32-39b7-44b5-a16d-823751adf4b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3586700240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3586700240
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1891312940
Short name T248
Test name
Test status
Simulation time 168284100256 ps
CPU time 425.65 seconds
Started Aug 04 05:09:45 PM PDT 24
Finished Aug 04 05:16:50 PM PDT 24
Peak memory 199912 kb
Host smart-7bf3bc37-1267-4fb6-ad16-fdf7d62065a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891312940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1891312940
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1643081072
Short name T350
Test name
Test status
Simulation time 3440114043 ps
CPU time 2.04 seconds
Started Aug 04 05:09:46 PM PDT 24
Finished Aug 04 05:09:48 PM PDT 24
Peak memory 196348 kb
Host smart-bf071b25-3776-40d2-99b6-f4c3cbcd8b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643081072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1643081072
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2578024859
Short name T40
Test name
Test status
Simulation time 690939874 ps
CPU time 3.46 seconds
Started Aug 04 05:09:43 PM PDT 24
Finished Aug 04 05:09:46 PM PDT 24
Peak memory 199548 kb
Host smart-710cae12-3e89-4352-a206-4f0443adf43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578024859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2578024859
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2044624161
Short name T817
Test name
Test status
Simulation time 307093369716 ps
CPU time 254.59 seconds
Started Aug 04 05:09:45 PM PDT 24
Finished Aug 04 05:14:00 PM PDT 24
Peak memory 199824 kb
Host smart-b019cae5-59f3-4055-8f33-8df53120fa1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044624161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2044624161
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.418395727
Short name T635
Test name
Test status
Simulation time 90258489387 ps
CPU time 1079.24 seconds
Started Aug 04 05:09:46 PM PDT 24
Finished Aug 04 05:27:46 PM PDT 24
Peak memory 216236 kb
Host smart-06893959-eab6-4b1c-8eb1-0f9321b0d0aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418395727 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.418395727
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2367407603
Short name T750
Test name
Test status
Simulation time 335614379 ps
CPU time 1.64 seconds
Started Aug 04 05:09:47 PM PDT 24
Finished Aug 04 05:09:49 PM PDT 24
Peak memory 198312 kb
Host smart-122b3e4e-a368-4ec4-9eec-5a6bfaa43c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367407603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2367407603
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2770339558
Short name T831
Test name
Test status
Simulation time 43176658422 ps
CPU time 44.96 seconds
Started Aug 04 05:09:44 PM PDT 24
Finished Aug 04 05:10:29 PM PDT 24
Peak memory 199928 kb
Host smart-e8216c46-85b5-4035-9a32-fbd0dd2349ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770339558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2770339558
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1592598699
Short name T826
Test name
Test status
Simulation time 49199165 ps
CPU time 0.56 seconds
Started Aug 04 05:09:54 PM PDT 24
Finished Aug 04 05:09:55 PM PDT 24
Peak memory 195200 kb
Host smart-509b7f50-74be-4420-90b6-4ab4eab6e1a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592598699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1592598699
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.346369742
Short name T558
Test name
Test status
Simulation time 54398934942 ps
CPU time 84.29 seconds
Started Aug 04 05:09:49 PM PDT 24
Finished Aug 04 05:11:13 PM PDT 24
Peak memory 199856 kb
Host smart-3949ac83-3313-4c13-bab3-fce9ea9c21c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346369742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.346369742
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2423852956
Short name T1013
Test name
Test status
Simulation time 49275239644 ps
CPU time 19.35 seconds
Started Aug 04 05:09:49 PM PDT 24
Finished Aug 04 05:10:09 PM PDT 24
Peak memory 199348 kb
Host smart-1208daf9-35cb-41d9-aba6-6843847ee358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423852956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2423852956
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3396821191
Short name T937
Test name
Test status
Simulation time 151450723170 ps
CPU time 181.72 seconds
Started Aug 04 05:09:51 PM PDT 24
Finished Aug 04 05:12:53 PM PDT 24
Peak memory 199756 kb
Host smart-56791406-c7fd-4594-aa4c-99abde4bc4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396821191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3396821191
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2258559785
Short name T839
Test name
Test status
Simulation time 30324293143 ps
CPU time 46.11 seconds
Started Aug 04 05:09:50 PM PDT 24
Finished Aug 04 05:10:36 PM PDT 24
Peak memory 199784 kb
Host smart-03690d0a-7972-4763-9c3d-9c798b12fb68
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258559785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2258559785
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2257339505
Short name T856
Test name
Test status
Simulation time 163768359614 ps
CPU time 1542.24 seconds
Started Aug 04 05:09:50 PM PDT 24
Finished Aug 04 05:35:33 PM PDT 24
Peak memory 199852 kb
Host smart-a95ef59a-5520-464d-ad17-f18fc8d6681d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2257339505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2257339505
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.684721967
Short name T810
Test name
Test status
Simulation time 8116170241 ps
CPU time 14.03 seconds
Started Aug 04 05:09:50 PM PDT 24
Finished Aug 04 05:10:04 PM PDT 24
Peak memory 199792 kb
Host smart-6cda6729-c3f8-44ab-b8b3-8db841a3b094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684721967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.684721967
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.689444584
Short name T760
Test name
Test status
Simulation time 104964694820 ps
CPU time 87.12 seconds
Started Aug 04 05:09:50 PM PDT 24
Finished Aug 04 05:11:17 PM PDT 24
Peak memory 199872 kb
Host smart-442f922a-6e84-4a14-88ad-31e2d9efff6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689444584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.689444584
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2104992118
Short name T247
Test name
Test status
Simulation time 16631444755 ps
CPU time 189.44 seconds
Started Aug 04 05:09:50 PM PDT 24
Finished Aug 04 05:12:59 PM PDT 24
Peak memory 199820 kb
Host smart-65a08779-116d-4f36-b25f-6bac8456eb66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104992118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2104992118
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.383567786
Short name T898
Test name
Test status
Simulation time 4480765994 ps
CPU time 36.78 seconds
Started Aug 04 05:09:52 PM PDT 24
Finished Aug 04 05:10:29 PM PDT 24
Peak memory 198016 kb
Host smart-2ee77417-865a-4e1e-825a-cd231853c300
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=383567786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.383567786
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1138279888
Short name T625
Test name
Test status
Simulation time 108065110301 ps
CPU time 110.43 seconds
Started Aug 04 05:09:49 PM PDT 24
Finished Aug 04 05:11:39 PM PDT 24
Peak memory 199880 kb
Host smart-f7d8c3b5-b65d-4b8f-961c-687b0bbb31ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138279888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1138279888
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.483531491
Short name T21
Test name
Test status
Simulation time 76196072225 ps
CPU time 115.42 seconds
Started Aug 04 05:09:49 PM PDT 24
Finished Aug 04 05:11:45 PM PDT 24
Peak memory 196932 kb
Host smart-478086a1-6762-4a7f-af72-6e33b0add6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483531491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.483531491
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.4001859389
Short name T923
Test name
Test status
Simulation time 11089218133 ps
CPU time 49.39 seconds
Started Aug 04 05:09:50 PM PDT 24
Finished Aug 04 05:10:39 PM PDT 24
Peak memory 199748 kb
Host smart-f516bc7d-9972-4a08-81b1-7e33c5477087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001859389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.4001859389
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.2082013805
Short name T1018
Test name
Test status
Simulation time 144857796118 ps
CPU time 196.03 seconds
Started Aug 04 05:09:55 PM PDT 24
Finished Aug 04 05:13:11 PM PDT 24
Peak memory 216120 kb
Host smart-02c70a87-e9b1-4f5f-9f8c-ce1a0be7456d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082013805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2082013805
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2192180777
Short name T54
Test name
Test status
Simulation time 141680683068 ps
CPU time 322.86 seconds
Started Aug 04 05:09:53 PM PDT 24
Finished Aug 04 05:15:16 PM PDT 24
Peak memory 216560 kb
Host smart-54dffebb-5d36-4b07-906b-ed4faf29357e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192180777 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2192180777
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3666136045
Short name T904
Test name
Test status
Simulation time 1078043499 ps
CPU time 1.86 seconds
Started Aug 04 05:09:49 PM PDT 24
Finished Aug 04 05:09:51 PM PDT 24
Peak memory 198492 kb
Host smart-de0ab892-1aeb-407f-94bf-fd627e962c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666136045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3666136045
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1193827232
Short name T1120
Test name
Test status
Simulation time 128566558962 ps
CPU time 115.55 seconds
Started Aug 04 05:09:49 PM PDT 24
Finished Aug 04 05:11:45 PM PDT 24
Peak memory 199864 kb
Host smart-4c3d79a4-05ab-491c-bb53-cd5bd33eb9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193827232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1193827232
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.727862984
Short name T551
Test name
Test status
Simulation time 13777704 ps
CPU time 0.56 seconds
Started Aug 04 05:10:00 PM PDT 24
Finished Aug 04 05:10:01 PM PDT 24
Peak memory 195200 kb
Host smart-1e187291-d539-4c2b-aa92-600be04c0cbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727862984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.727862984
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.873680683
Short name T604
Test name
Test status
Simulation time 101199088139 ps
CPU time 39.11 seconds
Started Aug 04 05:09:58 PM PDT 24
Finished Aug 04 05:10:37 PM PDT 24
Peak memory 199844 kb
Host smart-eb65c342-a5da-45c8-bc29-190ef8c4ce3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873680683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.873680683
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.895133720
Short name T835
Test name
Test status
Simulation time 107215818783 ps
CPU time 39.6 seconds
Started Aug 04 05:09:56 PM PDT 24
Finished Aug 04 05:10:36 PM PDT 24
Peak memory 199672 kb
Host smart-c6ab6b22-dc3b-4923-9545-3fd2718451b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895133720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.895133720
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2284541579
Short name T1110
Test name
Test status
Simulation time 37303592627 ps
CPU time 16.34 seconds
Started Aug 04 05:09:53 PM PDT 24
Finished Aug 04 05:10:09 PM PDT 24
Peak memory 199824 kb
Host smart-93908dc9-28c9-4742-9965-6e4c536f9963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284541579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2284541579
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.3699136039
Short name T936
Test name
Test status
Simulation time 33439413661 ps
CPU time 12.27 seconds
Started Aug 04 05:09:53 PM PDT 24
Finished Aug 04 05:10:06 PM PDT 24
Peak memory 199480 kb
Host smart-0319170e-efc8-4482-9864-890661db239e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699136039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3699136039
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3284911943
Short name T468
Test name
Test status
Simulation time 88291472352 ps
CPU time 478.15 seconds
Started Aug 04 05:10:00 PM PDT 24
Finished Aug 04 05:17:58 PM PDT 24
Peak memory 199836 kb
Host smart-ee8b9f37-1e82-45b7-ae2b-f8e97fbfb7aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3284911943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3284911943
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.2079865986
Short name T474
Test name
Test status
Simulation time 6293155178 ps
CPU time 4.74 seconds
Started Aug 04 05:09:59 PM PDT 24
Finished Aug 04 05:10:04 PM PDT 24
Peak memory 198588 kb
Host smart-d4df0205-f05a-4513-843f-fab88d52c57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079865986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2079865986
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.4202751204
Short name T952
Test name
Test status
Simulation time 228511758877 ps
CPU time 39 seconds
Started Aug 04 05:09:54 PM PDT 24
Finished Aug 04 05:10:33 PM PDT 24
Peak memory 199980 kb
Host smart-cc34e7c4-0938-40be-b7e7-ed7b86adab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202751204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.4202751204
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1832718840
Short name T451
Test name
Test status
Simulation time 7560156348 ps
CPU time 182.46 seconds
Started Aug 04 05:10:00 PM PDT 24
Finished Aug 04 05:13:03 PM PDT 24
Peak memory 199760 kb
Host smart-8351a797-3e62-4cfa-aed9-7a4af0ac650a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1832718840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1832718840
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.1037537337
Short name T981
Test name
Test status
Simulation time 4616846270 ps
CPU time 39.74 seconds
Started Aug 04 05:09:57 PM PDT 24
Finished Aug 04 05:10:37 PM PDT 24
Peak memory 199088 kb
Host smart-7d55784c-0985-4dc0-a20c-102da494552c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1037537337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1037537337
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1195400213
Short name T15
Test name
Test status
Simulation time 172791133817 ps
CPU time 116.22 seconds
Started Aug 04 05:09:53 PM PDT 24
Finished Aug 04 05:11:50 PM PDT 24
Peak memory 199920 kb
Host smart-f727f348-58f6-415c-a2b5-18ba44f584b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195400213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1195400213
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3357727095
Short name T275
Test name
Test status
Simulation time 33154880040 ps
CPU time 4.44 seconds
Started Aug 04 05:09:53 PM PDT 24
Finished Aug 04 05:09:57 PM PDT 24
Peak memory 196200 kb
Host smart-08231ddd-86c3-43eb-befc-dcd1c1a34c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357727095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3357727095
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.550281925
Short name T1106
Test name
Test status
Simulation time 107777626 ps
CPU time 0.88 seconds
Started Aug 04 05:09:55 PM PDT 24
Finished Aug 04 05:09:56 PM PDT 24
Peak memory 196940 kb
Host smart-72130fcd-953c-46c9-8682-722c5c3ba7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550281925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.550281925
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.3730812522
Short name T149
Test name
Test status
Simulation time 644377493115 ps
CPU time 545.42 seconds
Started Aug 04 05:10:00 PM PDT 24
Finished Aug 04 05:19:06 PM PDT 24
Peak memory 208160 kb
Host smart-583ffd80-e397-49c2-9199-5df5830ac3cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730812522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3730812522
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.454936249
Short name T276
Test name
Test status
Simulation time 1704363171 ps
CPU time 2.1 seconds
Started Aug 04 05:09:56 PM PDT 24
Finished Aug 04 05:09:59 PM PDT 24
Peak memory 199776 kb
Host smart-f9647035-b3c4-42d3-9cd0-4b22ffc9ffa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454936249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.454936249
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3524656830
Short name T811
Test name
Test status
Simulation time 20000957928 ps
CPU time 18.02 seconds
Started Aug 04 05:09:56 PM PDT 24
Finished Aug 04 05:10:14 PM PDT 24
Peak memory 199748 kb
Host smart-1a7f820f-8436-4cf8-bb6b-0e385b98b372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524656830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3524656830
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2980621776
Short name T436
Test name
Test status
Simulation time 42115393 ps
CPU time 0.56 seconds
Started Aug 04 05:10:01 PM PDT 24
Finished Aug 04 05:10:02 PM PDT 24
Peak memory 195480 kb
Host smart-31d09a5e-3232-4d6e-bad4-f24fe80c0c75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980621776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2980621776
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.45475955
Short name T156
Test name
Test status
Simulation time 138563898080 ps
CPU time 106.1 seconds
Started Aug 04 05:09:59 PM PDT 24
Finished Aug 04 05:11:46 PM PDT 24
Peak memory 199912 kb
Host smart-4cfc5f0b-bd90-44ae-bb4c-d00b8d400f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45475955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.45475955
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3417488212
Short name T508
Test name
Test status
Simulation time 52754493356 ps
CPU time 38.19 seconds
Started Aug 04 05:10:01 PM PDT 24
Finished Aug 04 05:10:39 PM PDT 24
Peak memory 199916 kb
Host smart-396ec0a5-da3b-49da-a82a-3beb8d874e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417488212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3417488212
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1793888061
Short name T113
Test name
Test status
Simulation time 61056851484 ps
CPU time 34.16 seconds
Started Aug 04 05:10:04 PM PDT 24
Finished Aug 04 05:10:38 PM PDT 24
Peak memory 199728 kb
Host smart-74f48f94-8ee3-4711-970e-7d6a8b755389
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793888061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1793888061
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.2165306178
Short name T1104
Test name
Test status
Simulation time 55503540899 ps
CPU time 384.19 seconds
Started Aug 04 05:10:03 PM PDT 24
Finished Aug 04 05:16:27 PM PDT 24
Peak memory 199740 kb
Host smart-75ed8cef-a4a9-4d7d-854f-43d5cc4a2c9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2165306178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2165306178
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.556615151
Short name T439
Test name
Test status
Simulation time 1907802843 ps
CPU time 3.87 seconds
Started Aug 04 05:10:04 PM PDT 24
Finished Aug 04 05:10:08 PM PDT 24
Peak memory 195952 kb
Host smart-52bcaf01-3c5c-4323-a387-a667a58dab2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556615151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.556615151
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.3525603866
Short name T606
Test name
Test status
Simulation time 30378591376 ps
CPU time 48.82 seconds
Started Aug 04 05:10:03 PM PDT 24
Finished Aug 04 05:10:52 PM PDT 24
Peak memory 197028 kb
Host smart-3a9cd744-e43f-46dd-bbf2-8d6576be4c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525603866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3525603866
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1750095310
Short name T757
Test name
Test status
Simulation time 15392217165 ps
CPU time 223.42 seconds
Started Aug 04 05:10:01 PM PDT 24
Finished Aug 04 05:13:45 PM PDT 24
Peak memory 199784 kb
Host smart-0d1e346c-e236-41fd-8940-b97161f08b4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1750095310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1750095310
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.188890969
Short name T789
Test name
Test status
Simulation time 5351714886 ps
CPU time 10.83 seconds
Started Aug 04 05:10:02 PM PDT 24
Finished Aug 04 05:10:13 PM PDT 24
Peak memory 198960 kb
Host smart-994d0159-8dda-49ef-8a3b-252fed572d15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=188890969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.188890969
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1284229557
Short name T152
Test name
Test status
Simulation time 27272728059 ps
CPU time 11.59 seconds
Started Aug 04 05:10:07 PM PDT 24
Finished Aug 04 05:10:19 PM PDT 24
Peak memory 199724 kb
Host smart-234a3942-5c40-4964-8b09-e88bff4ae128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284229557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1284229557
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2152746020
Short name T1000
Test name
Test status
Simulation time 5786564638 ps
CPU time 2.67 seconds
Started Aug 04 05:10:04 PM PDT 24
Finished Aug 04 05:10:07 PM PDT 24
Peak memory 196036 kb
Host smart-cd8d04c1-b6b9-4f0e-9e09-2d9e05c331a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152746020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2152746020
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.2879957262
Short name T1142
Test name
Test status
Simulation time 447280358 ps
CPU time 2.21 seconds
Started Aug 04 05:10:02 PM PDT 24
Finished Aug 04 05:10:04 PM PDT 24
Peak memory 198636 kb
Host smart-dba6173a-3e39-4e12-8004-07839b74bd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879957262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2879957262
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.404251580
Short name T574
Test name
Test status
Simulation time 52854973746 ps
CPU time 48.66 seconds
Started Aug 04 05:10:07 PM PDT 24
Finished Aug 04 05:10:55 PM PDT 24
Peak memory 199804 kb
Host smart-0b372b61-7733-43aa-9078-9501b75a97b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404251580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.404251580
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3160901139
Short name T627
Test name
Test status
Simulation time 101038002673 ps
CPU time 321.04 seconds
Started Aug 04 05:10:08 PM PDT 24
Finished Aug 04 05:15:29 PM PDT 24
Peak memory 215584 kb
Host smart-7e20ae5e-419a-469d-9f81-18eb0617ad5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160901139 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3160901139
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.111264778
Short name T714
Test name
Test status
Simulation time 879347773 ps
CPU time 3.17 seconds
Started Aug 04 05:10:03 PM PDT 24
Finished Aug 04 05:10:06 PM PDT 24
Peak memory 198776 kb
Host smart-50cc0a71-7e79-432f-943a-10267ee533c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111264778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.111264778
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.187408239
Short name T443
Test name
Test status
Simulation time 15726509939 ps
CPU time 22.87 seconds
Started Aug 04 05:10:00 PM PDT 24
Finished Aug 04 05:10:22 PM PDT 24
Peak memory 199876 kb
Host smart-05c9f9ac-5876-4456-bba6-0860d7c33732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187408239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.187408239
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1728984155
Short name T354
Test name
Test status
Simulation time 12195672 ps
CPU time 0.58 seconds
Started Aug 04 05:10:10 PM PDT 24
Finished Aug 04 05:10:11 PM PDT 24
Peak memory 195240 kb
Host smart-7fa9a538-89f7-4e5a-ac3b-b802d43b3e7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728984155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1728984155
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.2752974236
Short name T684
Test name
Test status
Simulation time 21798882937 ps
CPU time 33.42 seconds
Started Aug 04 05:10:06 PM PDT 24
Finished Aug 04 05:10:39 PM PDT 24
Peak memory 199772 kb
Host smart-b4b4c43e-b98e-40d7-acd7-fc506eb012e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752974236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2752974236
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3177365488
Short name T629
Test name
Test status
Simulation time 200575172547 ps
CPU time 71.38 seconds
Started Aug 04 05:10:05 PM PDT 24
Finished Aug 04 05:11:17 PM PDT 24
Peak memory 199792 kb
Host smart-7344a9e0-e4e0-4065-90d8-81b8f2a16583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177365488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3177365488
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2928252440
Short name T932
Test name
Test status
Simulation time 38203052466 ps
CPU time 33.58 seconds
Started Aug 04 05:10:06 PM PDT 24
Finished Aug 04 05:10:39 PM PDT 24
Peak memory 199840 kb
Host smart-fb361bfa-1d8a-48fd-8cb1-20c322c997d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928252440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2928252440
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2935691565
Short name T391
Test name
Test status
Simulation time 37044329081 ps
CPU time 12.05 seconds
Started Aug 04 05:10:05 PM PDT 24
Finished Aug 04 05:10:17 PM PDT 24
Peak memory 199856 kb
Host smart-9543513b-6e8d-4575-87c2-2eebd9345677
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935691565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2935691565
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.293079180
Short name T591
Test name
Test status
Simulation time 144941604155 ps
CPU time 244.92 seconds
Started Aug 04 05:10:09 PM PDT 24
Finished Aug 04 05:14:14 PM PDT 24
Peak memory 199964 kb
Host smart-6a57d2cd-0715-4bc4-90bf-862c29f87f5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=293079180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.293079180
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1694038217
Short name T620
Test name
Test status
Simulation time 4329774462 ps
CPU time 2.96 seconds
Started Aug 04 05:10:11 PM PDT 24
Finished Aug 04 05:10:14 PM PDT 24
Peak memory 197808 kb
Host smart-4ead321a-0a10-4c0a-b47f-cdb33436dfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694038217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1694038217
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2804018771
Short name T998
Test name
Test status
Simulation time 61751605657 ps
CPU time 52.35 seconds
Started Aug 04 05:10:06 PM PDT 24
Finished Aug 04 05:10:59 PM PDT 24
Peak memory 208152 kb
Host smart-dcefa5d8-3322-4380-93bc-1b25f204fd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804018771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2804018771
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2128312744
Short name T911
Test name
Test status
Simulation time 9392301809 ps
CPU time 48.61 seconds
Started Aug 04 05:10:10 PM PDT 24
Finished Aug 04 05:10:58 PM PDT 24
Peak memory 199900 kb
Host smart-9daad4cb-395c-416c-94fc-d1576bd37580
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2128312744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2128312744
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.4072000657
Short name T636
Test name
Test status
Simulation time 3992869119 ps
CPU time 8.44 seconds
Started Aug 04 05:10:06 PM PDT 24
Finished Aug 04 05:10:15 PM PDT 24
Peak memory 198320 kb
Host smart-fb300a10-7e95-4dc3-bbc8-a723a7455725
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4072000657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.4072000657
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1405133341
Short name T1127
Test name
Test status
Simulation time 53625753817 ps
CPU time 51.75 seconds
Started Aug 04 05:10:06 PM PDT 24
Finished Aug 04 05:10:57 PM PDT 24
Peak memory 199760 kb
Host smart-27ec6e92-ca46-47a2-910a-f05a65d5c49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405133341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1405133341
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3915723428
Short name T728
Test name
Test status
Simulation time 2951391389 ps
CPU time 1.23 seconds
Started Aug 04 05:10:07 PM PDT 24
Finished Aug 04 05:10:09 PM PDT 24
Peak memory 195840 kb
Host smart-e3446c19-8b97-4592-8df7-b0879d413593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915723428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3915723428
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3576200685
Short name T387
Test name
Test status
Simulation time 490214589 ps
CPU time 1.84 seconds
Started Aug 04 05:10:02 PM PDT 24
Finished Aug 04 05:10:04 PM PDT 24
Peak memory 199840 kb
Host smart-4510bd7e-a5b5-4741-aa91-e0bf17e27f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576200685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3576200685
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.146276425
Short name T1080
Test name
Test status
Simulation time 260698550829 ps
CPU time 1076.73 seconds
Started Aug 04 05:10:09 PM PDT 24
Finished Aug 04 05:28:06 PM PDT 24
Peak memory 199824 kb
Host smart-3be7482f-e1ab-4644-b67c-d281d9dd3d68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146276425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.146276425
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.701645500
Short name T57
Test name
Test status
Simulation time 59855165884 ps
CPU time 674.79 seconds
Started Aug 04 05:10:11 PM PDT 24
Finished Aug 04 05:21:26 PM PDT 24
Peak memory 215304 kb
Host smart-c9792c34-41d7-4e21-8ac1-baed99a9448e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701645500 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.701645500
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.474736112
Short name T288
Test name
Test status
Simulation time 7007799637 ps
CPU time 31.55 seconds
Started Aug 04 05:10:10 PM PDT 24
Finished Aug 04 05:10:42 PM PDT 24
Peak memory 199748 kb
Host smart-db004ddc-f19c-4162-ba61-24a75f274022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474736112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.474736112
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3478608291
Short name T1087
Test name
Test status
Simulation time 29160450110 ps
CPU time 47.1 seconds
Started Aug 04 05:10:06 PM PDT 24
Finished Aug 04 05:10:53 PM PDT 24
Peak memory 199868 kb
Host smart-c2aacb25-0f8c-46ea-9f5b-75ffac1f70fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478608291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3478608291
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3363528443
Short name T596
Test name
Test status
Simulation time 14112354 ps
CPU time 0.56 seconds
Started Aug 04 05:10:19 PM PDT 24
Finished Aug 04 05:10:20 PM PDT 24
Peak memory 195220 kb
Host smart-a6cc00aa-66af-4f91-93bd-bb23a6e6727a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363528443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3363528443
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.721281900
Short name T721
Test name
Test status
Simulation time 188470458971 ps
CPU time 74.77 seconds
Started Aug 04 05:10:09 PM PDT 24
Finished Aug 04 05:11:23 PM PDT 24
Peak memory 199848 kb
Host smart-4deb5743-4a19-4fce-a77f-d584ba0334a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721281900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.721281900
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2005594749
Short name T889
Test name
Test status
Simulation time 29793416847 ps
CPU time 45.36 seconds
Started Aug 04 05:10:14 PM PDT 24
Finished Aug 04 05:10:59 PM PDT 24
Peak memory 199852 kb
Host smart-4e5c4cc3-f4ce-4ad6-8cf3-069416961e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005594749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2005594749
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3660578259
Short name T1049
Test name
Test status
Simulation time 28204930957 ps
CPU time 20.12 seconds
Started Aug 04 05:10:13 PM PDT 24
Finished Aug 04 05:10:33 PM PDT 24
Peak memory 199808 kb
Host smart-c59f2fe7-7830-47e1-b9f4-31a783397786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660578259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3660578259
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3583616961
Short name T605
Test name
Test status
Simulation time 6656479259 ps
CPU time 4.22 seconds
Started Aug 04 05:10:14 PM PDT 24
Finished Aug 04 05:10:19 PM PDT 24
Peak memory 199072 kb
Host smart-26dc15cb-a929-4e26-a1e4-dd387231feaa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583616961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3583616961
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_loopback.1018008513
Short name T611
Test name
Test status
Simulation time 6235695849 ps
CPU time 11.97 seconds
Started Aug 04 05:10:15 PM PDT 24
Finished Aug 04 05:10:27 PM PDT 24
Peak memory 199496 kb
Host smart-5f03d419-ee0a-4daf-9e68-2bf8d3274ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018008513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1018008513
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2789644670
Short name T1040
Test name
Test status
Simulation time 295659886446 ps
CPU time 122.48 seconds
Started Aug 04 05:10:14 PM PDT 24
Finished Aug 04 05:12:17 PM PDT 24
Peak memory 207936 kb
Host smart-3a0afc2d-e4d2-4407-a842-14470707e6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789644670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2789644670
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3370702436
Short name T277
Test name
Test status
Simulation time 12460733392 ps
CPU time 349.32 seconds
Started Aug 04 05:10:14 PM PDT 24
Finished Aug 04 05:16:03 PM PDT 24
Peak memory 199900 kb
Host smart-0cb4a562-0dcc-4959-bd54-a1fb30e027fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3370702436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3370702436
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3279639884
Short name T348
Test name
Test status
Simulation time 4836789483 ps
CPU time 36.81 seconds
Started Aug 04 05:10:14 PM PDT 24
Finished Aug 04 05:10:51 PM PDT 24
Peak memory 197868 kb
Host smart-ce270d93-9281-4e80-95ca-50fbcdcb2822
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3279639884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3279639884
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1949143829
Short name T766
Test name
Test status
Simulation time 54784883931 ps
CPU time 31.3 seconds
Started Aug 04 05:10:14 PM PDT 24
Finished Aug 04 05:10:46 PM PDT 24
Peak memory 199704 kb
Host smart-cc3f30c9-b91f-46f0-9ae2-daa0c4a539cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949143829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1949143829
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2141768459
Short name T794
Test name
Test status
Simulation time 37771377289 ps
CPU time 14.55 seconds
Started Aug 04 05:10:17 PM PDT 24
Finished Aug 04 05:10:32 PM PDT 24
Peak memory 196212 kb
Host smart-608619c5-e8a8-4609-9535-3cd6b9313b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141768459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2141768459
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.297148399
Short name T797
Test name
Test status
Simulation time 491100857 ps
CPU time 2.91 seconds
Started Aug 04 05:10:10 PM PDT 24
Finished Aug 04 05:10:13 PM PDT 24
Peak memory 198852 kb
Host smart-119a7439-cf5b-458d-89da-a796b6a3339d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297148399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.297148399
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.3927711835
Short name T494
Test name
Test status
Simulation time 317407912059 ps
CPU time 132.17 seconds
Started Aug 04 05:10:20 PM PDT 24
Finished Aug 04 05:12:32 PM PDT 24
Peak memory 199900 kb
Host smart-5ea38c96-23b9-43bd-b605-7b8920beaa1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927711835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3927711835
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1966892316
Short name T460
Test name
Test status
Simulation time 1281155366 ps
CPU time 1.48 seconds
Started Aug 04 05:10:14 PM PDT 24
Finished Aug 04 05:10:15 PM PDT 24
Peak memory 198736 kb
Host smart-a74f65e0-1b31-4e72-bb79-3964d653d0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966892316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1966892316
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3734637616
Short name T875
Test name
Test status
Simulation time 55291744132 ps
CPU time 106.31 seconds
Started Aug 04 05:10:14 PM PDT 24
Finished Aug 04 05:12:01 PM PDT 24
Peak memory 199908 kb
Host smart-39f438a1-50e1-4f60-94f4-8075a9a9b309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734637616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3734637616
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2351657888
Short name T382
Test name
Test status
Simulation time 26713116 ps
CPU time 0.54 seconds
Started Aug 04 05:10:24 PM PDT 24
Finished Aug 04 05:10:25 PM PDT 24
Peak memory 194644 kb
Host smart-fe2864e6-65f8-4e6a-bef2-a7935c70225b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351657888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2351657888
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3313656503
Short name T481
Test name
Test status
Simulation time 16350651226 ps
CPU time 13.14 seconds
Started Aug 04 05:10:19 PM PDT 24
Finished Aug 04 05:10:33 PM PDT 24
Peak memory 199836 kb
Host smart-0b4dfe23-3a6f-4a99-90e2-cc80feb36efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313656503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3313656503
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2870211461
Short name T621
Test name
Test status
Simulation time 63630376605 ps
CPU time 280.98 seconds
Started Aug 04 05:10:19 PM PDT 24
Finished Aug 04 05:15:00 PM PDT 24
Peak memory 199840 kb
Host smart-1fc0a719-93db-426a-a72a-64cfea805944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870211461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2870211461
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1438528272
Short name T868
Test name
Test status
Simulation time 107094441382 ps
CPU time 53.65 seconds
Started Aug 04 05:10:19 PM PDT 24
Finished Aug 04 05:11:13 PM PDT 24
Peak memory 199912 kb
Host smart-b028b8a7-b332-458a-9b1c-bfa93671c617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438528272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1438528272
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.1688529654
Short name T1111
Test name
Test status
Simulation time 15096833993 ps
CPU time 26.31 seconds
Started Aug 04 05:10:18 PM PDT 24
Finished Aug 04 05:10:44 PM PDT 24
Peak memory 199904 kb
Host smart-9fb22962-2fa7-402d-b201-db7f2661a2b2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688529654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1688529654
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3825474429
Short name T1098
Test name
Test status
Simulation time 99871836428 ps
CPU time 279.27 seconds
Started Aug 04 05:10:23 PM PDT 24
Finished Aug 04 05:15:02 PM PDT 24
Peak memory 199820 kb
Host smart-5b28453a-372f-4ef9-9a6d-9f2fb8ae14ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3825474429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3825474429
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.644898842
Short name T527
Test name
Test status
Simulation time 9319391587 ps
CPU time 7.25 seconds
Started Aug 04 05:10:24 PM PDT 24
Finished Aug 04 05:10:31 PM PDT 24
Peak memory 199704 kb
Host smart-0507eafa-f0b8-4b8a-8e7f-433f3f5ddaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644898842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.644898842
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.922945632
Short name T602
Test name
Test status
Simulation time 166931017873 ps
CPU time 90.08 seconds
Started Aug 04 05:10:17 PM PDT 24
Finished Aug 04 05:11:48 PM PDT 24
Peak memory 199404 kb
Host smart-bc6e5894-e3b2-4ad5-8cc3-f08ae6b0f94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922945632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.922945632
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2721218818
Short name T252
Test name
Test status
Simulation time 22955904341 ps
CPU time 209.75 seconds
Started Aug 04 05:10:25 PM PDT 24
Finished Aug 04 05:13:55 PM PDT 24
Peak memory 199776 kb
Host smart-19d16efa-4ba9-400a-92bc-cf4566291c46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2721218818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2721218818
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3630455622
Short name T987
Test name
Test status
Simulation time 1730158197 ps
CPU time 1.64 seconds
Started Aug 04 05:10:19 PM PDT 24
Finished Aug 04 05:10:20 PM PDT 24
Peak memory 197972 kb
Host smart-b7509e10-9677-4045-929e-c28741bb36b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3630455622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3630455622
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.584967652
Short name T697
Test name
Test status
Simulation time 137795961374 ps
CPU time 89.77 seconds
Started Aug 04 05:10:22 PM PDT 24
Finished Aug 04 05:11:52 PM PDT 24
Peak memory 199868 kb
Host smart-65d43374-e5e7-4564-830d-d5715923c3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584967652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.584967652
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.4008417639
Short name T316
Test name
Test status
Simulation time 40079152918 ps
CPU time 16.79 seconds
Started Aug 04 05:10:21 PM PDT 24
Finished Aug 04 05:10:38 PM PDT 24
Peak memory 196000 kb
Host smart-6c21e8c4-4ab8-4142-9c84-92c23d1c3c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008417639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.4008417639
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1348324956
Short name T862
Test name
Test status
Simulation time 664481918 ps
CPU time 3.4 seconds
Started Aug 04 05:10:20 PM PDT 24
Finished Aug 04 05:10:24 PM PDT 24
Peak memory 198280 kb
Host smart-824af291-7f5f-4c02-9cd2-291d81ad2ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348324956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1348324956
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1484482012
Short name T1003
Test name
Test status
Simulation time 63541176620 ps
CPU time 966.43 seconds
Started Aug 04 05:10:26 PM PDT 24
Finished Aug 04 05:26:33 PM PDT 24
Peak memory 216308 kb
Host smart-30ba3aca-3793-48d0-814c-17b7e9695850
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484482012 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1484482012
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1821417736
Short name T784
Test name
Test status
Simulation time 8629492084 ps
CPU time 10.61 seconds
Started Aug 04 05:10:25 PM PDT 24
Finished Aug 04 05:10:36 PM PDT 24
Peak memory 199728 kb
Host smart-4ab87ea6-c2ba-4347-86cc-84150baa44ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821417736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1821417736
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3113412409
Short name T301
Test name
Test status
Simulation time 2378457484 ps
CPU time 1.23 seconds
Started Aug 04 05:10:18 PM PDT 24
Finished Aug 04 05:10:19 PM PDT 24
Peak memory 196792 kb
Host smart-08c68c24-e919-43ce-a75e-9a0940812872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113412409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3113412409
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1156185268
Short name T445
Test name
Test status
Simulation time 38767936 ps
CPU time 0.56 seconds
Started Aug 04 05:10:32 PM PDT 24
Finished Aug 04 05:10:32 PM PDT 24
Peak memory 195496 kb
Host smart-17bd1497-717b-4c5a-bd8f-164c3d6a013b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156185268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1156185268
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.4095125309
Short name T137
Test name
Test status
Simulation time 86354651205 ps
CPU time 128.34 seconds
Started Aug 04 05:10:23 PM PDT 24
Finished Aug 04 05:12:31 PM PDT 24
Peak memory 199920 kb
Host smart-66b36e90-5102-4332-a8f3-56bcdf8c520d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095125309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.4095125309
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1062245149
Short name T260
Test name
Test status
Simulation time 35218132642 ps
CPU time 28.58 seconds
Started Aug 04 05:10:23 PM PDT 24
Finished Aug 04 05:10:52 PM PDT 24
Peak memory 199920 kb
Host smart-efd5c381-3c4a-4b4e-b3aa-9aa4d449684c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062245149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1062245149
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3780721938
Short name T1121
Test name
Test status
Simulation time 27945525187 ps
CPU time 50.18 seconds
Started Aug 04 05:10:24 PM PDT 24
Finished Aug 04 05:11:15 PM PDT 24
Peak memory 199792 kb
Host smart-2e15c4d8-9b5b-410c-a702-f57f81499339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780721938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3780721938
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1706097270
Short name T642
Test name
Test status
Simulation time 65175241535 ps
CPU time 31.84 seconds
Started Aug 04 05:10:26 PM PDT 24
Finished Aug 04 05:10:58 PM PDT 24
Peak memory 199824 kb
Host smart-fc27f1ab-7f65-4b1d-b964-ce2df2d0a6e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706097270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1706097270
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.81174253
Short name T640
Test name
Test status
Simulation time 87352853679 ps
CPU time 382.7 seconds
Started Aug 04 05:10:26 PM PDT 24
Finished Aug 04 05:16:49 PM PDT 24
Peak memory 199820 kb
Host smart-67b391d8-ef56-4498-a325-40a424ec51e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81174253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.81174253
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.87150205
Short name T735
Test name
Test status
Simulation time 5363869591 ps
CPU time 5.25 seconds
Started Aug 04 05:10:26 PM PDT 24
Finished Aug 04 05:10:31 PM PDT 24
Peak memory 198372 kb
Host smart-0a8bcc81-3188-404e-b7cc-942d2b6a9a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87150205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.87150205
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2296196617
Short name T308
Test name
Test status
Simulation time 598350621144 ps
CPU time 54.51 seconds
Started Aug 04 05:10:26 PM PDT 24
Finished Aug 04 05:11:21 PM PDT 24
Peak memory 208212 kb
Host smart-7831ef92-5f13-4334-843b-8f1060a28146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296196617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2296196617
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2890774120
Short name T772
Test name
Test status
Simulation time 13890371140 ps
CPU time 332.52 seconds
Started Aug 04 05:10:27 PM PDT 24
Finished Aug 04 05:15:59 PM PDT 24
Peak memory 199808 kb
Host smart-b58d2a43-a34a-4642-9f9e-5239e8ff167c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890774120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2890774120
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.3474029764
Short name T1148
Test name
Test status
Simulation time 6726297018 ps
CPU time 31.95 seconds
Started Aug 04 05:10:23 PM PDT 24
Finished Aug 04 05:10:55 PM PDT 24
Peak memory 198068 kb
Host smart-e049a90e-a316-47ff-aa10-ccaf607c4cf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3474029764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3474029764
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.92361398
Short name T166
Test name
Test status
Simulation time 22309365770 ps
CPU time 10.94 seconds
Started Aug 04 05:10:28 PM PDT 24
Finished Aug 04 05:10:39 PM PDT 24
Peak memory 199796 kb
Host smart-069e4292-963c-4967-a85f-f56aae24f55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92361398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.92361398
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.416787538
Short name T514
Test name
Test status
Simulation time 28600546248 ps
CPU time 23.56 seconds
Started Aug 04 05:10:26 PM PDT 24
Finished Aug 04 05:10:50 PM PDT 24
Peak memory 195948 kb
Host smart-271ce84d-852d-4525-8dd8-d468677e2f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416787538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.416787538
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.1967435096
Short name T404
Test name
Test status
Simulation time 131252135 ps
CPU time 0.84 seconds
Started Aug 04 05:10:24 PM PDT 24
Finished Aug 04 05:10:25 PM PDT 24
Peak memory 196980 kb
Host smart-d5b56b40-c2d6-4e29-a3af-364a1cdbb8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967435096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1967435096
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.258547863
Short name T874
Test name
Test status
Simulation time 183992464048 ps
CPU time 190.65 seconds
Started Aug 04 05:10:26 PM PDT 24
Finished Aug 04 05:13:37 PM PDT 24
Peak memory 199924 kb
Host smart-1a2ea7b0-eeaf-45e2-a126-57603d0383dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258547863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.258547863
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1381692569
Short name T194
Test name
Test status
Simulation time 41543540997 ps
CPU time 675.41 seconds
Started Aug 04 05:10:26 PM PDT 24
Finished Aug 04 05:21:42 PM PDT 24
Peak memory 216480 kb
Host smart-4a8ad1a5-38ef-49b5-863c-294d5e3d10ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381692569 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1381692569
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2757583474
Short name T312
Test name
Test status
Simulation time 7342424385 ps
CPU time 8.18 seconds
Started Aug 04 05:10:26 PM PDT 24
Finished Aug 04 05:10:34 PM PDT 24
Peak memory 199816 kb
Host smart-ee53104d-cc39-4614-9625-ca2a45db55cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757583474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2757583474
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.796420051
Short name T580
Test name
Test status
Simulation time 20885044070 ps
CPU time 17.5 seconds
Started Aug 04 05:10:25 PM PDT 24
Finished Aug 04 05:10:42 PM PDT 24
Peak memory 199888 kb
Host smart-d4b7d920-b1e5-4b28-a898-83b81f0057ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796420051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.796420051
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2185318661
Short name T1113
Test name
Test status
Simulation time 42941764 ps
CPU time 0.61 seconds
Started Aug 04 05:10:36 PM PDT 24
Finished Aug 04 05:10:36 PM PDT 24
Peak memory 195484 kb
Host smart-b829f111-a2b6-47c2-86e8-bf5c1d56a4ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185318661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2185318661
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2266957016
Short name T1109
Test name
Test status
Simulation time 30947773418 ps
CPU time 41.52 seconds
Started Aug 04 05:10:31 PM PDT 24
Finished Aug 04 05:11:12 PM PDT 24
Peak memory 199888 kb
Host smart-5246e0f2-64c4-4885-9609-97ca85f7afc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266957016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2266957016
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.531724563
Short name T1125
Test name
Test status
Simulation time 105637529240 ps
CPU time 76.46 seconds
Started Aug 04 05:10:29 PM PDT 24
Finished Aug 04 05:11:46 PM PDT 24
Peak memory 199868 kb
Host smart-1d757e18-37fd-46ab-9336-96265d4e2872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531724563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.531724563
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.123401375
Short name T1008
Test name
Test status
Simulation time 147622225817 ps
CPU time 70.29 seconds
Started Aug 04 05:10:31 PM PDT 24
Finished Aug 04 05:11:41 PM PDT 24
Peak memory 199872 kb
Host smart-fcaef9fe-4d1d-464f-9d1b-ff0a5fa64e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123401375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.123401375
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3365931414
Short name T900
Test name
Test status
Simulation time 213430161992 ps
CPU time 330.61 seconds
Started Aug 04 05:10:30 PM PDT 24
Finished Aug 04 05:16:01 PM PDT 24
Peak memory 199804 kb
Host smart-234b9538-997c-437e-88f3-e2079159e82e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365931414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3365931414
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.292640511
Short name T883
Test name
Test status
Simulation time 90189120164 ps
CPU time 768.51 seconds
Started Aug 04 05:10:41 PM PDT 24
Finished Aug 04 05:23:30 PM PDT 24
Peak memory 199932 kb
Host smart-0ab167cf-4b51-447d-8d48-8117ffaf38c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=292640511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.292640511
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.779210019
Short name T424
Test name
Test status
Simulation time 4183667827 ps
CPU time 2.09 seconds
Started Aug 04 05:10:41 PM PDT 24
Finished Aug 04 05:10:43 PM PDT 24
Peak memory 198316 kb
Host smart-6d950b0e-5137-40b2-8a26-a9e62b20c47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779210019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.779210019
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.3953033102
Short name T440
Test name
Test status
Simulation time 15573320838 ps
CPU time 24.86 seconds
Started Aug 04 05:10:37 PM PDT 24
Finished Aug 04 05:11:02 PM PDT 24
Peak memory 198600 kb
Host smart-b1ce3966-96bc-4c4f-a400-67c5918847a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953033102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3953033102
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.81986473
Short name T109
Test name
Test status
Simulation time 6340586271 ps
CPU time 136.47 seconds
Started Aug 04 05:10:35 PM PDT 24
Finished Aug 04 05:12:51 PM PDT 24
Peak memory 199868 kb
Host smart-22a09d9a-ebd9-42a0-a25e-a74ceaf8c465
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81986473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.81986473
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2194573152
Short name T685
Test name
Test status
Simulation time 4070183494 ps
CPU time 3.21 seconds
Started Aug 04 05:10:29 PM PDT 24
Finished Aug 04 05:10:32 PM PDT 24
Peak memory 198392 kb
Host smart-e65e10a5-8a89-4c90-bea1-870d356fa7fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2194573152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2194573152
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.896067156
Short name T150
Test name
Test status
Simulation time 129879556086 ps
CPU time 63.02 seconds
Started Aug 04 05:10:41 PM PDT 24
Finished Aug 04 05:11:44 PM PDT 24
Peak memory 199932 kb
Host smart-579aee1d-9905-4b29-90d3-d7f8e25960ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896067156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.896067156
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2105606942
Short name T1068
Test name
Test status
Simulation time 512583736 ps
CPU time 1.49 seconds
Started Aug 04 05:10:31 PM PDT 24
Finished Aug 04 05:10:33 PM PDT 24
Peak memory 195376 kb
Host smart-434e1a5b-a4f6-4345-b34c-f4f8c0d02e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105606942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2105606942
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3682105159
Short name T1130
Test name
Test status
Simulation time 733080130 ps
CPU time 2.02 seconds
Started Aug 04 05:10:30 PM PDT 24
Finished Aug 04 05:10:32 PM PDT 24
Peak memory 199148 kb
Host smart-9e579249-65f7-4c65-9ae7-7fba5b7392d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682105159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3682105159
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2543958809
Short name T925
Test name
Test status
Simulation time 366350055588 ps
CPU time 44.32 seconds
Started Aug 04 05:10:41 PM PDT 24
Finished Aug 04 05:11:25 PM PDT 24
Peak memory 199852 kb
Host smart-f9889ce0-a27a-46f1-baf2-f883ec549651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543958809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2543958809
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.359302374
Short name T896
Test name
Test status
Simulation time 55591178488 ps
CPU time 148.93 seconds
Started Aug 04 05:10:33 PM PDT 24
Finished Aug 04 05:13:03 PM PDT 24
Peak memory 208184 kb
Host smart-77d751d7-1a3b-4604-8b09-1668827fb181
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359302374 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.359302374
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.401250506
Short name T631
Test name
Test status
Simulation time 6755660778 ps
CPU time 28.16 seconds
Started Aug 04 05:10:34 PM PDT 24
Finished Aug 04 05:11:03 PM PDT 24
Peak memory 199836 kb
Host smart-ab2ac186-7859-477d-ab26-6240a2069861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401250506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.401250506
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2856880482
Short name T966
Test name
Test status
Simulation time 108802271632 ps
CPU time 181.74 seconds
Started Aug 04 05:10:29 PM PDT 24
Finished Aug 04 05:13:31 PM PDT 24
Peak memory 199248 kb
Host smart-bac96843-e984-4554-875b-4b9c947f32b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856880482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2856880482
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.277864384
Short name T1019
Test name
Test status
Simulation time 14317221 ps
CPU time 0.57 seconds
Started Aug 04 05:10:38 PM PDT 24
Finished Aug 04 05:10:39 PM PDT 24
Peak memory 195204 kb
Host smart-91a0735c-e88a-43b9-a24b-2205b2c4ecfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277864384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.277864384
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.391040471
Short name T717
Test name
Test status
Simulation time 109338201533 ps
CPU time 44.7 seconds
Started Aug 04 05:10:40 PM PDT 24
Finished Aug 04 05:11:25 PM PDT 24
Peak memory 199884 kb
Host smart-15dc8128-c46a-4943-9ca8-9780f8e21e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391040471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.391040471
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.480737551
Short name T951
Test name
Test status
Simulation time 16452314962 ps
CPU time 25.43 seconds
Started Aug 04 05:10:41 PM PDT 24
Finished Aug 04 05:11:07 PM PDT 24
Peak memory 199932 kb
Host smart-2a919fa7-6ec5-44db-9df4-a1df9d264ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480737551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.480737551
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1292258070
Short name T370
Test name
Test status
Simulation time 20930826245 ps
CPU time 7.68 seconds
Started Aug 04 05:10:35 PM PDT 24
Finished Aug 04 05:10:43 PM PDT 24
Peak memory 198900 kb
Host smart-5c814198-193b-4d6b-8eac-d30b185b32bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292258070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1292258070
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1294119990
Short name T1031
Test name
Test status
Simulation time 25878134860 ps
CPU time 7.15 seconds
Started Aug 04 05:10:39 PM PDT 24
Finished Aug 04 05:10:47 PM PDT 24
Peak memory 199536 kb
Host smart-c0a1ba5d-5d49-4447-b8c7-a5682214becd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294119990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1294119990
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2353103989
Short name T310
Test name
Test status
Simulation time 114796641441 ps
CPU time 614.28 seconds
Started Aug 04 05:10:38 PM PDT 24
Finished Aug 04 05:20:53 PM PDT 24
Peak memory 199864 kb
Host smart-75cb2a08-6fc1-40b0-8da3-85a8d3964d94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2353103989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2353103989
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3726011621
Short name T437
Test name
Test status
Simulation time 1224444342 ps
CPU time 2.91 seconds
Started Aug 04 05:10:39 PM PDT 24
Finished Aug 04 05:10:42 PM PDT 24
Peak memory 197208 kb
Host smart-ced13565-37db-4cd2-a3a3-4567829c7b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726011621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3726011621
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1616171533
Short name T298
Test name
Test status
Simulation time 93426983455 ps
CPU time 121.46 seconds
Started Aug 04 05:10:39 PM PDT 24
Finished Aug 04 05:12:41 PM PDT 24
Peak memory 207960 kb
Host smart-9748db37-6348-438d-9fea-28d891b3b14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616171533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1616171533
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3434371258
Short name T429
Test name
Test status
Simulation time 11818125369 ps
CPU time 174.11 seconds
Started Aug 04 05:10:38 PM PDT 24
Finished Aug 04 05:13:32 PM PDT 24
Peak memory 199800 kb
Host smart-1f06deef-3002-44bd-8c1c-a6de9544a67c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3434371258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3434371258
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1899331968
Short name T689
Test name
Test status
Simulation time 3344670836 ps
CPU time 12.52 seconds
Started Aug 04 05:10:35 PM PDT 24
Finished Aug 04 05:10:48 PM PDT 24
Peak memory 198936 kb
Host smart-09f9405b-6d32-499a-9f9b-823f1905056a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1899331968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1899331968
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.808133594
Short name T1102
Test name
Test status
Simulation time 18377310110 ps
CPU time 35.2 seconds
Started Aug 04 05:10:38 PM PDT 24
Finished Aug 04 05:11:13 PM PDT 24
Peak memory 199904 kb
Host smart-16472bcb-d2c4-4888-8acd-6512f62197eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808133594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.808133594
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2517999444
Short name T808
Test name
Test status
Simulation time 41058449116 ps
CPU time 39.75 seconds
Started Aug 04 05:10:40 PM PDT 24
Finished Aug 04 05:11:20 PM PDT 24
Peak memory 195672 kb
Host smart-c3d8eb6e-2e28-4b9e-93fc-d5709a6e0a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517999444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2517999444
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.584378827
Short name T915
Test name
Test status
Simulation time 6284664505 ps
CPU time 8.33 seconds
Started Aug 04 05:10:34 PM PDT 24
Finished Aug 04 05:10:43 PM PDT 24
Peak memory 199724 kb
Host smart-d6d4aac1-a813-4703-87a8-3189f3081bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584378827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.584378827
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2641948217
Short name T928
Test name
Test status
Simulation time 21504757261 ps
CPU time 11.13 seconds
Started Aug 04 05:10:38 PM PDT 24
Finished Aug 04 05:10:50 PM PDT 24
Peak memory 200144 kb
Host smart-6fa4ddf5-8567-4593-ae9e-ec495632d417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641948217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2641948217
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.18167954
Short name T677
Test name
Test status
Simulation time 42265277524 ps
CPU time 374.69 seconds
Started Aug 04 05:10:39 PM PDT 24
Finished Aug 04 05:16:53 PM PDT 24
Peak memory 216540 kb
Host smart-2861bb67-9edc-4f21-b418-fd3b61f4c2e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18167954 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.18167954
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1250734559
Short name T282
Test name
Test status
Simulation time 6571925864 ps
CPU time 18.59 seconds
Started Aug 04 05:10:40 PM PDT 24
Finished Aug 04 05:10:58 PM PDT 24
Peak memory 199368 kb
Host smart-7ea9cc01-d500-452d-8163-d9769c045744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250734559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1250734559
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2319009761
Short name T815
Test name
Test status
Simulation time 38994936955 ps
CPU time 85.05 seconds
Started Aug 04 05:10:34 PM PDT 24
Finished Aug 04 05:11:59 PM PDT 24
Peak memory 199864 kb
Host smart-020a6ba9-0fc3-4bf2-86df-769a27c7dcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319009761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2319009761
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3237173846
Short name T980
Test name
Test status
Simulation time 12942528 ps
CPU time 0.54 seconds
Started Aug 04 05:06:09 PM PDT 24
Finished Aug 04 05:06:09 PM PDT 24
Peak memory 195240 kb
Host smart-b1f2022b-e2da-4790-aed6-8709ffeea62b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237173846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3237173846
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.177576245
Short name T413
Test name
Test status
Simulation time 31498536201 ps
CPU time 37.41 seconds
Started Aug 04 05:06:07 PM PDT 24
Finished Aug 04 05:06:44 PM PDT 24
Peak memory 199744 kb
Host smart-f5ab1a51-03e8-4af6-9829-73922632c962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177576245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.177576245
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.4077813928
Short name T671
Test name
Test status
Simulation time 16580525576 ps
CPU time 31.43 seconds
Started Aug 04 05:06:07 PM PDT 24
Finished Aug 04 05:06:38 PM PDT 24
Peak memory 199848 kb
Host smart-d0750dd4-78ef-4050-a856-623b63bf3852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077813928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.4077813928
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.883649291
Short name T720
Test name
Test status
Simulation time 166869981180 ps
CPU time 265.26 seconds
Started Aug 04 05:06:14 PM PDT 24
Finished Aug 04 05:10:39 PM PDT 24
Peak memory 199792 kb
Host smart-d7b320da-e895-4df0-8717-ffa91fcc0b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883649291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.883649291
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2633898308
Short name T942
Test name
Test status
Simulation time 38577075264 ps
CPU time 51.91 seconds
Started Aug 04 05:06:12 PM PDT 24
Finished Aug 04 05:07:04 PM PDT 24
Peak memory 199832 kb
Host smart-df75bae9-311c-4402-957d-64f8d04a4856
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2633898308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2633898308
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.331002302
Short name T359
Test name
Test status
Simulation time 9028529512 ps
CPU time 5.19 seconds
Started Aug 04 05:06:09 PM PDT 24
Finished Aug 04 05:06:15 PM PDT 24
Peak memory 198700 kb
Host smart-639e4cc4-be60-40bb-86d3-ce27180ae354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331002302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.331002302
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3822771562
Short name T809
Test name
Test status
Simulation time 87122959760 ps
CPU time 273.92 seconds
Started Aug 04 05:06:10 PM PDT 24
Finished Aug 04 05:10:44 PM PDT 24
Peak memory 208028 kb
Host smart-459689b6-53eb-4c10-8b25-3d76fb9a6c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822771562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3822771562
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2463133871
Short name T754
Test name
Test status
Simulation time 19977502484 ps
CPU time 1018.19 seconds
Started Aug 04 05:06:16 PM PDT 24
Finished Aug 04 05:23:14 PM PDT 24
Peak memory 199820 kb
Host smart-bdd8cd27-c58d-405d-8e69-a7a6f3296329
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2463133871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2463133871
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3554205812
Short name T526
Test name
Test status
Simulation time 5793670957 ps
CPU time 8.17 seconds
Started Aug 04 05:06:07 PM PDT 24
Finished Aug 04 05:06:15 PM PDT 24
Peak memory 198948 kb
Host smart-3c186c16-54b2-4f1b-a8e8-8c597e6788fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3554205812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3554205812
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.2516243534
Short name T534
Test name
Test status
Simulation time 155055690190 ps
CPU time 270.44 seconds
Started Aug 04 05:06:11 PM PDT 24
Finished Aug 04 05:10:42 PM PDT 24
Peak memory 199928 kb
Host smart-fee62a40-16d6-44e5-926a-d8b07fdcb02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516243534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2516243534
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1503698371
Short name T997
Test name
Test status
Simulation time 1554404270 ps
CPU time 3.11 seconds
Started Aug 04 05:06:09 PM PDT 24
Finished Aug 04 05:06:12 PM PDT 24
Peak memory 195332 kb
Host smart-8f06b5d7-4087-45ce-b07e-f261a1751589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503698371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1503698371
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.43630301
Short name T1176
Test name
Test status
Simulation time 635705719 ps
CPU time 1.87 seconds
Started Aug 04 05:06:05 PM PDT 24
Finished Aug 04 05:06:07 PM PDT 24
Peak memory 199640 kb
Host smart-68d3d134-95ee-45d4-b1a7-54224b615a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43630301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.43630301
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3626488046
Short name T473
Test name
Test status
Simulation time 115095633219 ps
CPU time 50.14 seconds
Started Aug 04 05:06:16 PM PDT 24
Finished Aug 04 05:07:06 PM PDT 24
Peak memory 199816 kb
Host smart-c5db1c7e-30b4-4ff3-b6fe-66d29501d527
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626488046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3626488046
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3751926211
Short name T304
Test name
Test status
Simulation time 20740106040 ps
CPU time 178.61 seconds
Started Aug 04 05:06:08 PM PDT 24
Finished Aug 04 05:09:07 PM PDT 24
Peak memory 215732 kb
Host smart-5450912b-6fec-4500-af08-8ff4ff74204c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751926211 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3751926211
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3677664446
Short name T1173
Test name
Test status
Simulation time 1738924743 ps
CPU time 1.94 seconds
Started Aug 04 05:06:12 PM PDT 24
Finished Aug 04 05:06:14 PM PDT 24
Peak memory 198644 kb
Host smart-d3468c54-4cbd-454d-8583-177dd27e81be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677664446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3677664446
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.208223934
Short name T1152
Test name
Test status
Simulation time 61897136269 ps
CPU time 61.22 seconds
Started Aug 04 05:06:06 PM PDT 24
Finished Aug 04 05:07:07 PM PDT 24
Peak memory 199884 kb
Host smart-a30d85e0-b321-410b-9edb-be1146b266dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208223934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.208223934
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1313491082
Short name T335
Test name
Test status
Simulation time 175911172089 ps
CPU time 32.24 seconds
Started Aug 04 05:10:39 PM PDT 24
Finished Aug 04 05:11:11 PM PDT 24
Peak memory 199864 kb
Host smart-c7961fdf-1bb6-48eb-9eb5-6603229f71f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313491082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1313491082
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.626949756
Short name T906
Test name
Test status
Simulation time 61076467501 ps
CPU time 346.83 seconds
Started Aug 04 05:10:42 PM PDT 24
Finished Aug 04 05:16:29 PM PDT 24
Peak memory 216284 kb
Host smart-06663d48-d736-46fe-b13e-88a5a949c3af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626949756 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.626949756
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.553109028
Short name T1007
Test name
Test status
Simulation time 19995706076 ps
CPU time 316.38 seconds
Started Aug 04 05:10:43 PM PDT 24
Finished Aug 04 05:16:00 PM PDT 24
Peak memory 216196 kb
Host smart-71a6a7fe-d032-49b6-bd61-122f6e866e02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553109028 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.553109028
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.961482748
Short name T258
Test name
Test status
Simulation time 37772048799 ps
CPU time 23.88 seconds
Started Aug 04 05:10:44 PM PDT 24
Finished Aug 04 05:11:08 PM PDT 24
Peak memory 199760 kb
Host smart-5f8e39de-533f-4d90-b28f-b65acbde0f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961482748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.961482748
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.4019898506
Short name T783
Test name
Test status
Simulation time 74451294248 ps
CPU time 320.37 seconds
Started Aug 04 05:10:43 PM PDT 24
Finished Aug 04 05:16:03 PM PDT 24
Peak memory 215448 kb
Host smart-22342d7b-ef60-4bc0-88d3-3e5a48b1cb61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019898506 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.4019898506
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1278924812
Short name T956
Test name
Test status
Simulation time 77734091181 ps
CPU time 664.85 seconds
Started Aug 04 05:10:43 PM PDT 24
Finished Aug 04 05:21:48 PM PDT 24
Peak memory 224752 kb
Host smart-1e5f9b12-5f42-4217-b1cb-5d4593213244
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278924812 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1278924812
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2896183396
Short name T212
Test name
Test status
Simulation time 33722423697 ps
CPU time 13.47 seconds
Started Aug 04 05:10:44 PM PDT 24
Finished Aug 04 05:10:57 PM PDT 24
Peak memory 199584 kb
Host smart-01202913-c0c2-49b7-a416-208badd69505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896183396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2896183396
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.331027592
Short name T159
Test name
Test status
Simulation time 44687676222 ps
CPU time 134.74 seconds
Started Aug 04 05:10:42 PM PDT 24
Finished Aug 04 05:12:56 PM PDT 24
Peak memory 208148 kb
Host smart-0b996e62-8569-4fa1-976c-5e2f24562dd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331027592 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.331027592
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3708410188
Short name T1114
Test name
Test status
Simulation time 158099826738 ps
CPU time 251.53 seconds
Started Aug 04 05:10:44 PM PDT 24
Finished Aug 04 05:14:56 PM PDT 24
Peak memory 199808 kb
Host smart-2945854b-6ab0-4555-a0a5-d7139f12e76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708410188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3708410188
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.919037674
Short name T788
Test name
Test status
Simulation time 78711119340 ps
CPU time 104.83 seconds
Started Aug 04 05:10:44 PM PDT 24
Finished Aug 04 05:12:29 PM PDT 24
Peak memory 199812 kb
Host smart-705ad3b4-269c-4a46-9bbc-4c100fd9b184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919037674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.919037674
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.65410971
Short name T204
Test name
Test status
Simulation time 187793393224 ps
CPU time 99.62 seconds
Started Aug 04 05:10:44 PM PDT 24
Finished Aug 04 05:12:24 PM PDT 24
Peak memory 199880 kb
Host smart-af2394b1-faec-4f86-af30-d58d410d1f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65410971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.65410971
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.606624274
Short name T1119
Test name
Test status
Simulation time 126523999974 ps
CPU time 468.87 seconds
Started Aug 04 05:10:42 PM PDT 24
Finished Aug 04 05:18:32 PM PDT 24
Peak memory 211032 kb
Host smart-aa4dc6b2-cc6d-43a8-af6b-d54fafb21cfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606624274 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.606624274
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.102525558
Short name T1079
Test name
Test status
Simulation time 76907707903 ps
CPU time 60.9 seconds
Started Aug 04 05:10:44 PM PDT 24
Finished Aug 04 05:11:45 PM PDT 24
Peak memory 199748 kb
Host smart-1433039e-59af-4fdb-854e-43b6f2dabe53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102525558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.102525558
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3367760505
Short name T959
Test name
Test status
Simulation time 247877951739 ps
CPU time 1422.64 seconds
Started Aug 04 05:10:48 PM PDT 24
Finished Aug 04 05:34:31 PM PDT 24
Peak memory 224708 kb
Host smart-bab4fd99-142e-4ad6-86c5-b9d55d2321ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367760505 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3367760505
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3940085248
Short name T186
Test name
Test status
Simulation time 44222575145 ps
CPU time 68.89 seconds
Started Aug 04 05:10:46 PM PDT 24
Finished Aug 04 05:11:55 PM PDT 24
Peak memory 199580 kb
Host smart-c8753f00-bed7-4a47-ad65-e083bfab0daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940085248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3940085248
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.47047521
Short name T770
Test name
Test status
Simulation time 79543898 ps
CPU time 0.54 seconds
Started Aug 04 05:06:19 PM PDT 24
Finished Aug 04 05:06:20 PM PDT 24
Peak memory 195276 kb
Host smart-3b69b28e-2081-4b28-bdfb-b27ea5e92ac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47047521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.47047521
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2330459897
Short name T336
Test name
Test status
Simulation time 52955449708 ps
CPU time 16.28 seconds
Started Aug 04 05:06:14 PM PDT 24
Finished Aug 04 05:06:30 PM PDT 24
Peak memory 199836 kb
Host smart-6f66f038-288f-4ece-9d28-eafc94094f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330459897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2330459897
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.325893416
Short name T806
Test name
Test status
Simulation time 82090915214 ps
CPU time 40.84 seconds
Started Aug 04 05:06:17 PM PDT 24
Finished Aug 04 05:06:58 PM PDT 24
Peak memory 199856 kb
Host smart-9e605b2d-8bf3-4314-add8-0c9bc060f17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325893416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.325893416
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1912317721
Short name T196
Test name
Test status
Simulation time 228019639227 ps
CPU time 243.6 seconds
Started Aug 04 05:06:15 PM PDT 24
Finished Aug 04 05:10:18 PM PDT 24
Peak memory 199852 kb
Host smart-82294282-dcd8-4eff-ab44-581655314007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912317721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1912317721
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1102825156
Short name T262
Test name
Test status
Simulation time 147869223875 ps
CPU time 97.78 seconds
Started Aug 04 05:06:16 PM PDT 24
Finished Aug 04 05:07:54 PM PDT 24
Peak memory 199524 kb
Host smart-d2dad7c3-3de8-4c34-958a-e06fed726055
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102825156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1102825156
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.4118812911
Short name T658
Test name
Test status
Simulation time 31577372809 ps
CPU time 152.5 seconds
Started Aug 04 05:06:14 PM PDT 24
Finished Aug 04 05:08:46 PM PDT 24
Peak memory 199772 kb
Host smart-f632b221-7a12-4acf-9007-c3533d71f3eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4118812911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.4118812911
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2458443513
Short name T1023
Test name
Test status
Simulation time 7189855410 ps
CPU time 4.72 seconds
Started Aug 04 05:06:16 PM PDT 24
Finished Aug 04 05:06:21 PM PDT 24
Peak memory 199784 kb
Host smart-c00cef63-452d-4992-ae94-0917e5f9d5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458443513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2458443513
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.4074499589
Short name T823
Test name
Test status
Simulation time 8858438992 ps
CPU time 14.25 seconds
Started Aug 04 05:06:13 PM PDT 24
Finished Aug 04 05:06:27 PM PDT 24
Peak memory 198588 kb
Host smart-1657125c-487d-4b06-89ad-227471932d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074499589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.4074499589
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.2471443420
Short name T388
Test name
Test status
Simulation time 11261176070 ps
CPU time 174.37 seconds
Started Aug 04 05:06:14 PM PDT 24
Finished Aug 04 05:09:09 PM PDT 24
Peak memory 199820 kb
Host smart-98474f1e-83b6-4aa5-96ca-7da5accd499d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2471443420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2471443420
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.4140632328
Short name T491
Test name
Test status
Simulation time 6127798769 ps
CPU time 8.72 seconds
Started Aug 04 05:06:13 PM PDT 24
Finished Aug 04 05:06:22 PM PDT 24
Peak memory 198064 kb
Host smart-aba7b9b2-c8cf-45a5-9c76-09394f3f7bef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4140632328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.4140632328
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.738929708
Short name T564
Test name
Test status
Simulation time 88490497122 ps
CPU time 42.21 seconds
Started Aug 04 05:06:17 PM PDT 24
Finished Aug 04 05:06:59 PM PDT 24
Peak memory 199888 kb
Host smart-bc9f79e3-0cbc-48d6-9f10-da1efe15e959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738929708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.738929708
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2506172338
Short name T969
Test name
Test status
Simulation time 42551074364 ps
CPU time 55.88 seconds
Started Aug 04 05:06:15 PM PDT 24
Finished Aug 04 05:07:11 PM PDT 24
Peak memory 195880 kb
Host smart-c0b7e876-1403-48f4-9403-2f926a95f7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506172338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2506172338
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1361489615
Short name T306
Test name
Test status
Simulation time 690584940 ps
CPU time 2.12 seconds
Started Aug 04 05:06:11 PM PDT 24
Finished Aug 04 05:06:13 PM PDT 24
Peak memory 199280 kb
Host smart-15faed98-48f1-4ac1-9187-78b448b3635f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361489615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1361489615
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.1481697609
Short name T887
Test name
Test status
Simulation time 140131297332 ps
CPU time 511.24 seconds
Started Aug 04 05:06:14 PM PDT 24
Finished Aug 04 05:14:45 PM PDT 24
Peak memory 199756 kb
Host smart-0c6210a5-c1a2-4aa7-86c4-f2948b491ed4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481697609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1481697609
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1231635143
Short name T501
Test name
Test status
Simulation time 22175695969 ps
CPU time 52.2 seconds
Started Aug 04 05:06:14 PM PDT 24
Finished Aug 04 05:07:07 PM PDT 24
Peak memory 208152 kb
Host smart-144191e4-40df-4710-9741-ca66b9ec7bf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231635143 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1231635143
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2795574542
Short name T554
Test name
Test status
Simulation time 648377129 ps
CPU time 1.24 seconds
Started Aug 04 05:06:13 PM PDT 24
Finished Aug 04 05:06:14 PM PDT 24
Peak memory 198200 kb
Host smart-c61f2738-e3e9-4d72-b95f-abdbe0f18a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795574542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2795574542
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2485533928
Short name T965
Test name
Test status
Simulation time 28922380465 ps
CPU time 47.38 seconds
Started Aug 04 05:06:16 PM PDT 24
Finished Aug 04 05:07:03 PM PDT 24
Peak memory 199776 kb
Host smart-c14f3537-08b1-42b5-9593-0a83f895b19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485533928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2485533928
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3738059044
Short name T871
Test name
Test status
Simulation time 30952444554 ps
CPU time 26.71 seconds
Started Aug 04 05:10:48 PM PDT 24
Finished Aug 04 05:11:14 PM PDT 24
Peak memory 199880 kb
Host smart-7ffa4ec6-bd41-436e-b137-30085fc4b342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738059044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3738059044
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.108896306
Short name T115
Test name
Test status
Simulation time 27854084240 ps
CPU time 292.51 seconds
Started Aug 04 05:10:48 PM PDT 24
Finished Aug 04 05:15:41 PM PDT 24
Peak memory 215336 kb
Host smart-c2995d5c-09d5-4dad-aeaf-7874fb71660e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108896306 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.108896306
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1118522464
Short name T713
Test name
Test status
Simulation time 42921566059 ps
CPU time 14 seconds
Started Aug 04 05:10:45 PM PDT 24
Finished Aug 04 05:11:00 PM PDT 24
Peak memory 199104 kb
Host smart-3970ac57-e06d-4622-a415-41e566f084f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118522464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1118522464
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.709650763
Short name T319
Test name
Test status
Simulation time 315041864930 ps
CPU time 327.27 seconds
Started Aug 04 05:10:47 PM PDT 24
Finished Aug 04 05:16:15 PM PDT 24
Peak memory 216552 kb
Host smart-c2ca4d0d-8cee-4c48-bdea-dddc96f912d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709650763 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.709650763
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.448435213
Short name T884
Test name
Test status
Simulation time 40515649020 ps
CPU time 20.94 seconds
Started Aug 04 05:10:47 PM PDT 24
Finished Aug 04 05:11:08 PM PDT 24
Peak memory 199812 kb
Host smart-5c933893-9ed8-4cf0-9912-48fa3054d11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448435213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.448435213
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.305396236
Short name T885
Test name
Test status
Simulation time 93163596314 ps
CPU time 380.42 seconds
Started Aug 04 05:10:48 PM PDT 24
Finished Aug 04 05:17:09 PM PDT 24
Peak memory 216436 kb
Host smart-9a25fc6c-80e4-40ec-aff7-69116350c886
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305396236 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.305396236
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2357130634
Short name T462
Test name
Test status
Simulation time 75884993532 ps
CPU time 25.8 seconds
Started Aug 04 05:10:48 PM PDT 24
Finished Aug 04 05:11:14 PM PDT 24
Peak memory 198524 kb
Host smart-18049262-5dd2-4ac9-97cd-5d777fed502f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357130634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2357130634
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.466362076
Short name T628
Test name
Test status
Simulation time 42371251994 ps
CPU time 863.4 seconds
Started Aug 04 05:10:47 PM PDT 24
Finished Aug 04 05:25:11 PM PDT 24
Peak memory 209196 kb
Host smart-22be7e08-7c91-4d26-bb20-64cd9d9ee856
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466362076 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.466362076
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3679560474
Short name T222
Test name
Test status
Simulation time 72221632326 ps
CPU time 34.39 seconds
Started Aug 04 05:10:49 PM PDT 24
Finished Aug 04 05:11:23 PM PDT 24
Peak memory 199856 kb
Host smart-1e4ce444-c620-4f4f-ac22-9c689a6eea37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679560474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3679560474
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1298737938
Short name T672
Test name
Test status
Simulation time 15116970108 ps
CPU time 245.92 seconds
Started Aug 04 05:10:46 PM PDT 24
Finished Aug 04 05:14:52 PM PDT 24
Peak memory 215740 kb
Host smart-2fcb9a74-1d2a-4fa7-b8c3-cf1381fa6911
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298737938 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1298737938
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3840482794
Short name T613
Test name
Test status
Simulation time 17945598097 ps
CPU time 9.26 seconds
Started Aug 04 05:10:47 PM PDT 24
Finished Aug 04 05:10:56 PM PDT 24
Peak memory 199816 kb
Host smart-25db2531-b1e9-49bb-9de1-ebb19b64f684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840482794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3840482794
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3674978662
Short name T879
Test name
Test status
Simulation time 147192043054 ps
CPU time 1243.53 seconds
Started Aug 04 05:10:46 PM PDT 24
Finished Aug 04 05:31:30 PM PDT 24
Peak memory 228024 kb
Host smart-0fe7f6ef-d0b8-4c08-a2ac-b6441480930f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674978662 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3674978662
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1495941713
Short name T804
Test name
Test status
Simulation time 20257983820 ps
CPU time 29.83 seconds
Started Aug 04 05:10:48 PM PDT 24
Finished Aug 04 05:11:18 PM PDT 24
Peak memory 199532 kb
Host smart-efda8a75-31f4-4344-a7cb-d798ebbdea41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495941713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1495941713
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3080594968
Short name T339
Test name
Test status
Simulation time 120720944867 ps
CPU time 573 seconds
Started Aug 04 05:10:51 PM PDT 24
Finished Aug 04 05:20:25 PM PDT 24
Peak memory 216384 kb
Host smart-b006688b-851a-4052-a66d-9fd663efc5d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080594968 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3080594968
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.565718912
Short name T1071
Test name
Test status
Simulation time 193551419222 ps
CPU time 47.54 seconds
Started Aug 04 05:10:50 PM PDT 24
Finished Aug 04 05:11:37 PM PDT 24
Peak memory 199844 kb
Host smart-8bedb700-4d86-4ee7-a32e-f7c2672bfe21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565718912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.565718912
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.339013715
Short name T544
Test name
Test status
Simulation time 36107792921 ps
CPU time 451.71 seconds
Started Aug 04 05:10:50 PM PDT 24
Finished Aug 04 05:18:22 PM PDT 24
Peak memory 216496 kb
Host smart-3b7311e8-935b-476c-a0bb-aa95b73198a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339013715 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.339013715
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3733874544
Short name T214
Test name
Test status
Simulation time 33689562293 ps
CPU time 51.86 seconds
Started Aug 04 05:10:51 PM PDT 24
Finished Aug 04 05:11:43 PM PDT 24
Peak memory 199744 kb
Host smart-7c299616-d8a9-4f67-a98b-ce7aa28d1f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733874544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3733874544
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2457073044
Short name T657
Test name
Test status
Simulation time 189098672659 ps
CPU time 924.38 seconds
Started Aug 04 05:10:50 PM PDT 24
Finished Aug 04 05:26:14 PM PDT 24
Peak memory 224756 kb
Host smart-aa490d60-7b65-4a46-87fe-5ca13f41251e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457073044 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2457073044
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.147819900
Short name T1097
Test name
Test status
Simulation time 54178710129 ps
CPU time 562.27 seconds
Started Aug 04 05:10:51 PM PDT 24
Finished Aug 04 05:20:13 PM PDT 24
Peak memory 216512 kb
Host smart-9ef03568-3e53-4ef3-bfbd-0f639c488a09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147819900 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.147819900
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1641610947
Short name T771
Test name
Test status
Simulation time 15215143 ps
CPU time 0.55 seconds
Started Aug 04 05:06:22 PM PDT 24
Finished Aug 04 05:06:23 PM PDT 24
Peak memory 195580 kb
Host smart-4fe664dd-ca9c-41f2-9d21-8860c3c7ac75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641610947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1641610947
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2891047370
Short name T662
Test name
Test status
Simulation time 42109782756 ps
CPU time 97.89 seconds
Started Aug 04 05:06:20 PM PDT 24
Finished Aug 04 05:07:58 PM PDT 24
Peak memory 199836 kb
Host smart-5e167de9-d481-49ac-a3f9-8e9a293419b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891047370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2891047370
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3266381806
Short name T123
Test name
Test status
Simulation time 25711623915 ps
CPU time 40.18 seconds
Started Aug 04 05:06:20 PM PDT 24
Finished Aug 04 05:07:00 PM PDT 24
Peak memory 199808 kb
Host smart-b8fdca4b-589d-40db-bb6f-77703bd794f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266381806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3266381806
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.4143243462
Short name T1041
Test name
Test status
Simulation time 132027478131 ps
CPU time 522.89 seconds
Started Aug 04 05:06:20 PM PDT 24
Finished Aug 04 05:15:03 PM PDT 24
Peak memory 199848 kb
Host smart-98203b0b-248e-4404-9294-c492f7993af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143243462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.4143243462
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.4216207090
Short name T38
Test name
Test status
Simulation time 54703085024 ps
CPU time 17.17 seconds
Started Aug 04 05:06:20 PM PDT 24
Finished Aug 04 05:06:37 PM PDT 24
Peak memory 199872 kb
Host smart-56027c61-885d-4e1c-99f0-943911e0b9fb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216207090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.4216207090
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.191703010
Short name T748
Test name
Test status
Simulation time 88047520138 ps
CPU time 806.67 seconds
Started Aug 04 05:06:22 PM PDT 24
Finished Aug 04 05:19:49 PM PDT 24
Peak memory 199776 kb
Host smart-65321c22-ae25-4731-8ad4-6546445c21fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=191703010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.191703010
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1904396635
Short name T385
Test name
Test status
Simulation time 2655186469 ps
CPU time 7.31 seconds
Started Aug 04 05:06:25 PM PDT 24
Finished Aug 04 05:06:32 PM PDT 24
Peak memory 199200 kb
Host smart-60bd52e8-29b1-4452-9ec4-a07c8a36566c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904396635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1904396635
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1165479951
Short name T7
Test name
Test status
Simulation time 103535393474 ps
CPU time 19.06 seconds
Started Aug 04 05:06:18 PM PDT 24
Finished Aug 04 05:06:37 PM PDT 24
Peak memory 207968 kb
Host smart-1f6d7c5f-e04f-4336-a435-75d8ffb9e688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165479951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1165479951
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.3923691787
Short name T245
Test name
Test status
Simulation time 11008377325 ps
CPU time 155.48 seconds
Started Aug 04 05:06:23 PM PDT 24
Finished Aug 04 05:08:59 PM PDT 24
Peak memory 199832 kb
Host smart-decb12e1-f04d-436f-b44f-9d397948330f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3923691787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3923691787
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3098603607
Short name T599
Test name
Test status
Simulation time 5922776598 ps
CPU time 5.85 seconds
Started Aug 04 05:06:19 PM PDT 24
Finished Aug 04 05:06:25 PM PDT 24
Peak memory 198024 kb
Host smart-b89b94d3-72f8-4368-9483-00453083a7a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3098603607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3098603607
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3821650963
Short name T587
Test name
Test status
Simulation time 148512093330 ps
CPU time 115.66 seconds
Started Aug 04 05:06:22 PM PDT 24
Finished Aug 04 05:08:18 PM PDT 24
Peak memory 199968 kb
Host smart-b39d5207-794d-4d82-b788-86881831418f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821650963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3821650963
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3460578059
Short name T913
Test name
Test status
Simulation time 35776809842 ps
CPU time 49.19 seconds
Started Aug 04 05:06:17 PM PDT 24
Finished Aug 04 05:07:07 PM PDT 24
Peak memory 195992 kb
Host smart-30125829-e1d3-4ab5-a342-0c383c6e9859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460578059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3460578059
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1034063703
Short name T1088
Test name
Test status
Simulation time 905701322 ps
CPU time 1.91 seconds
Started Aug 04 05:06:20 PM PDT 24
Finished Aug 04 05:06:22 PM PDT 24
Peak memory 199772 kb
Host smart-a624ab8d-97e5-4b06-837f-bd815b0ad252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034063703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1034063703
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2925739028
Short name T157
Test name
Test status
Simulation time 857424484371 ps
CPU time 169.59 seconds
Started Aug 04 05:06:23 PM PDT 24
Finished Aug 04 05:09:13 PM PDT 24
Peak memory 208100 kb
Host smart-041153c1-1a4f-4537-94aa-7b419621cf3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925739028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2925739028
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1746414552
Short name T417
Test name
Test status
Simulation time 1320396599 ps
CPU time 4.55 seconds
Started Aug 04 05:06:23 PM PDT 24
Finished Aug 04 05:06:28 PM PDT 24
Peak memory 199452 kb
Host smart-0dfcd14f-d118-464e-8db5-5d11c86f2431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746414552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1746414552
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2617150136
Short name T975
Test name
Test status
Simulation time 8501152051 ps
CPU time 9.7 seconds
Started Aug 04 05:06:19 PM PDT 24
Finished Aug 04 05:06:28 PM PDT 24
Peak memory 199880 kb
Host smart-e918011e-7ed9-48a5-bb4c-253a7c00a754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617150136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2617150136
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.3172648344
Short name T814
Test name
Test status
Simulation time 51785926200 ps
CPU time 596.64 seconds
Started Aug 04 05:10:51 PM PDT 24
Finished Aug 04 05:20:48 PM PDT 24
Peak memory 224708 kb
Host smart-76f4c2eb-07ef-40e0-b28c-b0324a8069c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172648344 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3172648344
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3377891874
Short name T890
Test name
Test status
Simulation time 10107548042 ps
CPU time 16.39 seconds
Started Aug 04 05:10:51 PM PDT 24
Finished Aug 04 05:11:08 PM PDT 24
Peak memory 199812 kb
Host smart-2b450178-bd5b-46c6-abc7-fef92a436a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377891874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3377891874
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3133403689
Short name T1128
Test name
Test status
Simulation time 96713072723 ps
CPU time 970.66 seconds
Started Aug 04 05:10:53 PM PDT 24
Finished Aug 04 05:27:04 PM PDT 24
Peak memory 216372 kb
Host smart-ac6ba04d-b1b6-4b4e-8e8b-c65b72b02cca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133403689 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3133403689
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2288234156
Short name T1175
Test name
Test status
Simulation time 125707137016 ps
CPU time 158.6 seconds
Started Aug 04 05:10:51 PM PDT 24
Finished Aug 04 05:13:30 PM PDT 24
Peak memory 199864 kb
Host smart-ad3cc036-a4a8-4917-bc60-5a6043349b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288234156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2288234156
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1326613714
Short name T31
Test name
Test status
Simulation time 79791883907 ps
CPU time 326.65 seconds
Started Aug 04 05:10:56 PM PDT 24
Finished Aug 04 05:16:23 PM PDT 24
Peak memory 216508 kb
Host smart-13709e84-1ed4-4520-9b06-746dc2ef2f8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326613714 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1326613714
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1976784198
Short name T562
Test name
Test status
Simulation time 132252967964 ps
CPU time 13.26 seconds
Started Aug 04 05:10:57 PM PDT 24
Finished Aug 04 05:11:10 PM PDT 24
Peak memory 199748 kb
Host smart-9b4f448b-630e-4d3c-8c04-1e6fc7ea3147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976784198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1976784198
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2426104489
Short name T1072
Test name
Test status
Simulation time 24024313818 ps
CPU time 14 seconds
Started Aug 04 05:10:54 PM PDT 24
Finished Aug 04 05:11:08 PM PDT 24
Peak memory 199848 kb
Host smart-0db74691-07b5-4ec4-a150-468faa08ce10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426104489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2426104489
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1604389753
Short name T1065
Test name
Test status
Simulation time 57347249338 ps
CPU time 697.38 seconds
Started Aug 04 05:10:55 PM PDT 24
Finished Aug 04 05:22:32 PM PDT 24
Peak memory 224708 kb
Host smart-1153f442-52f4-44bb-a898-ffb5dfa9b8bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604389753 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1604389753
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3325610449
Short name T1027
Test name
Test status
Simulation time 209024858942 ps
CPU time 136.73 seconds
Started Aug 04 05:10:54 PM PDT 24
Finished Aug 04 05:13:11 PM PDT 24
Peak memory 199840 kb
Host smart-d81b5da3-9003-4e0e-af90-5469507091c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325610449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3325610449
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.305506136
Short name T1075
Test name
Test status
Simulation time 248267186603 ps
CPU time 735.19 seconds
Started Aug 04 05:10:58 PM PDT 24
Finished Aug 04 05:23:13 PM PDT 24
Peak memory 224764 kb
Host smart-df8b076a-065d-4206-ace9-d12254295c86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305506136 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.305506136
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1934032035
Short name T1
Test name
Test status
Simulation time 196292898402 ps
CPU time 17.45 seconds
Started Aug 04 05:10:58 PM PDT 24
Finished Aug 04 05:11:16 PM PDT 24
Peak memory 199716 kb
Host smart-2dd17cff-2e70-4237-84d0-bb75774b178c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934032035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1934032035
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3748689095
Short name T453
Test name
Test status
Simulation time 31744856101 ps
CPU time 17.18 seconds
Started Aug 04 05:10:58 PM PDT 24
Finished Aug 04 05:11:16 PM PDT 24
Peak memory 199864 kb
Host smart-343bca1c-64c3-4340-811a-5bce8e093804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748689095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3748689095
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2182747600
Short name T103
Test name
Test status
Simulation time 102270282967 ps
CPU time 617.31 seconds
Started Aug 04 05:11:00 PM PDT 24
Finished Aug 04 05:21:17 PM PDT 24
Peak memory 216316 kb
Host smart-4b1c0f9a-1ff1-4229-9125-6d8af29be6b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182747600 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2182747600
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3928883476
Short name T124
Test name
Test status
Simulation time 5379551793 ps
CPU time 10.07 seconds
Started Aug 04 05:10:58 PM PDT 24
Finished Aug 04 05:11:08 PM PDT 24
Peak memory 199644 kb
Host smart-291e1f64-bb41-4e6b-acbb-d99371add041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928883476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3928883476
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1574410628
Short name T323
Test name
Test status
Simulation time 47148517804 ps
CPU time 565.1 seconds
Started Aug 04 05:11:03 PM PDT 24
Finished Aug 04 05:20:28 PM PDT 24
Peak memory 224756 kb
Host smart-3556dc18-91a8-4d20-8a15-efdb0031e128
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574410628 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1574410628
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2342461748
Short name T373
Test name
Test status
Simulation time 14986205 ps
CPU time 0.57 seconds
Started Aug 04 05:06:31 PM PDT 24
Finished Aug 04 05:06:32 PM PDT 24
Peak memory 195304 kb
Host smart-2d63ac71-4f08-4284-b161-c8188f352c54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342461748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2342461748
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.271990324
Short name T866
Test name
Test status
Simulation time 354988702819 ps
CPU time 74.68 seconds
Started Aug 04 05:06:24 PM PDT 24
Finished Aug 04 05:07:38 PM PDT 24
Peak memory 199740 kb
Host smart-9e239a09-5986-4828-8232-7671811e53f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271990324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.271990324
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2309941479
Short name T118
Test name
Test status
Simulation time 29017791854 ps
CPU time 60.1 seconds
Started Aug 04 05:06:27 PM PDT 24
Finished Aug 04 05:07:27 PM PDT 24
Peak memory 199888 kb
Host smart-afc7db4e-e671-432d-9456-0e357e386cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309941479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2309941479
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.901835804
Short name T960
Test name
Test status
Simulation time 20520970016 ps
CPU time 24.41 seconds
Started Aug 04 05:06:27 PM PDT 24
Finished Aug 04 05:06:51 PM PDT 24
Peak memory 199884 kb
Host smart-ef7a3e53-d2e8-4366-af17-cc338f551283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901835804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.901835804
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3978818126
Short name T1053
Test name
Test status
Simulation time 97679167742 ps
CPU time 40.4 seconds
Started Aug 04 05:06:27 PM PDT 24
Finished Aug 04 05:07:08 PM PDT 24
Peak memory 197904 kb
Host smart-42ce5132-5d50-4ab5-a2c7-a9927c65c7c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978818126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3978818126
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1939414188
Short name T954
Test name
Test status
Simulation time 452944175533 ps
CPU time 252.5 seconds
Started Aug 04 05:06:30 PM PDT 24
Finished Aug 04 05:10:43 PM PDT 24
Peak memory 199780 kb
Host smart-03f92e4a-933f-464f-872f-835828df57f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1939414188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1939414188
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2897373319
Short name T536
Test name
Test status
Simulation time 3564924489 ps
CPU time 1.51 seconds
Started Aug 04 05:06:31 PM PDT 24
Finished Aug 04 05:06:33 PM PDT 24
Peak memory 196348 kb
Host smart-cf0dafc9-aa32-43f3-b6ca-c78870b6eb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897373319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2897373319
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2628301360
Short name T656
Test name
Test status
Simulation time 105361609652 ps
CPU time 16.13 seconds
Started Aug 04 05:06:27 PM PDT 24
Finished Aug 04 05:06:44 PM PDT 24
Peak memory 200028 kb
Host smart-c067da18-afdb-48ad-ba80-af12683dbc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628301360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2628301360
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2923247103
Short name T410
Test name
Test status
Simulation time 19918184470 ps
CPU time 187.3 seconds
Started Aug 04 05:06:33 PM PDT 24
Finished Aug 04 05:09:41 PM PDT 24
Peak memory 199864 kb
Host smart-0068699d-b4c3-4ac7-b77f-4520c83a0167
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2923247103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2923247103
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3877620654
Short name T529
Test name
Test status
Simulation time 5723679082 ps
CPU time 14.78 seconds
Started Aug 04 05:06:27 PM PDT 24
Finished Aug 04 05:06:42 PM PDT 24
Peak memory 198728 kb
Host smart-d86a3b7e-f295-4f4a-a09f-b07aea18a0d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3877620654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3877620654
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.453230386
Short name T127
Test name
Test status
Simulation time 87983971806 ps
CPU time 43.11 seconds
Started Aug 04 05:06:28 PM PDT 24
Finished Aug 04 05:07:11 PM PDT 24
Peak memory 199808 kb
Host smart-4ae2aa0f-948d-4027-b71f-31dc5fa075e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453230386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.453230386
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2297954700
Short name T459
Test name
Test status
Simulation time 3248386498 ps
CPU time 2.26 seconds
Started Aug 04 05:06:27 PM PDT 24
Finished Aug 04 05:06:30 PM PDT 24
Peak memory 196784 kb
Host smart-53101f08-5e88-42de-a590-ad3239219f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297954700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2297954700
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.64579171
Short name T484
Test name
Test status
Simulation time 505635268 ps
CPU time 1.95 seconds
Started Aug 04 05:06:23 PM PDT 24
Finished Aug 04 05:06:25 PM PDT 24
Peak memory 198868 kb
Host smart-a03b4f79-cb91-4eac-9fa9-8caeda1a909c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64579171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.64579171
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.417900023
Short name T195
Test name
Test status
Simulation time 502110351847 ps
CPU time 1607.68 seconds
Started Aug 04 05:06:30 PM PDT 24
Finished Aug 04 05:33:18 PM PDT 24
Peak memory 199844 kb
Host smart-6172d637-3ed4-434d-90f2-5c3140b9e435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417900023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.417900023
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.32689009
Short name T793
Test name
Test status
Simulation time 89805693363 ps
CPU time 1143.33 seconds
Started Aug 04 05:06:33 PM PDT 24
Finished Aug 04 05:25:37 PM PDT 24
Peak memory 226216 kb
Host smart-94f5d262-156b-4573-a1f0-4d5fcbba2829
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32689009 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.32689009
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3822938997
Short name T1100
Test name
Test status
Simulation time 944216685 ps
CPU time 1.8 seconds
Started Aug 04 05:06:33 PM PDT 24
Finished Aug 04 05:06:35 PM PDT 24
Peak memory 198752 kb
Host smart-7ea77fd3-68b6-463d-a647-98d30418b36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822938997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3822938997
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1046711014
Short name T801
Test name
Test status
Simulation time 67333200451 ps
CPU time 23.46 seconds
Started Aug 04 05:06:25 PM PDT 24
Finished Aug 04 05:06:49 PM PDT 24
Peak memory 199852 kb
Host smart-7191a8e7-4ae2-44a8-8c71-9da40e4a8a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046711014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1046711014
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1978002349
Short name T827
Test name
Test status
Simulation time 36202152612 ps
CPU time 56.6 seconds
Started Aug 04 05:11:03 PM PDT 24
Finished Aug 04 05:11:59 PM PDT 24
Peak memory 199856 kb
Host smart-647bab90-74e0-4b48-9725-8d190c1ed1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978002349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1978002349
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.863170727
Short name T933
Test name
Test status
Simulation time 20419595115 ps
CPU time 227.73 seconds
Started Aug 04 05:11:03 PM PDT 24
Finished Aug 04 05:14:51 PM PDT 24
Peak memory 216376 kb
Host smart-1c46bec4-0f8d-46d1-be44-eea04af5e66a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863170727 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.863170727
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.2728537929
Short name T173
Test name
Test status
Simulation time 16860839473 ps
CPU time 33.87 seconds
Started Aug 04 05:11:02 PM PDT 24
Finished Aug 04 05:11:36 PM PDT 24
Peak memory 199884 kb
Host smart-eb55fbe9-a3de-4e43-a4bc-bcda52982071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728537929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2728537929
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.920479689
Short name T674
Test name
Test status
Simulation time 324423057471 ps
CPU time 1284.14 seconds
Started Aug 04 05:11:04 PM PDT 24
Finished Aug 04 05:32:29 PM PDT 24
Peak memory 225292 kb
Host smart-d442387d-686d-4e34-b9c5-ef78c6a09c25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920479689 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.920479689
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3458860547
Short name T776
Test name
Test status
Simulation time 110133993315 ps
CPU time 190.57 seconds
Started Aug 04 05:11:07 PM PDT 24
Finished Aug 04 05:14:17 PM PDT 24
Peak memory 199876 kb
Host smart-cbf49f03-83e3-4ea2-8441-d5d2a597c08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458860547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3458860547
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3308470158
Short name T61
Test name
Test status
Simulation time 38657164652 ps
CPU time 354.43 seconds
Started Aug 04 05:11:07 PM PDT 24
Finished Aug 04 05:17:02 PM PDT 24
Peak memory 216436 kb
Host smart-c4b05780-176f-489a-9b90-aa5c5d1bcdec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308470158 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3308470158
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2743346168
Short name T1046
Test name
Test status
Simulation time 37061199494 ps
CPU time 512.76 seconds
Started Aug 04 05:11:06 PM PDT 24
Finished Aug 04 05:19:39 PM PDT 24
Peak memory 216372 kb
Host smart-6392cbeb-e9b5-4d96-9c20-160cdc16487a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743346168 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2743346168
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2379989893
Short name T145
Test name
Test status
Simulation time 434550025277 ps
CPU time 639.22 seconds
Started Aug 04 05:11:12 PM PDT 24
Finished Aug 04 05:21:51 PM PDT 24
Peak memory 228084 kb
Host smart-5c233ee7-60b1-4a68-871b-722b2981a962
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379989893 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2379989893
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1640969920
Short name T230
Test name
Test status
Simulation time 58610433306 ps
CPU time 33.15 seconds
Started Aug 04 05:11:07 PM PDT 24
Finished Aug 04 05:11:40 PM PDT 24
Peak memory 199824 kb
Host smart-5323f5a2-f818-48ba-b951-9eccaf465e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640969920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1640969920
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2942539111
Short name T780
Test name
Test status
Simulation time 185825835476 ps
CPU time 584.22 seconds
Started Aug 04 05:11:12 PM PDT 24
Finished Aug 04 05:20:56 PM PDT 24
Peak memory 228556 kb
Host smart-30d8a2aa-3c29-40a1-a812-9547041f2282
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942539111 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2942539111
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2671851739
Short name T296
Test name
Test status
Simulation time 156892238506 ps
CPU time 193.13 seconds
Started Aug 04 05:11:06 PM PDT 24
Finished Aug 04 05:14:19 PM PDT 24
Peak memory 199812 kb
Host smart-da70a6d2-8c10-4113-84c9-0a3dbb777d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671851739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2671851739
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.898595516
Short name T845
Test name
Test status
Simulation time 52516899666 ps
CPU time 356.66 seconds
Started Aug 04 05:11:10 PM PDT 24
Finished Aug 04 05:17:06 PM PDT 24
Peak memory 216400 kb
Host smart-786ce0f9-04e7-43cc-9c50-37bcf1ec602b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898595516 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.898595516
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.945814427
Short name T701
Test name
Test status
Simulation time 40198567395 ps
CPU time 6.18 seconds
Started Aug 04 05:11:24 PM PDT 24
Finished Aug 04 05:11:30 PM PDT 24
Peak memory 199852 kb
Host smart-407acc9c-bb1f-413c-a0fc-7cb584e7eefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945814427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.945814427
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3113233999
Short name T120
Test name
Test status
Simulation time 42851526082 ps
CPU time 23.03 seconds
Started Aug 04 05:11:24 PM PDT 24
Finished Aug 04 05:11:47 PM PDT 24
Peak memory 199788 kb
Host smart-469d122b-96da-4283-bc80-ab0fd4cce0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113233999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3113233999
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.970232787
Short name T912
Test name
Test status
Simulation time 64939984976 ps
CPU time 398.3 seconds
Started Aug 04 05:11:12 PM PDT 24
Finished Aug 04 05:17:51 PM PDT 24
Peak memory 216312 kb
Host smart-20317870-5307-4fc0-ad77-8e578df6dee1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970232787 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.970232787
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.4094236922
Short name T346
Test name
Test status
Simulation time 12443427 ps
CPU time 0.59 seconds
Started Aug 04 05:06:39 PM PDT 24
Finished Aug 04 05:06:40 PM PDT 24
Peak memory 195556 kb
Host smart-6053b44f-c07c-448a-897e-2c19db2b1a55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094236922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.4094236922
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.4143735997
Short name T857
Test name
Test status
Simulation time 80129124668 ps
CPU time 41.31 seconds
Started Aug 04 05:06:38 PM PDT 24
Finished Aug 04 05:07:20 PM PDT 24
Peak memory 199860 kb
Host smart-7224280d-c4d6-458e-b1fc-2b6e43c2a8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143735997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.4143735997
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2977653879
Short name T1034
Test name
Test status
Simulation time 24324820162 ps
CPU time 36.94 seconds
Started Aug 04 05:06:35 PM PDT 24
Finished Aug 04 05:07:12 PM PDT 24
Peak memory 199772 kb
Host smart-4d7ce678-43c3-4c63-8d52-b64b14ba854c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977653879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2977653879
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.879266721
Short name T134
Test name
Test status
Simulation time 217575328832 ps
CPU time 22.78 seconds
Started Aug 04 05:06:35 PM PDT 24
Finished Aug 04 05:06:58 PM PDT 24
Peak memory 199744 kb
Host smart-f9266e36-4bb0-454c-80f8-2607c94fa7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879266721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.879266721
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.590410685
Short name T281
Test name
Test status
Simulation time 27342918598 ps
CPU time 49.24 seconds
Started Aug 04 05:06:35 PM PDT 24
Finished Aug 04 05:07:25 PM PDT 24
Peak memory 199772 kb
Host smart-bbd738a0-aabf-4098-a315-d60922c48f3b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590410685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.590410685
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.92274197
Short name T615
Test name
Test status
Simulation time 115216086012 ps
CPU time 233.89 seconds
Started Aug 04 05:06:40 PM PDT 24
Finished Aug 04 05:10:34 PM PDT 24
Peak memory 199768 kb
Host smart-c3fdd553-bf21-4804-9c71-2dbddb9a4457
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92274197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.92274197
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.3981553908
Short name T978
Test name
Test status
Simulation time 3242272341 ps
CPU time 6.76 seconds
Started Aug 04 05:06:39 PM PDT 24
Finished Aug 04 05:06:46 PM PDT 24
Peak memory 198792 kb
Host smart-9cd76438-fed8-4e7c-97e9-8be361dd0615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981553908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3981553908
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.587477993
Short name T786
Test name
Test status
Simulation time 35468503914 ps
CPU time 81.85 seconds
Started Aug 04 05:06:37 PM PDT 24
Finished Aug 04 05:07:59 PM PDT 24
Peak memory 199376 kb
Host smart-5ee5ea2b-42fa-4bab-a5ce-27a00e28b008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587477993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.587477993
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.2544426150
Short name T305
Test name
Test status
Simulation time 15805838726 ps
CPU time 101.67 seconds
Started Aug 04 05:06:38 PM PDT 24
Finished Aug 04 05:08:20 PM PDT 24
Peak memory 199860 kb
Host smart-387e439b-535d-4779-a0c9-55c710f742b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2544426150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2544426150
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1630146174
Short name T930
Test name
Test status
Simulation time 2979030080 ps
CPU time 5.36 seconds
Started Aug 04 05:06:35 PM PDT 24
Finished Aug 04 05:06:41 PM PDT 24
Peak memory 198780 kb
Host smart-a54d42c9-f329-491a-a276-1dbd8fbd6645
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1630146174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1630146174
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.1128116165
Short name T577
Test name
Test status
Simulation time 49750059980 ps
CPU time 37.82 seconds
Started Aug 04 05:06:42 PM PDT 24
Finished Aug 04 05:07:20 PM PDT 24
Peak memory 199852 kb
Host smart-7a617243-8324-48c1-a2d3-cad6d6900494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128116165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1128116165
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2610301770
Short name T1172
Test name
Test status
Simulation time 5209949837 ps
CPU time 2.38 seconds
Started Aug 04 05:06:38 PM PDT 24
Finished Aug 04 05:06:41 PM PDT 24
Peak memory 196172 kb
Host smart-9b7231d0-e292-4306-bcc6-db4df486d605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610301770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2610301770
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1629441688
Short name T686
Test name
Test status
Simulation time 270193928 ps
CPU time 1.38 seconds
Started Aug 04 05:06:30 PM PDT 24
Finished Aug 04 05:06:32 PM PDT 24
Peak memory 199700 kb
Host smart-8c86d710-9946-4831-b045-12b5703d784e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629441688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1629441688
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3885712941
Short name T612
Test name
Test status
Simulation time 104480503743 ps
CPU time 43.47 seconds
Started Aug 04 05:06:37 PM PDT 24
Finished Aug 04 05:07:21 PM PDT 24
Peak memory 199884 kb
Host smart-ac2a1efd-4681-4b40-b037-22005f285cf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885712941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3885712941
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.439251922
Short name T1014
Test name
Test status
Simulation time 66618618529 ps
CPU time 466.93 seconds
Started Aug 04 05:06:38 PM PDT 24
Finished Aug 04 05:14:25 PM PDT 24
Peak memory 216628 kb
Host smart-12caf9c2-43ef-4e63-b972-a28cbfa78009
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439251922 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.439251922
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2769710011
Short name T525
Test name
Test status
Simulation time 6948190853 ps
CPU time 8.97 seconds
Started Aug 04 05:06:39 PM PDT 24
Finished Aug 04 05:06:48 PM PDT 24
Peak memory 199936 kb
Host smart-c31bd3e3-1679-4f88-a97e-a2e3d7fc8762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769710011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2769710011
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3339856151
Short name T655
Test name
Test status
Simulation time 57478486218 ps
CPU time 76.06 seconds
Started Aug 04 05:06:33 PM PDT 24
Finished Aug 04 05:07:49 PM PDT 24
Peak memory 199880 kb
Host smart-c0de793d-2e76-4e07-b6b4-d3c3007f2874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339856151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3339856151
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3179576143
Short name T144
Test name
Test status
Simulation time 132541747176 ps
CPU time 107.6 seconds
Started Aug 04 05:11:14 PM PDT 24
Finished Aug 04 05:13:02 PM PDT 24
Peak memory 199848 kb
Host smart-13ef02fb-b6d1-4a53-ba57-2af845fe01d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179576143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3179576143
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1904179113
Short name T870
Test name
Test status
Simulation time 48636287508 ps
CPU time 164.08 seconds
Started Aug 04 05:11:24 PM PDT 24
Finished Aug 04 05:14:08 PM PDT 24
Peak memory 216536 kb
Host smart-bf23529b-f854-400c-8d2f-48d14ce735f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904179113 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1904179113
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.729870166
Short name T1158
Test name
Test status
Simulation time 80466390467 ps
CPU time 121.87 seconds
Started Aug 04 05:11:11 PM PDT 24
Finished Aug 04 05:13:13 PM PDT 24
Peak memory 199808 kb
Host smart-93cb3422-698a-446a-879b-87c1799f8a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729870166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.729870166
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.217307505
Short name T652
Test name
Test status
Simulation time 333015548902 ps
CPU time 1019.84 seconds
Started Aug 04 05:11:14 PM PDT 24
Finished Aug 04 05:28:14 PM PDT 24
Peak memory 216400 kb
Host smart-18b1b71d-925f-4629-a632-e0fa323aaa6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217307505 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.217307505
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2856374518
Short name T476
Test name
Test status
Simulation time 22136357057 ps
CPU time 32.16 seconds
Started Aug 04 05:11:14 PM PDT 24
Finished Aug 04 05:11:46 PM PDT 24
Peak memory 199756 kb
Host smart-aa2d5f58-bfa0-4f7e-9de0-0175af6cd9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856374518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2856374518
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3916750857
Short name T645
Test name
Test status
Simulation time 3446777817 ps
CPU time 39.75 seconds
Started Aug 04 05:11:14 PM PDT 24
Finished Aug 04 05:11:54 PM PDT 24
Peak memory 215816 kb
Host smart-dd4f54f0-fd9c-48b9-9b42-33e3bfce0b3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916750857 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3916750857
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1733582815
Short name T234
Test name
Test status
Simulation time 27548030306 ps
CPU time 20.95 seconds
Started Aug 04 05:11:11 PM PDT 24
Finished Aug 04 05:11:32 PM PDT 24
Peak memory 199844 kb
Host smart-2e5f87bd-138c-4419-8bb8-a8bd7b18136e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733582815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1733582815
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.732828265
Short name T278
Test name
Test status
Simulation time 122690528172 ps
CPU time 2084.27 seconds
Started Aug 04 05:11:24 PM PDT 24
Finished Aug 04 05:46:08 PM PDT 24
Peak memory 227320 kb
Host smart-ed9f8efd-69ce-49c1-9d29-115b88f1c2a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732828265 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.732828265
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3906407133
Short name T588
Test name
Test status
Simulation time 107190747936 ps
CPU time 46.97 seconds
Started Aug 04 05:11:13 PM PDT 24
Finished Aug 04 05:12:00 PM PDT 24
Peak memory 199788 kb
Host smart-4e376cf8-9f96-441e-8cc0-10feba2f42b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906407133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3906407133
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3932404877
Short name T1133
Test name
Test status
Simulation time 114208625082 ps
CPU time 209.67 seconds
Started Aug 04 05:11:11 PM PDT 24
Finished Aug 04 05:14:41 PM PDT 24
Peak memory 216340 kb
Host smart-07f5ff85-9a13-45b0-a39a-097bdf86178f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932404877 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3932404877
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.2973270205
Short name T854
Test name
Test status
Simulation time 138492437316 ps
CPU time 95 seconds
Started Aug 04 05:11:11 PM PDT 24
Finished Aug 04 05:12:46 PM PDT 24
Peak memory 199856 kb
Host smart-9e069f66-5c7c-4e14-9380-398e3ef16614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973270205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2973270205
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3397945193
Short name T35
Test name
Test status
Simulation time 42027609584 ps
CPU time 377.59 seconds
Started Aug 04 05:11:13 PM PDT 24
Finished Aug 04 05:17:31 PM PDT 24
Peak memory 216680 kb
Host smart-aaee3237-7282-4f45-8652-7bb16584ed6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397945193 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3397945193
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.461968050
Short name T579
Test name
Test status
Simulation time 77633887268 ps
CPU time 122.43 seconds
Started Aug 04 05:11:12 PM PDT 24
Finished Aug 04 05:13:15 PM PDT 24
Peak memory 199832 kb
Host smart-c3dd9bfd-c405-4863-8c71-bb91af6767b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461968050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.461968050
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2843827712
Short name T679
Test name
Test status
Simulation time 188960531787 ps
CPU time 520.63 seconds
Started Aug 04 05:11:13 PM PDT 24
Finished Aug 04 05:19:54 PM PDT 24
Peak memory 213872 kb
Host smart-2db8b33f-21dc-40f5-92b8-3f7a47895757
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843827712 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2843827712
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.4246105116
Short name T201
Test name
Test status
Simulation time 132893624750 ps
CPU time 101.8 seconds
Started Aug 04 05:11:24 PM PDT 24
Finished Aug 04 05:13:06 PM PDT 24
Peak memory 199816 kb
Host smart-76b6252d-3ade-4fae-9e5c-07d39c1c56b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246105116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.4246105116
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.360631964
Short name T1129
Test name
Test status
Simulation time 29969005369 ps
CPU time 259.11 seconds
Started Aug 04 05:11:11 PM PDT 24
Finished Aug 04 05:15:31 PM PDT 24
Peak memory 210608 kb
Host smart-97315591-12ae-4aaa-9138-3b6c4a915ad6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360631964 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.360631964
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3429157439
Short name T309
Test name
Test status
Simulation time 141806931158 ps
CPU time 51.79 seconds
Started Aug 04 05:11:12 PM PDT 24
Finished Aug 04 05:12:03 PM PDT 24
Peak memory 199788 kb
Host smart-f176ed64-6186-4665-879d-cf4b4f1dc00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429157439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3429157439
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3708101070
Short name T295
Test name
Test status
Simulation time 12312879856 ps
CPU time 450.18 seconds
Started Aug 04 05:11:10 PM PDT 24
Finished Aug 04 05:18:41 PM PDT 24
Peak memory 208240 kb
Host smart-3c0d52dc-74e3-47f9-a581-a1fd91f84dce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708101070 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3708101070
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1593440379
Short name T540
Test name
Test status
Simulation time 76693575288 ps
CPU time 81.43 seconds
Started Aug 04 05:11:14 PM PDT 24
Finished Aug 04 05:12:35 PM PDT 24
Peak memory 199916 kb
Host smart-4e2453ec-46f6-4131-9acf-52b5777e80dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593440379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1593440379
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.4063416743
Short name T106
Test name
Test status
Simulation time 274257398227 ps
CPU time 317.26 seconds
Started Aug 04 05:11:24 PM PDT 24
Finished Aug 04 05:16:42 PM PDT 24
Peak memory 216440 kb
Host smart-6e2e9917-ecf9-4ffe-bb3a-f78a7bfd78fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063416743 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.4063416743
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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