Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	108953	1			T1	2546		T2	31		T3	12
all_values[1]	108953	1			T1	2546		T2	31		T3	12
all_values[2]	108953	1			T1	2546		T2	31		T3	12
all_values[3]	108953	1			T1	2546		T2	31		T3	12
all_values[4]	108953	1			T1	2546		T2	31		T3	12
all_values[5]	108953	1			T1	2546		T2	31		T3	12
all_values[6]	108953	1			T1	2546		T2	31		T3	12
all_values[7]	108953	1			T1	2546		T2	31		T3	12
all_values[8]	108953	1			T1	2546		T2	31		T3	12

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

484093

1

T1

11792

T2

161

T3

53

auto[1]

496484

1

T1

11122

T2

118

T3

55

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

899224

1

T1

21949

T2

237

T3

75

auto[1]

81353

1

T1

965

T2

42

T3

33

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	34714	1			T1	997		T6	4		T7	5
all_values[0]	auto[0]	auto[1]	20496	1			T1	505		T2	3		T3	2
all_values[0]	auto[1]	auto[0]	33628	1			T1	889		T2	11		T4	2
all_values[0]	auto[1]	auto[1]	20115	1			T1	155		T2	17		T3	10
all_values[1]	auto[0]	auto[0]	51550	1			T1	1082		T3	7		T4	3
all_values[1]	auto[0]	auto[1]	1733	1			T1	3		T3	5		T33	7
all_values[1]	auto[1]	auto[0]	54069	1			T1	1458		T2	31		T4	2
all_values[1]	auto[1]	auto[1]	1601	1			T1	3		T8	1		T128	4
all_values[2]	auto[0]	auto[0]	46746	1			T1	1016		T2	1		T3	6
all_values[2]	auto[0]	auto[1]	2819	1			T1	11		T2	2		T3	1
all_values[2]	auto[1]	auto[0]	56999	1			T1	1513		T2	27		T3	4
all_values[2]	auto[1]	auto[1]	2389	1			T1	6		T2	1		T3	1
all_values[3]	auto[0]	auto[0]	53104	1			T1	803		T2	3		T3	4
all_values[3]	auto[0]	auto[1]	333	1			T1	2		T3	1		T11	1
all_values[3]	auto[1]	auto[0]	55194	1			T1	1741		T2	28		T3	6
all_values[3]	auto[1]	auto[1]	322	1			T3	1		T12	1		T20	2
all_values[4]	auto[0]	auto[0]	56539	1			T1	1579		T2	28		T3	5
all_values[4]	auto[0]	auto[1]	410	1			T1	1		T12	1		T13	7
all_values[4]	auto[1]	auto[0]	51536	1			T1	960		T2	3		T3	7
all_values[4]	auto[1]	auto[1]	468	1			T1	6		T11	16		T13	1
all_values[5]	auto[0]	auto[0]	54973	1			T1	1509		T2	31		T3	12
all_values[5]	auto[0]	auto[1]	193	1			T1	2		T17	1		T96	4
all_values[5]	auto[1]	auto[0]	53606	1			T1	1035		T4	3		T6	7
all_values[5]	auto[1]	auto[1]	181	1			T17	1		T96	3		T30	3
all_values[6]	auto[0]	auto[0]	50174	1			T1	1079		T2	31		T3	5
all_values[6]	auto[0]	auto[1]	194	1			T1	4		T17	1		T96	1
all_values[6]	auto[1]	auto[0]	58418	1			T1	1463		T3	7		T4	5
all_values[6]	auto[1]	auto[1]	167	1			T96	2		T30	1		T133	1
all_values[7]	auto[0]	auto[0]	55138	1			T1	1855		T2	31		T5	2
all_values[7]	auto[0]	auto[1]	371	1			T1	2		T7	1		T11	8
all_values[7]	auto[1]	auto[0]	53058	1			T1	687		T3	12		T4	5
all_values[7]	auto[1]	auto[1]	386	1			T1	2		T11	2		T139	5
all_values[8]	auto[0]	auto[0]	39019	1			T1	1115		T2	12		T6	4
all_values[8]	auto[0]	auto[1]	15587	1			T1	227		T2	19		T3	5
all_values[8]	auto[1]	auto[0]	40759	1			T1	1168		T4	2		T6	18
all_values[8]	auto[1]	auto[1]	13588	1			T1	36		T3	7		T4	3