Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2660

1

T1

11

T2

1

T3

1

auto[UartRx]

2660

1

T1

11

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4666	1			T1	17		T2	2		T3	2
values[1]	63	1			T1	1		T12	1		T18	2
values[2]	70	1			T27	1		T17	1		T28	1
values[3]	54	1			T18	1		T27	1		T28	1
values[4]	49	1			T12	1		T30	1		T31	1
values[5]	72	1			T18	3		T27	1		T32	1
values[6]	67	1			T12	1		T18	2		T17	2
values[7]	49	1			T1	1		T18	2		T27	1
values[8]	70	1			T1	1		T18	1		T17	1
values[9]	60	1			T1	2		T12	2		T27	1
values[10]	69	1			T12	1		T18	1		T28	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2433	1			T1	8		T2	1		T3	1
auto[UartTx]	values[1]	21	1			T12	1		T29	1		T119	1
auto[UartTx]	values[2]	22	1			T17	1		T318	1		T119	1
auto[UartTx]	values[3]	14	1			T167	1		T319	1		T57	1
auto[UartTx]	values[4]	18	1			T30	1		T32	1		T56	1
auto[UartTx]	values[5]	26	1			T18	1		T32	1		T118	1
auto[UartTx]	values[6]	27	1			T18	1		T135	1		T56	2
auto[UartTx]	values[7]	18	1			T18	2		T28	1		T135	1
auto[UartTx]	values[8]	25	1			T1	1		T18	1		T32	2
auto[UartTx]	values[9]	18	1			T1	2		T31	1		T118	1
auto[UartTx]	values[10]	25	1			T32	1		T135	1		T320	1
auto[UartRx]	values[0]	2233	1			T1	9		T2	1		T3	1
auto[UartRx]	values[1]	42	1			T1	1		T18	2		T17	1
auto[UartRx]	values[2]	48	1			T27	1		T28	1		T55	1
auto[UartRx]	values[3]	40	1			T18	1		T27	1		T28	1
auto[UartRx]	values[4]	31	1			T12	1		T31	1		T32	2
auto[UartRx]	values[5]	46	1			T18	2		T27	1		T55	1
auto[UartRx]	values[6]	40	1			T12	1		T18	1		T17	2
auto[UartRx]	values[7]	31	1			T1	1		T27	1		T17	1
auto[UartRx]	values[8]	45	1			T17	1		T28	1		T31	1
auto[UartRx]	values[9]	42	1			T12	2		T27	1		T32	1
auto[UartRx]	values[10]	44	1			T12	1		T18	1		T28	1