Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2345	1			T1	10		T2	2		T4	1
auto[BaudRate115200]	2076	1			T1	9		T2	1		T4	1
auto[BaudRate230400]	1962	1			T1	11		T3	1		T4	1
auto[BaudRate128Kbps]	2069	1			T1	7		T2	1		T6	3
auto[BaudRate256Kbps]	2312	1			T1	12		T3	2		T4	1
auto[BaudRate1Mbps]	1876	1			T1	7		T2	1		T3	1
auto[BaudRate1p5Mbps]	1338	1			T1	10		T2	3		T3	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	873	1			T5	2		T7	10		T12	80
freqs[25]	1592	1			T9	36		T14	2		T95	3
freqs[48]	696	1			T2	8		T128	6		T43	34
freqs[50]	654	1			T6	10		T123	9		T39	6
freqs[100]	1138	1			T3	5		T10	14		T33	9

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	158	1			T7	1		T12	15		T321	19
auto[BaudRate9600]	freqs[25]	284	1			T9	3		T95	3		T41	11
auto[BaudRate9600]	freqs[48]	113	1			T2	2		T43	3		T146	2
auto[BaudRate9600]	freqs[50]	98	1			T123	3		T39	1		T40	2
auto[BaudRate9600]	freqs[100]	190	1			T10	3		T122	2		T34	2
auto[BaudRate115200]	freqs[24]	150	1			T12	20		T289	1		T303	2
auto[BaudRate115200]	freqs[25]	202	1			T9	6		T14	1		T139	4
auto[BaudRate115200]	freqs[48]	93	1			T2	1		T128	1		T43	3
auto[BaudRate115200]	freqs[50]	91	1			T6	2		T39	1		T28	1
auto[BaudRate115200]	freqs[100]	157	1			T33	2		T16	1		T122	4
auto[BaudRate230400]	freqs[24]	124	1			T5	1		T7	4		T12	15
auto[BaudRate230400]	freqs[25]	194	1			T9	3		T272	3		T255	1
auto[BaudRate230400]	freqs[48]	110	1			T128	1		T43	9		T146	1
auto[BaudRate230400]	freqs[50]	76	1			T6	2		T123	3		T39	1
auto[BaudRate230400]	freqs[100]	143	1			T3	1		T10	3		T33	1
auto[BaudRate128Kbps]	freqs[24]	117	1			T7	3		T12	12		T96	3
auto[BaudRate128Kbps]	freqs[25]	264	1			T9	9		T14	1		T139	1
auto[BaudRate128Kbps]	freqs[48]	110	1			T2	1		T128	1		T43	6
auto[BaudRate128Kbps]	freqs[50]	90	1			T6	3		T39	1		T28	5
auto[BaudRate128Kbps]	freqs[100]	143	1			T10	3		T33	1		T34	1
auto[BaudRate256Kbps]	freqs[24]	136	1			T7	2		T12	12		T315	1
auto[BaudRate256Kbps]	freqs[25]	228	1			T9	6		T272	3		T30	22
auto[BaudRate256Kbps]	freqs[48]	96	1			T128	1		T43	5		T146	1
auto[BaudRate256Kbps]	freqs[50]	102	1			T6	2		T123	2		T39	1
auto[BaudRate256Kbps]	freqs[100]	164	1			T3	2		T10	1		T33	3
auto[BaudRate1Mbps]	freqs[24]	111	1			T12	4		T96	5		T322	1
auto[BaudRate1Mbps]	freqs[25]	294	1			T9	6		T139	2		T272	2
auto[BaudRate1Mbps]	freqs[48]	72	1			T2	1		T128	1		T43	4
auto[BaudRate1Mbps]	freqs[50]	93	1			T6	1		T123	1		T39	1
auto[BaudRate1Mbps]	freqs[100]	179	1			T3	1		T10	3		T122	1
auto[BaudRate1p5Mbps]	freqs[25]	126	1			T9	3		T139	1		T272	2
auto[BaudRate1p5Mbps]	freqs[48]	102	1			T2	3		T128	1		T43	4
auto[BaudRate1p5Mbps]	freqs[50]	104	1			T47	3		T28	1		T133	3
auto[BaudRate1p5Mbps]	freqs[100]	162	1			T3	1		T10	1		T33	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded