Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	11	119	91.54

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	11	119	91.54	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	29637995	1			T1	787710		T2	54		T3	3
all_levels[1]	183035	1			T1	353		T2	2		T3	1
all_levels[2]	2506	1			T6	1		T10	10		T33	2
all_levels[3]	1096	1			T1	1		T6	1		T7	3
all_levels[4]	765	1			T1	1		T3	1		T10	1
all_levels[5]	556	1			T1	2		T7	1		T10	5
all_levels[6]	456	1			T1	2		T7	1		T10	1
all_levels[7]	369	1			T1	1		T3	1		T10	1
all_levels[8]	282	1			T3	1		T10	1		T125	1
all_levels[9]	275	1			T1	1		T10	1		T33	1
all_levels[10]	190	1			T1	8		T33	1		T12	1
all_levels[11]	202	1			T1	1		T3	1		T6	3
all_levels[12]	175	1			T1	3		T2	1		T3	2
all_levels[13]	157	1			T1	1		T12	1		T122	1
all_levels[14]	133	1			T1	1		T39	1		T43	1
all_levels[15]	121	1			T7	1		T33	2		T128	1
all_levels[16]	98	1			T33	1		T123	1		T20	2
all_levels[17]	82	1			T3	2		T12	1		T20	1
all_levels[18]	89	1			T7	1		T33	1		T139	1
all_levels[19]	79	1			T1	1		T33	1		T125	1
all_levels[20]	73	1			T33	1		T128	1		T140	1
all_levels[21]	79	1			T33	1		T20	1		T42	4
all_levels[22]	83	1			T1	1		T125	1		T34	1
all_levels[23]	59	1			T1	1		T33	1		T34	1
all_levels[24]	53	1			T7	1		T122	2		T140	2
all_levels[25]	57	1			T12	2		T43	1		T141	1
all_levels[26]	57	1			T3	1		T18	1		T42	2
all_levels[27]	54	1			T3	1		T123	1		T20	1
all_levels[28]	45	1			T3	1		T123	2		T20	1
all_levels[29]	37	1			T33	1		T123	1		T34	1
all_levels[30]	41	1			T1	1		T12	1		T18	2
all_levels[31]	39	1			T1	1		T3	1		T142	2
all_levels[32]	37	1			T34	1		T30	1		T143	1
all_levels[33]	26	1			T34	1		T139	1		T144	1
all_levels[34]	27	1			T35	1		T17	1		T145	2
all_levels[35]	21	1			T146	1		T147	1		T32	1
all_levels[36]	27	1			T12	1		T124	2		T34	1
all_levels[37]	31	1			T20	1		T139	2		T129	2
all_levels[38]	19	1			T148	1		T149	1		T150	1
all_levels[39]	29	1			T18	4		T139	1		T141	1
all_levels[40]	20	1			T123	1		T35	3		T151	2
all_levels[41]	18	1			T34	1		T139	1		T152	1
all_levels[42]	15	1			T153	1		T154	1		T155	1
all_levels[43]	12	1			T43	1		T147	2		T156	1
all_levels[44]	14	1			T34	2		T157	1		T78	1
all_levels[45]	19	1			T34	1		T43	1		T17	2
all_levels[46]	9	1			T12	1		T158	1		T159	2
all_levels[47]	24	1			T17	3		T160	2		T161	1
all_levels[48]	12	1			T123	1		T35	1		T162	1
all_levels[49]	17	1			T123	1		T20	1		T163	1
all_levels[50]	5	1			T56	1		T164	1		T165	1
all_levels[51]	6	1			T166	1		T155	1		T167	1
all_levels[52]	10	1			T148	1		T168	1		T169	1
all_levels[53]	10	1			T17	1		T170	1		T171	1
all_levels[54]	10	1			T139	1		T48	1		T79	1
all_levels[55]	10	1			T18	1		T17	1		T156	1
all_levels[56]	11	1			T170	1		T172	2		T173	1
all_levels[57]	11	1			T48	1		T174	1		T175	1
all_levels[58]	4	1			T166	1		T176	1		T177	1
all_levels[59]	10	1			T18	1		T178	1		T179	3
all_levels[60]	10	1			T112	2		T158	1		T180	1
all_levels[61]	9	1			T112	1		T32	1		T181	1
all_levels[62]	15	1			T112	1		T182	1		T151	2
all_levels[63]	8	1			T20	1		T183	1		T184	4
all_levels[64]	119	1			T3	3		T20	1		T124	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29824942

1

T1

788079

T2

57

T3

14

auto[1]

5021

1

T1

11

T3

5

T4

5

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	11	119	91.54	11

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[33]]	[auto[1]]	0	1	1
[all_levels[41] , all_levels[42]]	[auto[1]]	--	--	2
[all_levels[48]]	[auto[1]]	0	1	1
[all_levels[50] , all_levels[51]]	[auto[1]]	--	--	2
[all_levels[54] , all_levels[55] , all_levels[56] , all_levels[57] , all_levels[58]]	[auto[1]]	--	--	5

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	29633507	1			T1	787699		T2	54		T3	2
all_levels[0]	auto[1]	4488	1			T1	11		T3	1		T4	4
all_levels[1]	auto[0]	182967	1			T1	353		T2	2		T3	1
all_levels[1]	auto[1]	68	1			T4	1		T185	1		T46	1
all_levels[2]	auto[0]	2471	1			T6	1		T10	10		T33	2
all_levels[2]	auto[1]	35	1			T34	1		T186	2		T151	1
all_levels[3]	auto[0]	1070	1			T1	1		T6	1		T7	3
all_levels[3]	auto[1]	26	1			T163	2		T187	1		T188	4
all_levels[4]	auto[0]	740	1			T1	1		T3	1		T10	1
all_levels[4]	auto[1]	25	1			T189	8		T190	1		T76	2
all_levels[5]	auto[0]	541	1			T1	2		T7	1		T10	5
all_levels[5]	auto[1]	15	1			T34	1		T180	3		T149	1
all_levels[6]	auto[0]	447	1			T1	2		T7	1		T10	1
all_levels[6]	auto[1]	9	1			T191	1		T171	1		T192	1
all_levels[7]	auto[0]	354	1			T1	1		T3	1		T10	1
all_levels[7]	auto[1]	15	1			T157	1		T193	1		T194	2
all_levels[8]	auto[0]	261	1			T3	1		T10	1		T125	1
all_levels[8]	auto[1]	21	1			T195	3		T196	1		T197	2
all_levels[9]	auto[0]	254	1			T1	1		T10	1		T33	1
all_levels[9]	auto[1]	21	1			T44	1		T182	1		T119	1
all_levels[10]	auto[0]	179	1			T1	8		T33	1		T12	1
all_levels[10]	auto[1]	11	1			T141	3		T198	1		T186	1
all_levels[11]	auto[0]	185	1			T1	1		T3	1		T6	1
all_levels[11]	auto[1]	17	1			T6	2		T147	2		T199	1
all_levels[12]	auto[0]	157	1			T1	3		T2	1		T3	1
all_levels[12]	auto[1]	18	1			T3	1		T48	1		T147	1
all_levels[13]	auto[0]	143	1			T1	1		T12	1		T122	1
all_levels[13]	auto[1]	14	1			T200	1		T201	1		T202	1
all_levels[14]	auto[0]	121	1			T1	1		T39	1		T43	1
all_levels[14]	auto[1]	12	1			T203	2		T204	1		T205	2
all_levels[15]	auto[0]	110	1			T7	1		T33	2		T128	1
all_levels[15]	auto[1]	11	1			T42	1		T206	1		T207	1
all_levels[16]	auto[0]	89	1			T33	1		T123	1		T20	2
all_levels[16]	auto[1]	9	1			T151	1		T208	1		T209	1
all_levels[17]	auto[0]	74	1			T3	1		T12	1		T20	1
all_levels[17]	auto[1]	8	1			T3	1		T191	1		T202	2
all_levels[18]	auto[0]	77	1			T7	1		T33	1		T139	1
all_levels[18]	auto[1]	12	1			T196	1		T210	1		T61	1
all_levels[19]	auto[0]	76	1			T1	1		T33	1		T125	1
all_levels[19]	auto[1]	3	1			T211	2		T212	1		-	-
all_levels[20]	auto[0]	63	1			T33	1		T128	1		T140	1
all_levels[20]	auto[1]	10	1			T194	1		T213	3		T214	2
all_levels[21]	auto[0]	69	1			T33	1		T20	1		T42	1
all_levels[21]	auto[1]	10	1			T42	3		T215	2		T216	1
all_levels[22]	auto[0]	53	1			T1	1		T125	1		T34	1
all_levels[22]	auto[1]	30	1			T187	1		T217	1		T218	26
all_levels[23]	auto[0]	49	1			T1	1		T33	1		T34	1
all_levels[23]	auto[1]	10	1			T219	1		T220	1		T221	3
all_levels[24]	auto[0]	50	1			T7	1		T122	2		T140	1
all_levels[24]	auto[1]	3	1			T140	1		T222	1		T223	1
all_levels[25]	auto[0]	46	1			T12	2		T43	1		T141	1
all_levels[25]	auto[1]	11	1			T224	1		T225	1		T57	2
all_levels[26]	auto[0]	52	1			T3	1		T18	1		T42	2
all_levels[26]	auto[1]	5	1			T195	1		T181	1		T179	1
all_levels[27]	auto[0]	50	1			T3	1		T123	1		T20	1
all_levels[27]	auto[1]	4	1			T154	1		T226	1		T227	2
all_levels[28]	auto[0]	40	1			T3	1		T123	2		T20	1
all_levels[28]	auto[1]	5	1			T34	1		T228	1		T229	2
all_levels[29]	auto[0]	36	1			T33	1		T123	1		T34	1
all_levels[29]	auto[1]	1	1			T230	1		-	-		-	-
all_levels[30]	auto[0]	38	1			T1	1		T12	1		T18	2
all_levels[30]	auto[1]	3	1			T231	1		T232	2		-	-
all_levels[31]	auto[0]	33	1			T1	1		T3	1		T142	2
all_levels[31]	auto[1]	6	1			T233	1		T234	2		T235	2
all_levels[32]	auto[0]	29	1			T34	1		T30	1		T143	1
all_levels[32]	auto[1]	8	1			T236	1		T237	4		T238	1
all_levels[33]	auto[0]	26	1			T34	1		T139	1		T144	1
all_levels[34]	auto[0]	23	1			T35	1		T17	1		T145	1
all_levels[34]	auto[1]	4	1			T145	1		T239	1		T58	1
all_levels[35]	auto[0]	17	1			T146	1		T147	1		T32	1
all_levels[35]	auto[1]	4	1			T56	1		T240	3		-	-
all_levels[36]	auto[0]	22	1			T12	1		T124	1		T34	1
all_levels[36]	auto[1]	5	1			T124	1		T241	1		T242	1
all_levels[37]	auto[0]	27	1			T20	1		T139	2		T129	1
all_levels[37]	auto[1]	4	1			T129	1		T243	1		T244	1
all_levels[38]	auto[0]	17	1			T148	1		T149	1		T150	1
all_levels[38]	auto[1]	2	1			T245	2		-	-		-	-
all_levels[39]	auto[0]	25	1			T18	1		T139	1		T141	1
all_levels[39]	auto[1]	4	1			T18	3		T246	1		-	-
all_levels[40]	auto[0]	18	1			T123	1		T35	2		T151	1
all_levels[40]	auto[1]	2	1			T35	1		T151	1		-	-
all_levels[41]	auto[0]	18	1			T34	1		T139	1		T152	1
all_levels[42]	auto[0]	15	1			T153	1		T154	1		T155	1
all_levels[43]	auto[0]	11	1			T43	1		T147	1		T156	1
all_levels[43]	auto[1]	1	1			T147	1		-	-		-	-
all_levels[44]	auto[0]	13	1			T34	1		T157	1		T78	1
all_levels[44]	auto[1]	1	1			T34	1		-	-		-	-
all_levels[45]	auto[0]	18	1			T34	1		T43	1		T17	2
all_levels[45]	auto[1]	1	1			T218	1		-	-		-	-
all_levels[46]	auto[0]	8	1			T12	1		T158	1		T159	1
all_levels[46]	auto[1]	1	1			T159	1		-	-		-	-
all_levels[47]	auto[0]	14	1			T17	1		T160	1		T161	1
all_levels[47]	auto[1]	10	1			T17	2		T160	1		T65	1
all_levels[48]	auto[0]	12	1			T123	1		T35	1		T162	1
all_levels[49]	auto[0]	12	1			T123	1		T20	1		T163	1
all_levels[49]	auto[1]	5	1			T247	2		T248	3		-	-
all_levels[50]	auto[0]	5	1			T56	1		T164	1		T165	1
all_levels[51]	auto[0]	6	1			T166	1		T155	1		T167	1
all_levels[52]	auto[0]	9	1			T148	1		T168	1		T169	1
all_levels[52]	auto[1]	1	1			T249	1		-	-		-	-
all_levels[53]	auto[0]	9	1			T17	1		T170	1		T171	1
all_levels[53]	auto[1]	1	1			T250	1		-	-		-	-
all_levels[54]	auto[0]	10	1			T139	1		T48	1		T79	1
all_levels[55]	auto[0]	10	1			T18	1		T17	1		T156	1
all_levels[56]	auto[0]	11	1			T170	1		T172	2		T173	1
all_levels[57]	auto[0]	11	1			T48	1		T174	1		T175	1
all_levels[58]	auto[0]	4	1			T166	1		T176	1		T177	1
all_levels[59]	auto[0]	6	1			T18	1		T178	1		T179	1
all_levels[59]	auto[1]	4	1			T179	2		T251	2		-	-
all_levels[60]	auto[0]	9	1			T112	1		T158	1		T180	1
all_levels[60]	auto[1]	1	1			T112	1		-	-		-	-
all_levels[61]	auto[0]	6	1			T112	1		T32	1		T181	1
all_levels[61]	auto[1]	3	1			T252	2		T230	1		-	-
all_levels[62]	auto[0]	10	1			T112	1		T182	1		T151	1
all_levels[62]	auto[1]	5	1			T151	1		T253	3		T254	1
all_levels[63]	auto[0]	7	1			T20	1		T183	1		T184	3
all_levels[63]	auto[1]	1	1			T184	1		-	-		-	-
all_levels[64]	auto[0]	102	1			T3	1		T20	1		T124	1
all_levels[64]	auto[1]	17	1			T3	2		T124	1		T147	2