Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 1 7 87.50


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 1 7 87.50 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 1 7 87.50


User Defined Bins for cp_watermark_lvl

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_levels[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 1602 1 T1 4 T8 1 T33 7
all_levels[1] 543 1 T11 11 T12 3 T123 4
all_levels[2] 361 1 T3 5 T128 4 T11 24
all_levels[3] 373 1 T1 2 T11 7 T122 5
all_levels[4] 253 1 T12 6 T48 1 T129 4
all_levels[5] 146 1 T13 2 T130 6 T131 11
all_levels[6] 43 1 T13 4 T132 4 T58 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%