Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	108953	1			T1	2546		T2	31		T3	12
all_pins[1]	108953	1			T1	2546		T2	31		T3	12
all_pins[2]	108953	1			T1	2546		T2	31		T3	12
all_pins[3]	108953	1			T1	2546		T2	31		T3	12
all_pins[4]	108953	1			T1	2546		T2	31		T3	12
all_pins[5]	108953	1			T1	2546		T2	31		T3	12
all_pins[6]	108953	1			T1	2546		T2	31		T3	12
all_pins[7]	108953	1			T1	2546		T2	31		T3	12
all_pins[8]	108953	1			T1	2546		T2	31		T3	12

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	940465	1			T1	22704		T2	261		T3	88
values[0x1]	40112	1			T1	210		T2	18		T3	20
transitions[0x0=>0x1]	32221	1			T1	180		T2	18		T3	14
transitions[0x1=>0x0]	31996	1			T1	180		T2	18		T3	14

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	88769	1			T1	2390		T2	14		T3	2
all_pins[0]	values[0x1]	20184	1			T1	156		T2	17		T3	10
all_pins[0]	transitions[0x0=>0x1]	19559	1			T1	154		T2	17		T3	10
all_pins[0]	transitions[0x1=>0x0]	971	1			T1	1		T8	1		T128	4
all_pins[1]	values[0x0]	107357	1			T1	2543		T2	31		T3	12
all_pins[1]	values[0x1]	1596	1			T1	3		T8	1		T128	4
all_pins[1]	transitions[0x0=>0x1]	1481	1			T1	3		T8	1		T128	4
all_pins[1]	transitions[0x1=>0x0]	2338	1			T1	6		T2	1		T3	1
all_pins[2]	values[0x0]	106500	1			T1	2540		T2	30		T3	11
all_pins[2]	values[0x1]	2453	1			T1	6		T2	1		T3	1
all_pins[2]	transitions[0x0=>0x1]	2380	1			T1	6		T2	1		T3	1
all_pins[2]	transitions[0x1=>0x0]	249	1			T3	1		T12	1		T20	2
all_pins[3]	values[0x0]	108631	1			T1	2546		T2	31		T3	11
all_pins[3]	values[0x1]	322	1			T3	1		T12	1		T20	2
all_pins[3]	transitions[0x0=>0x1]	275	1			T3	1		T12	1		T20	2
all_pins[3]	transitions[0x1=>0x0]	421	1			T1	6		T11	16		T13	1
all_pins[4]	values[0x0]	108485	1			T1	2540		T2	31		T3	12
all_pins[4]	values[0x1]	468	1			T1	6		T11	16		T13	1
all_pins[4]	transitions[0x0=>0x1]	393	1			T1	6		T11	16		T13	1
all_pins[4]	transitions[0x1=>0x0]	156	1			T13	1		T17	3		T96	3
all_pins[5]	values[0x0]	108722	1			T1	2546		T2	31		T3	12
all_pins[5]	values[0x1]	231	1			T13	1		T17	3		T29	1
all_pins[5]	transitions[0x0=>0x1]	193	1			T13	1		T17	3		T29	1
all_pins[5]	transitions[0x1=>0x0]	770	1			T3	1		T10	1		T11	4
all_pins[6]	values[0x0]	108145	1			T1	2546		T2	31		T3	11
all_pins[6]	values[0x1]	808	1			T3	1		T10	1		T11	4
all_pins[6]	transitions[0x0=>0x1]	749	1			T3	1		T10	1		T11	4
all_pins[6]	transitions[0x1=>0x0]	326	1			T1	2		T11	2		T139	4
all_pins[7]	values[0x0]	108568	1			T1	2544		T2	31		T3	12
all_pins[7]	values[0x1]	385	1			T1	2		T11	2		T139	5
all_pins[7]	transitions[0x0=>0x1]	226	1			T1	2		T139	5		T152	1
all_pins[7]	transitions[0x1=>0x0]	13506	1			T1	37		T3	7		T4	3
all_pins[8]	values[0x0]	95288	1			T1	2509		T2	31		T3	5
all_pins[8]	values[0x1]	13665	1			T1	37		T3	7		T4	3
all_pins[8]	transitions[0x0=>0x1]	6965	1			T1	9		T3	1		T4	1
all_pins[8]	transitions[0x1=>0x0]	13259	1			T1	128		T2	17		T3	4