Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	5830150	1			T1	64689		T2	16		T3	15
all_levels[1]	1360588	1			T1	31890		T2	3		T4	2
all_levels[2]	343546	1			T1	3564		T2	1		T3	3
all_levels[3]	403719	1			T1	83851		T8	14		T10	57
all_levels[4]	361016	1			T1	4196		T4	2		T8	13
all_levels[5]	367129	1			T1	3599		T7	3		T8	11
all_levels[6]	276197	1			T1	4053		T8	11		T10	36
all_levels[7]	232165	1			T1	3889		T4	2		T8	11
all_levels[8]	284470	1			T1	4045		T4	9		T8	12
all_levels[9]	233430	1			T1	3455		T8	15		T10	30
all_levels[10]	310384	1			T1	38899		T2	2		T8	11
all_levels[11]	304742	1			T1	3966		T8	11		T10	2
all_levels[12]	258622	1			T1	3346		T2	2		T8	17
all_levels[13]	277844	1			T1	3600		T4	38		T8	17
all_levels[14]	305583	1			T1	3746		T8	13		T10	1
all_levels[15]	272109	1			T1	3370		T8	13		T10	5
all_levels[16]	431966	1			T1	3056		T2	4		T8	13
all_levels[17]	635634	1			T1	3259		T2	10		T7	2
all_levels[18]	212920	1			T1	3540		T8	13		T10	34
all_levels[19]	351364	1			T1	49100		T8	11		T10	2
all_levels[20]	181320	1			T1	3237		T8	17		T10	5
all_levels[21]	294757	1			T1	2829		T7	3		T8	14
all_levels[22]	182797	1			T1	3310		T2	5		T8	14
all_levels[23]	347912	1			T1	2722		T2	15		T8	10
all_levels[24]	197011	1			T1	2958		T8	13		T10	4
all_levels[25]	246640	1			T1	3289		T8	12		T10	2
all_levels[26]	175384	1			T1	3398		T6	8		T7	2
all_levels[27]	819802	1			T1	3166		T7	2		T8	11
all_levels[28]	299308	1			T1	3548		T8	13		T10	1
all_levels[29]	180553	1			T1	3205		T8	11		T10	2
all_levels[30]	415460	1			T1	2875		T6	9		T8	17
all_levels[31]	529298	1			T1	10354		T8	346		T10	8
all_levels[32]	12905655	1			T1	420085		T6	6		T7	14

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29824942

1

T1

788079

T2

57

T3

14

auto[1]

4533

1

T1

10

T2

1

T3

4

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	5827380	1			T1	64680		T2	16		T3	12
all_levels[0]	auto[1]	2770	1			T1	9		T3	3		T6	2
all_levels[1]	auto[0]	1360372	1			T1	31890		T2	2		T4	1
all_levels[1]	auto[1]	216	1			T2	1		T4	1		T6	3
all_levels[2]	auto[0]	343487	1			T1	3564		T2	1		T3	2
all_levels[2]	auto[1]	59	1			T3	1		T264	1		T291	1
all_levels[3]	auto[0]	403620	1			T1	83851		T8	14		T10	57
all_levels[3]	auto[1]	99	1			T12	14		T124	2		T18	3
all_levels[4]	auto[0]	360983	1			T1	4196		T4	2		T8	13
all_levels[4]	auto[1]	33	1			T129	1		T275	1		T157	1
all_levels[5]	auto[0]	367107	1			T1	3599		T7	3		T8	11
all_levels[5]	auto[1]	22	1			T264	1		T243	1		T305	1
all_levels[6]	auto[0]	276163	1			T1	4053		T8	11		T10	36
all_levels[6]	auto[1]	34	1			T266	1		T157	1		T288	1
all_levels[7]	auto[0]	232001	1			T1	3889		T4	1		T8	11
all_levels[7]	auto[1]	164	1			T4	1		T299	7		T182	1
all_levels[8]	auto[0]	284446	1			T1	4045		T4	7		T8	12
all_levels[8]	auto[1]	24	1			T4	2		T111	1		T224	1
all_levels[9]	auto[0]	233403	1			T1	3455		T8	15		T10	30
all_levels[9]	auto[1]	27	1			T219	1		T264	1		T192	1
all_levels[10]	auto[0]	310360	1			T1	38899		T2	2		T8	11
all_levels[10]	auto[1]	24	1			T147	1		T116	1		T145	1
all_levels[11]	auto[0]	304722	1			T1	3966		T8	11		T10	2
all_levels[11]	auto[1]	20	1			T314	1		T77	3		T153	1
all_levels[12]	auto[0]	258594	1			T1	3346		T2	2		T8	17
all_levels[12]	auto[1]	28	1			T188	4		T134	2		T325	3
all_levels[13]	auto[0]	277811	1			T1	3600		T4	36		T8	17
all_levels[13]	auto[1]	33	1			T4	2		T326	1		T171	1
all_levels[14]	auto[0]	305551	1			T1	3746		T8	13		T10	1
all_levels[14]	auto[1]	32	1			T151	2		T154	1		T327	1
all_levels[15]	auto[0]	271989	1			T1	3370		T8	13		T10	5
all_levels[15]	auto[1]	120	1			T294	6		T271	1		T328	1
all_levels[16]	auto[0]	431934	1			T1	3056		T2	4		T8	13
all_levels[16]	auto[1]	32	1			T259	1		T241	1		T292	1
all_levels[17]	auto[0]	635604	1			T1	3259		T2	10		T7	2
all_levels[17]	auto[1]	30	1			T42	1		T196	1		T329	1
all_levels[18]	auto[0]	212894	1			T1	3540		T8	13		T10	33
all_levels[18]	auto[1]	26	1			T10	1		T197	1		T330	1
all_levels[19]	auto[0]	351332	1			T1	49100		T8	11		T10	2
all_levels[19]	auto[1]	32	1			T35	1		T331	1		T32	1
all_levels[20]	auto[0]	181298	1			T1	3237		T8	17		T10	5
all_levels[20]	auto[1]	22	1			T151	1		T332	1		T154	1
all_levels[21]	auto[0]	294730	1			T1	2829		T7	3		T8	14
all_levels[21]	auto[1]	27	1			T112	1		T269	1		T202	2
all_levels[22]	auto[0]	182779	1			T1	3310		T2	5		T8	14
all_levels[22]	auto[1]	18	1			T185	1		T256	1		T239	2
all_levels[23]	auto[0]	347893	1			T1	2722		T2	15		T8	10
all_levels[23]	auto[1]	19	1			T196	1		T149	1		T229	3
all_levels[24]	auto[0]	196991	1			T1	2958		T8	13		T10	4
all_levels[24]	auto[1]	20	1			T40	1		T263	1		T76	1
all_levels[25]	auto[0]	246623	1			T1	3289		T8	12		T10	2
all_levels[25]	auto[1]	17	1			T188	2		T333	4		T334	1
all_levels[26]	auto[0]	175358	1			T1	3398		T6	7		T7	2
all_levels[26]	auto[1]	26	1			T6	1		T44	1		T274	1
all_levels[27]	auto[0]	819787	1			T1	3166		T7	2		T8	11
all_levels[27]	auto[1]	15	1			T140	1		T129	1		T304	1
all_levels[28]	auto[0]	299279	1			T1	3548		T8	13		T10	1
all_levels[28]	auto[1]	29	1			T144	1		T265	1		T304	1
all_levels[29]	auto[0]	180542	1			T1	3205		T8	11		T10	2
all_levels[29]	auto[1]	11	1			T152	1		T190	1		T196	2
all_levels[30]	auto[0]	415435	1			T1	2875		T6	7		T8	17
all_levels[30]	auto[1]	25	1			T6	2		T34	2		T116	2
all_levels[31]	auto[0]	529288	1			T1	10354		T8	346		T10	8
all_levels[31]	auto[1]	10	1			T34	1		T44	1		T225	1
all_levels[32]	auto[0]	12905186	1			T1	420084		T6	5		T7	14
all_levels[32]	auto[1]	469	1			T1	1		T6	1		T8	1