Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	805	1			T1	8		T17	7		T96	7
all_values[1]	805	1			T1	8		T17	7		T96	7
all_values[2]	805	1			T1	8		T17	7		T96	7
all_values[3]	805	1			T1	8		T17	7		T96	7
all_values[4]	805	1			T1	8		T17	7		T96	7
all_values[5]	805	1			T1	8		T17	7		T96	7
all_values[6]	805	1			T1	8		T17	7		T96	7
all_values[7]	805	1			T1	8		T17	7		T96	7
all_values[8]	805	1			T1	8		T17	7		T96	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3932

1

T1

46

T17

40

T96

26

auto[1]

3313

1

T1

26

T17

23

T96

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2423

1

T1

23

T17

21

T96

20

auto[1]

4822

1

T1

49

T17

42

T96

43

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4374

1

T1

40

T17

39

T96

40

auto[1]

2871

1

T1

32

T17

24

T96

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	273	1			T1	1		T17	2		T96	2
all_values[0]	auto[0]	auto[1]	auto[1]	223	1			T1	3		T17	3		T96	2
all_values[0]	auto[1]	auto[0]	auto[1]	173	1			T1	2		T17	1		T96	1
all_values[0]	auto[1]	auto[1]	auto[1]	136	1			T1	2		T17	1		T96	2
all_values[1]	auto[0]	auto[0]	auto[0]	269	1			T1	1		T17	2		T96	2
all_values[1]	auto[0]	auto[1]	auto[0]	218	1			T1	3		T17	2		T96	2
all_values[1]	auto[1]	auto[0]	auto[1]	170	1			T1	2		T17	3		T30	1
all_values[1]	auto[1]	auto[1]	auto[1]	148	1			T1	2		T96	3		T133	2
all_values[2]	auto[0]	auto[0]	auto[0]	183	1			T1	1		T17	2		T96	2
all_values[2]	auto[0]	auto[0]	auto[1]	69	1			T1	2		T17	1		T30	1
all_values[2]	auto[0]	auto[1]	auto[0]	143	1			T1	1		T17	1		T32	3
all_values[2]	auto[0]	auto[1]	auto[1]	79	1			T17	1		T96	2		T133	1
all_values[2]	auto[1]	auto[0]	auto[1]	190	1			T1	4		T17	2		T96	2
all_values[2]	auto[1]	auto[1]	auto[1]	141	1			T96	1		T133	3		T55	1
all_values[3]	auto[0]	auto[0]	auto[0]	191	1			T1	3		T17	1		T96	1
all_values[3]	auto[0]	auto[0]	auto[1]	80	1			T1	1		T32	1		T134	1
all_values[3]	auto[0]	auto[1]	auto[0]	125	1			T1	1		T96	5		T30	1
all_values[3]	auto[0]	auto[1]	auto[1]	86	1			T17	2		T30	1		T55	1
all_values[3]	auto[1]	auto[0]	auto[1]	179	1			T1	3		T30	1		T133	3
all_values[3]	auto[1]	auto[1]	auto[1]	144	1			T17	4		T96	1		T30	1
all_values[4]	auto[0]	auto[0]	auto[0]	174	1			T17	3		T32	1		T135	1
all_values[4]	auto[0]	auto[0]	auto[1]	58	1			T96	4		T55	1		T56	1
all_values[4]	auto[0]	auto[1]	auto[0]	152	1			T1	1		T17	2		T96	1
all_values[4]	auto[0]	auto[1]	auto[1]	81	1			T1	3		T30	1		T32	1
all_values[4]	auto[1]	auto[0]	auto[1]	169	1			T1	3		T17	2		T96	1
all_values[4]	auto[1]	auto[1]	auto[1]	171	1			T1	1		T96	1		T133	1
all_values[5]	auto[0]	auto[0]	auto[0]	166	1			T1	4		T17	2		T133	1
all_values[5]	auto[0]	auto[0]	auto[1]	89	1			T1	1		T96	2		T133	2
all_values[5]	auto[0]	auto[1]	auto[0]	153	1			T1	2		T17	1		T30	1
all_values[5]	auto[0]	auto[1]	auto[1]	80	1			T17	2		T96	1		T30	1
all_values[5]	auto[1]	auto[0]	auto[1]	178	1			T1	1		T17	1		T96	1
all_values[5]	auto[1]	auto[1]	auto[1]	139	1			T17	1		T96	3		T30	2
all_values[6]	auto[0]	auto[0]	auto[0]	210	1			T17	4		T96	1		T135	3
all_values[6]	auto[0]	auto[0]	auto[1]	79	1			T1	1		T17	1		T30	2
all_values[6]	auto[0]	auto[1]	auto[0]	138	1			T1	3		T96	2		T133	2
all_values[6]	auto[0]	auto[1]	auto[1]	75	1			T96	1		T133	1		T32	1
all_values[6]	auto[1]	auto[0]	auto[1]	175	1			T1	4		T17	2		T96	1
all_values[6]	auto[1]	auto[1]	auto[1]	128	1			T96	2		T30	2		T133	2
all_values[7]	auto[0]	auto[0]	auto[0]	155	1			T1	3		T96	1		T30	2
all_values[7]	auto[0]	auto[0]	auto[1]	90	1			T17	1		T55	2		T134	4
all_values[7]	auto[0]	auto[1]	auto[0]	146	1			T17	1		T96	3		T30	2
all_values[7]	auto[0]	auto[1]	auto[1]	81	1			T1	1		T17	1		T96	1
all_values[7]	auto[1]	auto[0]	auto[1]	183	1			T1	2		T17	3		T96	1
all_values[7]	auto[1]	auto[1]	auto[1]	150	1			T1	2		T17	1		T96	1
all_values[8]	auto[0]	auto[0]	auto[1]	276	1			T1	4		T17	4		T96	3
all_values[8]	auto[0]	auto[1]	auto[1]	232	1			T96	2		T133	2		T32	3
all_values[8]	auto[1]	auto[0]	auto[1]	153	1			T1	3		T17	3		T96	1
all_values[8]	auto[1]	auto[1]	auto[1]	144	1			T1	1		T96	1		T133	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal