Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.53


Total test records in report: 1317
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T1257 /workspace/coverage/cover_reg_top/0.uart_intr_test.3117351500 Aug 05 04:21:37 PM PDT 24 Aug 05 04:21:39 PM PDT 24 23724827 ps
T1258 /workspace/coverage/cover_reg_top/38.uart_intr_test.1359941687 Aug 05 04:21:31 PM PDT 24 Aug 05 04:21:32 PM PDT 24 56507073 ps
T1259 /workspace/coverage/cover_reg_top/15.uart_csr_rw.797559479 Aug 05 04:22:12 PM PDT 24 Aug 05 04:22:13 PM PDT 24 13133699 ps
T1260 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1345475284 Aug 05 04:21:53 PM PDT 24 Aug 05 04:21:54 PM PDT 24 74863310 ps
T1261 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3291571566 Aug 05 04:19:33 PM PDT 24 Aug 05 04:19:34 PM PDT 24 296550952 ps
T1262 /workspace/coverage/cover_reg_top/3.uart_tl_errors.4274556160 Aug 05 04:21:56 PM PDT 24 Aug 05 04:21:58 PM PDT 24 80362021 ps
T1263 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2958785159 Aug 05 04:21:36 PM PDT 24 Aug 05 04:21:37 PM PDT 24 26170470 ps
T1264 /workspace/coverage/cover_reg_top/21.uart_intr_test.283418629 Aug 05 04:22:04 PM PDT 24 Aug 05 04:22:05 PM PDT 24 15015659 ps
T1265 /workspace/coverage/cover_reg_top/12.uart_csr_rw.3784261593 Aug 05 04:21:36 PM PDT 24 Aug 05 04:21:37 PM PDT 24 31889403 ps
T1266 /workspace/coverage/cover_reg_top/24.uart_intr_test.1131000825 Aug 05 04:21:52 PM PDT 24 Aug 05 04:21:52 PM PDT 24 11624394 ps
T1267 /workspace/coverage/cover_reg_top/17.uart_csr_rw.1012462323 Aug 05 04:20:08 PM PDT 24 Aug 05 04:20:09 PM PDT 24 19687127 ps
T1268 /workspace/coverage/cover_reg_top/35.uart_intr_test.4045364142 Aug 05 04:21:45 PM PDT 24 Aug 05 04:21:45 PM PDT 24 30346821 ps
T1269 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2445827965 Aug 05 04:19:39 PM PDT 24 Aug 05 04:19:40 PM PDT 24 78004705 ps
T104 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.4164762979 Aug 05 04:19:56 PM PDT 24 Aug 05 04:19:57 PM PDT 24 89603732 ps
T1270 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3719043013 Aug 05 04:19:08 PM PDT 24 Aug 05 04:19:09 PM PDT 24 158630268 ps
T1271 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1824023232 Aug 05 04:22:12 PM PDT 24 Aug 05 04:22:14 PM PDT 24 83798077 ps
T136 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.827557023 Aug 05 04:21:33 PM PDT 24 Aug 05 04:21:34 PM PDT 24 156026548 ps
T1272 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3097425313 Aug 05 04:21:56 PM PDT 24 Aug 05 04:21:57 PM PDT 24 44067257 ps
T1273 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1364173408 Aug 05 04:21:20 PM PDT 24 Aug 05 04:21:22 PM PDT 24 23019201 ps
T1274 /workspace/coverage/cover_reg_top/4.uart_csr_rw.274376750 Aug 05 04:22:14 PM PDT 24 Aug 05 04:22:15 PM PDT 24 14278363 ps
T1275 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2395304521 Aug 05 04:20:20 PM PDT 24 Aug 05 04:20:23 PM PDT 24 116151159 ps
T1276 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2309878838 Aug 05 04:21:40 PM PDT 24 Aug 05 04:21:41 PM PDT 24 103427569 ps
T1277 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.783112017 Aug 05 04:22:13 PM PDT 24 Aug 05 04:22:14 PM PDT 24 62228099 ps
T1278 /workspace/coverage/cover_reg_top/46.uart_intr_test.371297218 Aug 05 04:21:31 PM PDT 24 Aug 05 04:21:32 PM PDT 24 23225749 ps
T1279 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.926595605 Aug 05 04:21:53 PM PDT 24 Aug 05 04:21:55 PM PDT 24 88984810 ps
T102 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3993451980 Aug 05 04:19:17 PM PDT 24 Aug 05 04:19:18 PM PDT 24 40416655 ps
T1280 /workspace/coverage/cover_reg_top/7.uart_tl_errors.941025123 Aug 05 04:22:11 PM PDT 24 Aug 05 04:22:13 PM PDT 24 51045402 ps
T1281 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1244101052 Aug 05 04:22:29 PM PDT 24 Aug 05 04:22:30 PM PDT 24 17501668 ps
T137 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1800234695 Aug 05 04:21:19 PM PDT 24 Aug 05 04:21:21 PM PDT 24 256725784 ps
T1282 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2832424744 Aug 05 04:20:21 PM PDT 24 Aug 05 04:20:22 PM PDT 24 62670469 ps
T1283 /workspace/coverage/cover_reg_top/3.uart_csr_rw.2074425750 Aug 05 04:22:06 PM PDT 24 Aug 05 04:22:06 PM PDT 24 15750122 ps
T1284 /workspace/coverage/cover_reg_top/29.uart_intr_test.985515274 Aug 05 04:21:19 PM PDT 24 Aug 05 04:21:20 PM PDT 24 74941942 ps
T1285 /workspace/coverage/cover_reg_top/16.uart_intr_test.3298350029 Aug 05 04:21:20 PM PDT 24 Aug 05 04:21:21 PM PDT 24 24256830 ps
T1286 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2572964631 Aug 05 04:21:56 PM PDT 24 Aug 05 04:21:57 PM PDT 24 20262441 ps
T1287 /workspace/coverage/cover_reg_top/14.uart_tl_errors.2906032318 Aug 05 04:21:47 PM PDT 24 Aug 05 04:21:48 PM PDT 24 63157972 ps
T1288 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1687503297 Aug 05 04:21:28 PM PDT 24 Aug 05 04:21:29 PM PDT 24 271891123 ps
T74 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3314743796 Aug 05 04:18:48 PM PDT 24 Aug 05 04:18:51 PM PDT 24 786681596 ps
T1289 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.979921783 Aug 05 04:21:38 PM PDT 24 Aug 05 04:21:39 PM PDT 24 15175476 ps
T1290 /workspace/coverage/cover_reg_top/19.uart_csr_rw.4114660670 Aug 05 04:21:52 PM PDT 24 Aug 05 04:21:52 PM PDT 24 15136511 ps
T1291 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2618725579 Aug 05 04:22:08 PM PDT 24 Aug 05 04:22:10 PM PDT 24 492066577 ps
T1292 /workspace/coverage/cover_reg_top/7.uart_csr_rw.2200474554 Aug 05 04:22:11 PM PDT 24 Aug 05 04:22:12 PM PDT 24 16525383 ps
T1293 /workspace/coverage/cover_reg_top/15.uart_tl_errors.1045072805 Aug 05 04:19:26 PM PDT 24 Aug 05 04:19:27 PM PDT 24 46778844 ps
T1294 /workspace/coverage/cover_reg_top/30.uart_intr_test.3479716731 Aug 05 04:21:20 PM PDT 24 Aug 05 04:21:20 PM PDT 24 46071233 ps
T1295 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.4254423017 Aug 05 04:21:56 PM PDT 24 Aug 05 04:21:58 PM PDT 24 336107760 ps
T1296 /workspace/coverage/cover_reg_top/9.uart_intr_test.1427357801 Aug 05 04:21:57 PM PDT 24 Aug 05 04:21:58 PM PDT 24 35056126 ps
T1297 /workspace/coverage/cover_reg_top/31.uart_intr_test.2237596215 Aug 05 04:21:19 PM PDT 24 Aug 05 04:21:20 PM PDT 24 84638876 ps
T1298 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3581886425 Aug 05 04:21:36 PM PDT 24 Aug 05 04:21:37 PM PDT 24 31886608 ps
T1299 /workspace/coverage/cover_reg_top/32.uart_intr_test.1636623393 Aug 05 04:21:34 PM PDT 24 Aug 05 04:21:34 PM PDT 24 32898288 ps
T1300 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3760162417 Aug 05 04:22:19 PM PDT 24 Aug 05 04:22:20 PM PDT 24 56063756 ps
T1301 /workspace/coverage/cover_reg_top/0.uart_csr_rw.4106832724 Aug 05 04:18:41 PM PDT 24 Aug 05 04:18:41 PM PDT 24 14284373 ps
T1302 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3702498476 Aug 05 04:21:43 PM PDT 24 Aug 05 04:21:44 PM PDT 24 27343733 ps
T1303 /workspace/coverage/cover_reg_top/6.uart_intr_test.3082972817 Aug 05 04:22:31 PM PDT 24 Aug 05 04:22:31 PM PDT 24 46278843 ps
T1304 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.60013481 Aug 05 04:19:19 PM PDT 24 Aug 05 04:19:20 PM PDT 24 274795335 ps
T1305 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1738862532 Aug 05 04:22:29 PM PDT 24 Aug 05 04:22:30 PM PDT 24 188325940 ps
T1306 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1027414817 Aug 05 04:19:19 PM PDT 24 Aug 05 04:19:20 PM PDT 24 73040703 ps
T1307 /workspace/coverage/cover_reg_top/47.uart_intr_test.160702731 Aug 05 04:21:31 PM PDT 24 Aug 05 04:21:32 PM PDT 24 12088541 ps
T75 /workspace/coverage/cover_reg_top/6.uart_csr_rw.2448343959 Aug 05 04:21:52 PM PDT 24 Aug 05 04:21:53 PM PDT 24 13085838 ps
T1308 /workspace/coverage/cover_reg_top/48.uart_intr_test.289212637 Aug 05 04:21:44 PM PDT 24 Aug 05 04:21:45 PM PDT 24 30732903 ps
T1309 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3877237712 Aug 05 04:22:24 PM PDT 24 Aug 05 04:22:24 PM PDT 24 14827666 ps
T1310 /workspace/coverage/cover_reg_top/22.uart_intr_test.149988402 Aug 05 04:21:39 PM PDT 24 Aug 05 04:21:39 PM PDT 24 15039462 ps
T1311 /workspace/coverage/cover_reg_top/39.uart_intr_test.2292603089 Aug 05 04:21:21 PM PDT 24 Aug 05 04:21:22 PM PDT 24 14218207 ps
T1312 /workspace/coverage/cover_reg_top/27.uart_intr_test.3389800064 Aug 05 04:19:58 PM PDT 24 Aug 05 04:19:59 PM PDT 24 29189104 ps
T1313 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1875160748 Aug 05 04:21:55 PM PDT 24 Aug 05 04:21:56 PM PDT 24 52953158 ps
T1314 /workspace/coverage/cover_reg_top/20.uart_intr_test.843039905 Aug 05 04:19:49 PM PDT 24 Aug 05 04:19:50 PM PDT 24 13447459 ps
T1315 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2548431392 Aug 05 04:22:29 PM PDT 24 Aug 05 04:22:30 PM PDT 24 26046042 ps
T1316 /workspace/coverage/cover_reg_top/49.uart_intr_test.3508535605 Aug 05 04:21:44 PM PDT 24 Aug 05 04:21:44 PM PDT 24 118127849 ps
T1317 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.147137388 Aug 05 04:22:03 PM PDT 24 Aug 05 04:22:04 PM PDT 24 76322986 ps

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1605994507
Short name T1
Test name
Test status
Simulation time 65480815145 ps
CPU time 1916.74 seconds
Started Aug 05 05:16:15 PM PDT 24
Finished Aug 05 05:48:13 PM PDT 24
Peak memory 216528 kb
Host smart-99314e72-c60a-4d38-8731-f5c1022f0519
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605994507 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1605994507
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.218764104
Short name T17
Test name
Test status
Simulation time 752941011422 ps
CPU time 1250.77 seconds
Started Aug 05 05:14:19 PM PDT 24
Finished Aug 05 05:35:10 PM PDT 24
Peak memory 224632 kb
Host smart-10821132-2ee8-4b50-a545-63cfaf61d803
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218764104 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.218764104
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.915332697
Short name T12
Test name
Test status
Simulation time 377454233902 ps
CPU time 1016.66 seconds
Started Aug 05 05:14:09 PM PDT 24
Finished Aug 05 05:31:06 PM PDT 24
Peak memory 224932 kb
Host smart-2a6fa035-9519-4e1f-8774-bb0e749ed81f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915332697 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.915332697
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3894337758
Short name T18
Test name
Test status
Simulation time 167538056514 ps
CPU time 721.22 seconds
Started Aug 05 05:17:11 PM PDT 24
Finished Aug 05 05:29:12 PM PDT 24
Peak memory 216400 kb
Host smart-9bcfe07a-85ec-49b9-80be-eb5507c91d69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894337758 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3894337758
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_stress_all.119250311
Short name T148
Test name
Test status
Simulation time 122234423541 ps
CPU time 597.12 seconds
Started Aug 05 05:13:42 PM PDT 24
Finished Aug 05 05:23:39 PM PDT 24
Peak memory 199912 kb
Host smart-29ade0ac-a5e4-41cc-b666-e346be9e49de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119250311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.119250311
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all.2646224407
Short name T96
Test name
Test status
Simulation time 84620550919 ps
CPU time 233.6 seconds
Started Aug 05 05:15:55 PM PDT 24
Finished Aug 05 05:19:49 PM PDT 24
Peak memory 199976 kb
Host smart-a0f982b5-012d-4442-a105-89969d96e9c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646224407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2646224407
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.516942778
Short name T32
Test name
Test status
Simulation time 416579541653 ps
CPU time 418.13 seconds
Started Aug 05 05:18:28 PM PDT 24
Finished Aug 05 05:25:26 PM PDT 24
Peak memory 224844 kb
Host smart-8529133e-8a91-42a3-839b-97974edc0332
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516942778 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.516942778
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1184336960
Short name T24
Test name
Test status
Simulation time 63106374 ps
CPU time 0.85 seconds
Started Aug 05 05:13:24 PM PDT 24
Finished Aug 05 05:13:25 PM PDT 24
Peak memory 218356 kb
Host smart-d7085ba2-e518-468b-8d04-1fc2dfcb412a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184336960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1184336960
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/24.uart_stress_all.4150886890
Short name T43
Test name
Test status
Simulation time 351956586933 ps
CPU time 375.88 seconds
Started Aug 05 05:15:10 PM PDT 24
Finished Aug 05 05:21:26 PM PDT 24
Peak memory 199908 kb
Host smart-5c697acf-76d2-467a-ae6d-0379b7ca6f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150886890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.4150886890
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all.2772339588
Short name T265
Test name
Test status
Simulation time 326590960482 ps
CPU time 1128.89 seconds
Started Aug 05 05:17:17 PM PDT 24
Finished Aug 05 05:36:06 PM PDT 24
Peak memory 199868 kb
Host smart-dcc1ccf4-203a-499b-aa1f-4d2fa56eef9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772339588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2772339588
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1105743365
Short name T10
Test name
Test status
Simulation time 76878438914 ps
CPU time 141.09 seconds
Started Aug 05 05:17:39 PM PDT 24
Finished Aug 05 05:20:00 PM PDT 24
Peak memory 199852 kb
Host smart-b82a6ec0-1328-4a11-a403-989241b890e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105743365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1105743365
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.356862782
Short name T56
Test name
Test status
Simulation time 252291751044 ps
CPU time 793.93 seconds
Started Aug 05 05:18:45 PM PDT 24
Finished Aug 05 05:31:59 PM PDT 24
Peak memory 231516 kb
Host smart-07550679-d932-43e3-a6d2-aa6f31f1adfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356862782 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.356862782
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all.2329566629
Short name T153
Test name
Test status
Simulation time 508820544347 ps
CPU time 371.4 seconds
Started Aug 05 05:14:29 PM PDT 24
Finished Aug 05 05:20:41 PM PDT 24
Peak memory 199976 kb
Host smart-cc64fd40-2205-4851-a0f7-deaf0ce1de85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329566629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2329566629
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1028902046
Short name T113
Test name
Test status
Simulation time 51497245323 ps
CPU time 463.96 seconds
Started Aug 05 05:14:26 PM PDT 24
Finished Aug 05 05:22:10 PM PDT 24
Peak memory 199828 kb
Host smart-bcd2565e-e890-4d1d-8aff-a83af0d5a316
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1028902046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1028902046
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2222312877
Short name T123
Test name
Test status
Simulation time 125410520512 ps
CPU time 174 seconds
Started Aug 05 05:14:03 PM PDT 24
Finished Aug 05 05:16:57 PM PDT 24
Peak memory 199836 kb
Host smart-8990fc9a-92a9-4b51-960c-3d8aeed02ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222312877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2222312877
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1960217187
Short name T101
Test name
Test status
Simulation time 318822948 ps
CPU time 0.91 seconds
Started Aug 05 04:22:24 PM PDT 24
Finished Aug 05 04:22:25 PM PDT 24
Peak memory 198784 kb
Host smart-5fa980db-c039-430d-9472-dea87c92ff64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960217187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1960217187
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1719696594
Short name T191
Test name
Test status
Simulation time 95160927107 ps
CPU time 146.01 seconds
Started Aug 05 05:21:29 PM PDT 24
Finished Aug 05 05:23:56 PM PDT 24
Peak memory 199972 kb
Host smart-b59657b6-07c9-43c1-9a79-944cdb52a5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719696594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1719696594
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3402271134
Short name T30
Test name
Test status
Simulation time 160821487037 ps
CPU time 493.68 seconds
Started Aug 05 05:18:15 PM PDT 24
Finished Aug 05 05:26:28 PM PDT 24
Peak memory 216492 kb
Host smart-b5d3f5e0-ad34-43d1-a65b-796f5139b6b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402271134 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3402271134
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3704777676
Short name T23
Test name
Test status
Simulation time 15614577 ps
CPU time 0.55 seconds
Started Aug 05 05:14:26 PM PDT 24
Finished Aug 05 05:14:27 PM PDT 24
Peak memory 194688 kb
Host smart-17b6329e-be7d-4174-9503-9242c01b14b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704777676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3704777676
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.820224379
Short name T68
Test name
Test status
Simulation time 40913065 ps
CPU time 0.6 seconds
Started Aug 05 04:20:21 PM PDT 24
Finished Aug 05 04:20:21 PM PDT 24
Peak memory 195676 kb
Host smart-de626c09-75b3-440e-8d50-90fc4b9bdfb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820224379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.820224379
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2520443495
Short name T134
Test name
Test status
Simulation time 414252941270 ps
CPU time 1286.89 seconds
Started Aug 05 05:18:39 PM PDT 24
Finished Aug 05 05:40:06 PM PDT 24
Peak memory 228916 kb
Host smart-594b7041-e9a2-458f-b898-98da941e5987
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520443495 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2520443495
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3685841286
Short name T186
Test name
Test status
Simulation time 140935343050 ps
CPU time 216.14 seconds
Started Aug 05 05:20:17 PM PDT 24
Finished Aug 05 05:23:53 PM PDT 24
Peak memory 199976 kb
Host smart-79bce9db-d822-4e95-b11a-8b19decced43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685841286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3685841286
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2450437728
Short name T256
Test name
Test status
Simulation time 83311955767 ps
CPU time 118.28 seconds
Started Aug 05 05:14:20 PM PDT 24
Finished Aug 05 05:16:19 PM PDT 24
Peak memory 199988 kb
Host smart-859eea9f-06f6-4aaa-b392-8a3c2964def1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450437728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2450437728
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1295166397
Short name T34
Test name
Test status
Simulation time 97004611665 ps
CPU time 156.91 seconds
Started Aug 05 05:19:29 PM PDT 24
Finished Aug 05 05:22:06 PM PDT 24
Peak memory 199832 kb
Host smart-36d90d7c-219b-476f-ab22-64de346bd278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295166397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1295166397
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.3450196551
Short name T139
Test name
Test status
Simulation time 51186245725 ps
CPU time 30.8 seconds
Started Aug 05 05:14:35 PM PDT 24
Finished Aug 05 05:15:06 PM PDT 24
Peak memory 199988 kb
Host smart-194d2d75-8b2f-4093-b70e-79b49cd8ef92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450196551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3450196551
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.2422769901
Short name T151
Test name
Test status
Simulation time 72502337520 ps
CPU time 10.86 seconds
Started Aug 05 05:18:13 PM PDT 24
Finished Aug 05 05:18:24 PM PDT 24
Peak memory 199956 kb
Host smart-cbcb8715-6a1a-42a7-802a-d6a347a52e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422769901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2422769901
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all.4059365825
Short name T433
Test name
Test status
Simulation time 208699439042 ps
CPU time 264.46 seconds
Started Aug 05 05:15:08 PM PDT 24
Finished Aug 05 05:19:32 PM PDT 24
Peak memory 199988 kb
Host smart-14ec20df-16a8-40b0-ab78-d283a4fd068d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059365825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.4059365825
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2364095684
Short name T159
Test name
Test status
Simulation time 90340094791 ps
CPU time 54.89 seconds
Started Aug 05 05:21:11 PM PDT 24
Finished Aug 05 05:22:06 PM PDT 24
Peak memory 199912 kb
Host smart-b124fa62-5cee-4261-ae42-50c0fb71dfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364095684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2364095684
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2762483867
Short name T269
Test name
Test status
Simulation time 73045724485 ps
CPU time 205.87 seconds
Started Aug 05 05:15:26 PM PDT 24
Finished Aug 05 05:18:52 PM PDT 24
Peak memory 200036 kb
Host smart-f963ca15-e679-4a52-b952-bd59753250f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762483867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2762483867
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3611610042
Short name T196
Test name
Test status
Simulation time 61925695362 ps
CPU time 49.92 seconds
Started Aug 05 05:19:08 PM PDT 24
Finished Aug 05 05:19:58 PM PDT 24
Peak memory 199904 kb
Host smart-8b48a658-2eda-42b6-a722-57b1f686ecbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611610042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3611610042
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2340752181
Short name T183
Test name
Test status
Simulation time 245059596266 ps
CPU time 38.56 seconds
Started Aug 05 05:14:57 PM PDT 24
Finished Aug 05 05:15:36 PM PDT 24
Peak memory 199868 kb
Host smart-5e471568-4583-4d51-9396-3f5dafc935ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340752181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2340752181
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.132286280
Short name T42
Test name
Test status
Simulation time 39596096985 ps
CPU time 60.14 seconds
Started Aug 05 05:21:20 PM PDT 24
Finished Aug 05 05:22:20 PM PDT 24
Peak memory 199968 kb
Host smart-2008f376-b20d-4526-8ce4-81fdeee5909b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132286280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.132286280
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1502005957
Short name T100
Test name
Test status
Simulation time 91320001 ps
CPU time 1.25 seconds
Started Aug 05 04:21:57 PM PDT 24
Finished Aug 05 04:21:58 PM PDT 24
Peak memory 199516 kb
Host smart-5273f441-df5f-4eb3-b516-28fcd8a76b15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502005957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1502005957
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2160769211
Short name T122
Test name
Test status
Simulation time 238908461113 ps
CPU time 404.41 seconds
Started Aug 05 05:14:19 PM PDT 24
Finished Aug 05 05:21:04 PM PDT 24
Peak memory 199780 kb
Host smart-e604563e-160a-439d-a303-b3651c6de183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160769211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2160769211
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2199638867
Short name T190
Test name
Test status
Simulation time 19847469725 ps
CPU time 36.53 seconds
Started Aug 05 05:18:30 PM PDT 24
Finished Aug 05 05:19:07 PM PDT 24
Peak memory 199972 kb
Host smart-f3844bcb-57aa-4586-80fa-28d31e2455b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199638867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2199638867
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1699378552
Short name T157
Test name
Test status
Simulation time 108283008498 ps
CPU time 170.86 seconds
Started Aug 05 05:18:58 PM PDT 24
Finished Aug 05 05:21:49 PM PDT 24
Peak memory 200152 kb
Host smart-7a868ce1-38f3-442f-9981-4c207212c741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699378552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1699378552
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3017857881
Short name T211
Test name
Test status
Simulation time 32171426062 ps
CPU time 22.21 seconds
Started Aug 05 05:19:17 PM PDT 24
Finished Aug 05 05:19:40 PM PDT 24
Peak memory 199908 kb
Host smart-ae260690-1e66-4a07-a422-ba985f393099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017857881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3017857881
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1953315519
Short name T703
Test name
Test status
Simulation time 124315694398 ps
CPU time 127.12 seconds
Started Aug 05 05:14:13 PM PDT 24
Finished Aug 05 05:16:20 PM PDT 24
Peak memory 200004 kb
Host smart-ad19ca9d-0f9d-4ce7-8d07-5539b04b4942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953315519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1953315519
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.310559327
Short name T166
Test name
Test status
Simulation time 397614658978 ps
CPU time 224.75 seconds
Started Aug 05 05:13:25 PM PDT 24
Finished Aug 05 05:17:09 PM PDT 24
Peak memory 199924 kb
Host smart-6c63ea53-f637-470d-be88-5913810027dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310559327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.310559327
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_intr.4149010125
Short name T294
Test name
Test status
Simulation time 412518965125 ps
CPU time 195.54 seconds
Started Aug 05 05:13:31 PM PDT 24
Finished Aug 05 05:16:46 PM PDT 24
Peak memory 199908 kb
Host smart-5fff7035-1f51-436b-a7e0-112d352c7640
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149010125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.4149010125
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/33.uart_stress_all.2425496589
Short name T218
Test name
Test status
Simulation time 282124627662 ps
CPU time 113.01 seconds
Started Aug 05 05:16:04 PM PDT 24
Finished Aug 05 05:17:57 PM PDT 24
Peak memory 199972 kb
Host smart-bbc4611b-4179-4a04-b8a1-599c468c624e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425496589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2425496589
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1745729643
Short name T272
Test name
Test status
Simulation time 140000412124 ps
CPU time 82.4 seconds
Started Aug 05 05:13:12 PM PDT 24
Finished Aug 05 05:14:34 PM PDT 24
Peak memory 208260 kb
Host smart-9136f6fc-10e6-4fa3-a7dc-73cfda78fa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745729643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1745729643
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1144544590
Short name T250
Test name
Test status
Simulation time 54510656396 ps
CPU time 42.31 seconds
Started Aug 05 05:13:31 PM PDT 24
Finished Aug 05 05:14:14 PM PDT 24
Peak memory 199964 kb
Host smart-c5454a1a-ff39-41a1-b16f-f96b47880dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144544590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1144544590
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3422351420
Short name T248
Test name
Test status
Simulation time 99666132882 ps
CPU time 39.41 seconds
Started Aug 05 05:18:06 PM PDT 24
Finished Aug 05 05:18:46 PM PDT 24
Peak memory 199996 kb
Host smart-e2a27042-5b1e-4999-beb0-b9e9fa62bdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422351420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3422351420
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2354459274
Short name T57
Test name
Test status
Simulation time 107138475761 ps
CPU time 823.6 seconds
Started Aug 05 05:18:46 PM PDT 24
Finished Aug 05 05:32:30 PM PDT 24
Peak memory 224764 kb
Host smart-db2b7112-5ee3-4699-9d53-ea5f7ccc6055
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354459274 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2354459274
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3419779995
Short name T103
Test name
Test status
Simulation time 129003496 ps
CPU time 1.26 seconds
Started Aug 05 04:21:44 PM PDT 24
Finished Aug 05 04:21:45 PM PDT 24
Peak memory 199456 kb
Host smart-2f96508e-6e14-4a54-9018-e6755f902a99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419779995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3419779995
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.4249676949
Short name T129
Test name
Test status
Simulation time 54140194647 ps
CPU time 79.26 seconds
Started Aug 05 05:19:26 PM PDT 24
Finished Aug 05 05:20:45 PM PDT 24
Peak memory 199844 kb
Host smart-c6663cee-74ae-480f-9bd5-aad7dd1aedc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249676949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.4249676949
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2258656939
Short name T397
Test name
Test status
Simulation time 190460369488 ps
CPU time 59.58 seconds
Started Aug 05 05:14:15 PM PDT 24
Finished Aug 05 05:15:14 PM PDT 24
Peak memory 208268 kb
Host smart-1a352867-5506-4124-a731-6141e5df2da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258656939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2258656939
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.195067651
Short name T230
Test name
Test status
Simulation time 176295974128 ps
CPU time 22.91 seconds
Started Aug 05 05:20:20 PM PDT 24
Finished Aug 05 05:20:43 PM PDT 24
Peak memory 199624 kb
Host smart-b08168f2-7a57-4d44-9548-9f5f7ad7164b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195067651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.195067651
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2444607470
Short name T179
Test name
Test status
Simulation time 68717560343 ps
CPU time 33.69 seconds
Started Aug 05 05:20:29 PM PDT 24
Finished Aug 05 05:21:03 PM PDT 24
Peak memory 199980 kb
Host smart-5fca6517-445c-4f83-9781-eddc1a7435a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444607470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2444607470
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.716615818
Short name T231
Test name
Test status
Simulation time 36346219419 ps
CPU time 29.56 seconds
Started Aug 05 05:14:52 PM PDT 24
Finished Aug 05 05:15:22 PM PDT 24
Peak memory 199908 kb
Host smart-4cfd0314-04c8-497b-83ed-52cd48238d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716615818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.716615818
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3149879622
Short name T202
Test name
Test status
Simulation time 135982960889 ps
CPU time 65.8 seconds
Started Aug 05 05:21:10 PM PDT 24
Finished Aug 05 05:22:16 PM PDT 24
Peak memory 199976 kb
Host smart-7f1ff60a-e615-49bd-84df-155bae0c683c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149879622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3149879622
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3429523577
Short name T147
Test name
Test status
Simulation time 74822704106 ps
CPU time 32.68 seconds
Started Aug 05 05:21:40 PM PDT 24
Finished Aug 05 05:22:13 PM PDT 24
Peak memory 199876 kb
Host smart-b38aa775-8dba-46fa-b4f7-5e6f6e55cc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429523577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3429523577
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1884406248
Short name T249
Test name
Test status
Simulation time 34247991250 ps
CPU time 49.36 seconds
Started Aug 05 05:18:51 PM PDT 24
Finished Aug 05 05:19:40 PM PDT 24
Peak memory 199864 kb
Host smart-a97fad10-45c1-413e-b221-0c45c0e2acc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884406248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1884406248
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_perf.1413776381
Short name T286
Test name
Test status
Simulation time 11028657826 ps
CPU time 142.8 seconds
Started Aug 05 05:14:28 PM PDT 24
Finished Aug 05 05:16:51 PM PDT 24
Peak memory 199884 kb
Host smart-be2daaed-686a-40a9-a527-983a2071cc8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1413776381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1413776381
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.1061442564
Short name T234
Test name
Test status
Simulation time 93393806612 ps
CPU time 145.63 seconds
Started Aug 05 05:19:59 PM PDT 24
Finished Aug 05 05:22:25 PM PDT 24
Peak memory 199932 kb
Host smart-4de4138d-6658-453c-ab8f-ecb0653c51ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061442564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1061442564
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.4050462858
Short name T223
Test name
Test status
Simulation time 16827186378 ps
CPU time 27.74 seconds
Started Aug 05 05:20:08 PM PDT 24
Finished Aug 05 05:20:36 PM PDT 24
Peak memory 199988 kb
Host smart-1b1d95c6-2b5c-4c5c-8568-ecc6588ab218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050462858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.4050462858
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.70069049
Short name T227
Test name
Test status
Simulation time 172804008906 ps
CPU time 101.59 seconds
Started Aug 05 05:14:35 PM PDT 24
Finished Aug 05 05:16:16 PM PDT 24
Peak memory 199936 kb
Host smart-484037cf-e9ce-4f0d-9389-b28e32ea0bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70069049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.70069049
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all.3999571927
Short name T988
Test name
Test status
Simulation time 508995869664 ps
CPU time 2513.92 seconds
Started Aug 05 05:14:41 PM PDT 24
Finished Aug 05 05:56:36 PM PDT 24
Peak memory 208160 kb
Host smart-7f6b34ea-c0be-4877-9250-27815d6dbf2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999571927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3999571927
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3767211158
Short name T238
Test name
Test status
Simulation time 68380590154 ps
CPU time 99.53 seconds
Started Aug 05 05:20:31 PM PDT 24
Finished Aug 05 05:22:11 PM PDT 24
Peak memory 199992 kb
Host smart-d8de09ce-3d12-4a04-a10a-e5dc51eba64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767211158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3767211158
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3298818108
Short name T184
Test name
Test status
Simulation time 88433946771 ps
CPU time 11.23 seconds
Started Aug 05 05:20:34 PM PDT 24
Finished Aug 05 05:20:46 PM PDT 24
Peak memory 200032 kb
Host smart-dd9b2cb9-f260-4434-9bc6-aceae5353af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298818108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3298818108
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all.3962468201
Short name T245
Test name
Test status
Simulation time 369377031399 ps
CPU time 74.43 seconds
Started Aug 05 05:15:03 PM PDT 24
Finished Aug 05 05:16:18 PM PDT 24
Peak memory 208192 kb
Host smart-c93b5ad5-5af9-4964-a0c5-7d018bdf9715
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962468201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3962468201
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3508504516
Short name T112
Test name
Test status
Simulation time 103440258479 ps
CPU time 36.92 seconds
Started Aug 05 05:21:11 PM PDT 24
Finished Aug 05 05:21:48 PM PDT 24
Peak memory 199944 kb
Host smart-02e14470-64e2-45e9-84a6-3227e350c5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508504516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3508504516
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1918268173
Short name T67
Test name
Test status
Simulation time 40571962 ps
CPU time 0.73 seconds
Started Aug 05 04:18:40 PM PDT 24
Finished Aug 05 04:18:41 PM PDT 24
Peak memory 195564 kb
Host smart-2ff78715-3856-426a-a898-b41e835edc8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918268173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1918268173
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2618725579
Short name T1291
Test name
Test status
Simulation time 492066577 ps
CPU time 1.44 seconds
Started Aug 05 04:22:08 PM PDT 24
Finished Aug 05 04:22:10 PM PDT 24
Peak memory 197272 kb
Host smart-7501750e-92a1-4beb-a297-1419a0296b3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618725579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2618725579
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2816514773
Short name T1197
Test name
Test status
Simulation time 25371489 ps
CPU time 0.61 seconds
Started Aug 05 04:21:54 PM PDT 24
Finished Aug 05 04:21:54 PM PDT 24
Peak memory 195604 kb
Host smart-c4f2cf2c-2ff9-4753-bc6f-0a6fcbfec0b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816514773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2816514773
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2309878838
Short name T1276
Test name
Test status
Simulation time 103427569 ps
CPU time 0.83 seconds
Started Aug 05 04:21:40 PM PDT 24
Finished Aug 05 04:21:41 PM PDT 24
Peak memory 198212 kb
Host smart-ab40dc63-d3e4-4d7e-a5a1-61281b4742ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309878838 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2309878838
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.4106832724
Short name T1301
Test name
Test status
Simulation time 14284373 ps
CPU time 0.63 seconds
Started Aug 05 04:18:41 PM PDT 24
Finished Aug 05 04:18:41 PM PDT 24
Peak memory 195564 kb
Host smart-162ef237-0fbb-493d-8996-b5b738388b09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106832724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.4106832724
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3117351500
Short name T1257
Test name
Test status
Simulation time 23724827 ps
CPU time 0.6 seconds
Started Aug 05 04:21:37 PM PDT 24
Finished Aug 05 04:21:39 PM PDT 24
Peak memory 193732 kb
Host smart-5f8ba309-9a5d-4ae0-a660-8ea5f13bd93d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117351500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3117351500
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1415339622
Short name T1248
Test name
Test status
Simulation time 171869138 ps
CPU time 0.79 seconds
Started Aug 05 04:20:23 PM PDT 24
Finished Aug 05 04:20:24 PM PDT 24
Peak memory 196252 kb
Host smart-e543ef9e-ac67-459b-bb41-32fdc39dc0b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415339622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1415339622
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2832424744
Short name T1282
Test name
Test status
Simulation time 62670469 ps
CPU time 1.58 seconds
Started Aug 05 04:20:21 PM PDT 24
Finished Aug 05 04:20:22 PM PDT 24
Peak memory 200232 kb
Host smart-02bc9551-9407-4be8-a3b2-01154bcbff3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832424744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2832424744
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2102283465
Short name T106
Test name
Test status
Simulation time 716802290 ps
CPU time 0.94 seconds
Started Aug 05 04:21:53 PM PDT 24
Finished Aug 05 04:21:54 PM PDT 24
Peak memory 199208 kb
Host smart-636aa89e-ac80-42ae-a8a2-acce13e91af6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102283465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2102283465
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3169771130
Short name T70
Test name
Test status
Simulation time 123420815 ps
CPU time 0.76 seconds
Started Aug 05 04:22:24 PM PDT 24
Finished Aug 05 04:22:25 PM PDT 24
Peak memory 196596 kb
Host smart-5bc6ca39-8094-42b6-a741-cca479f114de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169771130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3169771130
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2395304521
Short name T1275
Test name
Test status
Simulation time 116151159 ps
CPU time 2.31 seconds
Started Aug 05 04:20:20 PM PDT 24
Finished Aug 05 04:20:23 PM PDT 24
Peak memory 197840 kb
Host smart-3b5e2b99-c55a-4c0d-8b99-bee5419009c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395304521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2395304521
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3877237712
Short name T1309
Test name
Test status
Simulation time 14827666 ps
CPU time 0.57 seconds
Started Aug 05 04:22:24 PM PDT 24
Finished Aug 05 04:22:24 PM PDT 24
Peak memory 195588 kb
Host smart-145583a3-0dfd-449e-9bc6-845ba615609a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877237712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3877237712
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2445827965
Short name T1269
Test name
Test status
Simulation time 78004705 ps
CPU time 0.9 seconds
Started Aug 05 04:19:39 PM PDT 24
Finished Aug 05 04:19:40 PM PDT 24
Peak memory 200424 kb
Host smart-0be87a5f-2f3b-43d9-ac11-c98a204443d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445827965 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2445827965
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.859168184
Short name T73
Test name
Test status
Simulation time 57162910 ps
CPU time 0.63 seconds
Started Aug 05 04:21:53 PM PDT 24
Finished Aug 05 04:21:54 PM PDT 24
Peak memory 195724 kb
Host smart-af6f5be1-2e68-45c8-97a5-057b1cfc3cfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859168184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.859168184
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2879804708
Short name T1202
Test name
Test status
Simulation time 13503248 ps
CPU time 0.56 seconds
Started Aug 05 04:21:53 PM PDT 24
Finished Aug 05 04:21:54 PM PDT 24
Peak memory 194572 kb
Host smart-cc0ad7a6-202f-424c-857d-db244fa90eb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879804708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2879804708
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1345475284
Short name T1260
Test name
Test status
Simulation time 74863310 ps
CPU time 0.67 seconds
Started Aug 05 04:21:53 PM PDT 24
Finished Aug 05 04:21:54 PM PDT 24
Peak memory 195992 kb
Host smart-bff4a2d0-360a-45e3-8e2e-a608877fd363
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345475284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1345475284
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.942490602
Short name T1251
Test name
Test status
Simulation time 100281026 ps
CPU time 1.71 seconds
Started Aug 05 04:21:53 PM PDT 24
Finished Aug 05 04:21:55 PM PDT 24
Peak memory 200224 kb
Host smart-0f5d350a-480e-4e17-a3f0-1c7d5c2ad574
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942490602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.942490602
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2701554770
Short name T1205
Test name
Test status
Simulation time 36814664 ps
CPU time 0.69 seconds
Started Aug 05 04:18:57 PM PDT 24
Finished Aug 05 04:18:57 PM PDT 24
Peak memory 197568 kb
Host smart-b71414ba-4dcb-4a86-8445-90ba8d46a332
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701554770 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2701554770
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2825263832
Short name T89
Test name
Test status
Simulation time 50827593 ps
CPU time 0.58 seconds
Started Aug 05 04:19:02 PM PDT 24
Finished Aug 05 04:19:02 PM PDT 24
Peak memory 195504 kb
Host smart-60d787e5-001c-43b2-bca2-22dc6b12a839
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825263832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2825263832
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2545916814
Short name T1220
Test name
Test status
Simulation time 14004524 ps
CPU time 0.62 seconds
Started Aug 05 04:22:13 PM PDT 24
Finished Aug 05 04:22:14 PM PDT 24
Peak memory 194196 kb
Host smart-8904933c-af4c-4740-b183-ac7be58156ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545916814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2545916814
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3760162417
Short name T1300
Test name
Test status
Simulation time 56063756 ps
CPU time 0.67 seconds
Started Aug 05 04:22:19 PM PDT 24
Finished Aug 05 04:22:20 PM PDT 24
Peak memory 195976 kb
Host smart-dac89c73-d66e-4419-a12d-b8a92c0f2f63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760162417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3760162417
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2907739130
Short name T1247
Test name
Test status
Simulation time 50460426 ps
CPU time 1.4 seconds
Started Aug 05 04:19:25 PM PDT 24
Finished Aug 05 04:19:26 PM PDT 24
Peak memory 200004 kb
Host smart-e7f25677-e329-4918-a33f-1ba32b527f1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907739130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2907739130
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3719043013
Short name T1270
Test name
Test status
Simulation time 158630268 ps
CPU time 0.97 seconds
Started Aug 05 04:19:08 PM PDT 24
Finished Aug 05 04:19:09 PM PDT 24
Peak memory 198840 kb
Host smart-e388f427-bb59-4ced-9512-b6e8d257e893
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719043013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3719043013
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.783112017
Short name T1277
Test name
Test status
Simulation time 62228099 ps
CPU time 0.68 seconds
Started Aug 05 04:22:13 PM PDT 24
Finished Aug 05 04:22:14 PM PDT 24
Peak memory 197904 kb
Host smart-a26ef1c4-ed92-442e-9b79-eb0894e41a1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783112017 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.783112017
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.167770259
Short name T1231
Test name
Test status
Simulation time 14634653 ps
CPU time 0.61 seconds
Started Aug 05 04:22:07 PM PDT 24
Finished Aug 05 04:22:07 PM PDT 24
Peak memory 194744 kb
Host smart-c7f5ea83-64bf-47e9-a45c-f286c78a2830
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167770259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.167770259
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1416651600
Short name T1191
Test name
Test status
Simulation time 50421485 ps
CPU time 0.59 seconds
Started Aug 05 04:19:25 PM PDT 24
Finished Aug 05 04:19:25 PM PDT 24
Peak memory 194252 kb
Host smart-3b70f61a-1e64-49ae-8f1b-e2bfd665ec12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416651600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1416651600
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.910986281
Short name T91
Test name
Test status
Simulation time 116182467 ps
CPU time 0.76 seconds
Started Aug 05 04:22:12 PM PDT 24
Finished Aug 05 04:22:13 PM PDT 24
Peak memory 196844 kb
Host smart-b897501b-ef43-4c85-88de-51e2681fc04d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910986281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.910986281
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1610690266
Short name T1240
Test name
Test status
Simulation time 135808455 ps
CPU time 1.77 seconds
Started Aug 05 04:19:30 PM PDT 24
Finished Aug 05 04:19:32 PM PDT 24
Peak memory 200276 kb
Host smart-3ba77862-bf49-47d2-86f2-020d2f9f4d54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610690266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1610690266
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3291571566
Short name T1261
Test name
Test status
Simulation time 296550952 ps
CPU time 1.35 seconds
Started Aug 05 04:19:33 PM PDT 24
Finished Aug 05 04:19:34 PM PDT 24
Peak memory 199792 kb
Host smart-5ff66ad4-4268-47d7-ab19-9fdca5b50c1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291571566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3291571566
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1136301950
Short name T1184
Test name
Test status
Simulation time 31880407 ps
CPU time 0.65 seconds
Started Aug 05 04:21:56 PM PDT 24
Finished Aug 05 04:21:57 PM PDT 24
Peak memory 196880 kb
Host smart-d92bfd50-1608-4080-97f1-fbe106feaa0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136301950 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1136301950
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3784261593
Short name T1265
Test name
Test status
Simulation time 31889403 ps
CPU time 0.61 seconds
Started Aug 05 04:21:36 PM PDT 24
Finished Aug 05 04:21:37 PM PDT 24
Peak memory 195696 kb
Host smart-3b102657-c9b3-40df-8db7-02c7828f21a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784261593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3784261593
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3017185332
Short name T1230
Test name
Test status
Simulation time 11143332 ps
CPU time 0.55 seconds
Started Aug 05 04:22:12 PM PDT 24
Finished Aug 05 04:22:13 PM PDT 24
Peak memory 194604 kb
Host smart-2a15a9cd-b749-40c1-8718-ebe0a79b2f12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017185332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3017185332
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2754025168
Short name T1226
Test name
Test status
Simulation time 26898514 ps
CPU time 0.74 seconds
Started Aug 05 04:21:36 PM PDT 24
Finished Aug 05 04:21:37 PM PDT 24
Peak memory 197300 kb
Host smart-db6c73fd-5954-4186-9afc-2318906f01d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754025168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2754025168
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2761749859
Short name T1200
Test name
Test status
Simulation time 99001667 ps
CPU time 2.01 seconds
Started Aug 05 04:21:34 PM PDT 24
Finished Aug 05 04:21:36 PM PDT 24
Peak memory 200268 kb
Host smart-dd3b3231-f02c-40ff-9a83-8ba7001aa1c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761749859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2761749859
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.4164762979
Short name T104
Test name
Test status
Simulation time 89603732 ps
CPU time 1.29 seconds
Started Aug 05 04:19:56 PM PDT 24
Finished Aug 05 04:19:57 PM PDT 24
Peak memory 199348 kb
Host smart-854dc2c3-404b-4aca-86c8-7e0b5cca8c1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164762979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.4164762979
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2958785159
Short name T1263
Test name
Test status
Simulation time 26170470 ps
CPU time 0.77 seconds
Started Aug 05 04:21:36 PM PDT 24
Finished Aug 05 04:21:37 PM PDT 24
Peak memory 199984 kb
Host smart-26b65bba-819e-4bb4-8aaa-424c6f62303d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958785159 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2958785159
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1444067063
Short name T1189
Test name
Test status
Simulation time 14831542 ps
CPU time 0.58 seconds
Started Aug 05 04:21:47 PM PDT 24
Finished Aug 05 04:21:48 PM PDT 24
Peak memory 195600 kb
Host smart-b713b517-4af3-48bf-9d5e-e6b26dea3b2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444067063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1444067063
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1442464181
Short name T1254
Test name
Test status
Simulation time 58657796 ps
CPU time 0.55 seconds
Started Aug 05 04:21:47 PM PDT 24
Finished Aug 05 04:21:48 PM PDT 24
Peak memory 194592 kb
Host smart-a675ed3f-5eaf-41af-b16b-dbb482980152
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442464181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1442464181
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3581886425
Short name T1298
Test name
Test status
Simulation time 31886608 ps
CPU time 0.7 seconds
Started Aug 05 04:21:36 PM PDT 24
Finished Aug 05 04:21:37 PM PDT 24
Peak memory 197124 kb
Host smart-df25fa68-dfac-406f-8681-4b15c71ed26c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581886425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3581886425
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3567455490
Short name T1252
Test name
Test status
Simulation time 80927224 ps
CPU time 1.25 seconds
Started Aug 05 04:21:43 PM PDT 24
Finished Aug 05 04:21:45 PM PDT 24
Peak memory 199348 kb
Host smart-4d568a9c-e464-477c-8ce8-8f80dcfc2f18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567455490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3567455490
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.60013481
Short name T1304
Test name
Test status
Simulation time 274795335 ps
CPU time 0.94 seconds
Started Aug 05 04:19:19 PM PDT 24
Finished Aug 05 04:19:20 PM PDT 24
Peak memory 200124 kb
Host smart-b913335e-dea1-4476-b13c-8552dc720b43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60013481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.60013481
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1861771555
Short name T1217
Test name
Test status
Simulation time 170785869 ps
CPU time 0.65 seconds
Started Aug 05 04:22:13 PM PDT 24
Finished Aug 05 04:22:13 PM PDT 24
Peak memory 197484 kb
Host smart-5873a83d-5fe5-433f-8379-52d2d38fa3ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861771555 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1861771555
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3087900941
Short name T1227
Test name
Test status
Simulation time 15951854 ps
CPU time 0.64 seconds
Started Aug 05 04:21:20 PM PDT 24
Finished Aug 05 04:21:22 PM PDT 24
Peak memory 194816 kb
Host smart-87c10fd9-d46e-4e7a-9bee-ef5105544d9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087900941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3087900941
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.31710851
Short name T1196
Test name
Test status
Simulation time 15525288 ps
CPU time 0.59 seconds
Started Aug 05 04:19:17 PM PDT 24
Finished Aug 05 04:19:17 PM PDT 24
Peak memory 194460 kb
Host smart-1b67377d-05a4-46c7-b9f4-0b1469047e84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31710851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.31710851
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4133645975
Short name T1241
Test name
Test status
Simulation time 25719058 ps
CPU time 0.83 seconds
Started Aug 05 04:21:19 PM PDT 24
Finished Aug 05 04:21:20 PM PDT 24
Peak memory 195092 kb
Host smart-70c83090-c039-42ae-9a32-e0b1606241cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133645975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.4133645975
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2906032318
Short name T1287
Test name
Test status
Simulation time 63157972 ps
CPU time 1.38 seconds
Started Aug 05 04:21:47 PM PDT 24
Finished Aug 05 04:21:48 PM PDT 24
Peak memory 200240 kb
Host smart-86a97e68-cb2f-4684-9714-8c4d07feb91f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906032318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2906032318
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3993451980
Short name T102
Test name
Test status
Simulation time 40416655 ps
CPU time 0.93 seconds
Started Aug 05 04:19:17 PM PDT 24
Finished Aug 05 04:19:18 PM PDT 24
Peak memory 199792 kb
Host smart-c4a86e3a-7c99-4e05-a905-33f6b29e9c1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993451980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3993451980
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3282984038
Short name T1186
Test name
Test status
Simulation time 17377497 ps
CPU time 0.65 seconds
Started Aug 05 04:22:13 PM PDT 24
Finished Aug 05 04:22:13 PM PDT 24
Peak memory 198056 kb
Host smart-e2d608c5-fa6f-44ae-83f8-87b161949686
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282984038 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3282984038
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.797559479
Short name T1259
Test name
Test status
Simulation time 13133699 ps
CPU time 0.6 seconds
Started Aug 05 04:22:12 PM PDT 24
Finished Aug 05 04:22:13 PM PDT 24
Peak memory 195608 kb
Host smart-6fe891e5-84c2-474d-a734-8f03aff96741
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797559479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.797559479
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.4078117383
Short name T1190
Test name
Test status
Simulation time 46177666 ps
CPU time 0.56 seconds
Started Aug 05 04:22:13 PM PDT 24
Finished Aug 05 04:22:13 PM PDT 24
Peak memory 194608 kb
Host smart-53322f28-0343-4243-9e9f-4b95c6edbf52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078117383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.4078117383
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2844664382
Short name T92
Test name
Test status
Simulation time 12344626 ps
CPU time 0.68 seconds
Started Aug 05 04:19:28 PM PDT 24
Finished Aug 05 04:19:29 PM PDT 24
Peak memory 195844 kb
Host smart-f4eb9970-ae7d-4bbc-8736-ed7f932a0611
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844664382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2844664382
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1045072805
Short name T1293
Test name
Test status
Simulation time 46778844 ps
CPU time 1.01 seconds
Started Aug 05 04:19:26 PM PDT 24
Finished Aug 05 04:19:27 PM PDT 24
Peak memory 200016 kb
Host smart-9532868e-f5ff-40e6-8093-05e7b42564f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045072805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1045072805
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1800234695
Short name T137
Test name
Test status
Simulation time 256725784 ps
CPU time 1.28 seconds
Started Aug 05 04:21:19 PM PDT 24
Finished Aug 05 04:21:21 PM PDT 24
Peak memory 198652 kb
Host smart-865cc753-cc7b-426d-873d-00c63d0a2081
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800234695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1800234695
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.899784438
Short name T1234
Test name
Test status
Simulation time 24501210 ps
CPU time 0.71 seconds
Started Aug 05 04:21:43 PM PDT 24
Finished Aug 05 04:21:43 PM PDT 24
Peak memory 198672 kb
Host smart-04e3ae04-b822-4917-b47c-2877194aa5f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899784438 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.899784438
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3702498476
Short name T1302
Test name
Test status
Simulation time 27343733 ps
CPU time 0.55 seconds
Started Aug 05 04:21:43 PM PDT 24
Finished Aug 05 04:21:44 PM PDT 24
Peak memory 195612 kb
Host smart-e8172e55-d98b-40f4-940e-e12afa26ca1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702498476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3702498476
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3298350029
Short name T1285
Test name
Test status
Simulation time 24256830 ps
CPU time 0.59 seconds
Started Aug 05 04:21:20 PM PDT 24
Finished Aug 05 04:21:21 PM PDT 24
Peak memory 192732 kb
Host smart-114380cf-f0ed-4cb6-979d-38733a8f5ac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298350029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3298350029
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1735874115
Short name T90
Test name
Test status
Simulation time 59830146 ps
CPU time 0.69 seconds
Started Aug 05 04:21:28 PM PDT 24
Finished Aug 05 04:21:29 PM PDT 24
Peak memory 195800 kb
Host smart-6e505181-979b-4564-9f20-9dc67d51a935
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735874115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1735874115
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1323422395
Short name T1249
Test name
Test status
Simulation time 135973731 ps
CPU time 1.14 seconds
Started Aug 05 04:21:34 PM PDT 24
Finished Aug 05 04:21:35 PM PDT 24
Peak memory 200232 kb
Host smart-f5b2c10d-2770-4c2d-8b71-c8afe6dc1527
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323422395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1323422395
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1824023232
Short name T1271
Test name
Test status
Simulation time 83798077 ps
CPU time 1.26 seconds
Started Aug 05 04:22:12 PM PDT 24
Finished Aug 05 04:22:14 PM PDT 24
Peak memory 199612 kb
Host smart-399454a1-1265-4f8c-b8e3-32fc1407f973
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824023232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1824023232
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1364173408
Short name T1273
Test name
Test status
Simulation time 23019201 ps
CPU time 1 seconds
Started Aug 05 04:21:20 PM PDT 24
Finished Aug 05 04:21:22 PM PDT 24
Peak memory 198092 kb
Host smart-8b55f7b1-9264-40f3-8fb8-67aebbd7c2a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364173408 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1364173408
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1012462323
Short name T1267
Test name
Test status
Simulation time 19687127 ps
CPU time 0.57 seconds
Started Aug 05 04:20:08 PM PDT 24
Finished Aug 05 04:20:09 PM PDT 24
Peak memory 195616 kb
Host smart-a10181b4-e5c3-4f65-ba8f-75f02331e1d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012462323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1012462323
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.144742735
Short name T1250
Test name
Test status
Simulation time 12804890 ps
CPU time 0.57 seconds
Started Aug 05 04:21:21 PM PDT 24
Finished Aug 05 04:21:22 PM PDT 24
Peak memory 194468 kb
Host smart-85b259d2-6f4c-4051-9644-5afd597fb9ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144742735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.144742735
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1875160748
Short name T1313
Test name
Test status
Simulation time 52953158 ps
CPU time 0.68 seconds
Started Aug 05 04:21:55 PM PDT 24
Finished Aug 05 04:21:56 PM PDT 24
Peak memory 194876 kb
Host smart-72eb6593-e560-48e6-b583-2859e732ef44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875160748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1875160748
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2868151196
Short name T1238
Test name
Test status
Simulation time 80015685 ps
CPU time 1.77 seconds
Started Aug 05 04:21:20 PM PDT 24
Finished Aug 05 04:21:23 PM PDT 24
Peak memory 198172 kb
Host smart-c24fe77c-92a4-44fb-bb4c-3f6068200eb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868151196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2868151196
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2923732922
Short name T1223
Test name
Test status
Simulation time 84962748 ps
CPU time 1.04 seconds
Started Aug 05 04:21:44 PM PDT 24
Finished Aug 05 04:21:45 PM PDT 24
Peak memory 200048 kb
Host smart-0588a2b1-5cd9-465e-9d2f-af88caa9123f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923732922 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2923732922
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.2828043281
Short name T1236
Test name
Test status
Simulation time 71428602 ps
CPU time 0.63 seconds
Started Aug 05 04:19:47 PM PDT 24
Finished Aug 05 04:19:48 PM PDT 24
Peak memory 196024 kb
Host smart-1f9e454c-aa32-4282-bd7a-8bfcbcee997e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828043281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2828043281
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3965813721
Short name T1204
Test name
Test status
Simulation time 13917116 ps
CPU time 0.6 seconds
Started Aug 05 04:21:20 PM PDT 24
Finished Aug 05 04:21:21 PM PDT 24
Peak memory 192484 kb
Host smart-d8ab6867-85c0-444d-889a-200d2db94a53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965813721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3965813721
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1539136121
Short name T93
Test name
Test status
Simulation time 47717887 ps
CPU time 0.63 seconds
Started Aug 05 04:21:44 PM PDT 24
Finished Aug 05 04:21:44 PM PDT 24
Peak memory 196664 kb
Host smart-16e03db8-38c0-49f7-9bf9-4449ceb71662
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539136121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.1539136121
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1836709083
Short name T1235
Test name
Test status
Simulation time 829319105 ps
CPU time 1.54 seconds
Started Aug 05 04:21:20 PM PDT 24
Finished Aug 05 04:21:22 PM PDT 24
Peak memory 198468 kb
Host smart-ed60e65d-5a39-4b15-900f-6f9df4a7de19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836709083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1836709083
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.827557023
Short name T136
Test name
Test status
Simulation time 156026548 ps
CPU time 1.25 seconds
Started Aug 05 04:21:33 PM PDT 24
Finished Aug 05 04:21:34 PM PDT 24
Peak memory 199208 kb
Host smart-9f8b399b-8b35-4b66-8e8a-3af7378d5e81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827557023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.827557023
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1922615715
Short name T1201
Test name
Test status
Simulation time 43101311 ps
CPU time 0.74 seconds
Started Aug 05 04:21:38 PM PDT 24
Finished Aug 05 04:21:39 PM PDT 24
Peak memory 198156 kb
Host smart-42be93e3-1bb6-45b6-b583-64d187d46c9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922615715 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1922615715
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.4114660670
Short name T1290
Test name
Test status
Simulation time 15136511 ps
CPU time 0.57 seconds
Started Aug 05 04:21:52 PM PDT 24
Finished Aug 05 04:21:52 PM PDT 24
Peak memory 195520 kb
Host smart-d8e23184-ad39-46fe-9292-f97c47adbdd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114660670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.4114660670
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2034863539
Short name T1218
Test name
Test status
Simulation time 12306476 ps
CPU time 0.56 seconds
Started Aug 05 04:21:33 PM PDT 24
Finished Aug 05 04:21:34 PM PDT 24
Peak memory 194568 kb
Host smart-b26bfeb5-d7dc-4b20-be46-b948db139571
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034863539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2034863539
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.979921783
Short name T1289
Test name
Test status
Simulation time 15175476 ps
CPU time 0.68 seconds
Started Aug 05 04:21:38 PM PDT 24
Finished Aug 05 04:21:39 PM PDT 24
Peak memory 194468 kb
Host smart-03162c08-8b6f-4686-96aa-c7c7201e4f24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979921783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.979921783
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3565445438
Short name T1225
Test name
Test status
Simulation time 215637069 ps
CPU time 1.33 seconds
Started Aug 05 04:21:43 PM PDT 24
Finished Aug 05 04:21:44 PM PDT 24
Peak memory 200276 kb
Host smart-30f4cf89-6730-40bc-8570-a58618560ca1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565445438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3565445438
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1687503297
Short name T1288
Test name
Test status
Simulation time 271891123 ps
CPU time 1.24 seconds
Started Aug 05 04:21:28 PM PDT 24
Finished Aug 05 04:21:29 PM PDT 24
Peak memory 198648 kb
Host smart-8d30bea5-d6d8-43d2-86ea-52b41ea7be11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687503297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1687503297
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3097425313
Short name T1272
Test name
Test status
Simulation time 44067257 ps
CPU time 0.72 seconds
Started Aug 05 04:21:56 PM PDT 24
Finished Aug 05 04:21:57 PM PDT 24
Peak memory 196560 kb
Host smart-48c2aabd-8032-42d3-a909-02ed2b45df63
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097425313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3097425313
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.4254423017
Short name T1295
Test name
Test status
Simulation time 336107760 ps
CPU time 2.38 seconds
Started Aug 05 04:21:56 PM PDT 24
Finished Aug 05 04:21:58 PM PDT 24
Peak memory 197844 kb
Host smart-7475c8c1-13bd-4196-83d9-94b45111df61
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254423017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.4254423017
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3554121209
Short name T69
Test name
Test status
Simulation time 16388386 ps
CPU time 0.62 seconds
Started Aug 05 04:21:40 PM PDT 24
Finished Aug 05 04:21:41 PM PDT 24
Peak memory 194808 kb
Host smart-6a65d65c-6bd4-465e-be63-5f3f3c38b931
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554121209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3554121209
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.856574754
Short name T1203
Test name
Test status
Simulation time 27756393 ps
CPU time 1.3 seconds
Started Aug 05 04:22:05 PM PDT 24
Finished Aug 05 04:22:07 PM PDT 24
Peak memory 200116 kb
Host smart-c7857ff1-11ef-4f40-888b-119b646cd7ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856574754 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.856574754
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.256901372
Short name T1242
Test name
Test status
Simulation time 13196457 ps
CPU time 0.55 seconds
Started Aug 05 04:22:05 PM PDT 24
Finished Aug 05 04:22:06 PM PDT 24
Peak memory 194492 kb
Host smart-0784e377-bd78-4af0-9353-97556178856a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256901372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.256901372
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2572964631
Short name T1286
Test name
Test status
Simulation time 20262441 ps
CPU time 0.66 seconds
Started Aug 05 04:21:56 PM PDT 24
Finished Aug 05 04:21:57 PM PDT 24
Peak memory 196792 kb
Host smart-8741913b-f13c-48df-8023-7c91259961a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572964631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2572964631
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.4255619711
Short name T1209
Test name
Test status
Simulation time 101182444 ps
CPU time 1.59 seconds
Started Aug 05 04:22:25 PM PDT 24
Finished Aug 05 04:22:26 PM PDT 24
Peak memory 200260 kb
Host smart-6b7b127c-3835-4bdc-80da-f93eec0370f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255619711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.4255619711
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.926595605
Short name T1279
Test name
Test status
Simulation time 88984810 ps
CPU time 1.29 seconds
Started Aug 05 04:21:53 PM PDT 24
Finished Aug 05 04:21:55 PM PDT 24
Peak memory 199548 kb
Host smart-06fcf601-1aa7-45e6-afac-2281cd76387e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926595605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.926595605
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.843039905
Short name T1314
Test name
Test status
Simulation time 13447459 ps
CPU time 0.58 seconds
Started Aug 05 04:19:49 PM PDT 24
Finished Aug 05 04:19:50 PM PDT 24
Peak memory 194604 kb
Host smart-6ecb090f-4a79-4afb-9282-57165b97194f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843039905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.843039905
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.283418629
Short name T1264
Test name
Test status
Simulation time 15015659 ps
CPU time 0.57 seconds
Started Aug 05 04:22:04 PM PDT 24
Finished Aug 05 04:22:05 PM PDT 24
Peak memory 193532 kb
Host smart-9133af9c-0f23-41c6-8319-3398e0efac24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283418629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.283418629
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.149988402
Short name T1310
Test name
Test status
Simulation time 15039462 ps
CPU time 0.55 seconds
Started Aug 05 04:21:39 PM PDT 24
Finished Aug 05 04:21:39 PM PDT 24
Peak memory 194300 kb
Host smart-714cf3a6-fad8-4a30-ab12-6be9a42022c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149988402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.149988402
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3202424703
Short name T1255
Test name
Test status
Simulation time 22882731 ps
CPU time 0.57 seconds
Started Aug 05 04:21:34 PM PDT 24
Finished Aug 05 04:21:35 PM PDT 24
Peak memory 194580 kb
Host smart-03dbf8cb-34f5-48ef-adad-f605ff788c9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202424703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3202424703
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1131000825
Short name T1266
Test name
Test status
Simulation time 11624394 ps
CPU time 0.54 seconds
Started Aug 05 04:21:52 PM PDT 24
Finished Aug 05 04:21:52 PM PDT 24
Peak memory 194508 kb
Host smart-3b64023a-2eb2-49a8-a53f-a68c2579c22e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131000825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1131000825
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3596675411
Short name T1213
Test name
Test status
Simulation time 14416875 ps
CPU time 0.62 seconds
Started Aug 05 04:22:04 PM PDT 24
Finished Aug 05 04:22:05 PM PDT 24
Peak memory 193628 kb
Host smart-68ab8a85-ef78-41ea-b593-da95b7dcbf2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596675411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3596675411
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3166002525
Short name T1214
Test name
Test status
Simulation time 17273186 ps
CPU time 0.61 seconds
Started Aug 05 04:21:38 PM PDT 24
Finished Aug 05 04:21:39 PM PDT 24
Peak memory 193304 kb
Host smart-a15ea385-71e6-43f7-8340-8f11380f0faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166002525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3166002525
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3389800064
Short name T1312
Test name
Test status
Simulation time 29189104 ps
CPU time 0.6 seconds
Started Aug 05 04:19:58 PM PDT 24
Finished Aug 05 04:19:59 PM PDT 24
Peak memory 194628 kb
Host smart-a19ba1bb-ef21-4834-8ccd-ddee725a1885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389800064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3389800064
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1552795870
Short name T1198
Test name
Test status
Simulation time 41695846 ps
CPU time 0.58 seconds
Started Aug 05 04:21:39 PM PDT 24
Finished Aug 05 04:21:39 PM PDT 24
Peak memory 194356 kb
Host smart-ebf6d079-5804-4dfd-92f9-36dab4bafb59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552795870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1552795870
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.985515274
Short name T1284
Test name
Test status
Simulation time 74941942 ps
CPU time 0.55 seconds
Started Aug 05 04:21:19 PM PDT 24
Finished Aug 05 04:21:20 PM PDT 24
Peak memory 194004 kb
Host smart-46e10571-39e8-4b45-9dc4-5c58d04b8d2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985515274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.985515274
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1774320356
Short name T72
Test name
Test status
Simulation time 50771555 ps
CPU time 0.77 seconds
Started Aug 05 04:22:12 PM PDT 24
Finished Aug 05 04:22:13 PM PDT 24
Peak memory 196504 kb
Host smart-6378030b-e0d3-450b-adaf-840eebc43761
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774320356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1774320356
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3314743796
Short name T74
Test name
Test status
Simulation time 786681596 ps
CPU time 2.56 seconds
Started Aug 05 04:18:48 PM PDT 24
Finished Aug 05 04:18:51 PM PDT 24
Peak memory 197924 kb
Host smart-6fad48eb-16c5-4abe-9688-148a3eaf6b04
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314743796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3314743796
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2157159309
Short name T71
Test name
Test status
Simulation time 34830479 ps
CPU time 0.57 seconds
Started Aug 05 04:21:56 PM PDT 24
Finished Aug 05 04:21:56 PM PDT 24
Peak memory 195580 kb
Host smart-78247ee3-be38-432d-a1b1-955bfcdd5ff0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157159309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2157159309
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3492247229
Short name T1215
Test name
Test status
Simulation time 21335935 ps
CPU time 1.05 seconds
Started Aug 05 04:21:56 PM PDT 24
Finished Aug 05 04:21:58 PM PDT 24
Peak memory 199968 kb
Host smart-a0eb0ede-eab7-4b38-a2d8-64142d23524c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492247229 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3492247229
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2074425750
Short name T1283
Test name
Test status
Simulation time 15750122 ps
CPU time 0.59 seconds
Started Aug 05 04:22:06 PM PDT 24
Finished Aug 05 04:22:06 PM PDT 24
Peak memory 195672 kb
Host smart-2d48b2e8-1932-49d8-8ce0-6417c3f2a82b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074425750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2074425750
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2496137167
Short name T1256
Test name
Test status
Simulation time 13806091 ps
CPU time 0.56 seconds
Started Aug 05 04:22:06 PM PDT 24
Finished Aug 05 04:22:06 PM PDT 24
Peak memory 194584 kb
Host smart-d1848c5b-62e9-460d-9e45-0b4828ec2b0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496137167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2496137167
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1993085025
Short name T1233
Test name
Test status
Simulation time 252763243 ps
CPU time 0.63 seconds
Started Aug 05 04:21:40 PM PDT 24
Finished Aug 05 04:21:41 PM PDT 24
Peak memory 194880 kb
Host smart-56603b67-50c7-4f8f-8533-92b2959c7ff2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993085025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1993085025
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.4274556160
Short name T1262
Test name
Test status
Simulation time 80362021 ps
CPU time 1.6 seconds
Started Aug 05 04:21:56 PM PDT 24
Finished Aug 05 04:21:58 PM PDT 24
Peak memory 200204 kb
Host smart-2a1451a2-c795-450c-8edd-491e5f8b749a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274556160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.4274556160
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3479716731
Short name T1294
Test name
Test status
Simulation time 46071233 ps
CPU time 0.58 seconds
Started Aug 05 04:21:20 PM PDT 24
Finished Aug 05 04:21:20 PM PDT 24
Peak memory 194392 kb
Host smart-9f59ba79-3df3-4d3c-b907-c0565495a1de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479716731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3479716731
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2237596215
Short name T1297
Test name
Test status
Simulation time 84638876 ps
CPU time 0.59 seconds
Started Aug 05 04:21:19 PM PDT 24
Finished Aug 05 04:21:20 PM PDT 24
Peak memory 192548 kb
Host smart-567f3ff6-f743-4d66-8a1a-aecc9388f77f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237596215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2237596215
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1636623393
Short name T1299
Test name
Test status
Simulation time 32898288 ps
CPU time 0.55 seconds
Started Aug 05 04:21:34 PM PDT 24
Finished Aug 05 04:21:34 PM PDT 24
Peak memory 194536 kb
Host smart-8539ae60-9d6c-4c33-a8a6-543ddc69c382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636623393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1636623393
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.4206292846
Short name T1207
Test name
Test status
Simulation time 14775425 ps
CPU time 0.6 seconds
Started Aug 05 04:21:43 PM PDT 24
Finished Aug 05 04:21:45 PM PDT 24
Peak memory 193804 kb
Host smart-42764948-db34-487a-ba69-56d8769cba9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206292846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.4206292846
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.744360220
Short name T1228
Test name
Test status
Simulation time 19953193 ps
CPU time 0.55 seconds
Started Aug 05 04:21:19 PM PDT 24
Finished Aug 05 04:21:20 PM PDT 24
Peak memory 192840 kb
Host smart-c9670ae7-42b9-49ec-89c3-712878a6826d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744360220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.744360220
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.4045364142
Short name T1268
Test name
Test status
Simulation time 30346821 ps
CPU time 0.62 seconds
Started Aug 05 04:21:45 PM PDT 24
Finished Aug 05 04:21:45 PM PDT 24
Peak memory 194596 kb
Host smart-e1445a7d-9115-4d7a-94b4-d6e18773b915
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045364142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.4045364142
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.458278529
Short name T1221
Test name
Test status
Simulation time 32862637 ps
CPU time 0.55 seconds
Started Aug 05 04:21:19 PM PDT 24
Finished Aug 05 04:21:20 PM PDT 24
Peak memory 192432 kb
Host smart-ddfb54e2-9ff5-4076-82d6-888226ac65ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458278529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.458278529
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1093930492
Short name T1208
Test name
Test status
Simulation time 30147735 ps
CPU time 0.55 seconds
Started Aug 05 04:21:35 PM PDT 24
Finished Aug 05 04:21:35 PM PDT 24
Peak memory 194588 kb
Host smart-72b3e1ac-60e2-4ae5-ab55-47b4d0f212f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093930492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1093930492
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1359941687
Short name T1258
Test name
Test status
Simulation time 56507073 ps
CPU time 0.58 seconds
Started Aug 05 04:21:31 PM PDT 24
Finished Aug 05 04:21:32 PM PDT 24
Peak memory 193252 kb
Host smart-7b9e2efb-8bf4-4e14-8f2d-b5c63478d10f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359941687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1359941687
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2292603089
Short name T1311
Test name
Test status
Simulation time 14218207 ps
CPU time 0.59 seconds
Started Aug 05 04:21:21 PM PDT 24
Finished Aug 05 04:21:22 PM PDT 24
Peak memory 193724 kb
Host smart-0c3ef00d-deee-4517-94fc-346537c19497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292603089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2292603089
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1027414817
Short name T1306
Test name
Test status
Simulation time 73040703 ps
CPU time 0.71 seconds
Started Aug 05 04:19:19 PM PDT 24
Finished Aug 05 04:19:20 PM PDT 24
Peak memory 195616 kb
Host smart-03da3c60-078c-4c7b-aa17-47a0eb2d80db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027414817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1027414817
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1155903299
Short name T1219
Test name
Test status
Simulation time 106572497 ps
CPU time 1.44 seconds
Started Aug 05 04:21:46 PM PDT 24
Finished Aug 05 04:21:48 PM PDT 24
Peak memory 197772 kb
Host smart-071d06f3-5403-4b73-a03f-fe0ff2bc9986
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155903299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1155903299
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1396853705
Short name T1192
Test name
Test status
Simulation time 13789567 ps
CPU time 0.57 seconds
Started Aug 05 04:19:51 PM PDT 24
Finished Aug 05 04:19:52 PM PDT 24
Peak memory 195676 kb
Host smart-291bf474-2a38-44ea-bc48-07b9d4280f43
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396853705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1396853705
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3451636455
Short name T1206
Test name
Test status
Simulation time 34421892 ps
CPU time 0.78 seconds
Started Aug 05 04:22:31 PM PDT 24
Finished Aug 05 04:22:31 PM PDT 24
Peak memory 199288 kb
Host smart-49783071-d565-4fd1-baf6-5ced4b41dc7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451636455 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3451636455
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.274376750
Short name T1274
Test name
Test status
Simulation time 14278363 ps
CPU time 0.61 seconds
Started Aug 05 04:22:14 PM PDT 24
Finished Aug 05 04:22:15 PM PDT 24
Peak memory 195736 kb
Host smart-df4c9081-d7e6-4cdf-891b-821f88baf3e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274376750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.274376750
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.667069982
Short name T1210
Test name
Test status
Simulation time 14481897 ps
CPU time 0.57 seconds
Started Aug 05 04:22:14 PM PDT 24
Finished Aug 05 04:22:14 PM PDT 24
Peak memory 194600 kb
Host smart-8a2e511e-9800-42ef-a90c-d43c82ee3980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667069982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.667069982
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3547357993
Short name T1224
Test name
Test status
Simulation time 23727616 ps
CPU time 0.78 seconds
Started Aug 05 04:22:51 PM PDT 24
Finished Aug 05 04:22:52 PM PDT 24
Peak memory 196876 kb
Host smart-756ca62e-ccc6-454c-b77b-3f1c9cfbfca5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547357993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3547357993
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2193408652
Short name T1211
Test name
Test status
Simulation time 126520627 ps
CPU time 0.97 seconds
Started Aug 05 04:21:46 PM PDT 24
Finished Aug 05 04:21:47 PM PDT 24
Peak memory 199804 kb
Host smart-2bdddb9f-4599-4688-a684-c6fa40a25993
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193408652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2193408652
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.467537102
Short name T1232
Test name
Test status
Simulation time 153561444 ps
CPU time 0.96 seconds
Started Aug 05 04:19:53 PM PDT 24
Finished Aug 05 04:19:54 PM PDT 24
Peak memory 199068 kb
Host smart-5cad254a-2b59-4da9-92a5-7fd2b5943750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467537102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.467537102
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3661776340
Short name T1229
Test name
Test status
Simulation time 100465171 ps
CPU time 0.58 seconds
Started Aug 05 04:20:05 PM PDT 24
Finished Aug 05 04:20:06 PM PDT 24
Peak memory 194532 kb
Host smart-514b82e6-a388-478f-9974-8f692baea483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661776340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3661776340
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1587824264
Short name T1239
Test name
Test status
Simulation time 25154051 ps
CPU time 0.56 seconds
Started Aug 05 04:21:33 PM PDT 24
Finished Aug 05 04:21:34 PM PDT 24
Peak memory 194592 kb
Host smart-62519080-0d1b-47ad-a40c-f21a8901cfd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587824264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1587824264
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1947089381
Short name T1188
Test name
Test status
Simulation time 12447347 ps
CPU time 0.57 seconds
Started Aug 05 04:21:47 PM PDT 24
Finished Aug 05 04:21:48 PM PDT 24
Peak memory 194592 kb
Host smart-4d871ddf-fbbc-45a4-82cf-a61bbd7744b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947089381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1947089381
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.4282186714
Short name T1193
Test name
Test status
Simulation time 16745632 ps
CPU time 0.64 seconds
Started Aug 05 04:20:03 PM PDT 24
Finished Aug 05 04:20:04 PM PDT 24
Peak memory 194612 kb
Host smart-a1b239b5-232c-43d1-81bb-07cba529d991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282186714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.4282186714
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.624715984
Short name T1245
Test name
Test status
Simulation time 21174309 ps
CPU time 0.57 seconds
Started Aug 05 04:21:34 PM PDT 24
Finished Aug 05 04:21:34 PM PDT 24
Peak memory 194532 kb
Host smart-a13c6c4e-2708-491d-ae90-844a9705dd16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624715984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.624715984
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1141538713
Short name T1216
Test name
Test status
Simulation time 42044206 ps
CPU time 0.62 seconds
Started Aug 05 04:21:19 PM PDT 24
Finished Aug 05 04:21:20 PM PDT 24
Peak memory 192644 kb
Host smart-cf1485ac-1849-48b8-a02e-fe81da4d0395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141538713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1141538713
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.371297218
Short name T1278
Test name
Test status
Simulation time 23225749 ps
CPU time 0.58 seconds
Started Aug 05 04:21:31 PM PDT 24
Finished Aug 05 04:21:32 PM PDT 24
Peak memory 193056 kb
Host smart-99499ee4-1459-41c4-8c08-e36e54f07b1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371297218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.371297218
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.160702731
Short name T1307
Test name
Test status
Simulation time 12088541 ps
CPU time 0.59 seconds
Started Aug 05 04:21:31 PM PDT 24
Finished Aug 05 04:21:32 PM PDT 24
Peak memory 193060 kb
Host smart-31f5d287-fa97-4458-87c0-5d6bb20a9b02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160702731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.160702731
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.289212637
Short name T1308
Test name
Test status
Simulation time 30732903 ps
CPU time 0.57 seconds
Started Aug 05 04:21:44 PM PDT 24
Finished Aug 05 04:21:45 PM PDT 24
Peak memory 194496 kb
Host smart-aa838295-d7cd-484c-b653-9ec6aff5576e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289212637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.289212637
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3508535605
Short name T1316
Test name
Test status
Simulation time 118127849 ps
CPU time 0.56 seconds
Started Aug 05 04:21:44 PM PDT 24
Finished Aug 05 04:21:44 PM PDT 24
Peak memory 193744 kb
Host smart-6d8d85b2-53d5-4af0-a688-af033a55e3aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508535605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3508535605
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1047289959
Short name T1195
Test name
Test status
Simulation time 98021221 ps
CPU time 1.12 seconds
Started Aug 05 04:22:21 PM PDT 24
Finished Aug 05 04:22:22 PM PDT 24
Peak memory 200280 kb
Host smart-2ac4113e-fd18-43b0-8373-a92cecfbfe39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047289959 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1047289959
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1625225684
Short name T1244
Test name
Test status
Simulation time 222972968 ps
CPU time 0.62 seconds
Started Aug 05 04:20:23 PM PDT 24
Finished Aug 05 04:20:24 PM PDT 24
Peak memory 195728 kb
Host smart-15ad0ea0-2933-4c06-9e2c-bcdc6d35835e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625225684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1625225684
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1506046001
Short name T1185
Test name
Test status
Simulation time 10409807 ps
CPU time 0.57 seconds
Started Aug 05 04:22:03 PM PDT 24
Finished Aug 05 04:22:04 PM PDT 24
Peak memory 193728 kb
Host smart-45136ad8-635a-407d-89a0-2a642cb96bd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506046001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1506046001
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1244101052
Short name T1281
Test name
Test status
Simulation time 17501668 ps
CPU time 0.74 seconds
Started Aug 05 04:22:29 PM PDT 24
Finished Aug 05 04:22:30 PM PDT 24
Peak memory 196412 kb
Host smart-819246c7-b6f9-4eb3-b19a-f3e36f75239f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244101052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1244101052
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2894926121
Short name T1253
Test name
Test status
Simulation time 71113637 ps
CPU time 1.23 seconds
Started Aug 05 04:18:47 PM PDT 24
Finished Aug 05 04:18:48 PM PDT 24
Peak memory 200160 kb
Host smart-2ef47560-5253-446b-a932-9959a60428e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894926121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2894926121
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.4051342062
Short name T138
Test name
Test status
Simulation time 177100881 ps
CPU time 1.03 seconds
Started Aug 05 04:18:41 PM PDT 24
Finished Aug 05 04:18:42 PM PDT 24
Peak memory 199068 kb
Host smart-23af5383-da56-4273-93b8-cf6951d7b953
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051342062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.4051342062
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1738862532
Short name T1305
Test name
Test status
Simulation time 188325940 ps
CPU time 0.79 seconds
Started Aug 05 04:22:29 PM PDT 24
Finished Aug 05 04:22:30 PM PDT 24
Peak memory 199800 kb
Host smart-0e0432a7-66b1-4b69-867f-25b35f284131
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738862532 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1738862532
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2448343959
Short name T75
Test name
Test status
Simulation time 13085838 ps
CPU time 0.59 seconds
Started Aug 05 04:21:52 PM PDT 24
Finished Aug 05 04:21:53 PM PDT 24
Peak memory 195412 kb
Host smart-72c9eff2-9aa2-448b-9c11-43c6ef75135a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448343959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2448343959
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3082972817
Short name T1303
Test name
Test status
Simulation time 46278843 ps
CPU time 0.57 seconds
Started Aug 05 04:22:31 PM PDT 24
Finished Aug 05 04:22:31 PM PDT 24
Peak memory 194604 kb
Host smart-dc98ef4b-3553-44c4-b581-290934e93760
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082972817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3082972817
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.317992766
Short name T94
Test name
Test status
Simulation time 50096374 ps
CPU time 0.79 seconds
Started Aug 05 04:22:30 PM PDT 24
Finished Aug 05 04:22:31 PM PDT 24
Peak memory 198232 kb
Host smart-360c359d-7cd8-4baf-8665-edf1f0dedbea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317992766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.317992766
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2864461508
Short name T1243
Test name
Test status
Simulation time 143045299 ps
CPU time 2.29 seconds
Started Aug 05 04:19:08 PM PDT 24
Finished Aug 05 04:19:11 PM PDT 24
Peak memory 200296 kb
Host smart-e46296d4-4826-4783-be65-8ef86ac39d43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864461508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2864461508
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.875461569
Short name T98
Test name
Test status
Simulation time 424502840 ps
CPU time 1.01 seconds
Started Aug 05 04:19:11 PM PDT 24
Finished Aug 05 04:19:13 PM PDT 24
Peak memory 199324 kb
Host smart-08af856b-1089-4159-ae1b-d5bfb0c81b62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875461569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.875461569
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.4157911155
Short name T1237
Test name
Test status
Simulation time 19398053 ps
CPU time 0.79 seconds
Started Aug 05 04:22:25 PM PDT 24
Finished Aug 05 04:22:26 PM PDT 24
Peak memory 198896 kb
Host smart-d1837b81-b8ee-460a-a619-a277af3a1fff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157911155 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.4157911155
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.2200474554
Short name T1292
Test name
Test status
Simulation time 16525383 ps
CPU time 0.63 seconds
Started Aug 05 04:22:11 PM PDT 24
Finished Aug 05 04:22:12 PM PDT 24
Peak memory 194264 kb
Host smart-3fcb6c0c-7fc0-419c-a352-38d7cb777c2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200474554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2200474554
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1297066655
Short name T1194
Test name
Test status
Simulation time 35236585 ps
CPU time 0.56 seconds
Started Aug 05 04:21:52 PM PDT 24
Finished Aug 05 04:21:52 PM PDT 24
Peak memory 193844 kb
Host smart-86b3a59d-6c84-4d0b-ada3-a375cf9473ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297066655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1297066655
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2548431392
Short name T1315
Test name
Test status
Simulation time 26046042 ps
CPU time 0.68 seconds
Started Aug 05 04:22:29 PM PDT 24
Finished Aug 05 04:22:30 PM PDT 24
Peak memory 196668 kb
Host smart-3fb9ed7b-cf2a-4dcf-98a6-c67459eac256
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548431392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2548431392
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.941025123
Short name T1280
Test name
Test status
Simulation time 51045402 ps
CPU time 1.19 seconds
Started Aug 05 04:22:11 PM PDT 24
Finished Aug 05 04:22:13 PM PDT 24
Peak memory 199100 kb
Host smart-f374e405-668f-4e66-8b12-4d7231ab8c95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941025123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.941025123
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1831053306
Short name T105
Test name
Test status
Simulation time 97196596 ps
CPU time 1.28 seconds
Started Aug 05 04:19:19 PM PDT 24
Finished Aug 05 04:19:21 PM PDT 24
Peak memory 199412 kb
Host smart-17105c59-8bc0-4522-aa1c-cefb3474c4af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831053306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1831053306
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2765264026
Short name T1246
Test name
Test status
Simulation time 101236910 ps
CPU time 0.88 seconds
Started Aug 05 04:22:14 PM PDT 24
Finished Aug 05 04:22:15 PM PDT 24
Peak memory 200016 kb
Host smart-8b0f5c61-2076-4885-99d1-fce244c29e55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765264026 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2765264026
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.288299201
Short name T88
Test name
Test status
Simulation time 34385382 ps
CPU time 0.59 seconds
Started Aug 05 04:19:31 PM PDT 24
Finished Aug 05 04:19:32 PM PDT 24
Peak memory 195716 kb
Host smart-2dd7d4bf-de79-40bb-a702-7e2c4b10be37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288299201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.288299201
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3877782405
Short name T1222
Test name
Test status
Simulation time 17643601 ps
CPU time 0.61 seconds
Started Aug 05 04:22:11 PM PDT 24
Finished Aug 05 04:22:12 PM PDT 24
Peak memory 193232 kb
Host smart-1a15f1ad-1017-4ef1-815e-50f4b5ecfc91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877782405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3877782405
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.147137388
Short name T1317
Test name
Test status
Simulation time 76322986 ps
CPU time 0.66 seconds
Started Aug 05 04:22:03 PM PDT 24
Finished Aug 05 04:22:04 PM PDT 24
Peak memory 195004 kb
Host smart-9edf275c-120a-45eb-b3c0-b275ad567a4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147137388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_
outstanding.147137388
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1104645896
Short name T1199
Test name
Test status
Simulation time 214433771 ps
CPU time 1.26 seconds
Started Aug 05 04:21:51 PM PDT 24
Finished Aug 05 04:21:53 PM PDT 24
Peak memory 199424 kb
Host smart-8c505a67-8015-4c77-93a7-6153bcfa0663
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104645896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1104645896
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.220877266
Short name T97
Test name
Test status
Simulation time 90735838 ps
CPU time 1.35 seconds
Started Aug 05 04:21:52 PM PDT 24
Finished Aug 05 04:21:53 PM PDT 24
Peak memory 199308 kb
Host smart-ae533f3e-b892-436b-a80a-d969d7f148c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220877266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.220877266
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.4186082671
Short name T1187
Test name
Test status
Simulation time 213492101 ps
CPU time 1.04 seconds
Started Aug 05 04:21:42 PM PDT 24
Finished Aug 05 04:21:44 PM PDT 24
Peak memory 199252 kb
Host smart-3d046a12-b195-47bb-aa67-2fd43ec7ddf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186082671 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.4186082671
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3627893615
Short name T86
Test name
Test status
Simulation time 13915877 ps
CPU time 0.65 seconds
Started Aug 05 04:18:52 PM PDT 24
Finished Aug 05 04:18:53 PM PDT 24
Peak memory 195260 kb
Host smart-b59cb0a0-809e-4058-8e2f-fc0af88976df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627893615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3627893615
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1427357801
Short name T1296
Test name
Test status
Simulation time 35056126 ps
CPU time 0.58 seconds
Started Aug 05 04:21:57 PM PDT 24
Finished Aug 05 04:21:58 PM PDT 24
Peak memory 193784 kb
Host smart-74b2f0c3-9825-4184-9b0b-f1bbbdd641eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427357801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1427357801
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4269358246
Short name T87
Test name
Test status
Simulation time 91974570 ps
CPU time 0.68 seconds
Started Aug 05 04:22:14 PM PDT 24
Finished Aug 05 04:22:14 PM PDT 24
Peak memory 196988 kb
Host smart-b37fd20d-6d74-4776-889c-2cadb1c13295
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269358246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.4269358246
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.151719014
Short name T1212
Test name
Test status
Simulation time 164657857 ps
CPU time 2.16 seconds
Started Aug 05 04:20:13 PM PDT 24
Finished Aug 05 04:20:15 PM PDT 24
Peak memory 200556 kb
Host smart-bb1c3bae-fdf1-4fa5-9cc5-26588085a399
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151719014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.151719014
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2110637907
Short name T99
Test name
Test status
Simulation time 53358369 ps
CPU time 0.97 seconds
Started Aug 05 04:19:01 PM PDT 24
Finished Aug 05 04:19:02 PM PDT 24
Peak memory 199380 kb
Host smart-47e04c80-0f6a-49ad-b6f1-75b3e642801d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110637907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2110637907
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.1280594828
Short name T1058
Test name
Test status
Simulation time 12005431 ps
CPU time 0.57 seconds
Started Aug 05 05:13:20 PM PDT 24
Finished Aug 05 05:13:20 PM PDT 24
Peak memory 195348 kb
Host smart-f4cfe7e2-5a3a-45c1-84d6-b6e355d7d851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280594828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1280594828
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3723455073
Short name T543
Test name
Test status
Simulation time 115686887993 ps
CPU time 298.14 seconds
Started Aug 05 05:13:11 PM PDT 24
Finished Aug 05 05:18:10 PM PDT 24
Peak memory 199876 kb
Host smart-9d290aa2-f439-4322-8c50-c667c53e370e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723455073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3723455073
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1624334369
Short name T987
Test name
Test status
Simulation time 18351818398 ps
CPU time 8.87 seconds
Started Aug 05 05:13:12 PM PDT 24
Finished Aug 05 05:13:21 PM PDT 24
Peak memory 198988 kb
Host smart-ad9775d3-583a-401b-af59-436ffe633fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624334369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1624334369
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3556500524
Short name T275
Test name
Test status
Simulation time 175061285047 ps
CPU time 78.34 seconds
Started Aug 05 05:13:14 PM PDT 24
Finished Aug 05 05:14:32 PM PDT 24
Peak memory 199904 kb
Host smart-d1d3368d-7248-4d47-8d8e-694c5d619d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556500524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3556500524
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.4242478480
Short name T323
Test name
Test status
Simulation time 40400443159 ps
CPU time 14.34 seconds
Started Aug 05 05:13:11 PM PDT 24
Finished Aug 05 05:13:25 PM PDT 24
Peak memory 198656 kb
Host smart-989e4eba-9dec-4106-9a1b-120499297ab3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242478480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.4242478480
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.865484050
Short name T447
Test name
Test status
Simulation time 68711386652 ps
CPU time 147.69 seconds
Started Aug 05 05:13:19 PM PDT 24
Finished Aug 05 05:15:47 PM PDT 24
Peak memory 199928 kb
Host smart-3bd05da8-7227-41dc-b0f7-d2b23ea1a3d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=865484050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.865484050
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1224004855
Short name T376
Test name
Test status
Simulation time 6309672240 ps
CPU time 13.45 seconds
Started Aug 05 05:13:11 PM PDT 24
Finished Aug 05 05:13:25 PM PDT 24
Peak memory 199676 kb
Host smart-d93dc6ce-f9c7-4a07-a996-afd787f9307d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224004855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1224004855
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.842252020
Short name T414
Test name
Test status
Simulation time 14916235998 ps
CPU time 141.95 seconds
Started Aug 05 05:13:13 PM PDT 24
Finished Aug 05 05:15:35 PM PDT 24
Peak memory 199928 kb
Host smart-ced80d9d-257b-4864-be17-6e5ae42f8dcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842252020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.842252020
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3663871625
Short name T1152
Test name
Test status
Simulation time 4432040127 ps
CPU time 37.32 seconds
Started Aug 05 05:13:15 PM PDT 24
Finished Aug 05 05:13:52 PM PDT 24
Peak memory 198212 kb
Host smart-7b69bbfe-daa1-4303-bce6-00bd23877c5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3663871625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3663871625
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2871420243
Short name T79
Test name
Test status
Simulation time 28130132868 ps
CPU time 23.23 seconds
Started Aug 05 05:13:13 PM PDT 24
Finished Aug 05 05:13:36 PM PDT 24
Peak memory 199980 kb
Host smart-0e980dbb-b8c4-4068-ac15-59a2952b6857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871420243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2871420243
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1577692758
Short name T856
Test name
Test status
Simulation time 2175498887 ps
CPU time 1.86 seconds
Started Aug 05 05:13:14 PM PDT 24
Finished Aug 05 05:13:16 PM PDT 24
Peak memory 195440 kb
Host smart-4145209e-9c0e-474a-8c71-26e00c0c8199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577692758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1577692758
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3763525937
Short name T107
Test name
Test status
Simulation time 219894930 ps
CPU time 0.86 seconds
Started Aug 05 05:13:18 PM PDT 24
Finished Aug 05 05:13:19 PM PDT 24
Peak memory 218296 kb
Host smart-347db758-7772-4e38-aef5-d6b3156cb64d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763525937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3763525937
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.703464995
Short name T276
Test name
Test status
Simulation time 5385860407 ps
CPU time 25.93 seconds
Started Aug 05 05:13:12 PM PDT 24
Finished Aug 05 05:13:38 PM PDT 24
Peak memory 199680 kb
Host smart-51ff1b27-2947-443a-9941-8750dc0d99c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703464995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.703464995
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.2747633533
Short name T20
Test name
Test status
Simulation time 47781334531 ps
CPU time 47.3 seconds
Started Aug 05 05:13:23 PM PDT 24
Finished Aug 05 05:14:11 PM PDT 24
Peak memory 199972 kb
Host smart-25da65e8-1e76-45ca-b485-090ede80b05d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747633533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2747633533
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2999335524
Short name T602
Test name
Test status
Simulation time 110804227194 ps
CPU time 1142.97 seconds
Started Aug 05 05:13:19 PM PDT 24
Finished Aug 05 05:32:22 PM PDT 24
Peak memory 224808 kb
Host smart-0c77c563-f4a4-447f-bb72-1c9a2d6bdbc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999335524 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2999335524
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1547670293
Short name T1155
Test name
Test status
Simulation time 1632957675 ps
CPU time 1.71 seconds
Started Aug 05 05:13:12 PM PDT 24
Finished Aug 05 05:13:14 PM PDT 24
Peak memory 198736 kb
Host smart-12f3c368-ff9a-4fda-865c-784140173220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547670293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1547670293
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.278382747
Short name T302
Test name
Test status
Simulation time 42864657150 ps
CPU time 60.06 seconds
Started Aug 05 05:13:11 PM PDT 24
Finished Aug 05 05:14:12 PM PDT 24
Peak memory 199988 kb
Host smart-d9b927d4-e3b4-4e28-9194-61b0d78d9063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278382747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.278382747
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1886978037
Short name T688
Test name
Test status
Simulation time 14073355 ps
CPU time 0.55 seconds
Started Aug 05 05:13:26 PM PDT 24
Finished Aug 05 05:13:27 PM PDT 24
Peak memory 195644 kb
Host smart-cfdd7924-d4d3-4a96-b461-3aa9fd1b2bbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886978037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1886978037
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3897462956
Short name T267
Test name
Test status
Simulation time 112003226751 ps
CPU time 155.07 seconds
Started Aug 05 05:13:22 PM PDT 24
Finished Aug 05 05:15:57 PM PDT 24
Peak memory 199972 kb
Host smart-1c2c3d1d-00f8-45fb-9466-fe229b748149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897462956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3897462956
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.577287074
Short name T980
Test name
Test status
Simulation time 21658903980 ps
CPU time 26.83 seconds
Started Aug 05 05:13:20 PM PDT 24
Finished Aug 05 05:13:47 PM PDT 24
Peak memory 199924 kb
Host smart-edfdf340-eb9f-44b4-a009-250d3d08bc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577287074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.577287074
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.629134838
Short name T1036
Test name
Test status
Simulation time 24255379805 ps
CPU time 30.21 seconds
Started Aug 05 05:14:47 PM PDT 24
Finished Aug 05 05:15:18 PM PDT 24
Peak memory 200000 kb
Host smart-11a63f16-9bf9-47b5-a78c-ee57d70759a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629134838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.629134838
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.1608860401
Short name T395
Test name
Test status
Simulation time 44892104961 ps
CPU time 75.34 seconds
Started Aug 05 05:13:19 PM PDT 24
Finished Aug 05 05:14:34 PM PDT 24
Peak memory 199820 kb
Host smart-b694d674-457f-4cda-9302-effd52ffab05
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608860401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1608860401
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1590791730
Short name T762
Test name
Test status
Simulation time 55231969714 ps
CPU time 173.58 seconds
Started Aug 05 05:15:39 PM PDT 24
Finished Aug 05 05:18:32 PM PDT 24
Peak memory 199900 kb
Host smart-4fb906fa-48fe-49cf-bf68-ed92d315ac2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1590791730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1590791730
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.401756256
Short name T778
Test name
Test status
Simulation time 741300374 ps
CPU time 1.5 seconds
Started Aug 05 05:13:20 PM PDT 24
Finished Aug 05 05:13:21 PM PDT 24
Peak memory 198312 kb
Host smart-4b405ee4-a50c-4c64-a0b0-2185824e94d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401756256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.401756256
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1521162192
Short name T977
Test name
Test status
Simulation time 150150635457 ps
CPU time 147.84 seconds
Started Aug 05 05:13:19 PM PDT 24
Finished Aug 05 05:15:47 PM PDT 24
Peak memory 200092 kb
Host smart-d843f18c-54fc-4e05-a04f-60b4b7abcc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521162192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1521162192
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.707751083
Short name T914
Test name
Test status
Simulation time 9513126146 ps
CPU time 124.76 seconds
Started Aug 05 05:13:24 PM PDT 24
Finished Aug 05 05:15:29 PM PDT 24
Peak memory 199904 kb
Host smart-52ff8048-ca78-43be-899b-db7ac4dbd730
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=707751083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.707751083
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.4092394177
Short name T1148
Test name
Test status
Simulation time 2968150268 ps
CPU time 21.23 seconds
Started Aug 05 05:13:21 PM PDT 24
Finished Aug 05 05:13:42 PM PDT 24
Peak memory 197932 kb
Host smart-91978e14-a8a4-45fa-9d47-43a79655ea5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4092394177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.4092394177
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.134657323
Short name T7
Test name
Test status
Simulation time 56299992125 ps
CPU time 25.59 seconds
Started Aug 05 05:13:20 PM PDT 24
Finished Aug 05 05:13:46 PM PDT 24
Peak memory 199920 kb
Host smart-da4f90fa-1133-4017-b058-523f143d89a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134657323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.134657323
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.617643948
Short name T114
Test name
Test status
Simulation time 39374195219 ps
CPU time 64.79 seconds
Started Aug 05 05:13:19 PM PDT 24
Finished Aug 05 05:14:24 PM PDT 24
Peak memory 196012 kb
Host smart-a0686c1f-8a23-4c70-aa29-bcc240408876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617643948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.617643948
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2906654635
Short name T108
Test name
Test status
Simulation time 210428712 ps
CPU time 0.87 seconds
Started Aug 05 05:13:23 PM PDT 24
Finished Aug 05 05:13:24 PM PDT 24
Peak memory 218492 kb
Host smart-36d65307-6941-4213-91f4-00515f7d88ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906654635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2906654635
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3818918218
Short name T354
Test name
Test status
Simulation time 6262283322 ps
CPU time 18.38 seconds
Started Aug 05 05:13:20 PM PDT 24
Finished Aug 05 05:13:38 PM PDT 24
Peak memory 199880 kb
Host smart-e000706b-7556-40cf-b7ea-a2c187aa8516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818918218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3818918218
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3370982118
Short name T799
Test name
Test status
Simulation time 90125545528 ps
CPU time 119.16 seconds
Started Aug 05 05:13:23 PM PDT 24
Finished Aug 05 05:15:23 PM PDT 24
Peak memory 208464 kb
Host smart-d2078125-6c48-4eda-9756-dae0cecbcf2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370982118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3370982118
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1050817637
Short name T905
Test name
Test status
Simulation time 171340548050 ps
CPU time 1983.14 seconds
Started Aug 05 05:13:24 PM PDT 24
Finished Aug 05 05:46:27 PM PDT 24
Peak memory 226132 kb
Host smart-e9e74ad8-9098-471f-9fa0-c5a777d7f342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050817637 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1050817637
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3413453708
Short name T950
Test name
Test status
Simulation time 1028519354 ps
CPU time 2.14 seconds
Started Aug 05 05:13:21 PM PDT 24
Finished Aug 05 05:13:23 PM PDT 24
Peak memory 198484 kb
Host smart-c89946a8-159a-4f91-b146-53ebb701ef0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413453708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3413453708
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2223599508
Short name T1150
Test name
Test status
Simulation time 119238742480 ps
CPU time 148.9 seconds
Started Aug 05 05:13:19 PM PDT 24
Finished Aug 05 05:15:48 PM PDT 24
Peak memory 199864 kb
Host smart-94597fcc-e9fd-4987-855f-ab8dd8238187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223599508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2223599508
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.1668001185
Short name T939
Test name
Test status
Simulation time 13259784 ps
CPU time 0.57 seconds
Started Aug 05 05:14:17 PM PDT 24
Finished Aug 05 05:14:18 PM PDT 24
Peak memory 194308 kb
Host smart-dd7bdf73-4655-4b00-ba7f-9222af805a73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668001185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1668001185
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2946935904
Short name T896
Test name
Test status
Simulation time 184965002473 ps
CPU time 254.52 seconds
Started Aug 05 05:14:05 PM PDT 24
Finished Aug 05 05:18:20 PM PDT 24
Peak memory 199992 kb
Host smart-251cb9cc-6ed7-4e3b-8a98-b3d51b9e26f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946935904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2946935904
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3988096768
Short name T160
Test name
Test status
Simulation time 115493394320 ps
CPU time 96.02 seconds
Started Aug 05 05:14:03 PM PDT 24
Finished Aug 05 05:15:39 PM PDT 24
Peak memory 199908 kb
Host smart-b14f3711-0f23-49bd-9df6-a4782676d5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988096768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3988096768
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.380216272
Short name T699
Test name
Test status
Simulation time 3857212445 ps
CPU time 3.85 seconds
Started Aug 05 05:14:04 PM PDT 24
Finished Aug 05 05:14:07 PM PDT 24
Peak memory 198916 kb
Host smart-95e47599-a1ad-4ed3-893d-779edbd92392
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380216272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.380216272
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3984050021
Short name T857
Test name
Test status
Simulation time 124318440221 ps
CPU time 83.33 seconds
Started Aug 05 05:14:08 PM PDT 24
Finished Aug 05 05:15:31 PM PDT 24
Peak memory 199820 kb
Host smart-dcc4c9f6-d6b3-4f55-a227-daa1bc27953f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3984050021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3984050021
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3504048430
Short name T870
Test name
Test status
Simulation time 550190897 ps
CPU time 1.08 seconds
Started Aug 05 05:14:17 PM PDT 24
Finished Aug 05 05:14:19 PM PDT 24
Peak memory 195620 kb
Host smart-03ab6a9e-078b-4624-b6af-3f02ffbc7987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504048430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3504048430
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3858842949
Short name T259
Test name
Test status
Simulation time 68262806029 ps
CPU time 116.87 seconds
Started Aug 05 05:14:03 PM PDT 24
Finished Aug 05 05:16:00 PM PDT 24
Peak memory 200096 kb
Host smart-9b41ca46-bea9-4e6b-9ce2-f86e61ba1d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858842949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3858842949
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.3806374045
Short name T567
Test name
Test status
Simulation time 21552637988 ps
CPU time 459.3 seconds
Started Aug 05 05:14:12 PM PDT 24
Finished Aug 05 05:21:51 PM PDT 24
Peak memory 199840 kb
Host smart-73c2718b-5727-43c5-9197-e19678522b42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3806374045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3806374045
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2384090164
Short name T343
Test name
Test status
Simulation time 6030545092 ps
CPU time 21.5 seconds
Started Aug 05 05:14:01 PM PDT 24
Finished Aug 05 05:14:22 PM PDT 24
Peak memory 198160 kb
Host smart-e441a485-5362-4c32-b90c-0feea9168aec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2384090164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2384090164
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2831468464
Short name T956
Test name
Test status
Simulation time 32894325683 ps
CPU time 23.46 seconds
Started Aug 05 05:14:08 PM PDT 24
Finished Aug 05 05:14:32 PM PDT 24
Peak memory 198828 kb
Host smart-5fecec1a-f2f0-4670-9dda-13eca0e07d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831468464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2831468464
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3613264798
Short name T993
Test name
Test status
Simulation time 720910470 ps
CPU time 0.89 seconds
Started Aug 05 05:14:12 PM PDT 24
Finished Aug 05 05:14:13 PM PDT 24
Peak memory 195436 kb
Host smart-cc46a8f8-024b-4e23-bcc1-a480baeb18ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613264798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3613264798
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.4110305492
Short name T636
Test name
Test status
Simulation time 298013548 ps
CPU time 1.44 seconds
Started Aug 05 05:14:04 PM PDT 24
Finished Aug 05 05:14:06 PM PDT 24
Peak memory 199776 kb
Host smart-f2d2d9e4-2227-4f97-9806-54900e92917d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110305492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.4110305492
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2033587848
Short name T477
Test name
Test status
Simulation time 272989153288 ps
CPU time 589.49 seconds
Started Aug 05 05:14:08 PM PDT 24
Finished Aug 05 05:23:57 PM PDT 24
Peak memory 208260 kb
Host smart-939b5c18-7647-4da0-be53-c88ed3266f90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033587848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2033587848
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3804946206
Short name T864
Test name
Test status
Simulation time 102553689759 ps
CPU time 829.66 seconds
Started Aug 05 05:14:17 PM PDT 24
Finished Aug 05 05:28:07 PM PDT 24
Peak memory 224776 kb
Host smart-76992e68-3725-46ba-a91b-e26e4ff38a0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804946206 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3804946206
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.2514041122
Short name T309
Test name
Test status
Simulation time 467420860 ps
CPU time 1.32 seconds
Started Aug 05 05:14:06 PM PDT 24
Finished Aug 05 05:14:08 PM PDT 24
Peak memory 199828 kb
Host smart-1552a7f6-c933-4178-b326-761f9f4d7499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514041122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2514041122
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.611974511
Short name T772
Test name
Test status
Simulation time 358118121478 ps
CPU time 40.14 seconds
Started Aug 05 05:14:05 PM PDT 24
Finished Aug 05 05:14:45 PM PDT 24
Peak memory 199924 kb
Host smart-861c5602-ab13-41c1-a053-5618f039d7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611974511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.611974511
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3609870665
Short name T1131
Test name
Test status
Simulation time 30880213178 ps
CPU time 47.46 seconds
Started Aug 05 05:19:08 PM PDT 24
Finished Aug 05 05:19:55 PM PDT 24
Peak memory 199884 kb
Host smart-bb98da44-2511-46c6-8e99-9a3993f4fc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609870665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3609870665
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.977862411
Short name T144
Test name
Test status
Simulation time 13020648681 ps
CPU time 41.45 seconds
Started Aug 05 05:19:15 PM PDT 24
Finished Aug 05 05:19:56 PM PDT 24
Peak memory 199652 kb
Host smart-ff02c569-db1e-4b61-8765-ed4b0c2f5933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977862411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.977862411
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3391703926
Short name T1170
Test name
Test status
Simulation time 89335107026 ps
CPU time 211.33 seconds
Started Aug 05 05:19:16 PM PDT 24
Finished Aug 05 05:22:47 PM PDT 24
Peak memory 199920 kb
Host smart-b14c33f3-e325-41d5-b2fa-aa2b4bf7b12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391703926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3391703926
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2562962448
Short name T668
Test name
Test status
Simulation time 184548473692 ps
CPU time 142.71 seconds
Started Aug 05 05:19:15 PM PDT 24
Finished Aug 05 05:21:38 PM PDT 24
Peak memory 199824 kb
Host smart-18bb9046-5a6d-476a-95cc-d0da990c13ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562962448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2562962448
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1319720706
Short name T175
Test name
Test status
Simulation time 68082319708 ps
CPU time 28.62 seconds
Started Aug 05 05:19:13 PM PDT 24
Finished Aug 05 05:19:42 PM PDT 24
Peak memory 199940 kb
Host smart-3d460317-b071-4945-bc32-8ee16c6af3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319720706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1319720706
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2799230702
Short name T817
Test name
Test status
Simulation time 43489808914 ps
CPU time 16.91 seconds
Started Aug 05 05:19:15 PM PDT 24
Finished Aug 05 05:19:32 PM PDT 24
Peak memory 199620 kb
Host smart-ac850cc8-4977-49b9-b4a0-79cdb7cd148b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799230702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2799230702
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.319429893
Short name T188
Test name
Test status
Simulation time 20355043398 ps
CPU time 28.92 seconds
Started Aug 05 05:19:22 PM PDT 24
Finished Aug 05 05:19:51 PM PDT 24
Peak memory 199848 kb
Host smart-3f909625-e93c-49a0-b676-6b2a5c73b400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319429893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.319429893
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1911732110
Short name T722
Test name
Test status
Simulation time 23124115718 ps
CPU time 36.48 seconds
Started Aug 05 05:19:20 PM PDT 24
Finished Aug 05 05:19:57 PM PDT 24
Peak memory 199920 kb
Host smart-b9b76aeb-2c07-4e06-bb4d-503e063fb987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911732110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1911732110
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.268884511
Short name T765
Test name
Test status
Simulation time 48502570 ps
CPU time 0.55 seconds
Started Aug 05 05:14:08 PM PDT 24
Finished Aug 05 05:14:08 PM PDT 24
Peak memory 195636 kb
Host smart-f32815b2-d0c6-45e4-82bb-93e023c91943
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268884511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.268884511
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.571788582
Short name T1106
Test name
Test status
Simulation time 112565458638 ps
CPU time 82.16 seconds
Started Aug 05 05:14:09 PM PDT 24
Finished Aug 05 05:15:31 PM PDT 24
Peak memory 199844 kb
Host smart-52f94908-76b5-4d22-9342-1df3efcbb81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571788582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.571788582
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2446277952
Short name T146
Test name
Test status
Simulation time 68841296987 ps
CPU time 67.17 seconds
Started Aug 05 05:14:09 PM PDT 24
Finished Aug 05 05:15:16 PM PDT 24
Peak memory 199972 kb
Host smart-f963ac9a-5c25-4a78-9c5f-e8db2cc84dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446277952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2446277952
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3835865715
Short name T304
Test name
Test status
Simulation time 48261606659 ps
CPU time 20.4 seconds
Started Aug 05 05:14:07 PM PDT 24
Finished Aug 05 05:14:27 PM PDT 24
Peak memory 199952 kb
Host smart-651ec959-eb1b-481f-baad-3a3919792d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835865715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3835865715
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.872794669
Short name T834
Test name
Test status
Simulation time 32952657266 ps
CPU time 17.34 seconds
Started Aug 05 05:14:08 PM PDT 24
Finished Aug 05 05:14:25 PM PDT 24
Peak memory 199992 kb
Host smart-829c2415-c9be-4797-b43c-347d9ebd79bb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872794669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.872794669
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.536205693
Short name T1182
Test name
Test status
Simulation time 62019879938 ps
CPU time 386.4 seconds
Started Aug 05 05:14:06 PM PDT 24
Finished Aug 05 05:20:33 PM PDT 24
Peak memory 199944 kb
Host smart-0f4c85a6-910a-489a-93ce-2243145574d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=536205693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.536205693
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.3172879410
Short name T80
Test name
Test status
Simulation time 408404062 ps
CPU time 1.22 seconds
Started Aug 05 05:14:17 PM PDT 24
Finished Aug 05 05:14:19 PM PDT 24
Peak memory 195636 kb
Host smart-fba2a098-34ae-4aba-aa48-096af1ba48f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172879410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3172879410
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2007796157
Short name T1053
Test name
Test status
Simulation time 31188720105 ps
CPU time 14.73 seconds
Started Aug 05 05:14:07 PM PDT 24
Finished Aug 05 05:14:22 PM PDT 24
Peak memory 199820 kb
Host smart-29c89893-0b2a-480d-bb37-0c12f527e3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007796157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2007796157
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.756330447
Short name T460
Test name
Test status
Simulation time 9165342455 ps
CPU time 89.17 seconds
Started Aug 05 05:14:12 PM PDT 24
Finished Aug 05 05:15:41 PM PDT 24
Peak memory 199840 kb
Host smart-bd51dae6-2133-46ad-a7ff-d1a4129be43b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=756330447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.756330447
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3282102119
Short name T644
Test name
Test status
Simulation time 2669733175 ps
CPU time 5.37 seconds
Started Aug 05 05:14:08 PM PDT 24
Finished Aug 05 05:14:14 PM PDT 24
Peak memory 198144 kb
Host smart-04a4cc65-5285-426b-ae22-a9fe6280b23b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3282102119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3282102119
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.338930742
Short name T893
Test name
Test status
Simulation time 19159771775 ps
CPU time 29.69 seconds
Started Aug 05 05:14:08 PM PDT 24
Finished Aug 05 05:14:38 PM PDT 24
Peak memory 199916 kb
Host smart-b510eb38-58d8-406a-9755-a39437491282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338930742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.338930742
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3996905796
Short name T36
Test name
Test status
Simulation time 2227006083 ps
CPU time 2.31 seconds
Started Aug 05 05:14:08 PM PDT 24
Finished Aug 05 05:14:10 PM PDT 24
Peak memory 195492 kb
Host smart-30be164f-bb0a-45e5-af81-e89393e6d246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996905796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3996905796
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2310596625
Short name T372
Test name
Test status
Simulation time 307090258 ps
CPU time 1.57 seconds
Started Aug 05 05:14:12 PM PDT 24
Finished Aug 05 05:14:14 PM PDT 24
Peak memory 199564 kb
Host smart-fa17dd3b-8932-4b6d-9c2e-7d0935caf953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310596625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2310596625
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2476888169
Short name T1045
Test name
Test status
Simulation time 515157733354 ps
CPU time 830.43 seconds
Started Aug 05 05:14:09 PM PDT 24
Finished Aug 05 05:28:00 PM PDT 24
Peak memory 199920 kb
Host smart-573a190e-04af-4e50-a19b-62929798dc95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476888169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2476888169
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.3378920862
Short name T506
Test name
Test status
Simulation time 937314818 ps
CPU time 1.47 seconds
Started Aug 05 05:14:08 PM PDT 24
Finished Aug 05 05:14:10 PM PDT 24
Peak memory 198620 kb
Host smart-c42e30b5-a102-496c-9bd9-c584c3800d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378920862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3378920862
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.7852124
Short name T734
Test name
Test status
Simulation time 41061016854 ps
CPU time 66.56 seconds
Started Aug 05 05:14:17 PM PDT 24
Finished Aug 05 05:15:24 PM PDT 24
Peak memory 199964 kb
Host smart-33061085-f635-42ac-8ac5-3835d59cc1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7852124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.7852124
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3870414607
Short name T443
Test name
Test status
Simulation time 69613266365 ps
CPU time 40.72 seconds
Started Aug 05 05:19:22 PM PDT 24
Finished Aug 05 05:20:02 PM PDT 24
Peak memory 199684 kb
Host smart-c3bcade5-e2e3-4f56-9e62-d40edc1359e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870414607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3870414607
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.330543743
Short name T382
Test name
Test status
Simulation time 70435189054 ps
CPU time 117.2 seconds
Started Aug 05 05:19:22 PM PDT 24
Finished Aug 05 05:21:19 PM PDT 24
Peak memory 199948 kb
Host smart-5d5c79c5-3c9b-46db-892d-f59d683e11b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330543743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.330543743
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1205484700
Short name T46
Test name
Test status
Simulation time 111300677828 ps
CPU time 319.52 seconds
Started Aug 05 05:19:22 PM PDT 24
Finished Aug 05 05:24:42 PM PDT 24
Peak memory 199824 kb
Host smart-45db9e49-c4ad-41e0-a871-12b1a1a195b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205484700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1205484700
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.4191605735
Short name T253
Test name
Test status
Simulation time 28065771371 ps
CPU time 7.86 seconds
Started Aug 05 05:19:29 PM PDT 24
Finished Aug 05 05:19:37 PM PDT 24
Peak memory 198816 kb
Host smart-5afd7f85-8a7c-407a-bb2d-02166891eea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191605735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.4191605735
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2399442472
Short name T907
Test name
Test status
Simulation time 266142292757 ps
CPU time 64.78 seconds
Started Aug 05 05:19:24 PM PDT 24
Finished Aug 05 05:20:29 PM PDT 24
Peak memory 199912 kb
Host smart-ebbe8fa7-3fdc-4309-af63-43d272feeec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399442472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2399442472
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.4154624899
Short name T627
Test name
Test status
Simulation time 171621199061 ps
CPU time 65.97 seconds
Started Aug 05 05:19:26 PM PDT 24
Finished Aug 05 05:20:32 PM PDT 24
Peak memory 199908 kb
Host smart-a34d64b7-c005-4207-a64f-524b850244dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154624899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.4154624899
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2765449660
Short name T737
Test name
Test status
Simulation time 139114529522 ps
CPU time 41.46 seconds
Started Aug 05 05:19:25 PM PDT 24
Finished Aug 05 05:20:07 PM PDT 24
Peak memory 199904 kb
Host smart-fec5531b-578f-4771-917f-3579aabdcc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765449660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2765449660
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3700606399
Short name T591
Test name
Test status
Simulation time 160723802289 ps
CPU time 188.98 seconds
Started Aug 05 05:19:25 PM PDT 24
Finished Aug 05 05:22:35 PM PDT 24
Peak memory 199964 kb
Host smart-8835f4e8-c4e9-458e-95ff-a75ad4e368a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700606399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3700606399
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.4063984916
Short name T892
Test name
Test status
Simulation time 13557789 ps
CPU time 0.58 seconds
Started Aug 05 05:14:13 PM PDT 24
Finished Aug 05 05:14:14 PM PDT 24
Peak memory 194324 kb
Host smart-6fc4ed73-894f-44aa-aea7-23e3086aa0c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063984916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.4063984916
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.4006669307
Short name T1004
Test name
Test status
Simulation time 68501074713 ps
CPU time 30.32 seconds
Started Aug 05 05:14:15 PM PDT 24
Finished Aug 05 05:14:46 PM PDT 24
Peak memory 199952 kb
Host smart-72402991-cb00-46b0-97b5-4132ad879b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006669307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.4006669307
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.3236953839
Short name T641
Test name
Test status
Simulation time 111569285753 ps
CPU time 79.67 seconds
Started Aug 05 05:14:15 PM PDT 24
Finished Aug 05 05:15:35 PM PDT 24
Peak memory 199916 kb
Host smart-3c0b36e4-3d53-41a9-a41d-826a618563a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236953839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3236953839
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2803727098
Short name T359
Test name
Test status
Simulation time 8561270698 ps
CPU time 15.65 seconds
Started Aug 05 05:14:16 PM PDT 24
Finished Aug 05 05:14:31 PM PDT 24
Peak memory 199860 kb
Host smart-43c3a38f-0973-4308-bb7d-2553c6546c39
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803727098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2803727098
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2928685052
Short name T1034
Test name
Test status
Simulation time 152908190931 ps
CPU time 305.68 seconds
Started Aug 05 05:14:13 PM PDT 24
Finished Aug 05 05:19:19 PM PDT 24
Peak memory 199908 kb
Host smart-8c1ba970-7c17-48e4-9792-280aeaf2455b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2928685052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2928685052
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.4066546494
Short name T441
Test name
Test status
Simulation time 6990687558 ps
CPU time 7.55 seconds
Started Aug 05 05:14:15 PM PDT 24
Finished Aug 05 05:14:22 PM PDT 24
Peak memory 199852 kb
Host smart-89822bcc-abbe-49a4-9799-345829c324ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066546494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.4066546494
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_perf.2103650590
Short name T740
Test name
Test status
Simulation time 12089644735 ps
CPU time 697.48 seconds
Started Aug 05 05:14:16 PM PDT 24
Finished Aug 05 05:25:53 PM PDT 24
Peak memory 199976 kb
Host smart-858310a7-5336-4d2c-8d1e-934fa9128983
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2103650590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2103650590
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1513036367
Short name T38
Test name
Test status
Simulation time 2740806004 ps
CPU time 14.39 seconds
Started Aug 05 05:14:14 PM PDT 24
Finished Aug 05 05:14:28 PM PDT 24
Peak memory 199048 kb
Host smart-f2428a15-d860-4813-831e-e2e7a69618d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1513036367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1513036367
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1984911720
Short name T297
Test name
Test status
Simulation time 77304145189 ps
CPU time 29.99 seconds
Started Aug 05 05:14:13 PM PDT 24
Finished Aug 05 05:14:43 PM PDT 24
Peak memory 199952 kb
Host smart-24779a08-566b-4e3a-aae7-3bdba813d839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984911720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1984911720
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.69437130
Short name T667
Test name
Test status
Simulation time 41890175945 ps
CPU time 16.57 seconds
Started Aug 05 05:14:14 PM PDT 24
Finished Aug 05 05:14:31 PM PDT 24
Peak memory 196128 kb
Host smart-6fe02449-1491-4251-9c0d-eede0b1b38a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69437130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.69437130
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2713215756
Short name T904
Test name
Test status
Simulation time 427428246 ps
CPU time 2.33 seconds
Started Aug 05 05:14:13 PM PDT 24
Finished Aug 05 05:14:16 PM PDT 24
Peak memory 198696 kb
Host smart-282d36ca-3d33-473f-9407-08b522b65e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713215756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2713215756
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.935674833
Short name T759
Test name
Test status
Simulation time 305641948899 ps
CPU time 2114.77 seconds
Started Aug 05 05:14:14 PM PDT 24
Finished Aug 05 05:49:29 PM PDT 24
Peak memory 208244 kb
Host smart-07dbba6c-a986-47cd-9378-17393f75c1b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935674833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.935674833
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2234831566
Short name T117
Test name
Test status
Simulation time 26431206808 ps
CPU time 257.41 seconds
Started Aug 05 05:14:14 PM PDT 24
Finished Aug 05 05:18:31 PM PDT 24
Peak memory 211728 kb
Host smart-c0731e29-cada-476f-9fe0-b0e339686510
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234831566 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2234831566
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2499527794
Short name T930
Test name
Test status
Simulation time 615302856 ps
CPU time 2.09 seconds
Started Aug 05 05:14:15 PM PDT 24
Finished Aug 05 05:14:18 PM PDT 24
Peak memory 199216 kb
Host smart-5d9af01b-ab2b-4f85-a089-20e0f28eb307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499527794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2499527794
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.4119987254
Short name T569
Test name
Test status
Simulation time 20020171119 ps
CPU time 35.22 seconds
Started Aug 05 05:14:17 PM PDT 24
Finished Aug 05 05:14:52 PM PDT 24
Peak memory 199840 kb
Host smart-ebe4008e-1caa-4752-8f20-e51479323835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119987254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.4119987254
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1213775784
Short name T1161
Test name
Test status
Simulation time 30358117511 ps
CPU time 99.99 seconds
Started Aug 05 05:19:31 PM PDT 24
Finished Aug 05 05:21:11 PM PDT 24
Peak memory 199860 kb
Host smart-14c0c494-5231-4db6-87f8-250c3571a9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213775784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1213775784
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.4042364932
Short name T645
Test name
Test status
Simulation time 91621198247 ps
CPU time 37.4 seconds
Started Aug 05 05:19:34 PM PDT 24
Finished Aug 05 05:20:12 PM PDT 24
Peak memory 199948 kb
Host smart-7b7eff61-a005-48cd-8a59-c89a336b4ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042364932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.4042364932
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3835940411
Short name T528
Test name
Test status
Simulation time 162434919849 ps
CPU time 92.58 seconds
Started Aug 05 05:19:33 PM PDT 24
Finished Aug 05 05:21:06 PM PDT 24
Peak memory 199880 kb
Host smart-345147d9-1b0c-4645-8214-9a9bd5cfc1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835940411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3835940411
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.816620745
Short name T547
Test name
Test status
Simulation time 6865658428 ps
CPU time 12.83 seconds
Started Aug 05 05:19:36 PM PDT 24
Finished Aug 05 05:19:49 PM PDT 24
Peak memory 199892 kb
Host smart-72ce5a8d-f640-455e-a375-d8a135054c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816620745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.816620745
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2776134657
Short name T322
Test name
Test status
Simulation time 44274380585 ps
CPU time 16.55 seconds
Started Aug 05 05:19:33 PM PDT 24
Finished Aug 05 05:19:50 PM PDT 24
Peak memory 199880 kb
Host smart-f4a7d92f-f8ba-438f-91e6-dce02834f813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776134657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2776134657
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3470913143
Short name T1157
Test name
Test status
Simulation time 41344959495 ps
CPU time 30.49 seconds
Started Aug 05 05:19:33 PM PDT 24
Finished Aug 05 05:20:03 PM PDT 24
Peak memory 200000 kb
Host smart-4ed0b1d4-0e77-44eb-a3ac-5f58e7d3d71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470913143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3470913143
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2319151563
Short name T380
Test name
Test status
Simulation time 19146089503 ps
CPU time 35.61 seconds
Started Aug 05 05:19:30 PM PDT 24
Finished Aug 05 05:20:05 PM PDT 24
Peak memory 199900 kb
Host smart-dfc5e573-03b4-4d4a-80ff-ee517d0b82d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319151563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2319151563
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3677492643
Short name T767
Test name
Test status
Simulation time 205101095525 ps
CPU time 78.59 seconds
Started Aug 05 05:19:37 PM PDT 24
Finished Aug 05 05:20:55 PM PDT 24
Peak memory 199888 kb
Host smart-f0056ebf-452f-4042-a6c7-c7c98e5bb449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677492643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3677492643
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3438291464
Short name T780
Test name
Test status
Simulation time 37622660316 ps
CPU time 17.78 seconds
Started Aug 05 05:19:40 PM PDT 24
Finished Aug 05 05:19:58 PM PDT 24
Peak memory 199952 kb
Host smart-dfc5a3ef-0f7c-4383-b751-2fd4085f5543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438291464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3438291464
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.846541524
Short name T1040
Test name
Test status
Simulation time 48914946814 ps
CPU time 72.95 seconds
Started Aug 05 05:19:35 PM PDT 24
Finished Aug 05 05:20:48 PM PDT 24
Peak memory 199956 kb
Host smart-4f64b8a6-30d6-4a22-9350-e8f259bf3a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846541524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.846541524
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2686114548
Short name T1146
Test name
Test status
Simulation time 15408095 ps
CPU time 0.57 seconds
Started Aug 05 05:14:20 PM PDT 24
Finished Aug 05 05:14:20 PM PDT 24
Peak memory 195352 kb
Host smart-d48f3a46-8e89-4495-9ed7-91dd40054468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686114548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2686114548
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3012346476
Short name T933
Test name
Test status
Simulation time 510575350934 ps
CPU time 69.24 seconds
Started Aug 05 05:14:15 PM PDT 24
Finished Aug 05 05:15:24 PM PDT 24
Peak memory 199816 kb
Host smart-d7039393-f4e1-447e-8d9f-9cf59c95c12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012346476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3012346476
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1144969289
Short name T1072
Test name
Test status
Simulation time 127111988023 ps
CPU time 19.69 seconds
Started Aug 05 05:14:15 PM PDT 24
Finished Aug 05 05:14:35 PM PDT 24
Peak memory 199944 kb
Host smart-11239fc4-738a-422d-9e51-40f217a9fd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144969289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1144969289
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3111347258
Short name T221
Test name
Test status
Simulation time 186265770428 ps
CPU time 69.04 seconds
Started Aug 05 05:14:16 PM PDT 24
Finished Aug 05 05:15:25 PM PDT 24
Peak memory 199976 kb
Host smart-fa01a000-768a-4646-952b-845978192ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111347258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3111347258
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2168110614
Short name T13
Test name
Test status
Simulation time 26662631335 ps
CPU time 38.56 seconds
Started Aug 05 05:14:14 PM PDT 24
Finished Aug 05 05:14:52 PM PDT 24
Peak memory 199300 kb
Host smart-5fbc203f-2689-4101-81ed-ec6f4f8455bf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168110614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2168110614
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3162060188
Short name T1135
Test name
Test status
Simulation time 91493014018 ps
CPU time 687.97 seconds
Started Aug 05 05:14:20 PM PDT 24
Finished Aug 05 05:25:48 PM PDT 24
Peak memory 199796 kb
Host smart-789d89c2-bc9a-4980-804e-1dd67fe4c5f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3162060188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3162060188
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3014089610
Short name T497
Test name
Test status
Simulation time 11768292601 ps
CPU time 24.27 seconds
Started Aug 05 05:14:19 PM PDT 24
Finished Aug 05 05:14:43 PM PDT 24
Peak memory 199832 kb
Host smart-0305c8ee-94b4-4d20-a4e6-1bcdaf311524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014089610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3014089610
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3467344128
Short name T425
Test name
Test status
Simulation time 25894602906 ps
CPU time 35.55 seconds
Started Aug 05 05:14:16 PM PDT 24
Finished Aug 05 05:14:51 PM PDT 24
Peak memory 197416 kb
Host smart-dfa74d0f-5f5d-44bf-ab14-c2fd74361fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467344128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3467344128
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.466514109
Short name T473
Test name
Test status
Simulation time 6328434850 ps
CPU time 353.39 seconds
Started Aug 05 05:14:17 PM PDT 24
Finished Aug 05 05:20:11 PM PDT 24
Peak memory 199940 kb
Host smart-9d14d8c8-79dc-4b61-adbe-a71e7b730958
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466514109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.466514109
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2453354607
Short name T84
Test name
Test status
Simulation time 6534004420 ps
CPU time 53.36 seconds
Started Aug 05 05:14:15 PM PDT 24
Finished Aug 05 05:15:08 PM PDT 24
Peak memory 199064 kb
Host smart-1d55de9e-2d5e-40d4-ab01-71457c4d1449
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2453354607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2453354607
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.348954165
Short name T511
Test name
Test status
Simulation time 22748680096 ps
CPU time 38.94 seconds
Started Aug 05 05:14:14 PM PDT 24
Finished Aug 05 05:14:53 PM PDT 24
Peak memory 199900 kb
Host smart-809cbc81-d154-456c-8faa-195ca0aae430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348954165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.348954165
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.136746080
Short name T838
Test name
Test status
Simulation time 1562585880 ps
CPU time 3.21 seconds
Started Aug 05 05:14:16 PM PDT 24
Finished Aug 05 05:14:19 PM PDT 24
Peak memory 195616 kb
Host smart-f269166b-5c26-400c-80e9-cf5f947eac77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136746080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.136746080
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2124292578
Short name T495
Test name
Test status
Simulation time 264466841 ps
CPU time 1.35 seconds
Started Aug 05 05:14:15 PM PDT 24
Finished Aug 05 05:14:16 PM PDT 24
Peak memory 198960 kb
Host smart-33db34de-6e61-41a1-843c-e750fe49a968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124292578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2124292578
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.2509175967
Short name T768
Test name
Test status
Simulation time 128028041888 ps
CPU time 226.71 seconds
Started Aug 05 05:14:18 PM PDT 24
Finished Aug 05 05:18:05 PM PDT 24
Peak memory 199824 kb
Host smart-8cfdbeaa-b482-4caa-bd0f-81d6cd9af067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509175967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2509175967
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.858460743
Short name T16
Test name
Test status
Simulation time 744412045 ps
CPU time 3.56 seconds
Started Aug 05 05:14:19 PM PDT 24
Finished Aug 05 05:14:23 PM PDT 24
Peak memory 199436 kb
Host smart-69053e60-6e32-41dc-aa29-41167c591ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858460743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.858460743
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.4086157508
Short name T840
Test name
Test status
Simulation time 132614302467 ps
CPU time 44.54 seconds
Started Aug 05 05:14:14 PM PDT 24
Finished Aug 05 05:14:59 PM PDT 24
Peak memory 199864 kb
Host smart-a3a59917-c105-4d30-8ea9-2f5bb60ef903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086157508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.4086157508
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2353889498
Short name T532
Test name
Test status
Simulation time 66594965765 ps
CPU time 71.22 seconds
Started Aug 05 05:19:38 PM PDT 24
Finished Aug 05 05:20:49 PM PDT 24
Peak memory 199836 kb
Host smart-4e1c0a60-3473-4eca-82b9-9694d92a6359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353889498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2353889498
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1281917764
Short name T216
Test name
Test status
Simulation time 138647621129 ps
CPU time 58.47 seconds
Started Aug 05 05:19:37 PM PDT 24
Finished Aug 05 05:20:36 PM PDT 24
Peak memory 199888 kb
Host smart-701ec1c6-a377-4173-b586-d26fa6f372be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281917764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1281917764
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.883486153
Short name T126
Test name
Test status
Simulation time 340193341522 ps
CPU time 33.34 seconds
Started Aug 05 05:19:40 PM PDT 24
Finished Aug 05 05:20:14 PM PDT 24
Peak memory 199932 kb
Host smart-7e4df0a2-57f1-4ab6-ad29-63f6219c8064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883486153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.883486153
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1955397105
Short name T1158
Test name
Test status
Simulation time 35263252148 ps
CPU time 15.56 seconds
Started Aug 05 05:19:44 PM PDT 24
Finished Aug 05 05:19:59 PM PDT 24
Peak memory 199796 kb
Host smart-5b0fb8a8-ed46-4210-a88f-87e1eedff605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955397105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1955397105
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2082277555
Short name T782
Test name
Test status
Simulation time 146412629641 ps
CPU time 99.43 seconds
Started Aug 05 05:19:43 PM PDT 24
Finished Aug 05 05:21:23 PM PDT 24
Peak memory 199912 kb
Host smart-3e2df16b-ab7b-4ac3-bbad-6cdce738aead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082277555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2082277555
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.4065890223
Short name T1178
Test name
Test status
Simulation time 297676672905 ps
CPU time 145.54 seconds
Started Aug 05 05:19:42 PM PDT 24
Finished Aug 05 05:22:08 PM PDT 24
Peak memory 199952 kb
Host smart-f38359f9-f525-42ab-87d8-43bf045fee9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065890223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.4065890223
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2048748275
Short name T650
Test name
Test status
Simulation time 64664671805 ps
CPU time 52.86 seconds
Started Aug 05 05:19:42 PM PDT 24
Finished Aug 05 05:20:35 PM PDT 24
Peak memory 199944 kb
Host smart-2081cefa-69c4-457f-a3ab-00c6b08b7229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048748275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2048748275
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.273122423
Short name T712
Test name
Test status
Simulation time 239514911944 ps
CPU time 83.11 seconds
Started Aug 05 05:19:42 PM PDT 24
Finished Aug 05 05:21:05 PM PDT 24
Peak memory 199964 kb
Host smart-0a7fa8dd-36df-4b9e-b69d-9bf9bc4195c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273122423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.273122423
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.624005896
Short name T210
Test name
Test status
Simulation time 43904766408 ps
CPU time 30.08 seconds
Started Aug 05 05:19:46 PM PDT 24
Finished Aug 05 05:20:16 PM PDT 24
Peak memory 199848 kb
Host smart-8f807f23-34e0-4e31-b4be-0cf6532e1d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624005896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.624005896
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2012666231
Short name T1074
Test name
Test status
Simulation time 33390285319 ps
CPU time 12.81 seconds
Started Aug 05 05:19:47 PM PDT 24
Finished Aug 05 05:20:00 PM PDT 24
Peak memory 199976 kb
Host smart-4ba49b66-c5c6-4777-9d0a-203e7a64e6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012666231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2012666231
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_full.4243988503
Short name T720
Test name
Test status
Simulation time 57502616202 ps
CPU time 62.95 seconds
Started Aug 05 05:14:18 PM PDT 24
Finished Aug 05 05:15:21 PM PDT 24
Peak memory 199892 kb
Host smart-54cf291c-a722-4692-98d8-d6c475fe9101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243988503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.4243988503
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.761303495
Short name T496
Test name
Test status
Simulation time 58532966837 ps
CPU time 16.88 seconds
Started Aug 05 05:14:21 PM PDT 24
Finished Aug 05 05:14:37 PM PDT 24
Peak memory 199652 kb
Host smart-ef4a7e6c-e0ef-4d1c-9459-e9d1cf6a4f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761303495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.761303495
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_intr.1010650158
Short name T598
Test name
Test status
Simulation time 20492541343 ps
CPU time 32.4 seconds
Started Aug 05 05:14:20 PM PDT 24
Finished Aug 05 05:14:52 PM PDT 24
Peak memory 197740 kb
Host smart-2d5b438a-e91f-4b18-81ea-ed30ee117296
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010650158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1010650158
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.618276311
Short name T344
Test name
Test status
Simulation time 102302500586 ps
CPU time 491.67 seconds
Started Aug 05 05:14:21 PM PDT 24
Finished Aug 05 05:22:33 PM PDT 24
Peak memory 199900 kb
Host smart-d6dddb96-dc72-4ff9-a06b-3897b3167f61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=618276311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.618276311
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2341073018
Short name T1094
Test name
Test status
Simulation time 6220019074 ps
CPU time 2.72 seconds
Started Aug 05 05:14:26 PM PDT 24
Finished Aug 05 05:14:29 PM PDT 24
Peak memory 199844 kb
Host smart-7dbc4c3e-41ad-4a8e-be7c-db1e85afc343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341073018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2341073018
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.118401126
Short name T954
Test name
Test status
Simulation time 113546352131 ps
CPU time 117.56 seconds
Started Aug 05 05:14:20 PM PDT 24
Finished Aug 05 05:16:17 PM PDT 24
Peak memory 199892 kb
Host smart-cd5db2d2-337e-4658-907e-d84c25a0f59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118401126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.118401126
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3203884188
Short name T877
Test name
Test status
Simulation time 7645489131 ps
CPU time 110.36 seconds
Started Aug 05 05:14:26 PM PDT 24
Finished Aug 05 05:16:16 PM PDT 24
Peak memory 199824 kb
Host smart-9644cfd3-5a39-435d-8094-32a7c5e3a860
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203884188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3203884188
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1367462611
Short name T561
Test name
Test status
Simulation time 1934402596 ps
CPU time 2.86 seconds
Started Aug 05 05:14:26 PM PDT 24
Finished Aug 05 05:14:29 PM PDT 24
Peak memory 197836 kb
Host smart-a117b738-4e37-4def-a5c8-061b8e5de00c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1367462611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1367462611
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.223699744
Short name T461
Test name
Test status
Simulation time 154811416324 ps
CPU time 12.43 seconds
Started Aug 05 05:14:20 PM PDT 24
Finished Aug 05 05:14:33 PM PDT 24
Peak memory 198456 kb
Host smart-7824ef10-62b7-4ca0-b33c-7a405afc57ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223699744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.223699744
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.411186801
Short name T385
Test name
Test status
Simulation time 3380477563 ps
CPU time 1.79 seconds
Started Aug 05 05:14:26 PM PDT 24
Finished Aug 05 05:14:28 PM PDT 24
Peak memory 196188 kb
Host smart-ad5249dc-786e-4e87-a414-e938b614b2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411186801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.411186801
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.645774774
Short name T462
Test name
Test status
Simulation time 5850884561 ps
CPU time 29.68 seconds
Started Aug 05 05:14:18 PM PDT 24
Finished Aug 05 05:14:48 PM PDT 24
Peak memory 199856 kb
Host smart-3d21dcf4-06e5-4638-93ec-a2ed0611a46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645774774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.645774774
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.3304608003
Short name T842
Test name
Test status
Simulation time 117329693612 ps
CPU time 473.73 seconds
Started Aug 05 05:14:19 PM PDT 24
Finished Aug 05 05:22:13 PM PDT 24
Peak memory 199952 kb
Host smart-09fca51d-6b4e-496b-8e22-8e75c561ab7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304608003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3304608003
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.42366478
Short name T594
Test name
Test status
Simulation time 67476162793 ps
CPU time 239.11 seconds
Started Aug 05 05:14:19 PM PDT 24
Finished Aug 05 05:18:18 PM PDT 24
Peak memory 208568 kb
Host smart-69bdc28e-7b0f-42f7-b7fa-70f4f3f2f858
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42366478 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.42366478
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2595598379
Short name T704
Test name
Test status
Simulation time 1917773705 ps
CPU time 1.66 seconds
Started Aug 05 05:14:21 PM PDT 24
Finished Aug 05 05:14:22 PM PDT 24
Peak memory 198520 kb
Host smart-bf46522c-c487-4d1f-bcdf-c4e6eba85c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595598379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2595598379
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1925790119
Short name T919
Test name
Test status
Simulation time 18744026920 ps
CPU time 24.82 seconds
Started Aug 05 05:14:21 PM PDT 24
Finished Aug 05 05:14:46 PM PDT 24
Peak memory 199312 kb
Host smart-ba574560-1bc5-4a89-b540-184cc45dac20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925790119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1925790119
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.37690497
Short name T1056
Test name
Test status
Simulation time 108724511344 ps
CPU time 114.67 seconds
Started Aug 05 05:19:46 PM PDT 24
Finished Aug 05 05:21:41 PM PDT 24
Peak memory 199956 kb
Host smart-e5f23cb0-23dc-410c-b086-b7bfeff3fd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37690497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.37690497
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3527253174
Short name T510
Test name
Test status
Simulation time 214106404648 ps
CPU time 79.69 seconds
Started Aug 05 05:19:53 PM PDT 24
Finished Aug 05 05:21:13 PM PDT 24
Peak memory 199968 kb
Host smart-ace740d2-2274-42c6-98d8-8be810871feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527253174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3527253174
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1036327880
Short name T1075
Test name
Test status
Simulation time 22008033405 ps
CPU time 32.08 seconds
Started Aug 05 05:19:52 PM PDT 24
Finished Aug 05 05:20:25 PM PDT 24
Peak memory 198640 kb
Host smart-d03492d5-4a73-43ed-a19b-6117b97d8fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036327880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1036327880
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2902462243
Short name T389
Test name
Test status
Simulation time 16969592071 ps
CPU time 33.71 seconds
Started Aug 05 05:19:54 PM PDT 24
Finished Aug 05 05:20:28 PM PDT 24
Peak memory 199916 kb
Host smart-14de9ecc-7995-41d2-851a-d726501714f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902462243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2902462243
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.4084349155
Short name T866
Test name
Test status
Simulation time 61310100489 ps
CPU time 19.83 seconds
Started Aug 05 05:19:54 PM PDT 24
Finished Aug 05 05:20:14 PM PDT 24
Peak memory 199852 kb
Host smart-158d8dba-d185-413f-90dd-506435bb73a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084349155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.4084349155
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2703604256
Short name T574
Test name
Test status
Simulation time 128855446531 ps
CPU time 82.4 seconds
Started Aug 05 05:19:51 PM PDT 24
Finished Aug 05 05:21:14 PM PDT 24
Peak memory 199908 kb
Host smart-5c8a5b08-9629-4098-b16f-5af606f11d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703604256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2703604256
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2014282905
Short name T77
Test name
Test status
Simulation time 88766217023 ps
CPU time 62.3 seconds
Started Aug 05 05:19:50 PM PDT 24
Finished Aug 05 05:20:52 PM PDT 24
Peak memory 199868 kb
Host smart-5e9e964b-c38f-4adf-aaa7-761c02472db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014282905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2014282905
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3519130457
Short name T203
Test name
Test status
Simulation time 180726512643 ps
CPU time 71.34 seconds
Started Aug 05 05:19:51 PM PDT 24
Finished Aug 05 05:21:02 PM PDT 24
Peak memory 199976 kb
Host smart-2696cd00-466d-4e8f-b680-ba6009710756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519130457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3519130457
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1368757112
Short name T212
Test name
Test status
Simulation time 96326321073 ps
CPU time 82.28 seconds
Started Aug 05 05:19:53 PM PDT 24
Finished Aug 05 05:21:15 PM PDT 24
Peak memory 199948 kb
Host smart-958ef509-f63d-4197-a378-b5ead6000b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368757112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1368757112
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1918144021
Short name T200
Test name
Test status
Simulation time 23564035119 ps
CPU time 38.14 seconds
Started Aug 05 05:19:51 PM PDT 24
Finished Aug 05 05:20:29 PM PDT 24
Peak memory 199860 kb
Host smart-053d671e-9f66-4279-9841-5d6c37c4d51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918144021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1918144021
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1718724282
Short name T754
Test name
Test status
Simulation time 13013113 ps
CPU time 0.57 seconds
Started Aug 05 05:14:25 PM PDT 24
Finished Aug 05 05:14:26 PM PDT 24
Peak memory 195332 kb
Host smart-9bc98d86-0a47-43a9-a6b6-5a6d300cc6c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718724282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1718724282
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.401306882
Short name T177
Test name
Test status
Simulation time 98199479660 ps
CPU time 39.53 seconds
Started Aug 05 05:14:19 PM PDT 24
Finished Aug 05 05:14:59 PM PDT 24
Peak memory 199952 kb
Host smart-9bec7811-c8d0-4972-bd45-82f643b36fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401306882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.401306882
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.489095098
Short name T730
Test name
Test status
Simulation time 127374197058 ps
CPU time 197.67 seconds
Started Aug 05 05:14:20 PM PDT 24
Finished Aug 05 05:17:38 PM PDT 24
Peak memory 199832 kb
Host smart-4a9f5ba0-da77-40b9-b292-76a6ec2b4e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489095098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.489095098
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.3638920574
Short name T628
Test name
Test status
Simulation time 21552213484 ps
CPU time 9.67 seconds
Started Aug 05 05:14:21 PM PDT 24
Finished Aug 05 05:14:31 PM PDT 24
Peak memory 197516 kb
Host smart-0d5a9681-839f-477e-afe2-b3288700a9dc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638920574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3638920574
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_loopback.3072975892
Short name T618
Test name
Test status
Simulation time 7881066321 ps
CPU time 12.59 seconds
Started Aug 05 05:14:26 PM PDT 24
Finished Aug 05 05:14:39 PM PDT 24
Peak memory 199076 kb
Host smart-0b79e358-de89-4e0a-be98-1b365b7751e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072975892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3072975892
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.142815894
Short name T1044
Test name
Test status
Simulation time 47595173226 ps
CPU time 24.85 seconds
Started Aug 05 05:14:26 PM PDT 24
Finished Aug 05 05:14:51 PM PDT 24
Peak memory 194552 kb
Host smart-f0e767af-0670-44de-a634-764608ababf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142815894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.142815894
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.283931320
Short name T381
Test name
Test status
Simulation time 3895852561 ps
CPU time 8.85 seconds
Started Aug 05 05:14:22 PM PDT 24
Finished Aug 05 05:14:31 PM PDT 24
Peak memory 198424 kb
Host smart-8a1f9ea1-1ab1-4bdf-95c6-d2fede3b8626
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=283931320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.283931320
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.452269102
Short name T150
Test name
Test status
Simulation time 11784406057 ps
CPU time 19.73 seconds
Started Aug 05 05:14:33 PM PDT 24
Finished Aug 05 05:14:53 PM PDT 24
Peak memory 199892 kb
Host smart-feb669e4-b286-44cd-a971-c99ab38c7cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452269102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.452269102
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2518752234
Short name T5
Test name
Test status
Simulation time 2008367707 ps
CPU time 1.4 seconds
Started Aug 05 05:14:27 PM PDT 24
Finished Aug 05 05:14:28 PM PDT 24
Peak memory 195420 kb
Host smart-839574cf-5b4c-4d79-993f-596ddceb1116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518752234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2518752234
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.286301625
Short name T739
Test name
Test status
Simulation time 287282154 ps
CPU time 2.11 seconds
Started Aug 05 05:14:21 PM PDT 24
Finished Aug 05 05:14:23 PM PDT 24
Peak memory 199904 kb
Host smart-7f0efeee-8856-4c15-abc4-389cc202e77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286301625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.286301625
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1130805206
Short name T132
Test name
Test status
Simulation time 52371449672 ps
CPU time 258.26 seconds
Started Aug 05 05:14:26 PM PDT 24
Finished Aug 05 05:18:45 PM PDT 24
Peak memory 200156 kb
Host smart-02eec602-50ed-42b5-878b-cbd96ec40ae9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130805206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1130805206
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3857845141
Short name T217
Test name
Test status
Simulation time 369518637973 ps
CPU time 980.62 seconds
Started Aug 05 05:14:26 PM PDT 24
Finished Aug 05 05:30:47 PM PDT 24
Peak memory 232796 kb
Host smart-9d9c1b03-fe87-43e6-9f72-25c5a08d6778
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857845141 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3857845141
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1060960139
Short name T906
Test name
Test status
Simulation time 920122178 ps
CPU time 1.19 seconds
Started Aug 05 05:14:27 PM PDT 24
Finished Aug 05 05:14:28 PM PDT 24
Peak memory 198140 kb
Host smart-689bb75f-d024-4c75-be90-7f183fc91add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060960139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1060960139
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.1770095291
Short name T860
Test name
Test status
Simulation time 104001705061 ps
CPU time 78.54 seconds
Started Aug 05 05:14:21 PM PDT 24
Finished Aug 05 05:15:40 PM PDT 24
Peak memory 199928 kb
Host smart-e7b9de09-41e1-48c9-860a-b66ef4c6a437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770095291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1770095291
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.122472902
Short name T292
Test name
Test status
Simulation time 108268746263 ps
CPU time 156.03 seconds
Started Aug 05 05:20:08 PM PDT 24
Finished Aug 05 05:22:44 PM PDT 24
Peak memory 199836 kb
Host smart-a6072191-1954-48f1-b429-edc7c1082961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122472902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.122472902
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1831036606
Short name T1084
Test name
Test status
Simulation time 46536485359 ps
CPU time 70.33 seconds
Started Aug 05 05:20:00 PM PDT 24
Finished Aug 05 05:21:11 PM PDT 24
Peak memory 200000 kb
Host smart-af8a826e-4a6c-4831-b6d7-8e9571bd1783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831036606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1831036606
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2812892013
Short name T776
Test name
Test status
Simulation time 9960923384 ps
CPU time 22.48 seconds
Started Aug 05 05:20:05 PM PDT 24
Finished Aug 05 05:20:27 PM PDT 24
Peak memory 199984 kb
Host smart-f6148e3f-b436-4452-95f7-40f195e8bdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812892013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2812892013
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1839675523
Short name T883
Test name
Test status
Simulation time 108265575233 ps
CPU time 176.88 seconds
Started Aug 05 05:19:56 PM PDT 24
Finished Aug 05 05:22:53 PM PDT 24
Peak memory 199828 kb
Host smart-0a9e5411-c60a-446b-9d8e-3ac1baff2f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839675523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1839675523
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3766864294
Short name T571
Test name
Test status
Simulation time 59556828415 ps
CPU time 50.31 seconds
Started Aug 05 05:20:05 PM PDT 24
Finished Aug 05 05:20:56 PM PDT 24
Peak memory 199976 kb
Host smart-b9de307c-4f85-4cbd-aca1-68060cf36d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766864294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3766864294
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.932094330
Short name T538
Test name
Test status
Simulation time 21730711486 ps
CPU time 17.1 seconds
Started Aug 05 05:20:07 PM PDT 24
Finished Aug 05 05:20:25 PM PDT 24
Peak memory 199972 kb
Host smart-f1ba4c87-2b5a-49a9-8726-b6e86d66757a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932094330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.932094330
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2022202557
Short name T1002
Test name
Test status
Simulation time 17845324055 ps
CPU time 8.97 seconds
Started Aug 05 05:20:08 PM PDT 24
Finished Aug 05 05:20:17 PM PDT 24
Peak memory 200092 kb
Host smart-40136f54-b262-434a-9c21-6f5e1aaa34a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022202557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2022202557
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.158413663
Short name T228
Test name
Test status
Simulation time 114729502314 ps
CPU time 176.78 seconds
Started Aug 05 05:20:08 PM PDT 24
Finished Aug 05 05:23:05 PM PDT 24
Peak memory 199964 kb
Host smart-36aa234a-bc98-4c76-b84f-340c206f6389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158413663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.158413663
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.890396812
Short name T995
Test name
Test status
Simulation time 176266920086 ps
CPU time 29.91 seconds
Started Aug 05 05:20:09 PM PDT 24
Finished Aug 05 05:20:39 PM PDT 24
Peak memory 199908 kb
Host smart-19710709-d2ec-4f8c-8976-48aba44ffb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890396812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.890396812
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.27762037
Short name T1101
Test name
Test status
Simulation time 12899406 ps
CPU time 0.57 seconds
Started Aug 05 05:14:27 PM PDT 24
Finished Aug 05 05:14:28 PM PDT 24
Peak memory 195352 kb
Host smart-89a55cbd-eb71-463f-954b-eac1045185d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27762037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.27762037
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1562630437
Short name T719
Test name
Test status
Simulation time 22266432002 ps
CPU time 28.71 seconds
Started Aug 05 05:14:26 PM PDT 24
Finished Aug 05 05:14:55 PM PDT 24
Peak memory 199956 kb
Host smart-f682980c-0f00-4fac-829a-ffdbb3b6219a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562630437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1562630437
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2730337913
Short name T53
Test name
Test status
Simulation time 8200699264 ps
CPU time 13 seconds
Started Aug 05 05:14:26 PM PDT 24
Finished Aug 05 05:14:39 PM PDT 24
Peak memory 199112 kb
Host smart-8b34e703-d6d0-4b13-8ab8-90ad8689672a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730337913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2730337913
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3851360211
Short name T1102
Test name
Test status
Simulation time 31777319320 ps
CPU time 16.88 seconds
Started Aug 05 05:14:28 PM PDT 24
Finished Aug 05 05:14:44 PM PDT 24
Peak memory 199908 kb
Host smart-281efe2b-201a-47be-b19c-8bdeaaaaaf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851360211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3851360211
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.3060055822
Short name T131
Test name
Test status
Simulation time 354611401637 ps
CPU time 527.75 seconds
Started Aug 05 05:14:32 PM PDT 24
Finished Aug 05 05:23:19 PM PDT 24
Peak memory 198180 kb
Host smart-ea167d33-0ffe-4179-b3e1-1a031ee13b57
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060055822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3060055822
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2954098395
Short name T710
Test name
Test status
Simulation time 133715808560 ps
CPU time 547.64 seconds
Started Aug 05 05:14:30 PM PDT 24
Finished Aug 05 05:23:38 PM PDT 24
Peak memory 199848 kb
Host smart-ca7a23fd-db3d-498e-869e-2ab0dc9ed1e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2954098395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2954098395
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2374669138
Short name T779
Test name
Test status
Simulation time 7886747364 ps
CPU time 3.42 seconds
Started Aug 05 05:14:26 PM PDT 24
Finished Aug 05 05:14:30 PM PDT 24
Peak memory 199356 kb
Host smart-b984fb7b-0b29-4bab-a55c-b3558ca55175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374669138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2374669138
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.683269067
Short name T829
Test name
Test status
Simulation time 62321393062 ps
CPU time 27.57 seconds
Started Aug 05 05:14:26 PM PDT 24
Finished Aug 05 05:14:54 PM PDT 24
Peak memory 199772 kb
Host smart-5c865d67-db44-43d1-ab6b-a4b8ca4d71a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683269067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.683269067
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2522382388
Short name T310
Test name
Test status
Simulation time 45707305342 ps
CPU time 152.24 seconds
Started Aug 05 05:14:29 PM PDT 24
Finished Aug 05 05:17:02 PM PDT 24
Peak memory 199972 kb
Host smart-5e02c08e-c06e-45e1-b240-5c144997c277
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2522382388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2522382388
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2787861464
Short name T336
Test name
Test status
Simulation time 3781577106 ps
CPU time 14.13 seconds
Started Aug 05 05:14:32 PM PDT 24
Finished Aug 05 05:14:46 PM PDT 24
Peak memory 199056 kb
Host smart-c330e2c9-1545-45eb-a2cd-4b46cf53a287
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2787861464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2787861464
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3264534948
Short name T529
Test name
Test status
Simulation time 22493569346 ps
CPU time 31.8 seconds
Started Aug 05 05:14:32 PM PDT 24
Finished Aug 05 05:15:03 PM PDT 24
Peak memory 199856 kb
Host smart-1c922ac7-40cc-4619-a2d0-c25795d30acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264534948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3264534948
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2287875776
Short name T649
Test name
Test status
Simulation time 46015292148 ps
CPU time 16.44 seconds
Started Aug 05 05:14:26 PM PDT 24
Finished Aug 05 05:14:43 PM PDT 24
Peak memory 196768 kb
Host smart-50ee2535-25fc-4528-9fb1-a9992ad0a8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287875776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2287875776
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.554852693
Short name T867
Test name
Test status
Simulation time 5685164048 ps
CPU time 13.91 seconds
Started Aug 05 05:14:25 PM PDT 24
Finished Aug 05 05:14:39 PM PDT 24
Peak memory 199108 kb
Host smart-ccb2d070-a955-41a4-b903-e38987346204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554852693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.554852693
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3007234510
Short name T1049
Test name
Test status
Simulation time 87611659026 ps
CPU time 1033.96 seconds
Started Aug 05 05:14:27 PM PDT 24
Finished Aug 05 05:31:41 PM PDT 24
Peak memory 227012 kb
Host smart-40d82337-598e-45b1-b1c9-6a31c384fb44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007234510 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3007234510
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.617431810
Short name T379
Test name
Test status
Simulation time 1575304444 ps
CPU time 2.9 seconds
Started Aug 05 05:14:28 PM PDT 24
Finished Aug 05 05:14:31 PM PDT 24
Peak memory 198472 kb
Host smart-2805de06-ba98-4c45-8d73-a7915f000469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617431810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.617431810
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3770980421
Short name T570
Test name
Test status
Simulation time 48465205103 ps
CPU time 8.75 seconds
Started Aug 05 05:14:33 PM PDT 24
Finished Aug 05 05:14:42 PM PDT 24
Peak memory 199968 kb
Host smart-d00c8720-d837-4035-946e-208567a430eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770980421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3770980421
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1437126620
Short name T504
Test name
Test status
Simulation time 63909573018 ps
CPU time 23.7 seconds
Started Aug 05 05:20:09 PM PDT 24
Finished Aug 05 05:20:33 PM PDT 24
Peak memory 199892 kb
Host smart-31d15408-b550-4291-aa85-5dacb648780f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437126620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1437126620
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.238852115
Short name T1003
Test name
Test status
Simulation time 89068827953 ps
CPU time 68.36 seconds
Started Aug 05 05:20:09 PM PDT 24
Finished Aug 05 05:21:18 PM PDT 24
Peak memory 199988 kb
Host smart-19a16da0-9ac6-4969-a6bb-a4f1a418b730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238852115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.238852115
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.376436337
Short name T541
Test name
Test status
Simulation time 19025122060 ps
CPU time 22.79 seconds
Started Aug 05 05:20:09 PM PDT 24
Finished Aug 05 05:20:32 PM PDT 24
Peak memory 199808 kb
Host smart-9e8e08af-5596-4333-90ed-b11569b98380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376436337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.376436337
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2955160702
Short name T251
Test name
Test status
Simulation time 17080535716 ps
CPU time 31.45 seconds
Started Aug 05 05:20:05 PM PDT 24
Finished Aug 05 05:20:36 PM PDT 24
Peak memory 199916 kb
Host smart-34a2198d-6b91-4957-a748-bc5fedd642a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955160702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2955160702
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1615938060
Short name T219
Test name
Test status
Simulation time 50321591242 ps
CPU time 86.36 seconds
Started Aug 05 05:20:09 PM PDT 24
Finished Aug 05 05:21:35 PM PDT 24
Peak memory 199788 kb
Host smart-2659d906-a679-4bb5-af3b-fdd1bbc86869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615938060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1615938060
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2902525391
Short name T661
Test name
Test status
Simulation time 74958599723 ps
CPU time 13.31 seconds
Started Aug 05 05:20:12 PM PDT 24
Finished Aug 05 05:20:25 PM PDT 24
Peak memory 199904 kb
Host smart-912ebc7f-66c1-479b-b4e1-ab08575fee98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902525391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2902525391
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1119852937
Short name T4
Test name
Test status
Simulation time 17797550873 ps
CPU time 29.14 seconds
Started Aug 05 05:20:10 PM PDT 24
Finished Aug 05 05:20:39 PM PDT 24
Peak memory 199220 kb
Host smart-8854e0bd-3eb4-44e1-b53c-3ffe83ed3705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119852937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1119852937
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2667979181
Short name T254
Test name
Test status
Simulation time 124725995180 ps
CPU time 45.43 seconds
Started Aug 05 05:20:19 PM PDT 24
Finished Aug 05 05:21:04 PM PDT 24
Peak memory 199948 kb
Host smart-1cb2eb44-3530-4956-b7d7-a2a700a8f713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667979181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2667979181
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.648630217
Short name T330
Test name
Test status
Simulation time 31916857354 ps
CPU time 20.29 seconds
Started Aug 05 05:20:09 PM PDT 24
Finished Aug 05 05:20:29 PM PDT 24
Peak memory 199888 kb
Host smart-2ffe9a95-5f29-4a47-b526-dd5148034a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648630217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.648630217
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.4068373773
Short name T348
Test name
Test status
Simulation time 21756686 ps
CPU time 0.57 seconds
Started Aug 05 05:14:35 PM PDT 24
Finished Aug 05 05:14:35 PM PDT 24
Peak memory 195352 kb
Host smart-b939c96d-7f32-46cd-9ad8-0bb4ed504363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068373773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.4068373773
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.132528213
Short name T1070
Test name
Test status
Simulation time 49615752020 ps
CPU time 79.22 seconds
Started Aug 05 05:14:29 PM PDT 24
Finished Aug 05 05:15:49 PM PDT 24
Peak memory 199968 kb
Host smart-2ed2d4b7-8ebe-449a-80d8-407e3c510e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132528213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.132528213
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3214382720
Short name T33
Test name
Test status
Simulation time 26192217426 ps
CPU time 43.13 seconds
Started Aug 05 05:14:26 PM PDT 24
Finished Aug 05 05:15:09 PM PDT 24
Peak memory 199920 kb
Host smart-3b093c44-6f2a-4576-93bc-43cc44bd9ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214382720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3214382720
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2030214776
Short name T327
Test name
Test status
Simulation time 28698824522 ps
CPU time 47.33 seconds
Started Aug 05 05:14:25 PM PDT 24
Finished Aug 05 05:15:12 PM PDT 24
Peak memory 199960 kb
Host smart-0387c407-2330-49c7-9584-48e2bbe1991a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030214776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2030214776
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1687846145
Short name T937
Test name
Test status
Simulation time 110050939356 ps
CPU time 47.79 seconds
Started Aug 05 05:14:33 PM PDT 24
Finished Aug 05 05:15:21 PM PDT 24
Peak memory 199912 kb
Host smart-d80e3911-bfd5-4efc-ac75-242d05da0abb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687846145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1687846145
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.1215657427
Short name T315
Test name
Test status
Simulation time 68199579738 ps
CPU time 89.35 seconds
Started Aug 05 05:14:33 PM PDT 24
Finished Aug 05 05:16:02 PM PDT 24
Peak memory 199940 kb
Host smart-81473d00-58a0-4900-9670-21354415fb4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1215657427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1215657427
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.3671403902
Short name T595
Test name
Test status
Simulation time 9663577069 ps
CPU time 11.35 seconds
Started Aug 05 05:14:35 PM PDT 24
Finished Aug 05 05:14:46 PM PDT 24
Peak memory 199592 kb
Host smart-b929604c-8c0f-4877-b842-4eaa0c52ca67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671403902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3671403902
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2666093240
Short name T469
Test name
Test status
Simulation time 141066233999 ps
CPU time 71.98 seconds
Started Aug 05 05:14:35 PM PDT 24
Finished Aug 05 05:15:47 PM PDT 24
Peak memory 208248 kb
Host smart-59a71396-880b-4f8a-8c71-af1a69febac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666093240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2666093240
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.802846697
Short name T1130
Test name
Test status
Simulation time 8979995805 ps
CPU time 546.71 seconds
Started Aug 05 05:14:34 PM PDT 24
Finished Aug 05 05:23:41 PM PDT 24
Peak memory 199920 kb
Host smart-b1cb18b8-124c-4115-a84c-73077822ba06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=802846697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.802846697
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.4229370809
Short name T944
Test name
Test status
Simulation time 2766676972 ps
CPU time 19.3 seconds
Started Aug 05 05:14:32 PM PDT 24
Finished Aug 05 05:14:51 PM PDT 24
Peak memory 198896 kb
Host smart-faacb761-6d64-4bfc-a855-95b8789227f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4229370809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.4229370809
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1549204433
Short name T808
Test name
Test status
Simulation time 219592755123 ps
CPU time 61.61 seconds
Started Aug 05 05:14:32 PM PDT 24
Finished Aug 05 05:15:34 PM PDT 24
Peak memory 199860 kb
Host smart-a037a68c-6fc6-44ef-80ee-86ddc69eee3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549204433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1549204433
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.4011170220
Short name T815
Test name
Test status
Simulation time 642367063 ps
CPU time 1.06 seconds
Started Aug 05 05:14:34 PM PDT 24
Finished Aug 05 05:14:35 PM PDT 24
Peak memory 195576 kb
Host smart-3efb34bc-b472-4b7d-91a9-90ef5e8d3da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011170220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.4011170220
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1935789046
Short name T501
Test name
Test status
Simulation time 11635106408 ps
CPU time 40.45 seconds
Started Aug 05 05:14:27 PM PDT 24
Finished Aug 05 05:15:07 PM PDT 24
Peak memory 199836 kb
Host smart-589f01db-b389-4e95-b624-779316111d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935789046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1935789046
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1868879044
Short name T491
Test name
Test status
Simulation time 121437043272 ps
CPU time 731.28 seconds
Started Aug 05 05:14:32 PM PDT 24
Finished Aug 05 05:26:43 PM PDT 24
Peak memory 199920 kb
Host smart-c7ecc4f5-6ca1-4481-8c04-13de032e8545
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868879044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1868879044
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.806664458
Short name T63
Test name
Test status
Simulation time 14696555585 ps
CPU time 167.51 seconds
Started Aug 05 05:14:34 PM PDT 24
Finished Aug 05 05:17:22 PM PDT 24
Peak memory 216248 kb
Host smart-1d81bf45-186b-411d-8bc2-6429d14e6351
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806664458 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.806664458
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.4288801827
Short name T508
Test name
Test status
Simulation time 7123203053 ps
CPU time 21.73 seconds
Started Aug 05 05:14:31 PM PDT 24
Finished Aug 05 05:14:53 PM PDT 24
Peak memory 199436 kb
Host smart-34e847ce-a6ad-4e4b-8e21-d716d17b2300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288801827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.4288801827
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3385285431
Short name T757
Test name
Test status
Simulation time 1273585229 ps
CPU time 1.39 seconds
Started Aug 05 05:14:26 PM PDT 24
Finished Aug 05 05:14:28 PM PDT 24
Peak memory 196824 kb
Host smart-83550017-1fa3-4424-93ea-2da4943616c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385285431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3385285431
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.1420156350
Short name T507
Test name
Test status
Simulation time 28992034704 ps
CPU time 27.65 seconds
Started Aug 05 05:20:10 PM PDT 24
Finished Aug 05 05:20:38 PM PDT 24
Peak memory 199904 kb
Host smart-7e56cb24-6f75-437b-b55a-490ec1eff433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420156350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1420156350
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.917682758
Short name T149
Test name
Test status
Simulation time 34391366344 ps
CPU time 35.83 seconds
Started Aug 05 05:20:09 PM PDT 24
Finished Aug 05 05:20:45 PM PDT 24
Peak memory 199884 kb
Host smart-bbbf0a22-3e63-4e98-b885-6496941b1f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917682758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.917682758
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1285354445
Short name T164
Test name
Test status
Simulation time 14047505411 ps
CPU time 23.32 seconds
Started Aug 05 05:20:16 PM PDT 24
Finished Aug 05 05:20:39 PM PDT 24
Peak memory 200088 kb
Host smart-eb385aac-8f66-4920-8bde-fd31f1d5c027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285354445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1285354445
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3541531395
Short name T665
Test name
Test status
Simulation time 93770604676 ps
CPU time 37.81 seconds
Started Aug 05 05:20:17 PM PDT 24
Finished Aug 05 05:20:55 PM PDT 24
Peak memory 199896 kb
Host smart-07442964-142b-4d50-b491-2b68917d7d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541531395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3541531395
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2326824297
Short name T206
Test name
Test status
Simulation time 59163740300 ps
CPU time 49.8 seconds
Started Aug 05 05:20:16 PM PDT 24
Finished Aug 05 05:21:06 PM PDT 24
Peak memory 199952 kb
Host smart-e772e823-ba04-414c-b189-c667270a8acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326824297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2326824297
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.437316441
Short name T899
Test name
Test status
Simulation time 25063727638 ps
CPU time 11.7 seconds
Started Aug 05 05:20:15 PM PDT 24
Finished Aug 05 05:20:27 PM PDT 24
Peak memory 199972 kb
Host smart-eb3dc6d3-9692-484e-a784-66066c26a8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437316441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.437316441
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1325397782
Short name T1165
Test name
Test status
Simulation time 235678090191 ps
CPU time 20.35 seconds
Started Aug 05 05:20:15 PM PDT 24
Finished Aug 05 05:20:36 PM PDT 24
Peak memory 199884 kb
Host smart-a2eb50bf-b37e-480a-a708-4fbf90e31919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325397782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1325397782
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1654010679
Short name T816
Test name
Test status
Simulation time 46701612885 ps
CPU time 101.09 seconds
Started Aug 05 05:20:16 PM PDT 24
Finished Aug 05 05:21:57 PM PDT 24
Peak memory 199892 kb
Host smart-a8811585-51d5-47f6-8040-27a7601b6c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654010679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1654010679
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1708358926
Short name T480
Test name
Test status
Simulation time 29706816 ps
CPU time 0.56 seconds
Started Aug 05 05:14:44 PM PDT 24
Finished Aug 05 05:14:45 PM PDT 24
Peak memory 194548 kb
Host smart-7677ed83-418d-4829-90e4-fa1a372047a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708358926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1708358926
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2077473279
Short name T290
Test name
Test status
Simulation time 121295979558 ps
CPU time 290.37 seconds
Started Aug 05 05:14:33 PM PDT 24
Finished Aug 05 05:19:24 PM PDT 24
Peak memory 199832 kb
Host smart-b31e5e8f-f279-4c6a-83ca-2a808edcc525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077473279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2077473279
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.4094972047
Short name T402
Test name
Test status
Simulation time 71652601290 ps
CPU time 107.91 seconds
Started Aug 05 05:14:33 PM PDT 24
Finished Aug 05 05:16:21 PM PDT 24
Peak memory 199904 kb
Host smart-6e44eb2a-ae30-4b9d-96e3-29a091bf2994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094972047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.4094972047
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_intr.1621901098
Short name T283
Test name
Test status
Simulation time 303114232921 ps
CPU time 515.42 seconds
Started Aug 05 05:14:36 PM PDT 24
Finished Aug 05 05:23:11 PM PDT 24
Peak memory 199964 kb
Host smart-118a6809-39a3-438b-8e81-8baf0d4e5f17
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621901098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1621901098
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.306188414
Short name T629
Test name
Test status
Simulation time 197300105881 ps
CPU time 845.63 seconds
Started Aug 05 05:14:40 PM PDT 24
Finished Aug 05 05:28:45 PM PDT 24
Peak memory 199868 kb
Host smart-b9645a68-965b-4504-a94c-132efaa4426a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=306188414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.306188414
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.756517364
Short name T456
Test name
Test status
Simulation time 96017658 ps
CPU time 0.93 seconds
Started Aug 05 05:14:36 PM PDT 24
Finished Aug 05 05:14:37 PM PDT 24
Peak memory 198160 kb
Host smart-092bc6fb-86c6-4f40-a4ba-72b51a53918c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756517364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.756517364
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2737803559
Short name T305
Test name
Test status
Simulation time 37535445092 ps
CPU time 62.7 seconds
Started Aug 05 05:14:35 PM PDT 24
Finished Aug 05 05:15:38 PM PDT 24
Peak memory 208268 kb
Host smart-c717569d-b29f-4859-a2e4-da865a24c19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737803559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2737803559
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3915372610
Short name T531
Test name
Test status
Simulation time 10613858874 ps
CPU time 79.58 seconds
Started Aug 05 05:14:34 PM PDT 24
Finished Aug 05 05:15:54 PM PDT 24
Peak memory 199972 kb
Host smart-091d513f-89db-4ec5-ad8b-6011e94c1947
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3915372610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3915372610
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.581463707
Short name T701
Test name
Test status
Simulation time 6611985498 ps
CPU time 63.49 seconds
Started Aug 05 05:14:33 PM PDT 24
Finished Aug 05 05:15:37 PM PDT 24
Peak memory 197788 kb
Host smart-16dc0d09-0dc7-4fe9-9125-68cc3e2bbc7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=581463707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.581463707
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1921099881
Short name T1008
Test name
Test status
Simulation time 39598406186 ps
CPU time 53.75 seconds
Started Aug 05 05:14:32 PM PDT 24
Finished Aug 05 05:15:26 PM PDT 24
Peak memory 196276 kb
Host smart-4faf5320-59bc-4b53-ac30-6129b8919137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921099881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1921099881
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.90398712
Short name T1066
Test name
Test status
Simulation time 933844021 ps
CPU time 3.97 seconds
Started Aug 05 05:14:34 PM PDT 24
Finished Aug 05 05:14:38 PM PDT 24
Peak memory 199780 kb
Host smart-c3c92d39-2b4c-4523-84b7-63ce8f806d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90398712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.90398712
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2632501160
Short name T1177
Test name
Test status
Simulation time 6467274483 ps
CPU time 15.88 seconds
Started Aug 05 05:14:34 PM PDT 24
Finished Aug 05 05:14:49 PM PDT 24
Peak memory 199728 kb
Host smart-6eba17b1-b1ff-40c9-ba8e-332cf2359f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632501160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2632501160
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.178777128
Short name T1111
Test name
Test status
Simulation time 27392831453 ps
CPU time 18.86 seconds
Started Aug 05 05:14:37 PM PDT 24
Finished Aug 05 05:14:56 PM PDT 24
Peak memory 199924 kb
Host smart-4fb08e18-14c6-4585-b908-5871fe1a01d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178777128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.178777128
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1072277353
Short name T242
Test name
Test status
Simulation time 55737145538 ps
CPU time 43.45 seconds
Started Aug 05 05:20:15 PM PDT 24
Finished Aug 05 05:20:59 PM PDT 24
Peak memory 199912 kb
Host smart-83f5a52f-96e3-493e-9b92-468de180eb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072277353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1072277353
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1422093540
Short name T854
Test name
Test status
Simulation time 12658545363 ps
CPU time 17.17 seconds
Started Aug 05 05:20:16 PM PDT 24
Finished Aug 05 05:20:33 PM PDT 24
Peak memory 199908 kb
Host smart-30eaa150-a43a-450d-807a-89cc70387e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422093540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1422093540
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3752215206
Short name T116
Test name
Test status
Simulation time 70356725560 ps
CPU time 102.23 seconds
Started Aug 05 05:20:16 PM PDT 24
Finished Aug 05 05:21:59 PM PDT 24
Peak memory 199968 kb
Host smart-144e90ae-29e9-4664-936d-25ded7a41011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752215206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3752215206
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1844781072
Short name T1069
Test name
Test status
Simulation time 120890615073 ps
CPU time 690.98 seconds
Started Aug 05 05:20:17 PM PDT 24
Finished Aug 05 05:31:48 PM PDT 24
Peak memory 199812 kb
Host smart-73ffc03e-0769-40c4-a0ab-6f9681232a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844781072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1844781072
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2478763262
Short name T921
Test name
Test status
Simulation time 89866211178 ps
CPU time 152.3 seconds
Started Aug 05 05:20:15 PM PDT 24
Finished Aug 05 05:22:47 PM PDT 24
Peak memory 199848 kb
Host smart-a4490bde-c7a8-4584-8c24-40c4f4b7068b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478763262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2478763262
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.654438459
Short name T1105
Test name
Test status
Simulation time 23463246982 ps
CPU time 35.83 seconds
Started Aug 05 05:20:23 PM PDT 24
Finished Aug 05 05:20:59 PM PDT 24
Peak memory 199972 kb
Host smart-8201a3c3-5a23-4cd9-937e-dd3b6b977187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654438459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.654438459
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1570409950
Short name T201
Test name
Test status
Simulation time 60848943826 ps
CPU time 25.02 seconds
Started Aug 05 05:20:23 PM PDT 24
Finished Aug 05 05:20:48 PM PDT 24
Peak memory 199944 kb
Host smart-9674aca5-d89b-496a-8a81-8d142ba7bd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570409950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1570409950
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.738183341
Short name T735
Test name
Test status
Simulation time 245828903654 ps
CPU time 64.53 seconds
Started Aug 05 05:20:23 PM PDT 24
Finished Aug 05 05:21:28 PM PDT 24
Peak memory 199872 kb
Host smart-84d50c4c-8490-43e3-b290-48da70469c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738183341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.738183341
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.538756139
Short name T76
Test name
Test status
Simulation time 49704847221 ps
CPU time 18.5 seconds
Started Aug 05 05:20:25 PM PDT 24
Finished Aug 05 05:20:43 PM PDT 24
Peak memory 199952 kb
Host smart-93038388-756b-46f2-8c69-b8bd24181745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538756139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.538756139
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2583054672
Short name T171
Test name
Test status
Simulation time 79509112841 ps
CPU time 35.54 seconds
Started Aug 05 05:20:21 PM PDT 24
Finished Aug 05 05:20:56 PM PDT 24
Peak memory 199892 kb
Host smart-6de8c545-80dc-499f-9d25-b669d7623ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583054672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2583054672
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1315509084
Short name T771
Test name
Test status
Simulation time 92998101 ps
CPU time 0.55 seconds
Started Aug 05 05:14:50 PM PDT 24
Finished Aug 05 05:14:50 PM PDT 24
Peak memory 195636 kb
Host smart-d672c1c4-173e-446b-b21e-4d69208d5492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315509084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1315509084
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1960221755
Short name T828
Test name
Test status
Simulation time 68313162259 ps
CPU time 58.36 seconds
Started Aug 05 05:14:41 PM PDT 24
Finished Aug 05 05:15:40 PM PDT 24
Peak memory 199908 kb
Host smart-435e8615-3d18-4969-92f5-911c29b811e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960221755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1960221755
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1156414983
Short name T633
Test name
Test status
Simulation time 154385887659 ps
CPU time 221.48 seconds
Started Aug 05 05:14:43 PM PDT 24
Finished Aug 05 05:18:24 PM PDT 24
Peak memory 199836 kb
Host smart-1fd07aa5-ee34-4dcd-94f7-e36d3ce63459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156414983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1156414983
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3932288501
Short name T1151
Test name
Test status
Simulation time 196972499966 ps
CPU time 38.48 seconds
Started Aug 05 05:14:41 PM PDT 24
Finished Aug 05 05:15:20 PM PDT 24
Peak memory 199960 kb
Host smart-5627d18b-247f-41ea-a3cf-d4f782fa6296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932288501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3932288501
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.2588424632
Short name T299
Test name
Test status
Simulation time 150260621560 ps
CPU time 76.55 seconds
Started Aug 05 05:14:43 PM PDT 24
Finished Aug 05 05:16:00 PM PDT 24
Peak memory 199404 kb
Host smart-3dc78ce5-8a91-4592-9120-0a45f276460c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588424632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2588424632
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.4190859792
Short name T715
Test name
Test status
Simulation time 87401299460 ps
CPU time 626.25 seconds
Started Aug 05 05:14:41 PM PDT 24
Finished Aug 05 05:25:08 PM PDT 24
Peak memory 199924 kb
Host smart-d7607a17-8da0-404f-a167-cd0a581cf654
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4190859792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.4190859792
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1441732530
Short name T806
Test name
Test status
Simulation time 9085798006 ps
CPU time 17.34 seconds
Started Aug 05 05:14:39 PM PDT 24
Finished Aug 05 05:14:57 PM PDT 24
Peak memory 199384 kb
Host smart-a7042ed4-5060-4f85-b737-39fcdf8f9b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441732530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1441732530
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.4165780363
Short name T663
Test name
Test status
Simulation time 126087033637 ps
CPU time 167.51 seconds
Started Aug 05 05:14:40 PM PDT 24
Finished Aug 05 05:17:27 PM PDT 24
Peak memory 199980 kb
Host smart-9e712f6d-0a52-4d4b-bd72-f49c85e1295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165780363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.4165780363
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3174399318
Short name T509
Test name
Test status
Simulation time 10395088697 ps
CPU time 242.02 seconds
Started Aug 05 05:14:39 PM PDT 24
Finished Aug 05 05:18:41 PM PDT 24
Peak memory 199840 kb
Host smart-26f5f6d7-64bd-469f-8fa9-c8d848cf8cd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3174399318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3174399318
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2145465932
Short name T321
Test name
Test status
Simulation time 7277764564 ps
CPU time 16.23 seconds
Started Aug 05 05:14:38 PM PDT 24
Finished Aug 05 05:14:55 PM PDT 24
Peak memory 199816 kb
Host smart-1a958070-8f01-425f-b0af-7e6dffc41f24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2145465932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2145465932
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2874202430
Short name T1116
Test name
Test status
Simulation time 268876132073 ps
CPU time 40.28 seconds
Started Aug 05 05:14:42 PM PDT 24
Finished Aug 05 05:15:22 PM PDT 24
Peak memory 199868 kb
Host smart-0fce2828-6f7a-4e17-ac18-30fdb6b72f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874202430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2874202430
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3131499910
Short name T920
Test name
Test status
Simulation time 2740710586 ps
CPU time 2.01 seconds
Started Aug 05 05:14:40 PM PDT 24
Finished Aug 05 05:14:42 PM PDT 24
Peak memory 196456 kb
Host smart-ac802df2-f226-413d-a299-7937d7901431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131499910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3131499910
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1282378334
Short name T413
Test name
Test status
Simulation time 11065431227 ps
CPU time 35.59 seconds
Started Aug 05 05:14:42 PM PDT 24
Finished Aug 05 05:15:18 PM PDT 24
Peak memory 199828 kb
Host smart-a864b418-ce91-43cd-bb2f-2e471fc60d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282378334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1282378334
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1145490160
Short name T239
Test name
Test status
Simulation time 381911791071 ps
CPU time 218.18 seconds
Started Aug 05 05:14:46 PM PDT 24
Finished Aug 05 05:18:24 PM PDT 24
Peak memory 199848 kb
Host smart-6bd3bc14-5825-48f2-a004-d84e17f2177d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145490160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1145490160
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.4258354770
Short name T62
Test name
Test status
Simulation time 168254290220 ps
CPU time 463.27 seconds
Started Aug 05 05:14:40 PM PDT 24
Finished Aug 05 05:22:23 PM PDT 24
Peak memory 216500 kb
Host smart-27985770-0aa6-4a39-a83a-149774a7ccb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258354770 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.4258354770
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2807465175
Short name T536
Test name
Test status
Simulation time 1501390692 ps
CPU time 2.52 seconds
Started Aug 05 05:14:45 PM PDT 24
Finished Aug 05 05:14:47 PM PDT 24
Peak memory 198452 kb
Host smart-7c6121bc-39da-45f8-8e91-e664178182ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807465175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2807465175
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.738651960
Short name T1042
Test name
Test status
Simulation time 118736497652 ps
CPU time 226.52 seconds
Started Aug 05 05:14:42 PM PDT 24
Finished Aug 05 05:18:28 PM PDT 24
Peak memory 200148 kb
Host smart-bfdca030-2db0-46b4-b707-336fb055c5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738651960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.738651960
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2442125109
Short name T197
Test name
Test status
Simulation time 54375352774 ps
CPU time 26.27 seconds
Started Aug 05 05:20:23 PM PDT 24
Finished Aug 05 05:20:49 PM PDT 24
Peak memory 199980 kb
Host smart-adb1d078-1ce1-4475-9d48-bb254fac648e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442125109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2442125109
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3725790930
Short name T1167
Test name
Test status
Simulation time 108521533952 ps
CPU time 237.99 seconds
Started Aug 05 05:20:24 PM PDT 24
Finished Aug 05 05:24:22 PM PDT 24
Peak memory 199916 kb
Host smart-57fa6ba7-692f-4c39-bcfd-7a6fa8e5b16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725790930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3725790930
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.4084064397
Short name T400
Test name
Test status
Simulation time 114677038094 ps
CPU time 70.14 seconds
Started Aug 05 05:20:26 PM PDT 24
Finished Aug 05 05:21:36 PM PDT 24
Peak memory 199972 kb
Host smart-ad78c73a-b119-4e19-8fe2-17d032212ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084064397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.4084064397
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3887391477
Short name T741
Test name
Test status
Simulation time 12323845207 ps
CPU time 13.15 seconds
Started Aug 05 05:20:26 PM PDT 24
Finished Aug 05 05:20:39 PM PDT 24
Peak memory 199908 kb
Host smart-7ca3ef52-4613-410d-ba24-30fdad3e7340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887391477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3887391477
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.576081447
Short name T274
Test name
Test status
Simulation time 37748259557 ps
CPU time 68.49 seconds
Started Aug 05 05:20:27 PM PDT 24
Finished Aug 05 05:21:36 PM PDT 24
Peak memory 199944 kb
Host smart-f295ed89-65ce-4d2f-b798-2cde3127828f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576081447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.576081447
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.622481688
Short name T204
Test name
Test status
Simulation time 26843980350 ps
CPU time 43.96 seconds
Started Aug 05 05:20:30 PM PDT 24
Finished Aug 05 05:21:14 PM PDT 24
Peak memory 199776 kb
Host smart-e84897eb-0dd2-49ce-99fb-9efe6c718510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622481688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.622481688
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.1961127604
Short name T1175
Test name
Test status
Simulation time 93657585581 ps
CPU time 24.64 seconds
Started Aug 05 05:20:32 PM PDT 24
Finished Aug 05 05:20:57 PM PDT 24
Peak memory 199980 kb
Host smart-d5afe317-65b1-4206-b7e2-64ab7aad4f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961127604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1961127604
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.171454264
Short name T938
Test name
Test status
Simulation time 9563657371 ps
CPU time 17.21 seconds
Started Aug 05 05:20:32 PM PDT 24
Finished Aug 05 05:20:49 PM PDT 24
Peak memory 199812 kb
Host smart-5fe8e3e4-f280-4bbf-b778-a8eed15fbaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171454264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.171454264
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2776294727
Short name T482
Test name
Test status
Simulation time 18209530169 ps
CPU time 12.26 seconds
Started Aug 05 05:20:32 PM PDT 24
Finished Aug 05 05:20:45 PM PDT 24
Peak memory 199912 kb
Host smart-6e7e83ab-dc7b-4d55-9c33-70fcc766d1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776294727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2776294727
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2875396530
Short name T417
Test name
Test status
Simulation time 13253727 ps
CPU time 0.57 seconds
Started Aug 05 05:13:26 PM PDT 24
Finished Aug 05 05:13:26 PM PDT 24
Peak memory 195288 kb
Host smart-0c9722cc-888b-4c0e-a2ce-4cb3a0841b79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875396530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2875396530
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1938245210
Short name T1099
Test name
Test status
Simulation time 9691785551 ps
CPU time 14.14 seconds
Started Aug 05 05:13:24 PM PDT 24
Finished Aug 05 05:13:38 PM PDT 24
Peak memory 199964 kb
Host smart-4a2eb19c-4a5b-4471-8cf8-650a77242652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938245210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1938245210
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.472136573
Short name T457
Test name
Test status
Simulation time 28949106357 ps
CPU time 69.51 seconds
Started Aug 05 05:13:29 PM PDT 24
Finished Aug 05 05:14:39 PM PDT 24
Peak memory 199988 kb
Host smart-a7299d4d-85e7-45c5-b895-50b8cda8934a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472136573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.472136573
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1973701139
Short name T586
Test name
Test status
Simulation time 28560392345 ps
CPU time 25.7 seconds
Started Aug 05 05:13:25 PM PDT 24
Finished Aug 05 05:13:51 PM PDT 24
Peak memory 199892 kb
Host smart-cd9325e4-36ea-4ccd-9e8d-dee2a09b800e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973701139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1973701139
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3360039986
Short name T317
Test name
Test status
Simulation time 7457922219 ps
CPU time 3.01 seconds
Started Aug 05 05:13:27 PM PDT 24
Finished Aug 05 05:13:31 PM PDT 24
Peak memory 196716 kb
Host smart-672bc0f3-5b00-47f7-8ff3-0a843de95999
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360039986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3360039986
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.337882079
Short name T1110
Test name
Test status
Simulation time 115731662101 ps
CPU time 202.65 seconds
Started Aug 05 05:13:25 PM PDT 24
Finished Aug 05 05:16:48 PM PDT 24
Peak memory 199940 kb
Host smart-a4829cba-ae07-4052-801c-f9c97236a2f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=337882079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.337882079
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1223693804
Short name T858
Test name
Test status
Simulation time 11423712828 ps
CPU time 13.36 seconds
Started Aug 05 05:13:25 PM PDT 24
Finished Aug 05 05:13:38 PM PDT 24
Peak memory 199644 kb
Host smart-abf6077e-970a-44e8-93f6-3c85182021d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223693804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1223693804
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3398443793
Short name T1128
Test name
Test status
Simulation time 19236542994 ps
CPU time 31.97 seconds
Started Aug 05 05:13:25 PM PDT 24
Finished Aug 05 05:13:57 PM PDT 24
Peak memory 197972 kb
Host smart-69327d69-3f8e-414c-96b1-0d2ba04e361a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398443793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3398443793
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.146895633
Short name T606
Test name
Test status
Simulation time 19783180251 ps
CPU time 585.72 seconds
Started Aug 05 05:13:24 PM PDT 24
Finished Aug 05 05:23:10 PM PDT 24
Peak memory 199924 kb
Host smart-017af08e-acd5-4056-87d9-a23e790ba807
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=146895633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.146895633
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.720451078
Short name T802
Test name
Test status
Simulation time 2115087618 ps
CPU time 10.18 seconds
Started Aug 05 05:13:26 PM PDT 24
Finished Aug 05 05:13:36 PM PDT 24
Peak memory 198064 kb
Host smart-63bc896a-751a-460e-8196-d5c241d7e1be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=720451078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.720451078
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.77249818
Short name T879
Test name
Test status
Simulation time 34767839789 ps
CPU time 56.72 seconds
Started Aug 05 05:13:24 PM PDT 24
Finished Aug 05 05:14:21 PM PDT 24
Peak memory 196120 kb
Host smart-03e7defe-8c46-4e6f-81e0-9b7686a3791b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77249818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.77249818
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_smoke.962847420
Short name T388
Test name
Test status
Simulation time 437589958 ps
CPU time 1.4 seconds
Started Aug 05 05:13:27 PM PDT 24
Finished Aug 05 05:13:28 PM PDT 24
Peak memory 199900 kb
Host smart-d36619aa-4cb5-4a20-a61a-a0847f0bcdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962847420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.962847420
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.2616295135
Short name T973
Test name
Test status
Simulation time 63957024903 ps
CPU time 749.42 seconds
Started Aug 05 05:13:25 PM PDT 24
Finished Aug 05 05:25:54 PM PDT 24
Peak memory 208156 kb
Host smart-78eb132d-64e1-43df-ac17-55a6dbfb5c59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616295135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2616295135
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.2151491919
Short name T999
Test name
Test status
Simulation time 42362711509 ps
CPU time 457.88 seconds
Started Aug 05 05:13:25 PM PDT 24
Finished Aug 05 05:21:03 PM PDT 24
Peak memory 216608 kb
Host smart-126f4e82-6f3f-4e3a-adcf-c7a01eccfdf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151491919 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2151491919
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2100937002
Short name T362
Test name
Test status
Simulation time 1893348797 ps
CPU time 1.91 seconds
Started Aug 05 05:13:23 PM PDT 24
Finished Aug 05 05:13:25 PM PDT 24
Peak memory 198556 kb
Host smart-95f1a27a-b36a-4e27-b8aa-f72ca32259ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100937002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2100937002
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1694461493
Short name T996
Test name
Test status
Simulation time 48284542718 ps
CPU time 20.55 seconds
Started Aug 05 05:13:28 PM PDT 24
Finished Aug 05 05:13:48 PM PDT 24
Peak memory 199992 kb
Host smart-dfdc0c33-eabd-41a2-8ac0-24d7118ff244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694461493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1694461493
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1903887487
Short name T339
Test name
Test status
Simulation time 44823145 ps
CPU time 0.52 seconds
Started Aug 05 05:14:52 PM PDT 24
Finished Aug 05 05:14:53 PM PDT 24
Peak memory 195288 kb
Host smart-2ccab1e4-068e-46e1-b3ea-0c2076ec30e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903887487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1903887487
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2129198099
Short name T178
Test name
Test status
Simulation time 152947348143 ps
CPU time 48.97 seconds
Started Aug 05 05:14:49 PM PDT 24
Finished Aug 05 05:15:38 PM PDT 24
Peak memory 199840 kb
Host smart-e2c88097-7739-4168-953b-deb2bdc111f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129198099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2129198099
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1014557619
Short name T843
Test name
Test status
Simulation time 51759678951 ps
CPU time 42.14 seconds
Started Aug 05 05:14:45 PM PDT 24
Finished Aug 05 05:15:27 PM PDT 24
Peak memory 199988 kb
Host smart-3bcb5774-8880-4ead-94d9-0889a0b09c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014557619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1014557619
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1362153993
Short name T306
Test name
Test status
Simulation time 29188271359 ps
CPU time 24.28 seconds
Started Aug 05 05:14:47 PM PDT 24
Finished Aug 05 05:15:11 PM PDT 24
Peak memory 199868 kb
Host smart-394aae73-7ea1-4fca-a183-d3212876d16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362153993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1362153993
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.785965609
Short name T324
Test name
Test status
Simulation time 23747858778 ps
CPU time 20.13 seconds
Started Aug 05 05:14:49 PM PDT 24
Finished Aug 05 05:15:09 PM PDT 24
Peak memory 198892 kb
Host smart-2a12698d-fa33-44cd-9d8b-52605ef01262
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785965609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.785965609
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1376237089
Short name T976
Test name
Test status
Simulation time 106147554223 ps
CPU time 854.17 seconds
Started Aug 05 05:14:50 PM PDT 24
Finished Aug 05 05:29:04 PM PDT 24
Peak memory 199900 kb
Host smart-e86aa954-eea9-4130-9d2b-699919c836fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1376237089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1376237089
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1714381011
Short name T335
Test name
Test status
Simulation time 7985330803 ps
CPU time 20.8 seconds
Started Aug 05 05:14:49 PM PDT 24
Finished Aug 05 05:15:10 PM PDT 24
Peak memory 199504 kb
Host smart-3e5eabd5-b3a5-4657-8fe4-9643389da7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714381011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1714381011
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2980144700
Short name T827
Test name
Test status
Simulation time 20080523572 ps
CPU time 34.89 seconds
Started Aug 05 05:14:46 PM PDT 24
Finished Aug 05 05:15:21 PM PDT 24
Peak memory 199004 kb
Host smart-dd2a777f-b688-4449-a5e4-0a7905e66e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980144700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2980144700
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3158559181
Short name T311
Test name
Test status
Simulation time 20245326680 ps
CPU time 268.23 seconds
Started Aug 05 05:14:47 PM PDT 24
Finished Aug 05 05:19:16 PM PDT 24
Peak memory 199912 kb
Host smart-e96ab291-498e-4d58-b01f-74ae9842132d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3158559181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3158559181
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3995446761
Short name T399
Test name
Test status
Simulation time 1503506492 ps
CPU time 1.99 seconds
Started Aug 05 05:14:47 PM PDT 24
Finished Aug 05 05:14:49 PM PDT 24
Peak memory 198096 kb
Host smart-f2734d61-5537-4587-9d2c-9098cdeac667
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3995446761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3995446761
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1398070375
Short name T452
Test name
Test status
Simulation time 57388245159 ps
CPU time 85.08 seconds
Started Aug 05 05:14:50 PM PDT 24
Finished Aug 05 05:16:15 PM PDT 24
Peak memory 199728 kb
Host smart-d272644d-2f31-4ce1-9c89-cb168adfc1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398070375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1398070375
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2151955135
Short name T837
Test name
Test status
Simulation time 38737428142 ps
CPU time 48.1 seconds
Started Aug 05 05:14:45 PM PDT 24
Finished Aug 05 05:15:33 PM PDT 24
Peak memory 195772 kb
Host smart-f89e5959-8a76-4daf-99ca-d216ba011d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151955135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2151955135
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.595026003
Short name T404
Test name
Test status
Simulation time 987309277 ps
CPU time 2.62 seconds
Started Aug 05 05:14:50 PM PDT 24
Finished Aug 05 05:14:52 PM PDT 24
Peak memory 198196 kb
Host smart-4cd7b204-dc25-4e96-bf60-016fe4370b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595026003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.595026003
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.3447243350
Short name T420
Test name
Test status
Simulation time 248591978570 ps
CPU time 1105.74 seconds
Started Aug 05 05:14:46 PM PDT 24
Finished Aug 05 05:33:11 PM PDT 24
Peak memory 216176 kb
Host smart-0c5ce787-187b-446b-a106-b99ac540c841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447243350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3447243350
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1844789288
Short name T1164
Test name
Test status
Simulation time 60694892430 ps
CPU time 267.47 seconds
Started Aug 05 05:14:50 PM PDT 24
Finished Aug 05 05:19:17 PM PDT 24
Peak memory 216488 kb
Host smart-f808a279-c079-43a6-bf38-7420afd47e45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844789288 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1844789288
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.838309442
Short name T1172
Test name
Test status
Simulation time 1484705019 ps
CPU time 1.97 seconds
Started Aug 05 05:14:49 PM PDT 24
Finished Aug 05 05:14:51 PM PDT 24
Peak memory 198804 kb
Host smart-22a75af8-5a24-4975-a575-5324ae77f3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838309442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.838309442
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.4134255956
Short name T549
Test name
Test status
Simulation time 46468011086 ps
CPU time 14.57 seconds
Started Aug 05 05:14:45 PM PDT 24
Finished Aug 05 05:15:00 PM PDT 24
Peak memory 199344 kb
Host smart-8c96bedf-cf72-45fa-80e0-de71c4622170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134255956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.4134255956
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1056046523
Short name T494
Test name
Test status
Simulation time 44836932974 ps
CPU time 60.13 seconds
Started Aug 05 05:20:37 PM PDT 24
Finished Aug 05 05:21:38 PM PDT 24
Peak memory 199928 kb
Host smart-c32498b4-9de5-4ab4-af77-cd2a334d6d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056046523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1056046523
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1736724083
Short name T691
Test name
Test status
Simulation time 52782397257 ps
CPU time 341.44 seconds
Started Aug 05 05:20:31 PM PDT 24
Finished Aug 05 05:26:12 PM PDT 24
Peak memory 199968 kb
Host smart-6de90810-47bc-4f99-9af6-3316c747c44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736724083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1736724083
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1066883924
Short name T35
Test name
Test status
Simulation time 73178854685 ps
CPU time 201.42 seconds
Started Aug 05 05:20:33 PM PDT 24
Finished Aug 05 05:23:55 PM PDT 24
Peak memory 199940 kb
Host smart-6b984253-4be0-4c85-9fa3-599f144a6e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066883924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1066883924
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2452648758
Short name T48
Test name
Test status
Simulation time 34536127637 ps
CPU time 57.37 seconds
Started Aug 05 05:20:30 PM PDT 24
Finished Aug 05 05:21:28 PM PDT 24
Peak memory 199920 kb
Host smart-5a7bcd23-6df1-4e69-bf2c-27fe6201e16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452648758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2452648758
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3782257412
Short name T881
Test name
Test status
Simulation time 15031362707 ps
CPU time 24.29 seconds
Started Aug 05 05:20:37 PM PDT 24
Finished Aug 05 05:21:01 PM PDT 24
Peak memory 199688 kb
Host smart-6eb95c7e-b1fe-4d34-8f6f-b43423bb77cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782257412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3782257412
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.756178446
Short name T875
Test name
Test status
Simulation time 26574614334 ps
CPU time 35.06 seconds
Started Aug 05 05:20:35 PM PDT 24
Finished Aug 05 05:21:11 PM PDT 24
Peak memory 199452 kb
Host smart-84ffd9e6-a3d7-4ae0-a91d-d8b16de00551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756178446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.756178446
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.4205836843
Short name T601
Test name
Test status
Simulation time 16496615337 ps
CPU time 29.95 seconds
Started Aug 05 05:20:38 PM PDT 24
Finished Aug 05 05:21:08 PM PDT 24
Peak memory 199976 kb
Host smart-6ada9fc7-05f5-49f2-a4b7-b554a0331472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205836843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.4205836843
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1187135410
Short name T332
Test name
Test status
Simulation time 243213921124 ps
CPU time 126.28 seconds
Started Aug 05 05:20:40 PM PDT 24
Finished Aug 05 05:22:47 PM PDT 24
Peak memory 199844 kb
Host smart-b275d096-ee3b-4cf5-9ea2-1790957307a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187135410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1187135410
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2340721117
Short name T361
Test name
Test status
Simulation time 36444810 ps
CPU time 0.56 seconds
Started Aug 05 05:14:59 PM PDT 24
Finished Aug 05 05:14:59 PM PDT 24
Peak memory 195352 kb
Host smart-1265af67-c76a-4295-b6a1-83872c5838a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340721117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2340721117
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2441872911
Short name T805
Test name
Test status
Simulation time 269726159370 ps
CPU time 231.63 seconds
Started Aug 05 05:14:54 PM PDT 24
Finished Aug 05 05:18:45 PM PDT 24
Peak memory 199964 kb
Host smart-5e480ce7-13f8-4f92-a80f-87f441d3098d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441872911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2441872911
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2904358639
Short name T515
Test name
Test status
Simulation time 68753813397 ps
CPU time 30.35 seconds
Started Aug 05 05:14:51 PM PDT 24
Finished Aug 05 05:15:22 PM PDT 24
Peak memory 199956 kb
Host smart-6dc7778b-c159-487c-ac86-1f5e7a727520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904358639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2904358639
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_intr.2346333524
Short name T917
Test name
Test status
Simulation time 39132222250 ps
CPU time 66.2 seconds
Started Aug 05 05:14:51 PM PDT 24
Finished Aug 05 05:15:58 PM PDT 24
Peak memory 199300 kb
Host smart-8eb831fc-a69f-48d2-a64b-58aecac27702
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346333524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2346333524
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3526584398
Short name T8
Test name
Test status
Simulation time 102419252226 ps
CPU time 335.27 seconds
Started Aug 05 05:14:52 PM PDT 24
Finished Aug 05 05:20:27 PM PDT 24
Peak memory 199972 kb
Host smart-50b40f6a-3234-40f7-a73b-04e27c78ac4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3526584398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3526584398
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1723219112
Short name T349
Test name
Test status
Simulation time 3477763135 ps
CPU time 8.95 seconds
Started Aug 05 05:14:52 PM PDT 24
Finished Aug 05 05:15:01 PM PDT 24
Peak memory 199080 kb
Host smart-a1ccd196-ca80-4033-9fa2-35ccaf535971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723219112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1723219112
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.2945907926
Short name T1057
Test name
Test status
Simulation time 61823335455 ps
CPU time 24.48 seconds
Started Aug 05 05:14:50 PM PDT 24
Finished Aug 05 05:15:15 PM PDT 24
Peak memory 200104 kb
Host smart-cddcf3e5-4021-476d-9838-502d3aa0f6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945907926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2945907926
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.89895837
Short name T751
Test name
Test status
Simulation time 6160091451 ps
CPU time 170.11 seconds
Started Aug 05 05:14:52 PM PDT 24
Finished Aug 05 05:17:42 PM PDT 24
Peak memory 199896 kb
Host smart-8ba1362f-5639-436d-81d2-b04f64bcc6e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89895837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.89895837
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.434766006
Short name T968
Test name
Test status
Simulation time 6561835689 ps
CPU time 17.6 seconds
Started Aug 05 05:14:51 PM PDT 24
Finished Aug 05 05:15:09 PM PDT 24
Peak memory 199192 kb
Host smart-eb935cae-b49e-45b6-88f5-f4e39dfa43ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=434766006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.434766006
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3147698962
Short name T761
Test name
Test status
Simulation time 25722512628 ps
CPU time 39.79 seconds
Started Aug 05 05:14:54 PM PDT 24
Finished Aug 05 05:15:34 PM PDT 24
Peak memory 199884 kb
Host smart-2698618c-fc4e-4ab8-95b1-e0230a96c5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147698962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3147698962
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2390062905
Short name T530
Test name
Test status
Simulation time 765340703 ps
CPU time 0.97 seconds
Started Aug 05 05:14:52 PM PDT 24
Finished Aug 05 05:14:53 PM PDT 24
Peak memory 195524 kb
Host smart-d110c076-1c11-4ae3-a402-b4b4b56c5e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390062905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2390062905
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3366165725
Short name T386
Test name
Test status
Simulation time 686460241 ps
CPU time 1.52 seconds
Started Aug 05 05:14:53 PM PDT 24
Finished Aug 05 05:14:54 PM PDT 24
Peak memory 198192 kb
Host smart-a0407012-6c89-4c51-9044-08b0907d3a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366165725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3366165725
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.3650635362
Short name T1147
Test name
Test status
Simulation time 251922939555 ps
CPU time 297.21 seconds
Started Aug 05 05:14:57 PM PDT 24
Finished Aug 05 05:19:54 PM PDT 24
Peak memory 216440 kb
Host smart-a6d233a7-3d61-426b-b404-d4e76a7bc188
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650635362 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3650635362
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2760734498
Short name T289
Test name
Test status
Simulation time 1569464355 ps
CPU time 2.01 seconds
Started Aug 05 05:14:56 PM PDT 24
Finished Aug 05 05:14:58 PM PDT 24
Peak memory 199048 kb
Host smart-c2b125b2-fb61-48e2-954c-abfd2ee8d254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760734498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2760734498
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1574474317
Short name T1086
Test name
Test status
Simulation time 78182829119 ps
CPU time 13.16 seconds
Started Aug 05 05:14:53 PM PDT 24
Finished Aug 05 05:15:06 PM PDT 24
Peak memory 199904 kb
Host smart-3265cf49-2697-49cb-a16a-80dbc648372c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574474317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1574474317
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3904347495
Short name T1077
Test name
Test status
Simulation time 171576760439 ps
CPU time 98.25 seconds
Started Aug 05 05:20:38 PM PDT 24
Finished Aug 05 05:22:17 PM PDT 24
Peak memory 199916 kb
Host smart-6a74b82b-3fda-4419-a68f-567ca595bda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904347495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3904347495
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.4232981158
Short name T835
Test name
Test status
Simulation time 95336168328 ps
CPU time 129.81 seconds
Started Aug 05 05:20:37 PM PDT 24
Finished Aug 05 05:22:47 PM PDT 24
Peak memory 199956 kb
Host smart-651413be-3f60-4fe2-bcfd-30a05364bdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232981158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.4232981158
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.1751517269
Short name T189
Test name
Test status
Simulation time 88396857325 ps
CPU time 11.38 seconds
Started Aug 05 05:20:39 PM PDT 24
Finished Aug 05 05:20:50 PM PDT 24
Peak memory 199400 kb
Host smart-c17386eb-b33b-4026-bc89-b2b664f9f64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751517269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1751517269
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2315085337
Short name T902
Test name
Test status
Simulation time 179711550450 ps
CPU time 97.02 seconds
Started Aug 05 05:20:37 PM PDT 24
Finished Aug 05 05:22:14 PM PDT 24
Peak memory 199996 kb
Host smart-791aae92-c68e-4cd8-9f66-3146a73bde8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315085337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2315085337
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3997065944
Short name T334
Test name
Test status
Simulation time 79982532568 ps
CPU time 49.15 seconds
Started Aug 05 05:20:37 PM PDT 24
Finished Aug 05 05:21:26 PM PDT 24
Peak memory 199892 kb
Host smart-e8883bbc-24ee-422a-8a42-020d6f39d818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997065944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3997065944
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3450225052
Short name T489
Test name
Test status
Simulation time 16989694721 ps
CPU time 24.96 seconds
Started Aug 05 05:20:44 PM PDT 24
Finished Aug 05 05:21:09 PM PDT 24
Peak memory 199972 kb
Host smart-26389e29-f2ef-49da-83dd-24a3185c48c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450225052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3450225052
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2203514948
Short name T809
Test name
Test status
Simulation time 26277223633 ps
CPU time 23.64 seconds
Started Aug 05 05:20:43 PM PDT 24
Finished Aug 05 05:21:07 PM PDT 24
Peak memory 199848 kb
Host smart-4c49c455-46fb-475b-9b37-57d7a5fb7bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203514948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2203514948
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.3670299739
Short name T611
Test name
Test status
Simulation time 19453899765 ps
CPU time 10.34 seconds
Started Aug 05 05:20:43 PM PDT 24
Finished Aug 05 05:20:53 PM PDT 24
Peak memory 199848 kb
Host smart-7d8d616d-33ef-4965-966e-f7bd28d6b8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670299739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3670299739
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2121987001
Short name T1126
Test name
Test status
Simulation time 120868945986 ps
CPU time 166.63 seconds
Started Aug 05 05:20:43 PM PDT 24
Finished Aug 05 05:23:30 PM PDT 24
Peak memory 199860 kb
Host smart-e47228ef-14f3-4706-8c5c-634224bd6949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121987001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2121987001
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.966579604
Short name T733
Test name
Test status
Simulation time 159507524878 ps
CPU time 22.03 seconds
Started Aug 05 05:20:43 PM PDT 24
Finished Aug 05 05:21:06 PM PDT 24
Peak memory 199812 kb
Host smart-cc35d34b-1739-4b25-b7b8-25d7d001bb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966579604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.966579604
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.912157840
Short name T832
Test name
Test status
Simulation time 41546037 ps
CPU time 0.57 seconds
Started Aug 05 05:15:04 PM PDT 24
Finished Aug 05 05:15:04 PM PDT 24
Peak memory 194804 kb
Host smart-bfc537ae-c299-45ff-a999-aafc6b6ab6a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912157840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.912157840
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3974594220
Short name T929
Test name
Test status
Simulation time 111418209644 ps
CPU time 50.59 seconds
Started Aug 05 05:14:59 PM PDT 24
Finished Aug 05 05:15:49 PM PDT 24
Peak memory 199944 kb
Host smart-7c77e055-8132-4d13-a196-d47444f6b30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974594220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3974594220
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3388349488
Short name T1129
Test name
Test status
Simulation time 28321267892 ps
CPU time 52.38 seconds
Started Aug 05 05:14:56 PM PDT 24
Finished Aug 05 05:15:48 PM PDT 24
Peak memory 199976 kb
Host smart-0994069b-a5c6-4ffd-ae52-d25d204467b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388349488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3388349488
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3631760696
Short name T859
Test name
Test status
Simulation time 17217720974 ps
CPU time 6.95 seconds
Started Aug 05 05:15:08 PM PDT 24
Finished Aug 05 05:15:15 PM PDT 24
Peak memory 196908 kb
Host smart-32cb8c7d-97af-4969-908f-dba2d66d48b0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631760696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3631760696
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2073105145
Short name T746
Test name
Test status
Simulation time 100320920147 ps
CPU time 848.84 seconds
Started Aug 05 05:15:08 PM PDT 24
Finished Aug 05 05:29:17 PM PDT 24
Peak memory 199992 kb
Host smart-437c5606-c4da-4534-8727-e7dc79abc4e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2073105145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2073105145
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.494048734
Short name T1181
Test name
Test status
Simulation time 9677599990 ps
CPU time 4.29 seconds
Started Aug 05 05:14:57 PM PDT 24
Finished Aug 05 05:15:02 PM PDT 24
Peak memory 199868 kb
Host smart-dffefa99-6f93-4d5e-9882-1049d2c414b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494048734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.494048734
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.898573012
Short name T1138
Test name
Test status
Simulation time 42901509805 ps
CPU time 33.43 seconds
Started Aug 05 05:14:58 PM PDT 24
Finished Aug 05 05:15:32 PM PDT 24
Peak memory 200264 kb
Host smart-3f5bd051-7322-419e-bf6f-82c862f73277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898573012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.898573012
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.364002724
Short name T285
Test name
Test status
Simulation time 11665076416 ps
CPU time 473.74 seconds
Started Aug 05 05:14:57 PM PDT 24
Finished Aug 05 05:22:51 PM PDT 24
Peak memory 199840 kb
Host smart-f1943caf-487d-4160-8123-eb0655a815f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=364002724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.364002724
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2235567696
Short name T589
Test name
Test status
Simulation time 1902230506 ps
CPU time 3.78 seconds
Started Aug 05 05:15:01 PM PDT 24
Finished Aug 05 05:15:05 PM PDT 24
Peak memory 198572 kb
Host smart-abe05e5b-cc67-4ddb-874b-979b47238c65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2235567696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2235567696
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.138474171
Short name T407
Test name
Test status
Simulation time 51480692970 ps
CPU time 20.66 seconds
Started Aug 05 05:14:58 PM PDT 24
Finished Aug 05 05:15:19 PM PDT 24
Peak memory 199960 kb
Host smart-501892c4-b8b7-40cf-a387-f761ecc14a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138474171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.138474171
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2022603589
Short name T1071
Test name
Test status
Simulation time 592971435 ps
CPU time 1.69 seconds
Started Aug 05 05:14:57 PM PDT 24
Finished Aug 05 05:14:59 PM PDT 24
Peak memory 195504 kb
Host smart-91f6fa07-ed2a-4c81-839c-85053e256df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022603589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2022603589
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2186730569
Short name T1068
Test name
Test status
Simulation time 727456323 ps
CPU time 1.57 seconds
Started Aug 05 05:15:08 PM PDT 24
Finished Aug 05 05:15:09 PM PDT 24
Peak memory 199640 kb
Host smart-db24dbf7-7868-4710-9aa1-7ddf5de6595d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186730569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2186730569
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2146036685
Short name T318
Test name
Test status
Simulation time 53776258613 ps
CPU time 135.27 seconds
Started Aug 05 05:15:00 PM PDT 24
Finished Aug 05 05:17:16 PM PDT 24
Peak memory 208224 kb
Host smart-69254e93-66db-4ea3-94af-a3c544f2b211
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146036685 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2146036685
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.468392981
Short name T110
Test name
Test status
Simulation time 1230849069 ps
CPU time 1.4 seconds
Started Aug 05 05:15:08 PM PDT 24
Finished Aug 05 05:15:09 PM PDT 24
Peak memory 199268 kb
Host smart-57e9627f-78c8-415c-a48d-c20eab270053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468392981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.468392981
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2026072984
Short name T804
Test name
Test status
Simulation time 174034431757 ps
CPU time 39.59 seconds
Started Aug 05 05:15:08 PM PDT 24
Finished Aug 05 05:15:47 PM PDT 24
Peak memory 200000 kb
Host smart-4fefef4b-2ac1-4cf4-8e9c-0d3a6400d857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026072984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2026072984
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1645729691
Short name T270
Test name
Test status
Simulation time 25580985844 ps
CPU time 67.41 seconds
Started Aug 05 05:20:42 PM PDT 24
Finished Aug 05 05:21:49 PM PDT 24
Peak memory 199876 kb
Host smart-464c426f-27b5-4e32-93b8-26380b7c469a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645729691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1645729691
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2745040816
Short name T777
Test name
Test status
Simulation time 27660578166 ps
CPU time 24.22 seconds
Started Aug 05 05:20:43 PM PDT 24
Finished Aug 05 05:21:08 PM PDT 24
Peak memory 199820 kb
Host smart-fc604067-9bd7-4c10-acb4-11b5f6d671e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745040816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2745040816
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2476322043
Short name T639
Test name
Test status
Simulation time 76451394277 ps
CPU time 257.75 seconds
Started Aug 05 05:20:42 PM PDT 24
Finished Aug 05 05:25:00 PM PDT 24
Peak memory 199844 kb
Host smart-58fc0d8b-1c6d-461f-97aa-c5ed90391b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476322043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2476322043
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2905380041
Short name T185
Test name
Test status
Simulation time 21451056548 ps
CPU time 30.51 seconds
Started Aug 05 05:20:47 PM PDT 24
Finished Aug 05 05:21:18 PM PDT 24
Peak memory 199844 kb
Host smart-65e843f9-026e-4413-95cf-e1e202579a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905380041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2905380041
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3757645446
Short name T1065
Test name
Test status
Simulation time 22773254513 ps
CPU time 14.27 seconds
Started Aug 05 05:20:48 PM PDT 24
Finished Aug 05 05:21:02 PM PDT 24
Peak memory 199956 kb
Host smart-a7688a9c-a7a0-4fb3-9585-15430e1ff0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757645446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3757645446
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1845713060
Short name T154
Test name
Test status
Simulation time 39145516750 ps
CPU time 32.2 seconds
Started Aug 05 05:20:48 PM PDT 24
Finished Aug 05 05:21:20 PM PDT 24
Peak memory 199956 kb
Host smart-ec7a60d9-cd10-4c47-9bbb-06fbf7ac85cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845713060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1845713060
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2223490031
Short name T1060
Test name
Test status
Simulation time 8969332097 ps
CPU time 19.33 seconds
Started Aug 05 05:20:48 PM PDT 24
Finished Aug 05 05:21:07 PM PDT 24
Peak memory 199908 kb
Host smart-2e0ae413-ebc4-4d0d-af26-c3ebbfb7fc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223490031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2223490031
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3140258330
Short name T689
Test name
Test status
Simulation time 71345366360 ps
CPU time 73.4 seconds
Started Aug 05 05:20:48 PM PDT 24
Finished Aug 05 05:22:01 PM PDT 24
Peak memory 199912 kb
Host smart-cb46e68d-7006-45c6-b5a4-f9e99e8898c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140258330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3140258330
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.870497819
Short name T78
Test name
Test status
Simulation time 26715144204 ps
CPU time 17.64 seconds
Started Aug 05 05:20:47 PM PDT 24
Finished Aug 05 05:21:05 PM PDT 24
Peak memory 199836 kb
Host smart-767b23c2-432b-4e78-a58f-83d0a91f5ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870497819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.870497819
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1188773745
Short name T895
Test name
Test status
Simulation time 152088931441 ps
CPU time 193.09 seconds
Started Aug 05 05:20:58 PM PDT 24
Finished Aug 05 05:24:11 PM PDT 24
Peak memory 199940 kb
Host smart-202887ac-33a2-4c9b-b862-54da043fb7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188773745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1188773745
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3858968786
Short name T21
Test name
Test status
Simulation time 41539565 ps
CPU time 0.57 seconds
Started Aug 05 05:15:06 PM PDT 24
Finished Aug 05 05:15:07 PM PDT 24
Peak memory 195292 kb
Host smart-c6d9ada8-0815-406d-8ec9-c8240e6af784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858968786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3858968786
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2156903860
Short name T608
Test name
Test status
Simulation time 160255367946 ps
CPU time 430.21 seconds
Started Aug 05 05:15:03 PM PDT 24
Finished Aug 05 05:22:13 PM PDT 24
Peak memory 199948 kb
Host smart-1a7e31e8-7cb9-4cd2-ad6a-8539badd69e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156903860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2156903860
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3663934366
Short name T791
Test name
Test status
Simulation time 123534121598 ps
CPU time 32.6 seconds
Started Aug 05 05:15:07 PM PDT 24
Finished Aug 05 05:15:40 PM PDT 24
Peak memory 199944 kb
Host smart-7364986d-afc0-484d-a69a-7ee074dcbd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663934366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3663934366
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.4246892119
Short name T522
Test name
Test status
Simulation time 165232007771 ps
CPU time 82.9 seconds
Started Aug 05 05:15:06 PM PDT 24
Finished Aug 05 05:16:29 PM PDT 24
Peak memory 199972 kb
Host smart-23e5ed63-7cf9-4600-91a6-f6b1bbdaf321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246892119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.4246892119
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.3470109707
Short name T427
Test name
Test status
Simulation time 38569086994 ps
CPU time 23.23 seconds
Started Aug 05 05:15:04 PM PDT 24
Finished Aug 05 05:15:28 PM PDT 24
Peak memory 199284 kb
Host smart-a1086773-b487-451f-bbab-8b3383f77c54
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470109707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3470109707
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.4019018759
Short name T520
Test name
Test status
Simulation time 62298321106 ps
CPU time 530.27 seconds
Started Aug 05 05:15:07 PM PDT 24
Finished Aug 05 05:23:58 PM PDT 24
Peak memory 199872 kb
Host smart-3eda3fb0-145d-4294-8cc1-60ae5a0b70a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4019018759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.4019018759
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1295481237
Short name T721
Test name
Test status
Simulation time 9862939264 ps
CPU time 3.54 seconds
Started Aug 05 05:15:07 PM PDT 24
Finished Aug 05 05:15:11 PM PDT 24
Peak memory 199420 kb
Host smart-fefd356d-118b-4d66-a3da-44d453cf2e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295481237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1295481237
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.248135956
Short name T612
Test name
Test status
Simulation time 57805422228 ps
CPU time 50.33 seconds
Started Aug 05 05:15:07 PM PDT 24
Finished Aug 05 05:15:57 PM PDT 24
Peak memory 198696 kb
Host smart-8ab86d60-6bce-4200-9c44-998be0e3a038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248135956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.248135956
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.2941100501
Short name T479
Test name
Test status
Simulation time 7282622850 ps
CPU time 294.23 seconds
Started Aug 05 05:15:05 PM PDT 24
Finished Aug 05 05:20:00 PM PDT 24
Peak memory 199948 kb
Host smart-a1584a22-03f4-406a-85cb-9747b589a6f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2941100501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2941100501
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2523465839
Short name T760
Test name
Test status
Simulation time 3970056495 ps
CPU time 29.49 seconds
Started Aug 05 05:15:05 PM PDT 24
Finished Aug 05 05:15:34 PM PDT 24
Peak memory 198756 kb
Host smart-a1a23dec-df90-4d17-b589-16a4b20d1e74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2523465839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2523465839
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3868055291
Short name T994
Test name
Test status
Simulation time 23376236038 ps
CPU time 39.86 seconds
Started Aug 05 05:15:06 PM PDT 24
Finished Aug 05 05:15:46 PM PDT 24
Peak memory 199892 kb
Host smart-679668b9-5e74-4529-b40e-6b223487647a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868055291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3868055291
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2896443042
Short name T711
Test name
Test status
Simulation time 5709112842 ps
CPU time 1.56 seconds
Started Aug 05 05:15:03 PM PDT 24
Finished Aug 05 05:15:05 PM PDT 24
Peak memory 196220 kb
Host smart-533b5ba1-1054-47fc-a78d-c21b039ae5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896443042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2896443042
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.3782311846
Short name T753
Test name
Test status
Simulation time 270648181 ps
CPU time 1.53 seconds
Started Aug 05 05:15:03 PM PDT 24
Finished Aug 05 05:15:04 PM PDT 24
Peak memory 198184 kb
Host smart-59c8cae2-5969-4aa4-bafe-4084fa8d0879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782311846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3782311846
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3663599899
Short name T28
Test name
Test status
Simulation time 50140494011 ps
CPU time 304.08 seconds
Started Aug 05 05:15:04 PM PDT 24
Finished Aug 05 05:20:08 PM PDT 24
Peak memory 215612 kb
Host smart-091ac7bc-ae16-409d-8f20-9805b97a141a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663599899 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3663599899
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2754452328
Short name T416
Test name
Test status
Simulation time 1049834617 ps
CPU time 2.94 seconds
Started Aug 05 05:15:03 PM PDT 24
Finished Aug 05 05:15:06 PM PDT 24
Peak memory 198948 kb
Host smart-5ea0d48f-234a-41b8-8afa-2e6f76c3e1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754452328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2754452328
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3797577268
Short name T851
Test name
Test status
Simulation time 45191976886 ps
CPU time 17.21 seconds
Started Aug 05 05:15:06 PM PDT 24
Finished Aug 05 05:15:23 PM PDT 24
Peak memory 199968 kb
Host smart-f10dcc18-813c-49cf-ab40-6acff33ce4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797577268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3797577268
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.3396755212
Short name T1091
Test name
Test status
Simulation time 51173823801 ps
CPU time 42.98 seconds
Started Aug 05 05:20:52 PM PDT 24
Finished Aug 05 05:21:36 PM PDT 24
Peak memory 199900 kb
Host smart-0c491a65-9004-41f8-a357-de2f556e9abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396755212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3396755212
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.2162271004
Short name T163
Test name
Test status
Simulation time 215929991046 ps
CPU time 176.73 seconds
Started Aug 05 05:20:54 PM PDT 24
Finished Aug 05 05:23:51 PM PDT 24
Peak memory 199976 kb
Host smart-b612c22f-ba4e-4a15-93f5-0c924784f0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162271004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2162271004
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.4220497077
Short name T672
Test name
Test status
Simulation time 114083854286 ps
CPU time 53.62 seconds
Started Aug 05 05:20:54 PM PDT 24
Finished Aug 05 05:21:47 PM PDT 24
Peak memory 199848 kb
Host smart-ec067d62-87e3-46d9-998f-e3d418933994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220497077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.4220497077
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3056707386
Short name T428
Test name
Test status
Simulation time 95385312553 ps
CPU time 30.9 seconds
Started Aug 05 05:20:54 PM PDT 24
Finished Aug 05 05:21:25 PM PDT 24
Peak memory 199940 kb
Host smart-f3436907-d590-4291-974d-ccf4d042795f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056707386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3056707386
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.1509116072
Short name T207
Test name
Test status
Simulation time 28011574554 ps
CPU time 25.22 seconds
Started Aug 05 05:20:54 PM PDT 24
Finished Aug 05 05:21:19 PM PDT 24
Peak memory 199844 kb
Host smart-5feef3d5-0caf-4864-8e46-b6bd55f3aacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509116072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1509116072
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3635373800
Short name T852
Test name
Test status
Simulation time 41828089090 ps
CPU time 77.92 seconds
Started Aug 05 05:20:52 PM PDT 24
Finished Aug 05 05:22:10 PM PDT 24
Peak memory 199876 kb
Host smart-933cb83b-5f8f-48ba-8d95-d22c06607b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635373800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3635373800
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.634439723
Short name T156
Test name
Test status
Simulation time 341990923117 ps
CPU time 152.35 seconds
Started Aug 05 05:20:59 PM PDT 24
Finished Aug 05 05:23:32 PM PDT 24
Peak memory 199836 kb
Host smart-cd1986b6-916b-4035-8bdf-729c0d1f84cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634439723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.634439723
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3918578892
Short name T970
Test name
Test status
Simulation time 143381478942 ps
CPU time 215.11 seconds
Started Aug 05 05:20:59 PM PDT 24
Finished Aug 05 05:24:35 PM PDT 24
Peak memory 199900 kb
Host smart-d2f0f3f8-f7c8-4038-8c34-add94846d8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918578892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3918578892
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2285447574
Short name T233
Test name
Test status
Simulation time 54574265469 ps
CPU time 30.12 seconds
Started Aug 05 05:21:02 PM PDT 24
Finished Aug 05 05:21:32 PM PDT 24
Peak memory 199908 kb
Host smart-d80f68fc-9ce8-49e6-abcc-e435bee82eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285447574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2285447574
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2780941583
Short name T140
Test name
Test status
Simulation time 19612889061 ps
CPU time 8.28 seconds
Started Aug 05 05:21:03 PM PDT 24
Finished Aug 05 05:21:12 PM PDT 24
Peak memory 199908 kb
Host smart-e9fde4e5-8d3d-44ff-aa66-d45563de74ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780941583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2780941583
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.2388801172
Short name T363
Test name
Test status
Simulation time 17711205 ps
CPU time 0.56 seconds
Started Aug 05 05:15:08 PM PDT 24
Finished Aug 05 05:15:09 PM PDT 24
Peak memory 195360 kb
Host smart-be00d731-3b0c-462c-aca2-34ea5867d61c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388801172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2388801172
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2252371452
Short name T266
Test name
Test status
Simulation time 140041112717 ps
CPU time 60.09 seconds
Started Aug 05 05:15:06 PM PDT 24
Finished Aug 05 05:16:06 PM PDT 24
Peak memory 199904 kb
Host smart-3e62b67e-c1fb-4f76-8a45-35146b742190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252371452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2252371452
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1111776536
Short name T865
Test name
Test status
Simulation time 145957967190 ps
CPU time 63.45 seconds
Started Aug 05 05:15:07 PM PDT 24
Finished Aug 05 05:16:10 PM PDT 24
Peak memory 199892 kb
Host smart-be0bace9-4d23-4cff-91b0-f2a28cbec9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111776536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1111776536
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2024467638
Short name T198
Test name
Test status
Simulation time 205621255216 ps
CPU time 127.27 seconds
Started Aug 05 05:15:05 PM PDT 24
Finished Aug 05 05:17:13 PM PDT 24
Peak memory 199972 kb
Host smart-43c4dc7e-2468-4305-ac17-296261036355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024467638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2024467638
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3878974315
Short name T559
Test name
Test status
Simulation time 39540735174 ps
CPU time 12.01 seconds
Started Aug 05 05:15:10 PM PDT 24
Finished Aug 05 05:15:22 PM PDT 24
Peak memory 199972 kb
Host smart-22ba6c87-e768-42f0-9986-b7abfae4cef0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878974315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3878974315
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.11602845
Short name T1005
Test name
Test status
Simulation time 212276350313 ps
CPU time 385.65 seconds
Started Aug 05 05:15:09 PM PDT 24
Finished Aug 05 05:21:35 PM PDT 24
Peak memory 199892 kb
Host smart-af1fb909-49c6-4e97-bd1e-f4e40b1b3f20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11602845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.11602845
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1235142591
Short name T850
Test name
Test status
Simulation time 6971833972 ps
CPU time 2.05 seconds
Started Aug 05 05:15:09 PM PDT 24
Finished Aug 05 05:15:11 PM PDT 24
Peak memory 198648 kb
Host smart-fb0a19d5-56b9-478b-811f-a8b869bbd415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235142591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1235142591
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.1306518492
Short name T1123
Test name
Test status
Simulation time 7873894704 ps
CPU time 13.28 seconds
Started Aug 05 05:15:10 PM PDT 24
Finished Aug 05 05:15:24 PM PDT 24
Peak memory 199860 kb
Host smart-e2f211cf-e7ff-46e9-a387-a97b5c12af8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306518492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1306518492
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3788808334
Short name T579
Test name
Test status
Simulation time 26815293739 ps
CPU time 1418.82 seconds
Started Aug 05 05:15:09 PM PDT 24
Finished Aug 05 05:38:48 PM PDT 24
Peak memory 199756 kb
Host smart-1af9511c-c95b-4d40-8f37-0f26f6502a20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3788808334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3788808334
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1477308730
Short name T705
Test name
Test status
Simulation time 5240644378 ps
CPU time 19.75 seconds
Started Aug 05 05:15:11 PM PDT 24
Finished Aug 05 05:15:31 PM PDT 24
Peak memory 198696 kb
Host smart-24e1df38-67b8-4cae-a2da-f932712de447
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1477308730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1477308730
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1420495854
Short name T1029
Test name
Test status
Simulation time 71536747085 ps
CPU time 150.33 seconds
Started Aug 05 05:15:09 PM PDT 24
Finished Aug 05 05:17:40 PM PDT 24
Peak memory 199940 kb
Host smart-8e3cec00-392f-4f41-b0d2-de5f4bdf07fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420495854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1420495854
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1549087020
Short name T1085
Test name
Test status
Simulation time 40751610720 ps
CPU time 17.23 seconds
Started Aug 05 05:15:09 PM PDT 24
Finished Aug 05 05:15:26 PM PDT 24
Peak memory 195884 kb
Host smart-294c960a-ea02-407f-afaa-f1dd8283e3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549087020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1549087020
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3098710928
Short name T822
Test name
Test status
Simulation time 731278135 ps
CPU time 1.76 seconds
Started Aug 05 05:15:08 PM PDT 24
Finished Aug 05 05:15:10 PM PDT 24
Peak memory 198712 kb
Host smart-02e219a4-155f-46ac-9cc5-d3a6b9b9ca1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098710928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3098710928
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2804820060
Short name T29
Test name
Test status
Simulation time 24729692258 ps
CPU time 287.67 seconds
Started Aug 05 05:15:09 PM PDT 24
Finished Aug 05 05:19:56 PM PDT 24
Peak memory 211784 kb
Host smart-bdcbda0c-8e69-48a2-847d-7f0371a79bce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804820060 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2804820060
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.316439445
Short name T15
Test name
Test status
Simulation time 1786629357 ps
CPU time 2.29 seconds
Started Aug 05 05:15:08 PM PDT 24
Finished Aug 05 05:15:10 PM PDT 24
Peak memory 198308 kb
Host smart-fd281c82-356b-429a-8523-b3bbcf6f904d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316439445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.316439445
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1206778677
Short name T291
Test name
Test status
Simulation time 152592496568 ps
CPU time 290.94 seconds
Started Aug 05 05:15:04 PM PDT 24
Finished Aug 05 05:19:55 PM PDT 24
Peak memory 199980 kb
Host smart-51f293d4-783a-4661-9a6e-e9b6eb0fa2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206778677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1206778677
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3188597190
Short name T943
Test name
Test status
Simulation time 193501336317 ps
CPU time 149.41 seconds
Started Aug 05 05:21:01 PM PDT 24
Finished Aug 05 05:23:31 PM PDT 24
Peak memory 199840 kb
Host smart-593982fa-2176-43d0-a4bb-b708b2cd9968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188597190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3188597190
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3783616436
Short name T1006
Test name
Test status
Simulation time 20491254578 ps
CPU time 16.41 seconds
Started Aug 05 05:21:03 PM PDT 24
Finished Aug 05 05:21:19 PM PDT 24
Peak memory 199908 kb
Host smart-5f981939-8bfb-4039-bf3f-0063a5e06540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783616436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3783616436
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1886474237
Short name T900
Test name
Test status
Simulation time 44391616430 ps
CPU time 25.52 seconds
Started Aug 05 05:20:58 PM PDT 24
Finished Aug 05 05:21:24 PM PDT 24
Peak memory 199912 kb
Host smart-227f0620-2f59-48ce-bc19-3caaf065a759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886474237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1886474237
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.1239468667
Short name T225
Test name
Test status
Simulation time 51909526641 ps
CPU time 131.06 seconds
Started Aug 05 05:20:58 PM PDT 24
Finished Aug 05 05:23:10 PM PDT 24
Peak memory 199976 kb
Host smart-4ac09846-f387-4104-bf5f-c9f67297586f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239468667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1239468667
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1734438597
Short name T333
Test name
Test status
Simulation time 90587903143 ps
CPU time 28.65 seconds
Started Aug 05 05:21:30 PM PDT 24
Finished Aug 05 05:21:59 PM PDT 24
Peak memory 199760 kb
Host smart-3ef5d7f5-0682-4408-aa38-5200c729ebc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734438597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1734438597
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3226494693
Short name T786
Test name
Test status
Simulation time 6291705845 ps
CPU time 9.99 seconds
Started Aug 05 05:21:03 PM PDT 24
Finished Aug 05 05:21:13 PM PDT 24
Peak memory 199908 kb
Host smart-0de0b607-5be1-4137-9243-612c4f42f500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226494693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3226494693
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.627403108
Short name T244
Test name
Test status
Simulation time 144017301325 ps
CPU time 292.69 seconds
Started Aug 05 05:21:11 PM PDT 24
Finished Aug 05 05:26:04 PM PDT 24
Peak memory 199848 kb
Host smart-36eaacb1-ec7e-4b27-84a5-5eff8e1c7286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627403108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.627403108
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.20687667
Short name T1171
Test name
Test status
Simulation time 40332978990 ps
CPU time 79.84 seconds
Started Aug 05 05:21:05 PM PDT 24
Finished Aug 05 05:22:25 PM PDT 24
Peak memory 199912 kb
Host smart-7f849024-e879-4e5f-a8fe-2c6236a850a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20687667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.20687667
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.728875281
Short name T195
Test name
Test status
Simulation time 28198699065 ps
CPU time 39.61 seconds
Started Aug 05 05:21:13 PM PDT 24
Finished Aug 05 05:21:53 PM PDT 24
Peak memory 199916 kb
Host smart-6435af3a-93e6-4ac6-9b60-1b22a59eedb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728875281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.728875281
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1031010998
Short name T1041
Test name
Test status
Simulation time 37028292 ps
CPU time 0.6 seconds
Started Aug 05 05:15:25 PM PDT 24
Finished Aug 05 05:15:26 PM PDT 24
Peak memory 195332 kb
Host smart-354a4fd9-a2b0-4a66-9773-6438df743adb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031010998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1031010998
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.291377385
Short name T564
Test name
Test status
Simulation time 27010351571 ps
CPU time 42.33 seconds
Started Aug 05 05:15:14 PM PDT 24
Finished Aug 05 05:15:56 PM PDT 24
Peak memory 199932 kb
Host smart-e43d593e-1197-4697-801d-01045e48f08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291377385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.291377385
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.3096080788
Short name T763
Test name
Test status
Simulation time 24594644217 ps
CPU time 14.86 seconds
Started Aug 05 05:15:15 PM PDT 24
Finished Aug 05 05:15:30 PM PDT 24
Peak memory 199480 kb
Host smart-e9a08776-914f-4074-8531-cf03b0123523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096080788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3096080788
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3399099363
Short name T823
Test name
Test status
Simulation time 83094942188 ps
CPU time 73.38 seconds
Started Aug 05 05:15:15 PM PDT 24
Finished Aug 05 05:16:28 PM PDT 24
Peak memory 199900 kb
Host smart-88f4d008-9161-4c1b-a0eb-4d9c7511996a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399099363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3399099363
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.1645104227
Short name T655
Test name
Test status
Simulation time 27208189808 ps
CPU time 13.34 seconds
Started Aug 05 05:15:16 PM PDT 24
Finished Aug 05 05:15:30 PM PDT 24
Peak memory 199888 kb
Host smart-b26508a1-419b-4999-b85d-08222afa8b3c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645104227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1645104227
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.918069226
Short name T262
Test name
Test status
Simulation time 53592126711 ps
CPU time 307.22 seconds
Started Aug 05 05:15:16 PM PDT 24
Finished Aug 05 05:20:23 PM PDT 24
Peak memory 199900 kb
Host smart-b4806e45-0c4f-40f3-831d-162a2dac6c10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=918069226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.918069226
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.191806569
Short name T666
Test name
Test status
Simulation time 3005562420 ps
CPU time 5.58 seconds
Started Aug 05 05:15:15 PM PDT 24
Finished Aug 05 05:15:21 PM PDT 24
Peak memory 197376 kb
Host smart-04c520a7-baaa-44e9-915f-f4f967b8e8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191806569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.191806569
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.638489292
Short name T585
Test name
Test status
Simulation time 73494614562 ps
CPU time 56.52 seconds
Started Aug 05 05:15:14 PM PDT 24
Finished Aug 05 05:16:11 PM PDT 24
Peak memory 200096 kb
Host smart-3c4753d8-2eb0-43d3-ae7d-3bcc7ad912a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638489292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.638489292
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1181835498
Short name T454
Test name
Test status
Simulation time 5040377317 ps
CPU time 153.44 seconds
Started Aug 05 05:15:16 PM PDT 24
Finished Aug 05 05:17:49 PM PDT 24
Peak memory 199928 kb
Host smart-08f0b5eb-dfa4-4412-b817-d8040f9d2b8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1181835498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1181835498
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3609257088
Short name T1104
Test name
Test status
Simulation time 3051134207 ps
CPU time 5 seconds
Started Aug 05 05:15:41 PM PDT 24
Finished Aug 05 05:15:46 PM PDT 24
Peak memory 198020 kb
Host smart-e608d403-6667-4eee-9df3-bcc5626e5e3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3609257088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3609257088
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3256322528
Short name T965
Test name
Test status
Simulation time 92488237056 ps
CPU time 18.34 seconds
Started Aug 05 05:15:15 PM PDT 24
Finished Aug 05 05:15:33 PM PDT 24
Peak memory 199916 kb
Host smart-d65c0d4d-b361-4256-b3d6-1ce1b1ebfa3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256322528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3256322528
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1444553551
Short name T848
Test name
Test status
Simulation time 4249200282 ps
CPU time 5.85 seconds
Started Aug 05 05:15:16 PM PDT 24
Finished Aug 05 05:15:22 PM PDT 24
Peak memory 196484 kb
Host smart-3d5632b7-ec19-41c7-a106-965d68617df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444553551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1444553551
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1105515230
Short name T1007
Test name
Test status
Simulation time 5722060094 ps
CPU time 11.4 seconds
Started Aug 05 05:15:10 PM PDT 24
Finished Aug 05 05:15:21 PM PDT 24
Peak memory 199848 kb
Host smart-22f0ae9d-62d3-402c-8950-449dadba1330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105515230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1105515230
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2444109160
Short name T653
Test name
Test status
Simulation time 72903563521 ps
CPU time 33.54 seconds
Started Aug 05 05:15:25 PM PDT 24
Finished Aug 05 05:15:59 PM PDT 24
Peak memory 199952 kb
Host smart-df69ddb9-f7a8-4692-b1ff-cd94999b1a8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444109160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2444109160
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1346532714
Short name T607
Test name
Test status
Simulation time 148476078757 ps
CPU time 858.42 seconds
Started Aug 05 05:15:15 PM PDT 24
Finished Aug 05 05:29:33 PM PDT 24
Peak memory 213716 kb
Host smart-1380a6e4-cbda-4dc0-b764-a417a4c17026
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346532714 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1346532714
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.904284791
Short name T526
Test name
Test status
Simulation time 7288937581 ps
CPU time 12.62 seconds
Started Aug 05 05:15:14 PM PDT 24
Finished Aug 05 05:15:27 PM PDT 24
Peak memory 199856 kb
Host smart-a8ed83c5-097e-42e0-88b8-20036152eea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904284791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.904284791
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.4164380294
Short name T953
Test name
Test status
Simulation time 5538710018 ps
CPU time 9.15 seconds
Started Aug 05 05:15:09 PM PDT 24
Finished Aug 05 05:15:18 PM PDT 24
Peak memory 197612 kb
Host smart-c83570a0-058a-45dd-814c-9ee160595f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164380294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.4164380294
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3849991694
Short name T770
Test name
Test status
Simulation time 58313278310 ps
CPU time 29.01 seconds
Started Aug 05 05:21:05 PM PDT 24
Finished Aug 05 05:21:34 PM PDT 24
Peak memory 199904 kb
Host smart-b3f76494-9cc2-4b38-a300-cca9c751f672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849991694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3849991694
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3886384049
Short name T702
Test name
Test status
Simulation time 39668795091 ps
CPU time 6.95 seconds
Started Aug 05 05:21:27 PM PDT 24
Finished Aug 05 05:21:34 PM PDT 24
Peak memory 199772 kb
Host smart-32390634-96a1-4a05-98c3-09d08e06864b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886384049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3886384049
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3867901362
Short name T226
Test name
Test status
Simulation time 96123090983 ps
CPU time 131.89 seconds
Started Aug 05 05:21:11 PM PDT 24
Finished Aug 05 05:23:24 PM PDT 24
Peak memory 199980 kb
Host smart-5929c3b9-cc12-49c2-948d-c570a48a9693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867901362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3867901362
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.514723006
Short name T880
Test name
Test status
Simulation time 20341923226 ps
CPU time 22.73 seconds
Started Aug 05 05:21:10 PM PDT 24
Finished Aug 05 05:21:33 PM PDT 24
Peak memory 199908 kb
Host smart-7e024072-4ac6-42ad-a25e-388111a8b69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514723006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.514723006
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.4045659518
Short name T214
Test name
Test status
Simulation time 96168260456 ps
CPU time 100.12 seconds
Started Aug 05 05:21:11 PM PDT 24
Finished Aug 05 05:22:52 PM PDT 24
Peak memory 199908 kb
Host smart-286611e3-fa60-4957-9ce5-71744902c105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045659518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.4045659518
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3847663130
Short name T264
Test name
Test status
Simulation time 198292425871 ps
CPU time 68.31 seconds
Started Aug 05 05:21:10 PM PDT 24
Finished Aug 05 05:22:18 PM PDT 24
Peak memory 199952 kb
Host smart-fa3c94da-834a-4d15-9190-a0b335217b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847663130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3847663130
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3602074483
Short name T3
Test name
Test status
Simulation time 13052731997 ps
CPU time 19.09 seconds
Started Aug 05 05:21:11 PM PDT 24
Finished Aug 05 05:21:30 PM PDT 24
Peak memory 199756 kb
Host smart-497cc911-9502-4ac0-b768-b964f7263822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602074483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3602074483
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2076828821
Short name T124
Test name
Test status
Simulation time 113596986810 ps
CPU time 15.46 seconds
Started Aug 05 05:21:10 PM PDT 24
Finished Aug 05 05:21:26 PM PDT 24
Peak memory 199940 kb
Host smart-472e9e17-c84e-4abb-b38b-72ac9050c279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076828821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2076828821
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.584566202
Short name T377
Test name
Test status
Simulation time 10897354 ps
CPU time 0.55 seconds
Started Aug 05 05:15:25 PM PDT 24
Finished Aug 05 05:15:25 PM PDT 24
Peak memory 194312 kb
Host smart-79ef5438-c7d1-42f0-85ae-c001c8fd8ebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584566202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.584566202
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1629465024
Short name T1179
Test name
Test status
Simulation time 152359890866 ps
CPU time 116.49 seconds
Started Aug 05 05:15:20 PM PDT 24
Finished Aug 05 05:17:17 PM PDT 24
Peak memory 199904 kb
Host smart-1527b038-e7e9-4528-9a59-79d5f1092dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629465024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1629465024
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.870884222
Short name T882
Test name
Test status
Simulation time 20178533261 ps
CPU time 29.02 seconds
Started Aug 05 05:15:19 PM PDT 24
Finished Aug 05 05:15:48 PM PDT 24
Peak memory 199904 kb
Host smart-809bce85-3d67-450b-9f7c-1baab4512e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870884222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.870884222
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.304691084
Short name T525
Test name
Test status
Simulation time 133602542488 ps
CPU time 124.76 seconds
Started Aug 05 05:15:22 PM PDT 24
Finished Aug 05 05:17:26 PM PDT 24
Peak memory 199852 kb
Host smart-14783838-42dd-44ce-9f5d-9a5524a103a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304691084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.304691084
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1005040797
Short name T1046
Test name
Test status
Simulation time 38770433974 ps
CPU time 21.96 seconds
Started Aug 05 05:15:19 PM PDT 24
Finished Aug 05 05:15:41 PM PDT 24
Peak memory 199868 kb
Host smart-7af82906-1504-4a27-8d31-de8a61d870b4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005040797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1005040797
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3825954783
Short name T566
Test name
Test status
Simulation time 193857018329 ps
CPU time 436.59 seconds
Started Aug 05 05:15:19 PM PDT 24
Finished Aug 05 05:22:36 PM PDT 24
Peak memory 199984 kb
Host smart-980472e8-d10e-4ee2-8c48-b20d0f5bc041
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3825954783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3825954783
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2063413141
Short name T949
Test name
Test status
Simulation time 5429660912 ps
CPU time 10.77 seconds
Started Aug 05 05:15:20 PM PDT 24
Finished Aug 05 05:15:31 PM PDT 24
Peak memory 198652 kb
Host smart-29ee8427-e4ae-4b28-9f58-5f1ddaab187e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063413141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2063413141
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.2375398609
Short name T886
Test name
Test status
Simulation time 18249389921 ps
CPU time 8.53 seconds
Started Aug 05 05:15:20 PM PDT 24
Finished Aug 05 05:15:29 PM PDT 24
Peak memory 196764 kb
Host smart-f5f47e9b-71d2-4d2e-9ab8-e73174c395a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375398609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2375398609
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.717948787
Short name T463
Test name
Test status
Simulation time 9524076466 ps
CPU time 425.37 seconds
Started Aug 05 05:15:22 PM PDT 24
Finished Aug 05 05:22:27 PM PDT 24
Peak memory 199856 kb
Host smart-3f3dc200-48d9-460e-b18a-d75550fb7143
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=717948787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.717948787
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1458974167
Short name T436
Test name
Test status
Simulation time 2961537674 ps
CPU time 3.64 seconds
Started Aug 05 05:15:21 PM PDT 24
Finished Aug 05 05:15:25 PM PDT 24
Peak memory 197972 kb
Host smart-a955bdab-bb52-49e2-8f0e-b2d90d46a54e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1458974167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1458974167
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1715307485
Short name T1173
Test name
Test status
Simulation time 34941520420 ps
CPU time 52.5 seconds
Started Aug 05 05:15:25 PM PDT 24
Finished Aug 05 05:16:17 PM PDT 24
Peak memory 199892 kb
Host smart-fef54556-0e29-4a4f-8750-a22f723c20a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715307485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1715307485
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2547240096
Short name T449
Test name
Test status
Simulation time 4511069629 ps
CPU time 2.54 seconds
Started Aug 05 05:15:25 PM PDT 24
Finished Aug 05 05:15:28 PM PDT 24
Peak memory 196532 kb
Host smart-85d4171a-f2be-4f6a-be38-b0e1d0be791f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547240096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2547240096
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3975176843
Short name T781
Test name
Test status
Simulation time 6316956725 ps
CPU time 13.08 seconds
Started Aug 05 05:15:19 PM PDT 24
Finished Aug 05 05:15:32 PM PDT 24
Peak memory 199200 kb
Host smart-4783e380-a6a0-45b7-80ef-e3ad261a93a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975176843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3975176843
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.2320266938
Short name T787
Test name
Test status
Simulation time 290597498990 ps
CPU time 493.01 seconds
Started Aug 05 05:15:24 PM PDT 24
Finished Aug 05 05:23:37 PM PDT 24
Peak memory 200088 kb
Host smart-21acea75-b54e-4fb1-a05e-c6db5797375f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320266938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2320266938
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.4136186759
Short name T572
Test name
Test status
Simulation time 71534130365 ps
CPU time 825.44 seconds
Started Aug 05 05:15:21 PM PDT 24
Finished Aug 05 05:29:07 PM PDT 24
Peak memory 216408 kb
Host smart-c5301ff2-11b5-4e24-a827-f74755ce7092
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136186759 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.4136186759
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.733926149
Short name T1061
Test name
Test status
Simulation time 962384685 ps
CPU time 3.05 seconds
Started Aug 05 05:15:19 PM PDT 24
Finished Aug 05 05:15:22 PM PDT 24
Peak memory 199600 kb
Host smart-604e4913-956e-4302-9918-ba4f3ee43c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733926149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.733926149
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1241843943
Short name T1117
Test name
Test status
Simulation time 15918177133 ps
CPU time 9.12 seconds
Started Aug 05 05:15:22 PM PDT 24
Finished Aug 05 05:15:31 PM PDT 24
Peak memory 199856 kb
Host smart-a19f3e24-b411-4145-a05b-158da5671d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241843943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1241843943
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.348106881
Short name T243
Test name
Test status
Simulation time 28014875830 ps
CPU time 22.71 seconds
Started Aug 05 05:21:10 PM PDT 24
Finished Aug 05 05:21:33 PM PDT 24
Peak memory 199528 kb
Host smart-68ef0bd9-b8bd-46d6-9f2d-837534d96c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348106881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.348106881
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3572628217
Short name T240
Test name
Test status
Simulation time 64642782318 ps
CPU time 41.42 seconds
Started Aug 05 05:21:12 PM PDT 24
Finished Aug 05 05:21:53 PM PDT 24
Peak memory 199908 kb
Host smart-d8f3ad07-0d89-45b3-b342-1dd104cd0788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572628217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3572628217
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1583439715
Short name T187
Test name
Test status
Simulation time 121209940862 ps
CPU time 88.64 seconds
Started Aug 05 05:21:17 PM PDT 24
Finished Aug 05 05:22:46 PM PDT 24
Peak memory 199772 kb
Host smart-050e1263-70d2-4284-b943-9b938e6cc364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583439715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1583439715
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2180691564
Short name T750
Test name
Test status
Simulation time 127153216698 ps
CPU time 12.12 seconds
Started Aug 05 05:21:14 PM PDT 24
Finished Aug 05 05:21:26 PM PDT 24
Peak memory 199960 kb
Host smart-ef548060-48ae-4607-815d-a44c501d5c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180691564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2180691564
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2662332286
Short name T284
Test name
Test status
Simulation time 105777391829 ps
CPU time 42.13 seconds
Started Aug 05 05:21:18 PM PDT 24
Finished Aug 05 05:22:00 PM PDT 24
Peak memory 199968 kb
Host smart-f93d7b10-a10c-4b90-903d-ace98f835bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662332286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2662332286
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1034215659
Short name T552
Test name
Test status
Simulation time 222779780747 ps
CPU time 26.85 seconds
Started Aug 05 05:21:17 PM PDT 24
Finished Aug 05 05:21:43 PM PDT 24
Peak memory 199672 kb
Host smart-4ae139ee-2054-4408-918d-04108c040364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034215659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1034215659
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3450518838
Short name T141
Test name
Test status
Simulation time 135683255059 ps
CPU time 61.2 seconds
Started Aug 05 05:21:14 PM PDT 24
Finished Aug 05 05:22:15 PM PDT 24
Peak memory 199916 kb
Host smart-bd6b9b40-221c-4680-8012-f5c71f6848bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450518838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3450518838
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.170886891
Short name T396
Test name
Test status
Simulation time 58219647623 ps
CPU time 102.97 seconds
Started Aug 05 05:21:13 PM PDT 24
Finished Aug 05 05:22:56 PM PDT 24
Peak memory 199936 kb
Host smart-c7e51455-e40c-485f-83ef-815fa1ef167f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170886891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.170886891
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2109064319
Short name T1153
Test name
Test status
Simulation time 106123684689 ps
CPU time 173.94 seconds
Started Aug 05 05:21:31 PM PDT 24
Finished Aug 05 05:24:25 PM PDT 24
Peak memory 199784 kb
Host smart-e1fdd791-b133-4b28-9bcd-fd39539d8263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109064319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2109064319
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3978216523
Short name T869
Test name
Test status
Simulation time 73132762981 ps
CPU time 57.1 seconds
Started Aug 05 05:21:20 PM PDT 24
Finished Aug 05 05:22:18 PM PDT 24
Peak memory 199928 kb
Host smart-86778be0-707e-4dd3-acd7-4522699d4213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978216523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3978216523
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3573161705
Short name T758
Test name
Test status
Simulation time 16096732 ps
CPU time 0.55 seconds
Started Aug 05 05:15:28 PM PDT 24
Finished Aug 05 05:15:29 PM PDT 24
Peak memory 195360 kb
Host smart-f9a93f82-0f70-4dd6-a884-175cc140b669
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573161705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3573161705
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3609621726
Short name T258
Test name
Test status
Simulation time 29144546229 ps
CPU time 48.61 seconds
Started Aug 05 05:15:27 PM PDT 24
Finished Aug 05 05:16:16 PM PDT 24
Peak memory 199956 kb
Host smart-59377063-bc77-43ba-8d25-ca7bde9ebd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609621726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3609621726
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1118486458
Short name T143
Test name
Test status
Simulation time 53430678902 ps
CPU time 86.53 seconds
Started Aug 05 05:15:25 PM PDT 24
Finished Aug 05 05:16:52 PM PDT 24
Peak memory 199824 kb
Host smart-3a83cd4c-c24b-4acb-95b5-234188f0ce85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118486458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1118486458
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.913660606
Short name T193
Test name
Test status
Simulation time 112637178890 ps
CPU time 161.4 seconds
Started Aug 05 05:15:25 PM PDT 24
Finished Aug 05 05:18:07 PM PDT 24
Peak memory 199972 kb
Host smart-35d6da76-3be9-490c-a9ee-d6efeb435a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913660606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.913660606
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.433489769
Short name T444
Test name
Test status
Simulation time 43688316526 ps
CPU time 62.12 seconds
Started Aug 05 05:15:24 PM PDT 24
Finished Aug 05 05:16:26 PM PDT 24
Peak memory 199908 kb
Host smart-56a19f8f-84a1-4ae3-85ff-1fa67a71794f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433489769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.433489769
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2847295038
Short name T1062
Test name
Test status
Simulation time 95094877835 ps
CPU time 570.69 seconds
Started Aug 05 05:15:30 PM PDT 24
Finished Aug 05 05:25:01 PM PDT 24
Peak memory 199904 kb
Host smart-d1aad96a-ba81-4d5d-bc23-8ae1affa3558
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2847295038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2847295038
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1349571678
Short name T478
Test name
Test status
Simulation time 6137149106 ps
CPU time 5.92 seconds
Started Aug 05 05:15:28 PM PDT 24
Finished Aug 05 05:15:34 PM PDT 24
Peak memory 199520 kb
Host smart-7ae966cb-a45e-45bf-af01-f9f647841d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349571678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1349571678
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.4034954966
Short name T887
Test name
Test status
Simulation time 13023939640 ps
CPU time 772.79 seconds
Started Aug 05 05:15:30 PM PDT 24
Finished Aug 05 05:28:23 PM PDT 24
Peak memory 199980 kb
Host smart-30f48a5d-9cb7-454d-b42f-7a7a13514d8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4034954966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.4034954966
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1820236861
Short name T901
Test name
Test status
Simulation time 5814018487 ps
CPU time 6.76 seconds
Started Aug 05 05:15:25 PM PDT 24
Finished Aug 05 05:15:32 PM PDT 24
Peak memory 197728 kb
Host smart-53e980fb-d9bc-436f-8f03-6873240b2a30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1820236861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1820236861
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1437925936
Short name T979
Test name
Test status
Simulation time 9480114860 ps
CPU time 14.94 seconds
Started Aug 05 05:15:24 PM PDT 24
Finished Aug 05 05:15:39 PM PDT 24
Peak memory 199696 kb
Host smart-7638c62f-d1b0-4f4b-b134-1be5b25275b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437925936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1437925936
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3521540662
Short name T1051
Test name
Test status
Simulation time 45590046992 ps
CPU time 33.8 seconds
Started Aug 05 05:15:25 PM PDT 24
Finished Aug 05 05:15:59 PM PDT 24
Peak memory 195812 kb
Host smart-c7593318-d973-4641-afb4-bc5e980a0f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521540662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3521540662
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1418449429
Short name T358
Test name
Test status
Simulation time 535678017 ps
CPU time 1.3 seconds
Started Aug 05 05:15:25 PM PDT 24
Finished Aug 05 05:15:26 PM PDT 24
Peak memory 198856 kb
Host smart-5962193c-f94d-46eb-ba37-f03a966e2ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418449429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1418449429
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1336482089
Short name T1140
Test name
Test status
Simulation time 103365228331 ps
CPU time 159.3 seconds
Started Aug 05 05:15:33 PM PDT 24
Finished Aug 05 05:18:13 PM PDT 24
Peak memory 216412 kb
Host smart-aa8c3575-8cdf-4e9d-bb4a-7090fc04df49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336482089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1336482089
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.67281915
Short name T135
Test name
Test status
Simulation time 94351044284 ps
CPU time 998.79 seconds
Started Aug 05 05:15:29 PM PDT 24
Finished Aug 05 05:32:08 PM PDT 24
Peak memory 216432 kb
Host smart-33b27c57-c56e-422d-853b-3511c8ac0042
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67281915 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.67281915
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1450664442
Short name T1013
Test name
Test status
Simulation time 821982136 ps
CPU time 2.44 seconds
Started Aug 05 05:15:25 PM PDT 24
Finished Aug 05 05:15:27 PM PDT 24
Peak memory 199636 kb
Host smart-bf762c33-c3b5-43d1-9643-256cdc3cb159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450664442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1450664442
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2150579226
Short name T82
Test name
Test status
Simulation time 90917736451 ps
CPU time 39.26 seconds
Started Aug 05 05:15:27 PM PDT 24
Finished Aug 05 05:16:06 PM PDT 24
Peak memory 199904 kb
Host smart-a97cac28-3787-45ef-b716-0fcffcc7e4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150579226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2150579226
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.285691811
Short name T232
Test name
Test status
Simulation time 29343877024 ps
CPU time 40.84 seconds
Started Aug 05 05:21:21 PM PDT 24
Finished Aug 05 05:22:02 PM PDT 24
Peak memory 199896 kb
Host smart-960d406d-8809-461a-845b-4b4904fe0954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285691811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.285691811
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3967651799
Short name T846
Test name
Test status
Simulation time 16757346129 ps
CPU time 27.87 seconds
Started Aug 05 05:21:28 PM PDT 24
Finished Aug 05 05:21:56 PM PDT 24
Peak memory 198872 kb
Host smart-38c79c6c-3db5-4aa8-8e58-2d454a7a145a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967651799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3967651799
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1072223240
Short name T924
Test name
Test status
Simulation time 47417352728 ps
CPU time 20.56 seconds
Started Aug 05 05:21:28 PM PDT 24
Finished Aug 05 05:21:49 PM PDT 24
Peak memory 200088 kb
Host smart-9ce6311f-ddd3-4828-8364-fdfac2725c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072223240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1072223240
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3926984345
Short name T208
Test name
Test status
Simulation time 216658244017 ps
CPU time 331.37 seconds
Started Aug 05 05:21:20 PM PDT 24
Finished Aug 05 05:26:52 PM PDT 24
Peak memory 199852 kb
Host smart-468c2c38-029c-412a-a8f2-83e4573c4e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926984345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3926984345
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1864081385
Short name T172
Test name
Test status
Simulation time 72659645773 ps
CPU time 13 seconds
Started Aug 05 05:21:20 PM PDT 24
Finished Aug 05 05:21:33 PM PDT 24
Peak memory 199844 kb
Host smart-33ce8936-3afd-434f-a378-13535ecb317a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864081385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1864081385
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.201019601
Short name T1144
Test name
Test status
Simulation time 37446999227 ps
CPU time 37.39 seconds
Started Aug 05 05:21:22 PM PDT 24
Finished Aug 05 05:21:59 PM PDT 24
Peak memory 199940 kb
Host smart-c7049fc4-f87b-4557-9c61-dce632059d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201019601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.201019601
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3408128614
Short name T199
Test name
Test status
Simulation time 36535280204 ps
CPU time 50.07 seconds
Started Aug 05 05:21:28 PM PDT 24
Finished Aug 05 05:22:18 PM PDT 24
Peak memory 199952 kb
Host smart-638109f6-5cb7-450c-aa3d-f76ebc7fcaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408128614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3408128614
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.4201164148
Short name T236
Test name
Test status
Simulation time 110027894259 ps
CPU time 48.19 seconds
Started Aug 05 05:21:25 PM PDT 24
Finished Aug 05 05:22:13 PM PDT 24
Peak memory 199944 kb
Host smart-e2700e45-7085-4a02-af27-d2965312c4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201164148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.4201164148
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.2072946088
Short name T783
Test name
Test status
Simulation time 44833937920 ps
CPU time 82.22 seconds
Started Aug 05 05:21:27 PM PDT 24
Finished Aug 05 05:22:49 PM PDT 24
Peak memory 199944 kb
Host smart-fd9d2d43-106a-4f78-8009-93aeff891d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072946088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2072946088
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3259797251
Short name T500
Test name
Test status
Simulation time 50804916 ps
CPU time 0.61 seconds
Started Aug 05 05:15:37 PM PDT 24
Finished Aug 05 05:15:37 PM PDT 24
Peak memory 194740 kb
Host smart-16959ccb-5c78-4a4e-97c2-9dd307795584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259797251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3259797251
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.4017843303
Short name T1028
Test name
Test status
Simulation time 132404549831 ps
CPU time 52.29 seconds
Started Aug 05 05:15:29 PM PDT 24
Finished Aug 05 05:16:22 PM PDT 24
Peak memory 199936 kb
Host smart-a1f14901-363d-4d3c-8826-ece935eab083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017843303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.4017843303
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1062723799
Short name T170
Test name
Test status
Simulation time 37595808809 ps
CPU time 55.68 seconds
Started Aug 05 05:15:33 PM PDT 24
Finished Aug 05 05:16:29 PM PDT 24
Peak memory 199976 kb
Host smart-b45e3801-a34c-46d9-adbb-bf2ae4bce20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062723799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1062723799
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3987936863
Short name T844
Test name
Test status
Simulation time 18614763214 ps
CPU time 28.1 seconds
Started Aug 05 05:15:34 PM PDT 24
Finished Aug 05 05:16:02 PM PDT 24
Peak memory 199812 kb
Host smart-6ec639cc-5381-4648-88d7-15500d5b79d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987936863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3987936863
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.4158508101
Short name T11
Test name
Test status
Simulation time 62928253957 ps
CPU time 29.69 seconds
Started Aug 05 05:15:33 PM PDT 24
Finished Aug 05 05:16:03 PM PDT 24
Peak memory 199872 kb
Host smart-308e79f8-4d5b-4014-a4c9-b9fd60ec872c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158508101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.4158508101
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1599310706
Short name T909
Test name
Test status
Simulation time 137909490603 ps
CPU time 385.88 seconds
Started Aug 05 05:15:32 PM PDT 24
Finished Aug 05 05:21:58 PM PDT 24
Peak memory 199912 kb
Host smart-2d52d886-2b65-45bb-94f8-a1877c36b479
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1599310706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1599310706
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3439889716
Short name T891
Test name
Test status
Simulation time 3355171614 ps
CPU time 6.2 seconds
Started Aug 05 05:15:29 PM PDT 24
Finished Aug 05 05:15:35 PM PDT 24
Peak memory 197164 kb
Host smart-cdbd5840-87fd-48f1-b340-027f6c7a48e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439889716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3439889716
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.196028779
Short name T54
Test name
Test status
Simulation time 67128960714 ps
CPU time 44.12 seconds
Started Aug 05 05:15:29 PM PDT 24
Finished Aug 05 05:16:14 PM PDT 24
Peak memory 200064 kb
Host smart-83e97cc3-7ff8-463d-a2f0-715911057593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196028779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.196028779
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.590025260
Short name T370
Test name
Test status
Simulation time 21682202483 ps
CPU time 851.89 seconds
Started Aug 05 05:15:32 PM PDT 24
Finished Aug 05 05:29:44 PM PDT 24
Peak memory 199440 kb
Host smart-e79c4116-ee0f-46d4-9f86-364787ebc306
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=590025260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.590025260
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2542712338
Short name T578
Test name
Test status
Simulation time 1487834227 ps
CPU time 6.22 seconds
Started Aug 05 05:15:30 PM PDT 24
Finished Aug 05 05:15:36 PM PDT 24
Peak memory 198232 kb
Host smart-b0e7fa4d-83fe-4fc9-8282-0820b513c1c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2542712338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2542712338
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2731547932
Short name T635
Test name
Test status
Simulation time 42299747465 ps
CPU time 35.53 seconds
Started Aug 05 05:15:42 PM PDT 24
Finished Aug 05 05:16:17 PM PDT 24
Peak memory 199984 kb
Host smart-8d60a80d-08de-412d-94e1-1fe0c102645b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731547932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2731547932
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1772938191
Short name T295
Test name
Test status
Simulation time 4302135935 ps
CPU time 7.01 seconds
Started Aug 05 05:15:32 PM PDT 24
Finished Aug 05 05:15:40 PM PDT 24
Peak memory 196736 kb
Host smart-5d97c0d2-b137-4a9b-8eab-4b53a34269cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772938191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1772938191
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.4023766063
Short name T903
Test name
Test status
Simulation time 894747877 ps
CPU time 2.56 seconds
Started Aug 05 05:15:32 PM PDT 24
Finished Aug 05 05:15:35 PM PDT 24
Peak memory 198012 kb
Host smart-040be45f-fa4d-46ad-b7ca-d94eb66b9302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023766063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.4023766063
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.1329544909
Short name T660
Test name
Test status
Simulation time 605276397148 ps
CPU time 346.91 seconds
Started Aug 05 05:15:33 PM PDT 24
Finished Aug 05 05:21:20 PM PDT 24
Peak memory 199972 kb
Host smart-7b2f9fd8-7461-4019-be95-c050170dc03f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329544909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1329544909
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3038724635
Short name T679
Test name
Test status
Simulation time 915475270464 ps
CPU time 608.49 seconds
Started Aug 05 05:15:34 PM PDT 24
Finished Aug 05 05:25:42 PM PDT 24
Peak memory 224768 kb
Host smart-2c4145a1-4212-457f-982a-85ed33e36465
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038724635 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3038724635
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2085523885
Short name T51
Test name
Test status
Simulation time 6130326246 ps
CPU time 20.46 seconds
Started Aug 05 05:15:30 PM PDT 24
Finished Aug 05 05:15:50 PM PDT 24
Peak memory 199852 kb
Host smart-5b74c669-d381-42e7-a3ce-6057f0b5e491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085523885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2085523885
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2981827603
Short name T646
Test name
Test status
Simulation time 22152933110 ps
CPU time 34.72 seconds
Started Aug 05 05:15:32 PM PDT 24
Finished Aug 05 05:16:07 PM PDT 24
Peak memory 199916 kb
Host smart-e5985541-d77d-42a0-b2f8-faf281f44538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981827603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2981827603
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3703985574
Short name T1156
Test name
Test status
Simulation time 266731138370 ps
CPU time 39.83 seconds
Started Aug 05 05:21:27 PM PDT 24
Finished Aug 05 05:22:07 PM PDT 24
Peak memory 199968 kb
Host smart-2519aa3d-716b-45f9-a248-254dac4763b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703985574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3703985574
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1586664291
Short name T632
Test name
Test status
Simulation time 178793358834 ps
CPU time 29.37 seconds
Started Aug 05 05:21:30 PM PDT 24
Finished Aug 05 05:21:59 PM PDT 24
Peak memory 199852 kb
Host smart-54646bfd-192a-4e4f-998d-2c354d88c8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586664291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1586664291
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1666551192
Short name T475
Test name
Test status
Simulation time 117495615414 ps
CPU time 40.76 seconds
Started Aug 05 05:21:27 PM PDT 24
Finished Aug 05 05:22:08 PM PDT 24
Peak memory 199860 kb
Host smart-83d7a586-c6a2-401f-8caf-e963413dce77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666551192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1666551192
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.758918495
Short name T658
Test name
Test status
Simulation time 20832332404 ps
CPU time 35.36 seconds
Started Aug 05 05:21:29 PM PDT 24
Finished Aug 05 05:22:05 PM PDT 24
Peak memory 199932 kb
Host smart-6a5435d9-31b8-415c-8f5d-25051ba8e011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758918495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.758918495
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.328453584
Short name T517
Test name
Test status
Simulation time 60418060500 ps
CPU time 87.57 seconds
Started Aug 05 05:21:25 PM PDT 24
Finished Aug 05 05:22:53 PM PDT 24
Peak memory 199952 kb
Host smart-5993cb47-ba97-4917-816a-799a77e91b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328453584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.328453584
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.60445073
Short name T642
Test name
Test status
Simulation time 19079067522 ps
CPU time 29.57 seconds
Started Aug 05 05:21:34 PM PDT 24
Finished Aug 05 05:22:04 PM PDT 24
Peak memory 198812 kb
Host smart-3c894b33-7652-4ab5-bd68-2eeabadedeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60445073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.60445073
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2577791539
Short name T1079
Test name
Test status
Simulation time 69953144227 ps
CPU time 32.26 seconds
Started Aug 05 05:21:32 PM PDT 24
Finished Aug 05 05:22:05 PM PDT 24
Peak memory 199980 kb
Host smart-415968e7-dc9f-4d9b-ab12-f4399728dcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577791539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2577791539
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1418859887
Short name T1098
Test name
Test status
Simulation time 154676904955 ps
CPU time 144.79 seconds
Started Aug 05 05:21:31 PM PDT 24
Finished Aug 05 05:23:56 PM PDT 24
Peak memory 199836 kb
Host smart-9c5d7430-9c8b-4d1b-bd6b-d314ce3117e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418859887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1418859887
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3746016183
Short name T709
Test name
Test status
Simulation time 115600315855 ps
CPU time 24.42 seconds
Started Aug 05 05:21:31 PM PDT 24
Finished Aug 05 05:21:56 PM PDT 24
Peak memory 199680 kb
Host smart-6ede5695-19f3-422f-863d-bd6f8a0af8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746016183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3746016183
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.319333048
Short name T237
Test name
Test status
Simulation time 60381958353 ps
CPU time 23.45 seconds
Started Aug 05 05:21:30 PM PDT 24
Finished Aug 05 05:21:54 PM PDT 24
Peak memory 199480 kb
Host smart-381e5ec5-aa6d-43ec-80a6-85c2196c7fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319333048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.319333048
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.567851918
Short name T342
Test name
Test status
Simulation time 12237785 ps
CPU time 0.56 seconds
Started Aug 05 05:15:40 PM PDT 24
Finished Aug 05 05:15:41 PM PDT 24
Peak memory 195336 kb
Host smart-39b22abf-a8c1-417e-b69e-7c8d7f8af7a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567851918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.567851918
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.820414275
Short name T357
Test name
Test status
Simulation time 60649923952 ps
CPU time 13.62 seconds
Started Aug 05 05:15:37 PM PDT 24
Finished Aug 05 05:15:51 PM PDT 24
Peak memory 199820 kb
Host smart-3d216de1-75f7-494c-b952-d26fd08abb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820414275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.820414275
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1010639958
Short name T331
Test name
Test status
Simulation time 29857271142 ps
CPU time 10.78 seconds
Started Aug 05 05:15:35 PM PDT 24
Finished Aug 05 05:15:46 PM PDT 24
Peak memory 198716 kb
Host smart-c48c9a25-b61f-4a2b-927d-81c426dbea63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010639958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1010639958
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3173954972
Short name T44
Test name
Test status
Simulation time 20806758219 ps
CPU time 47.24 seconds
Started Aug 05 05:15:37 PM PDT 24
Finished Aug 05 05:16:24 PM PDT 24
Peak memory 199824 kb
Host smart-d091716d-c9b5-4b13-9f2f-2170173f8161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173954972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3173954972
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1255812636
Short name T130
Test name
Test status
Simulation time 64868243117 ps
CPU time 24.92 seconds
Started Aug 05 05:15:39 PM PDT 24
Finished Aug 05 05:16:04 PM PDT 24
Peak memory 199928 kb
Host smart-b9afc4f6-3518-4cd1-83a4-2437ddcbeb73
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255812636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1255812636
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1155249535
Short name T440
Test name
Test status
Simulation time 153234199294 ps
CPU time 383.17 seconds
Started Aug 05 05:15:41 PM PDT 24
Finished Aug 05 05:22:04 PM PDT 24
Peak memory 199904 kb
Host smart-38ff7659-6472-428f-930a-72ead65bf8ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1155249535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1155249535
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.162687002
Short name T622
Test name
Test status
Simulation time 6833041057 ps
CPU time 6.71 seconds
Started Aug 05 05:15:40 PM PDT 24
Finished Aug 05 05:15:46 PM PDT 24
Peak memory 198664 kb
Host smart-b153132b-15c7-446b-b914-8dba482e956d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162687002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.162687002
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.1380216522
Short name T281
Test name
Test status
Simulation time 3753726945 ps
CPU time 7.72 seconds
Started Aug 05 05:15:34 PM PDT 24
Finished Aug 05 05:15:42 PM PDT 24
Peak memory 199980 kb
Host smart-17df4df7-8c75-4266-95cc-f9d8116f685e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380216522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1380216522
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.1428801500
Short name T484
Test name
Test status
Simulation time 7028930867 ps
CPU time 95.32 seconds
Started Aug 05 05:15:37 PM PDT 24
Finished Aug 05 05:17:13 PM PDT 24
Peak memory 199896 kb
Host smart-fc18f13c-acea-4280-b3fe-e452c44f1551
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1428801500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1428801500
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2484238553
Short name T744
Test name
Test status
Simulation time 2645579509 ps
CPU time 1.77 seconds
Started Aug 05 05:15:34 PM PDT 24
Finished Aug 05 05:15:36 PM PDT 24
Peak memory 198148 kb
Host smart-b1d2f539-5947-463e-acc3-e3dd17599d27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2484238553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2484238553
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.189995306
Short name T694
Test name
Test status
Simulation time 93520307686 ps
CPU time 199.13 seconds
Started Aug 05 05:15:41 PM PDT 24
Finished Aug 05 05:19:00 PM PDT 24
Peak memory 199948 kb
Host smart-12375cd7-7aa4-4f57-a835-d91d6704cec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189995306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.189995306
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.154701087
Short name T888
Test name
Test status
Simulation time 2585927317 ps
CPU time 2.76 seconds
Started Aug 05 05:15:33 PM PDT 24
Finished Aug 05 05:15:36 PM PDT 24
Peak memory 196432 kb
Host smart-3f26f346-088a-4602-a477-dc4aa3c15325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154701087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.154701087
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2724439577
Short name T824
Test name
Test status
Simulation time 753377672 ps
CPU time 1.24 seconds
Started Aug 05 05:15:32 PM PDT 24
Finished Aug 05 05:15:34 PM PDT 24
Peak memory 199528 kb
Host smart-fcbb48fe-5d2e-4163-af0e-d41dfaddfbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724439577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2724439577
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2349029260
Short name T1052
Test name
Test status
Simulation time 217198501082 ps
CPU time 362.3 seconds
Started Aug 05 05:15:40 PM PDT 24
Finished Aug 05 05:21:42 PM PDT 24
Peak memory 199836 kb
Host smart-639eb03f-f7d0-4bdb-82ee-3a2d469f5564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349029260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2349029260
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3913937634
Short name T998
Test name
Test status
Simulation time 113384085255 ps
CPU time 561.16 seconds
Started Aug 05 05:15:39 PM PDT 24
Finished Aug 05 05:25:00 PM PDT 24
Peak memory 216548 kb
Host smart-0e8dd592-f709-402b-8a3c-803a66483734
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913937634 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3913937634
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3719469484
Short name T565
Test name
Test status
Simulation time 6373896184 ps
CPU time 37.78 seconds
Started Aug 05 05:15:42 PM PDT 24
Finished Aug 05 05:16:20 PM PDT 24
Peak memory 199776 kb
Host smart-07f7e3dd-617b-4b79-bfaa-0660c0db9b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719469484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3719469484
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.958460815
Short name T752
Test name
Test status
Simulation time 41071753984 ps
CPU time 65.18 seconds
Started Aug 05 05:15:34 PM PDT 24
Finished Aug 05 05:16:39 PM PDT 24
Peak memory 199908 kb
Host smart-05f4f124-39a7-4664-b202-187cf5d01c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958460815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.958460815
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.758355624
Short name T252
Test name
Test status
Simulation time 247373591307 ps
CPU time 182.86 seconds
Started Aug 05 05:21:34 PM PDT 24
Finished Aug 05 05:24:37 PM PDT 24
Peak memory 198916 kb
Host smart-0b27edbc-3bfa-4bec-9b87-282e763bf1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758355624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.758355624
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1471317548
Short name T182
Test name
Test status
Simulation time 126696749064 ps
CPU time 101.02 seconds
Started Aug 05 05:21:29 PM PDT 24
Finished Aug 05 05:23:10 PM PDT 24
Peak memory 199856 kb
Host smart-08b2ed8e-0792-449b-9301-3fe4290197cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471317548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1471317548
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2065984216
Short name T839
Test name
Test status
Simulation time 82297221991 ps
CPU time 124.54 seconds
Started Aug 05 05:21:37 PM PDT 24
Finished Aug 05 05:23:42 PM PDT 24
Peak memory 199884 kb
Host smart-eed55560-cdd5-40fb-a538-6f2b9cebd38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065984216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2065984216
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1908357076
Short name T989
Test name
Test status
Simulation time 206383427436 ps
CPU time 25.56 seconds
Started Aug 05 05:21:37 PM PDT 24
Finished Aug 05 05:22:02 PM PDT 24
Peak memory 199904 kb
Host smart-722b125b-f38f-4c9e-b2c3-61aaec3bcaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908357076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1908357076
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1522991048
Short name T1064
Test name
Test status
Simulation time 25305825311 ps
CPU time 21.25 seconds
Started Aug 05 05:21:37 PM PDT 24
Finished Aug 05 05:21:58 PM PDT 24
Peak memory 199972 kb
Host smart-b4035855-246a-4a31-813c-983cd6f3e9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522991048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1522991048
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3624572038
Short name T855
Test name
Test status
Simulation time 63734332701 ps
CPU time 44.21 seconds
Started Aug 05 05:21:37 PM PDT 24
Finished Aug 05 05:22:22 PM PDT 24
Peak memory 199956 kb
Host smart-a50d03af-8c18-46fa-80bd-bea3d1036ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624572038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3624572038
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2364256980
Short name T774
Test name
Test status
Simulation time 22692462151 ps
CPU time 35.39 seconds
Started Aug 05 05:21:40 PM PDT 24
Finished Aug 05 05:22:16 PM PDT 24
Peak memory 199864 kb
Host smart-224ac996-3460-45ca-b8e5-69dff8b73476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364256980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2364256980
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3001445057
Short name T963
Test name
Test status
Simulation time 85534473605 ps
CPU time 30.76 seconds
Started Aug 05 05:21:40 PM PDT 24
Finished Aug 05 05:22:11 PM PDT 24
Peak memory 199916 kb
Host smart-615532b4-9d2d-4f5d-9277-a97112d41d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001445057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3001445057
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3413604356
Short name T52
Test name
Test status
Simulation time 12988345 ps
CPU time 0.56 seconds
Started Aug 05 05:13:31 PM PDT 24
Finished Aug 05 05:13:32 PM PDT 24
Peak memory 195228 kb
Host smart-83c8fa89-30c3-4c24-8104-9918e6fb908d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413604356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3413604356
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2653433166
Short name T155
Test name
Test status
Simulation time 38067946430 ps
CPU time 25 seconds
Started Aug 05 05:13:31 PM PDT 24
Finished Aug 05 05:13:56 PM PDT 24
Peak memory 199936 kb
Host smart-9fcf40a5-9587-4594-a56a-075af7d5a13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653433166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2653433166
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3051194486
Short name T1095
Test name
Test status
Simulation time 74309146936 ps
CPU time 43.5 seconds
Started Aug 05 05:13:32 PM PDT 24
Finished Aug 05 05:14:15 PM PDT 24
Peak memory 199800 kb
Host smart-9f7b5335-a2e4-40a7-958f-aaf6a52d362a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051194486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3051194486
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1653246550
Short name T268
Test name
Test status
Simulation time 122745684524 ps
CPU time 919.01 seconds
Started Aug 05 05:13:31 PM PDT 24
Finished Aug 05 05:28:50 PM PDT 24
Peak memory 199928 kb
Host smart-2bb90915-3eb7-40c1-85bd-4f3cf989ece7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653246550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1653246550
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3331152801
Short name T408
Test name
Test status
Simulation time 895376669 ps
CPU time 1.85 seconds
Started Aug 05 05:13:33 PM PDT 24
Finished Aug 05 05:13:35 PM PDT 24
Peak memory 195936 kb
Host smart-452f112e-cb05-4410-981c-172b99e36c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331152801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3331152801
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3591668070
Short name T908
Test name
Test status
Simulation time 48512507568 ps
CPU time 81.83 seconds
Started Aug 05 05:13:30 PM PDT 24
Finished Aug 05 05:14:53 PM PDT 24
Peak memory 199812 kb
Host smart-cba4c7e5-67ca-4a9e-b5cc-b62bdd6252a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591668070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3591668070
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1827925929
Short name T1113
Test name
Test status
Simulation time 11413048066 ps
CPU time 696.2 seconds
Started Aug 05 05:13:31 PM PDT 24
Finished Aug 05 05:25:07 PM PDT 24
Peak memory 199920 kb
Host smart-222bd4c7-71bb-4038-b04b-8a6542d13e36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1827925929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1827925929
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1994628413
Short name T820
Test name
Test status
Simulation time 6318895018 ps
CPU time 15.2 seconds
Started Aug 05 05:13:34 PM PDT 24
Finished Aug 05 05:13:49 PM PDT 24
Peak memory 198212 kb
Host smart-f23e72b8-ea8b-4f4b-8c33-bb2dc89c6c0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1994628413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1994628413
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2934815576
Short name T1081
Test name
Test status
Simulation time 107606865649 ps
CPU time 110.36 seconds
Started Aug 05 05:13:31 PM PDT 24
Finished Aug 05 05:15:22 PM PDT 24
Peak memory 199820 kb
Host smart-ec190d74-cac9-4ab4-8776-05d3d9c69085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934815576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2934815576
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.619477901
Short name T825
Test name
Test status
Simulation time 3293687270 ps
CPU time 1.15 seconds
Started Aug 05 05:13:30 PM PDT 24
Finished Aug 05 05:13:32 PM PDT 24
Peak memory 196548 kb
Host smart-ee39b971-e14d-4fe9-90c8-c756595a628a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619477901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.619477901
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.4168094876
Short name T25
Test name
Test status
Simulation time 46412370 ps
CPU time 0.78 seconds
Started Aug 05 05:13:32 PM PDT 24
Finished Aug 05 05:13:33 PM PDT 24
Peak memory 218480 kb
Host smart-5d13a9be-b33b-48e1-824d-4ea41738bf59
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168094876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.4168094876
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.4167726854
Short name T280
Test name
Test status
Simulation time 949694020 ps
CPU time 2.42 seconds
Started Aug 05 05:13:26 PM PDT 24
Finished Aug 05 05:13:28 PM PDT 24
Peak memory 198740 kb
Host smart-9aa643bd-fd5c-454d-a46f-4430c0a0b531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167726854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.4167726854
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.31442417
Short name T224
Test name
Test status
Simulation time 89090981012 ps
CPU time 72.65 seconds
Started Aug 05 05:13:32 PM PDT 24
Finished Aug 05 05:14:44 PM PDT 24
Peak memory 199952 kb
Host smart-088bfd83-92c9-4030-9f30-12d97003ee69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31442417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.31442417
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.4034808617
Short name T66
Test name
Test status
Simulation time 35312594737 ps
CPU time 473.41 seconds
Started Aug 05 05:13:31 PM PDT 24
Finished Aug 05 05:21:24 PM PDT 24
Peak memory 215448 kb
Host smart-f763600b-2ce1-4639-8549-f90b7012dd3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034808617 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.4034808617
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2417713309
Short name T748
Test name
Test status
Simulation time 1482710727 ps
CPU time 4.43 seconds
Started Aug 05 05:13:31 PM PDT 24
Finished Aug 05 05:13:35 PM PDT 24
Peak memory 198888 kb
Host smart-92ad5f34-6171-47e1-a987-3078f8bc4b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417713309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2417713309
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.246470096
Short name T597
Test name
Test status
Simulation time 9735358134 ps
CPU time 4.92 seconds
Started Aug 05 05:13:31 PM PDT 24
Finished Aug 05 05:13:36 PM PDT 24
Peak memory 199684 kb
Host smart-e8ba201c-1655-4559-81fe-e8807100738e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246470096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.246470096
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.4270021282
Short name T609
Test name
Test status
Simulation time 23230063 ps
CPU time 0.55 seconds
Started Aug 05 05:15:44 PM PDT 24
Finished Aug 05 05:15:45 PM PDT 24
Peak memory 195356 kb
Host smart-e1d1b0e7-8a62-41c2-bd05-7bf3c476ed64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270021282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.4270021282
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3832932077
Short name T439
Test name
Test status
Simulation time 28535385678 ps
CPU time 20.34 seconds
Started Aug 05 05:15:40 PM PDT 24
Finished Aug 05 05:16:00 PM PDT 24
Peak memory 199932 kb
Host smart-f8caaf12-ba58-4bb5-93fb-ad12d9a098b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832932077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3832932077
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1277736831
Short name T437
Test name
Test status
Simulation time 55878464349 ps
CPU time 118.24 seconds
Started Aug 05 05:15:40 PM PDT 24
Finished Aug 05 05:17:38 PM PDT 24
Peak memory 199808 kb
Host smart-b5999f46-ef22-4d1b-9ba3-17966de0d934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277736831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1277736831
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1638918207
Short name T1050
Test name
Test status
Simulation time 48458985834 ps
CPU time 33.58 seconds
Started Aug 05 05:15:40 PM PDT 24
Finished Aug 05 05:16:14 PM PDT 24
Peak memory 199896 kb
Host smart-90b3031a-086a-4083-a865-82d8f43943ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638918207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1638918207
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.1211275934
Short name T1090
Test name
Test status
Simulation time 110127452326 ps
CPU time 135.77 seconds
Started Aug 05 05:15:52 PM PDT 24
Finished Aug 05 05:18:08 PM PDT 24
Peak memory 199772 kb
Host smart-3ab22ab2-cebd-4e69-a370-2af5937b2786
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211275934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1211275934
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2091118266
Short name T885
Test name
Test status
Simulation time 78825379185 ps
CPU time 328.6 seconds
Started Aug 05 05:15:44 PM PDT 24
Finished Aug 05 05:21:12 PM PDT 24
Peak memory 199864 kb
Host smart-917c8710-d022-4bb1-9b66-b0e98a502fda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2091118266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2091118266
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3171040461
Short name T337
Test name
Test status
Simulation time 9022834984 ps
CPU time 6.09 seconds
Started Aug 05 05:15:42 PM PDT 24
Finished Aug 05 05:15:48 PM PDT 24
Peak memory 199740 kb
Host smart-ecae3f65-a02d-4535-bf03-8d87f77a0774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171040461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3171040461
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2763196520
Short name T648
Test name
Test status
Simulation time 14955717523 ps
CPU time 16.46 seconds
Started Aug 05 05:15:45 PM PDT 24
Finished Aug 05 05:16:01 PM PDT 24
Peak memory 196208 kb
Host smart-4ddd8b25-cbd8-4352-bb5c-4102a78af926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763196520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2763196520
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2112814880
Short name T524
Test name
Test status
Simulation time 11011447020 ps
CPU time 159.06 seconds
Started Aug 05 05:15:43 PM PDT 24
Finished Aug 05 05:18:22 PM PDT 24
Peak memory 199960 kb
Host smart-6a6d23e8-6cb3-4825-8a07-1c773646781d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112814880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2112814880
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2564275211
Short name T498
Test name
Test status
Simulation time 4671524508 ps
CPU time 4.44 seconds
Started Aug 05 05:15:52 PM PDT 24
Finished Aug 05 05:15:56 PM PDT 24
Peak memory 199088 kb
Host smart-94c76ffe-82fe-4a5e-980b-1a38f0ff36b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2564275211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2564275211
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2265140566
Short name T638
Test name
Test status
Simulation time 19578435523 ps
CPU time 29.81 seconds
Started Aug 05 05:15:51 PM PDT 24
Finished Aug 05 05:16:21 PM PDT 24
Peak memory 199624 kb
Host smart-3c6c5bfb-d683-4204-9bbe-e956ee666460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265140566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2265140566
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3051313549
Short name T1107
Test name
Test status
Simulation time 1752669510 ps
CPU time 1.96 seconds
Started Aug 05 05:15:44 PM PDT 24
Finished Aug 05 05:15:46 PM PDT 24
Peak memory 195668 kb
Host smart-1181fe21-ecd4-4f43-8edc-dc2184f23305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051313549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3051313549
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2236492641
Short name T296
Test name
Test status
Simulation time 982553852 ps
CPU time 1.57 seconds
Started Aug 05 05:15:39 PM PDT 24
Finished Aug 05 05:15:41 PM PDT 24
Peak memory 198264 kb
Host smart-09708343-2c4b-49ec-ba38-99f5c938019f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236492641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2236492641
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.160212803
Short name T1078
Test name
Test status
Simulation time 282714564502 ps
CPU time 914.49 seconds
Started Aug 05 05:15:52 PM PDT 24
Finished Aug 05 05:31:07 PM PDT 24
Peak memory 208172 kb
Host smart-25c6a86a-7586-458c-87f2-3d7350e9076a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160212803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.160212803
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.386829564
Short name T952
Test name
Test status
Simulation time 146951703827 ps
CPU time 637.09 seconds
Started Aug 05 05:15:51 PM PDT 24
Finished Aug 05 05:26:29 PM PDT 24
Peak memory 216348 kb
Host smart-4a8834a5-caec-427e-8e22-9b883d0d7b7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386829564 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.386829564
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1664049374
Short name T470
Test name
Test status
Simulation time 1372471621 ps
CPU time 1.66 seconds
Started Aug 05 05:15:52 PM PDT 24
Finished Aug 05 05:15:53 PM PDT 24
Peak memory 199780 kb
Host smart-50189683-7583-4cc3-8a96-0b709ea74edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664049374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1664049374
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.625901268
Short name T813
Test name
Test status
Simulation time 111668981578 ps
CPU time 133.85 seconds
Started Aug 05 05:15:40 PM PDT 24
Finished Aug 05 05:17:54 PM PDT 24
Peak memory 199836 kb
Host smart-3bc8e8f4-f93a-4e60-a4c2-0790af1cc9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625901268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.625901268
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.606456031
Short name T390
Test name
Test status
Simulation time 14347809 ps
CPU time 0.57 seconds
Started Aug 05 05:15:56 PM PDT 24
Finished Aug 05 05:15:56 PM PDT 24
Peak memory 195356 kb
Host smart-82f597c1-1691-48e7-8afe-d99e3e7b7cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606456031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.606456031
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1423694499
Short name T45
Test name
Test status
Simulation time 175644304566 ps
CPU time 215.99 seconds
Started Aug 05 05:15:46 PM PDT 24
Finished Aug 05 05:19:22 PM PDT 24
Peak memory 199740 kb
Host smart-dcbd3897-2c81-49e6-97ec-f174a6878c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423694499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1423694499
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3270044333
Short name T922
Test name
Test status
Simulation time 63026091055 ps
CPU time 51.94 seconds
Started Aug 05 05:15:44 PM PDT 24
Finished Aug 05 05:16:36 PM PDT 24
Peak memory 199916 kb
Host smart-8c73d9ed-9f7e-40ce-b7c0-76832af54d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270044333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3270044333
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3456370969
Short name T583
Test name
Test status
Simulation time 71782627106 ps
CPU time 33.26 seconds
Started Aug 05 05:15:46 PM PDT 24
Finished Aug 05 05:16:20 PM PDT 24
Peak memory 199752 kb
Host smart-f06c1ee8-c9ef-4e62-9554-45a4c961db33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456370969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3456370969
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3680362864
Short name T986
Test name
Test status
Simulation time 85720972594 ps
CPU time 19.17 seconds
Started Aug 05 05:15:50 PM PDT 24
Finished Aug 05 05:16:10 PM PDT 24
Peak memory 199960 kb
Host smart-2a5660bf-e354-4b9c-a94e-5a38eeb57348
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680362864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3680362864
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.4145126828
Short name T466
Test name
Test status
Simulation time 139995958439 ps
CPU time 413.99 seconds
Started Aug 05 05:15:50 PM PDT 24
Finished Aug 05 05:22:45 PM PDT 24
Peak memory 199972 kb
Host smart-4ca5112e-1fc9-4294-afc0-b23ad2113368
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4145126828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.4145126828
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2383674101
Short name T1168
Test name
Test status
Simulation time 1619852505 ps
CPU time 3.26 seconds
Started Aug 05 05:15:51 PM PDT 24
Finished Aug 05 05:15:55 PM PDT 24
Peak memory 197344 kb
Host smart-d027bb21-3b33-423f-8ecc-b41c28e0d1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383674101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2383674101
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3593386776
Short name T792
Test name
Test status
Simulation time 6672943550 ps
CPU time 6.15 seconds
Started Aug 05 05:15:53 PM PDT 24
Finished Aug 05 05:15:59 PM PDT 24
Peak memory 198416 kb
Host smart-f925d04b-9efb-42f1-a4ea-06abaa2ec341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593386776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3593386776
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3095645711
Short name T539
Test name
Test status
Simulation time 27718568118 ps
CPU time 195.14 seconds
Started Aug 05 05:15:50 PM PDT 24
Finished Aug 05 05:19:06 PM PDT 24
Peak memory 199844 kb
Host smart-268ceedf-ee7a-494a-8568-9c7044bdbf3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3095645711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3095645711
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.60741039
Short name T351
Test name
Test status
Simulation time 1888203770 ps
CPU time 8.88 seconds
Started Aug 05 05:15:51 PM PDT 24
Finished Aug 05 05:16:00 PM PDT 24
Peak memory 197844 kb
Host smart-8da35b84-d6d5-4a36-964d-addd6da40dd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=60741039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.60741039
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1521867541
Short name T387
Test name
Test status
Simulation time 20351922397 ps
CPU time 33.12 seconds
Started Aug 05 05:15:51 PM PDT 24
Finished Aug 05 05:16:24 PM PDT 24
Peak memory 199752 kb
Host smart-7c55a99a-da7f-42b5-a911-af308627c768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521867541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1521867541
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3165360691
Short name T50
Test name
Test status
Simulation time 6416478535 ps
CPU time 2.75 seconds
Started Aug 05 05:15:50 PM PDT 24
Finished Aug 05 05:15:53 PM PDT 24
Peak memory 196828 kb
Host smart-4fb42293-5636-462c-8098-4112a4ce59e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165360691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3165360691
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3837812835
Short name T282
Test name
Test status
Simulation time 291864254 ps
CPU time 1.42 seconds
Started Aug 05 05:15:45 PM PDT 24
Finished Aug 05 05:15:46 PM PDT 24
Peak memory 198096 kb
Host smart-a65fc8fd-91ad-48f8-8451-0d6f9eef9e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837812835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3837812835
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.15129163
Short name T845
Test name
Test status
Simulation time 46766763705 ps
CPU time 268.04 seconds
Started Aug 05 05:15:49 PM PDT 24
Finished Aug 05 05:20:17 PM PDT 24
Peak memory 216360 kb
Host smart-bf7f69cd-484a-45fc-a0a6-1e6775be9b0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15129163 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.15129163
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2517790509
Short name T1136
Test name
Test status
Simulation time 1470064548 ps
CPU time 2.27 seconds
Started Aug 05 05:15:52 PM PDT 24
Finished Aug 05 05:15:54 PM PDT 24
Peak memory 199340 kb
Host smart-017f455f-c2d1-424c-993d-5d6ef1c5433d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517790509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2517790509
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2840707118
Short name T1134
Test name
Test status
Simulation time 27625315251 ps
CPU time 57.74 seconds
Started Aug 05 05:15:48 PM PDT 24
Finished Aug 05 05:16:46 PM PDT 24
Peak memory 199796 kb
Host smart-666118b9-af3f-4139-803a-da9d398dc4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840707118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2840707118
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2152252193
Short name T1021
Test name
Test status
Simulation time 21876061 ps
CPU time 0.56 seconds
Started Aug 05 05:16:08 PM PDT 24
Finished Aug 05 05:16:08 PM PDT 24
Peak memory 194744 kb
Host smart-f0330df7-4ed8-4e24-919e-6bf79c08dc41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152252193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2152252193
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.4244528236
Short name T669
Test name
Test status
Simulation time 113300460797 ps
CPU time 71.34 seconds
Started Aug 05 05:15:55 PM PDT 24
Finished Aug 05 05:17:07 PM PDT 24
Peak memory 199908 kb
Host smart-47eec5b0-c82f-4e08-879f-65525f18b326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244528236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.4244528236
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2620701103
Short name T640
Test name
Test status
Simulation time 45623833008 ps
CPU time 17.05 seconds
Started Aug 05 05:15:57 PM PDT 24
Finished Aug 05 05:16:14 PM PDT 24
Peak memory 199872 kb
Host smart-20983737-8d39-49a5-8b97-ff7b484c2982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620701103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2620701103
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1267374763
Short name T220
Test name
Test status
Simulation time 14519653281 ps
CPU time 13.38 seconds
Started Aug 05 05:15:56 PM PDT 24
Finished Aug 05 05:16:09 PM PDT 24
Peak memory 199876 kb
Host smart-b21b6c45-7f65-4041-aad6-527c94bed690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267374763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1267374763
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2412976838
Short name T435
Test name
Test status
Simulation time 26923203052 ps
CPU time 41.04 seconds
Started Aug 05 05:15:58 PM PDT 24
Finished Aug 05 05:16:39 PM PDT 24
Peak memory 199832 kb
Host smart-f0c981b9-2b51-4cf5-b600-442d257bcc4a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412976838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2412976838
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1131809961
Short name T1001
Test name
Test status
Simulation time 110035487677 ps
CPU time 618.49 seconds
Started Aug 05 05:16:05 PM PDT 24
Finished Aug 05 05:26:24 PM PDT 24
Peak memory 199904 kb
Host smart-cb4e4265-97b0-4b2c-82bb-a978d92da175
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1131809961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1131809961
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3298283064
Short name T941
Test name
Test status
Simulation time 5803937341 ps
CPU time 2.65 seconds
Started Aug 05 05:16:04 PM PDT 24
Finished Aug 05 05:16:07 PM PDT 24
Peak memory 198256 kb
Host smart-96c41c27-96e7-4530-8156-9fd8e3d28849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298283064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3298283064
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1224950508
Short name T474
Test name
Test status
Simulation time 103790626357 ps
CPU time 44.41 seconds
Started Aug 05 05:15:57 PM PDT 24
Finished Aug 05 05:16:42 PM PDT 24
Peak memory 199860 kb
Host smart-9eb23170-4322-4192-9dbc-88f6b86b5455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224950508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1224950508
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2708222849
Short name T983
Test name
Test status
Simulation time 16069890404 ps
CPU time 819.36 seconds
Started Aug 05 05:16:03 PM PDT 24
Finished Aug 05 05:29:42 PM PDT 24
Peak memory 199896 kb
Host smart-ff8bcb17-78e5-4a21-b4ac-acaba2472079
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2708222849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2708222849
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.4172687578
Short name T347
Test name
Test status
Simulation time 3257044577 ps
CPU time 12.87 seconds
Started Aug 05 05:15:55 PM PDT 24
Finished Aug 05 05:16:08 PM PDT 24
Peak memory 198308 kb
Host smart-7938b4b1-f602-4629-8962-80c97a3802a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172687578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.4172687578
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2630013041
Short name T485
Test name
Test status
Simulation time 289037593366 ps
CPU time 411.62 seconds
Started Aug 05 05:15:55 PM PDT 24
Finished Aug 05 05:22:47 PM PDT 24
Peak memory 199888 kb
Host smart-87113dd7-9402-474d-8987-e6e14f0f84ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630013041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2630013041
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3071423918
Short name T512
Test name
Test status
Simulation time 366928058 ps
CPU time 1.27 seconds
Started Aug 05 05:15:55 PM PDT 24
Finished Aug 05 05:15:56 PM PDT 24
Peak memory 195492 kb
Host smart-756427e2-e659-47a7-bc97-db7e7cb50963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071423918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3071423918
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.357910899
Short name T766
Test name
Test status
Simulation time 6301541438 ps
CPU time 20.39 seconds
Started Aug 05 05:15:55 PM PDT 24
Finished Aug 05 05:16:15 PM PDT 24
Peak memory 199864 kb
Host smart-f1f69150-c970-40ee-bef5-2838f5f41561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357910899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.357910899
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3794106528
Short name T1055
Test name
Test status
Simulation time 54113864167 ps
CPU time 80.83 seconds
Started Aug 05 05:16:08 PM PDT 24
Finished Aug 05 05:17:28 PM PDT 24
Peak memory 198876 kb
Host smart-6255ccee-5d26-4a40-84f9-2d9e6851ae73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794106528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3794106528
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1169800236
Short name T1137
Test name
Test status
Simulation time 25948148255 ps
CPU time 685.67 seconds
Started Aug 05 05:16:05 PM PDT 24
Finished Aug 05 05:27:31 PM PDT 24
Peak memory 208228 kb
Host smart-f4a4aebe-8a2b-4749-8bb8-19c97223d0dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169800236 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1169800236
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2870220572
Short name T459
Test name
Test status
Simulation time 700110541 ps
CPU time 1.62 seconds
Started Aug 05 05:17:00 PM PDT 24
Finished Aug 05 05:17:02 PM PDT 24
Peak memory 198712 kb
Host smart-3b8b59a8-beea-4119-a7c2-290a2511c445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870220572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2870220572
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1395842677
Short name T1011
Test name
Test status
Simulation time 66352808922 ps
CPU time 38.36 seconds
Started Aug 05 05:16:00 PM PDT 24
Finished Aug 05 05:16:39 PM PDT 24
Peak memory 199920 kb
Host smart-fc10b837-7cc0-49d7-92b3-e1981d9d0a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395842677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1395842677
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2489329500
Short name T948
Test name
Test status
Simulation time 12276386 ps
CPU time 0.58 seconds
Started Aug 05 05:16:03 PM PDT 24
Finished Aug 05 05:16:04 PM PDT 24
Peak memory 195276 kb
Host smart-4017127b-a352-4af9-a238-25e57416ed4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489329500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2489329500
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.610020407
Short name T301
Test name
Test status
Simulation time 28781310652 ps
CPU time 16.61 seconds
Started Aug 05 05:16:04 PM PDT 24
Finished Aug 05 05:16:20 PM PDT 24
Peak memory 199904 kb
Host smart-fb992c17-9126-4715-b196-0c7f6c34943c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610020407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.610020407
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2192540107
Short name T128
Test name
Test status
Simulation time 20611487866 ps
CPU time 16.47 seconds
Started Aug 05 05:16:05 PM PDT 24
Finished Aug 05 05:16:22 PM PDT 24
Peak memory 198488 kb
Host smart-50a146b1-bb40-45fa-b940-02a2a825549a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192540107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2192540107
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2643398317
Short name T241
Test name
Test status
Simulation time 19127694285 ps
CPU time 15.13 seconds
Started Aug 05 05:16:04 PM PDT 24
Finished Aug 05 05:16:19 PM PDT 24
Peak memory 199000 kb
Host smart-858ba71f-2ed5-4c31-a7de-8e005e82dc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643398317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2643398317
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2260985205
Short name T472
Test name
Test status
Simulation time 7059365363 ps
CPU time 14.72 seconds
Started Aug 05 05:16:06 PM PDT 24
Finished Aug 05 05:16:20 PM PDT 24
Peak memory 199932 kb
Host smart-a1998874-cce8-433f-8fc3-831b55896c2c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260985205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2260985205
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1060215262
Short name T698
Test name
Test status
Simulation time 91286787085 ps
CPU time 179.2 seconds
Started Aug 05 05:16:08 PM PDT 24
Finished Aug 05 05:19:07 PM PDT 24
Peak memory 199836 kb
Host smart-98df7637-21b8-4c42-bc67-bf0441f6aa63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1060215262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1060215262
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3479247980
Short name T818
Test name
Test status
Simulation time 1128104907 ps
CPU time 2.42 seconds
Started Aug 05 05:16:04 PM PDT 24
Finished Aug 05 05:16:07 PM PDT 24
Peak memory 196140 kb
Host smart-e885f0f8-1248-4f21-983a-0892aae55961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479247980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3479247980
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2940594294
Short name T957
Test name
Test status
Simulation time 23014874697 ps
CPU time 42.11 seconds
Started Aug 05 05:16:03 PM PDT 24
Finished Aug 05 05:16:46 PM PDT 24
Peak memory 199116 kb
Host smart-f8d83bfb-cefa-4c00-9a0f-8bed40e5391c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940594294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2940594294
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2613776627
Short name T1166
Test name
Test status
Simulation time 18429647300 ps
CPU time 787.95 seconds
Started Aug 05 05:16:04 PM PDT 24
Finished Aug 05 05:29:12 PM PDT 24
Peak memory 199940 kb
Host smart-654e0df2-722c-41b3-a42f-5af6584a2493
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2613776627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2613776627
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1332980519
Short name T558
Test name
Test status
Simulation time 5172937696 ps
CPU time 13.13 seconds
Started Aug 05 05:16:05 PM PDT 24
Finished Aug 05 05:16:19 PM PDT 24
Peak memory 199356 kb
Host smart-9a35e562-25de-4433-97e0-df958412bf01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1332980519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1332980519
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3589193246
Short name T2
Test name
Test status
Simulation time 41452536066 ps
CPU time 30.91 seconds
Started Aug 05 05:16:04 PM PDT 24
Finished Aug 05 05:16:36 PM PDT 24
Peak memory 199168 kb
Host smart-348a00e8-014e-4b3a-9c19-2d3ff2eb8d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589193246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3589193246
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.3281950066
Short name T293
Test name
Test status
Simulation time 4280055543 ps
CPU time 4.12 seconds
Started Aug 05 05:16:04 PM PDT 24
Finished Aug 05 05:16:09 PM PDT 24
Peak memory 196072 kb
Host smart-c49b69b1-f4a7-41d7-824f-da1a0166f8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281950066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3281950066
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3790654416
Short name T573
Test name
Test status
Simulation time 6062302580 ps
CPU time 7.84 seconds
Started Aug 05 05:16:03 PM PDT 24
Finished Aug 05 05:16:11 PM PDT 24
Peak memory 199848 kb
Host smart-c31be35b-45a1-48cb-8ab7-a6afbfeb7f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790654416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3790654416
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.648081179
Short name T121
Test name
Test status
Simulation time 49055144294 ps
CPU time 216.73 seconds
Started Aug 05 05:16:05 PM PDT 24
Finished Aug 05 05:19:41 PM PDT 24
Peak memory 215448 kb
Host smart-27859256-90ef-4e35-96e9-c4791bb71e4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648081179 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.648081179
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.612133761
Short name T686
Test name
Test status
Simulation time 984277294 ps
CPU time 1.64 seconds
Started Aug 05 05:16:04 PM PDT 24
Finished Aug 05 05:16:05 PM PDT 24
Peak memory 198276 kb
Host smart-dcf5ccfa-ef97-4b4a-b900-0e28f42d135c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612133761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.612133761
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3939138966
Short name T621
Test name
Test status
Simulation time 102999379155 ps
CPU time 75.76 seconds
Started Aug 05 05:16:03 PM PDT 24
Finished Aug 05 05:17:19 PM PDT 24
Peak memory 199988 kb
Host smart-e8fe5efb-71fb-4bd7-8393-9301db56821e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939138966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3939138966
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1745040193
Short name T927
Test name
Test status
Simulation time 14890958 ps
CPU time 0.61 seconds
Started Aug 05 05:16:16 PM PDT 24
Finished Aug 05 05:16:17 PM PDT 24
Peak memory 195336 kb
Host smart-1a7cb540-5bc6-40e0-aff5-7611ecb057ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745040193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1745040193
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.2275257421
Short name T125
Test name
Test status
Simulation time 70995558597 ps
CPU time 21.93 seconds
Started Aug 05 05:16:04 PM PDT 24
Finished Aug 05 05:16:26 PM PDT 24
Peak memory 199896 kb
Host smart-47094872-7613-4cbb-9514-c681e71bd19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275257421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2275257421
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3983728527
Short name T503
Test name
Test status
Simulation time 69597968205 ps
CPU time 26.15 seconds
Started Aug 05 05:16:03 PM PDT 24
Finished Aug 05 05:16:30 PM PDT 24
Peak memory 199896 kb
Host smart-273b01c7-9885-4622-8ca8-d6654c8e0454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983728527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3983728527
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2585162593
Short name T329
Test name
Test status
Simulation time 43485590755 ps
CPU time 34.95 seconds
Started Aug 05 05:16:05 PM PDT 24
Finished Aug 05 05:16:40 PM PDT 24
Peak memory 199848 kb
Host smart-d6fdcff4-8e8b-42c6-b9ec-61bb2e44ed1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585162593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2585162593
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1146472935
Short name T773
Test name
Test status
Simulation time 20555504121 ps
CPU time 31.39 seconds
Started Aug 05 05:16:14 PM PDT 24
Finished Aug 05 05:16:45 PM PDT 24
Peak memory 199192 kb
Host smart-b51465c7-e11a-4172-b921-776ab093e056
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146472935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1146472935
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2908946390
Short name T1009
Test name
Test status
Simulation time 175517291724 ps
CPU time 590.33 seconds
Started Aug 05 05:16:15 PM PDT 24
Finished Aug 05 05:26:05 PM PDT 24
Peak memory 199940 kb
Host smart-4737d659-0eee-40de-8db3-a98261f39475
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2908946390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2908946390
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3002538101
Short name T356
Test name
Test status
Simulation time 3597081839 ps
CPU time 1.76 seconds
Started Aug 05 05:16:15 PM PDT 24
Finished Aug 05 05:16:17 PM PDT 24
Peak memory 198640 kb
Host smart-384b33b2-02eb-415e-a6a2-9c3972621e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002538101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3002538101
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.909907212
Short name T790
Test name
Test status
Simulation time 44312453795 ps
CPU time 71.96 seconds
Started Aug 05 05:16:18 PM PDT 24
Finished Aug 05 05:17:30 PM PDT 24
Peak memory 198472 kb
Host smart-4c9fd790-948f-4f4f-84dc-2983c8b869ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909907212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.909907212
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1381994169
Short name T657
Test name
Test status
Simulation time 12012113227 ps
CPU time 342.25 seconds
Started Aug 05 05:16:17 PM PDT 24
Finished Aug 05 05:21:59 PM PDT 24
Peak memory 199920 kb
Host smart-d6da9b43-c404-4b10-b94b-d9cbd34b50de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1381994169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1381994169
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2556502460
Short name T1169
Test name
Test status
Simulation time 1952185681 ps
CPU time 1.81 seconds
Started Aug 05 05:16:14 PM PDT 24
Finished Aug 05 05:16:16 PM PDT 24
Peak memory 198052 kb
Host smart-bc035d2d-000f-4f0c-aff6-1e8978f2f0c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2556502460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2556502460
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1088809952
Short name T623
Test name
Test status
Simulation time 38260200501 ps
CPU time 55.26 seconds
Started Aug 05 05:16:14 PM PDT 24
Finished Aug 05 05:17:09 PM PDT 24
Peak memory 199904 kb
Host smart-3cab3df1-12ee-4797-bc33-167f4595708d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088809952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1088809952
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3318457053
Short name T544
Test name
Test status
Simulation time 3590119384 ps
CPU time 1.83 seconds
Started Aug 05 05:16:17 PM PDT 24
Finished Aug 05 05:16:19 PM PDT 24
Peak memory 196492 kb
Host smart-dc23c239-43d1-4e58-9711-946e171effb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318457053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3318457053
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3677906568
Short name T974
Test name
Test status
Simulation time 464457103 ps
CPU time 1.88 seconds
Started Aug 05 05:16:07 PM PDT 24
Finished Aug 05 05:16:09 PM PDT 24
Peak memory 198280 kb
Host smart-0dfbda6f-0706-46f6-8916-9f13903d7a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677906568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3677906568
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1849313199
Short name T683
Test name
Test status
Simulation time 128063270452 ps
CPU time 118.89 seconds
Started Aug 05 05:16:13 PM PDT 24
Finished Aug 05 05:18:12 PM PDT 24
Peak memory 199944 kb
Host smart-6dda3b9e-1d51-4943-a198-2cc226148bfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849313199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1849313199
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2609921828
Short name T918
Test name
Test status
Simulation time 31354067525 ps
CPU time 224.99 seconds
Started Aug 05 05:16:14 PM PDT 24
Finished Aug 05 05:20:00 PM PDT 24
Peak memory 215652 kb
Host smart-089f6f32-3cef-4243-a370-38f320b2cfd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609921828 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2609921828
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2029053610
Short name T972
Test name
Test status
Simulation time 7868010538 ps
CPU time 8.69 seconds
Started Aug 05 05:16:15 PM PDT 24
Finished Aug 05 05:16:24 PM PDT 24
Peak memory 199436 kb
Host smart-122b6137-d4e8-4cb5-9638-c0a1317f56d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029053610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2029053610
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1100066590
Short name T369
Test name
Test status
Simulation time 97872561838 ps
CPU time 18.87 seconds
Started Aug 05 05:16:08 PM PDT 24
Finished Aug 05 05:16:27 PM PDT 24
Peak memory 199864 kb
Host smart-ca0030fa-2e00-48af-ac91-5ef9cf97069a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100066590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1100066590
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1349638263
Short name T643
Test name
Test status
Simulation time 44746573 ps
CPU time 0.53 seconds
Started Aug 05 05:16:19 PM PDT 24
Finished Aug 05 05:16:20 PM PDT 24
Peak memory 195320 kb
Host smart-b289fdd8-ebdd-43af-8971-e8e37ad3eb4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349638263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1349638263
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.161089767
Short name T803
Test name
Test status
Simulation time 8635594691 ps
CPU time 12.61 seconds
Started Aug 05 05:16:14 PM PDT 24
Finished Aug 05 05:16:27 PM PDT 24
Peak memory 199628 kb
Host smart-2a66cddd-2394-4497-aeb9-24d20f84947d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161089767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.161089767
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.787435166
Short name T260
Test name
Test status
Simulation time 12700194917 ps
CPU time 19.98 seconds
Started Aug 05 05:16:16 PM PDT 24
Finished Aug 05 05:16:36 PM PDT 24
Peak memory 199928 kb
Host smart-4746b375-bc68-4d5f-8861-fc99178e8700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787435166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.787435166
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1040837401
Short name T325
Test name
Test status
Simulation time 291285038051 ps
CPU time 41.96 seconds
Started Aug 05 05:16:15 PM PDT 24
Finished Aug 05 05:16:57 PM PDT 24
Peak memory 199840 kb
Host smart-0bfc8f1a-5f23-4b2f-a22f-68ae5c8997a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040837401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1040837401
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1614061107
Short name T961
Test name
Test status
Simulation time 24706463546 ps
CPU time 36.21 seconds
Started Aug 05 05:16:14 PM PDT 24
Finished Aug 05 05:16:51 PM PDT 24
Peak memory 199360 kb
Host smart-0ea79169-cd0e-46a8-9c60-ab7e3f6ff705
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614061107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1614061107
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3861831698
Short name T590
Test name
Test status
Simulation time 33615950284 ps
CPU time 106.91 seconds
Started Aug 05 05:16:12 PM PDT 24
Finished Aug 05 05:17:59 PM PDT 24
Peak memory 199972 kb
Host smart-9b17619d-ef8b-4962-8479-0ded6b96ce3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3861831698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3861831698
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.419243181
Short name T9
Test name
Test status
Simulation time 6355133674 ps
CPU time 5.99 seconds
Started Aug 05 05:16:16 PM PDT 24
Finished Aug 05 05:16:22 PM PDT 24
Peak memory 199580 kb
Host smart-0add7360-1af8-4603-b6eb-04955a974b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419243181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.419243181
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1382699211
Short name T557
Test name
Test status
Simulation time 79169619779 ps
CPU time 32.79 seconds
Started Aug 05 05:16:13 PM PDT 24
Finished Aug 05 05:16:46 PM PDT 24
Peak memory 199184 kb
Host smart-020cb23c-6bb3-4b26-a547-80b8a80ac7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382699211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1382699211
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2029929475
Short name T654
Test name
Test status
Simulation time 27169413909 ps
CPU time 508.85 seconds
Started Aug 05 05:16:17 PM PDT 24
Finished Aug 05 05:24:46 PM PDT 24
Peak memory 199884 kb
Host smart-b342084b-e3a3-4847-ae63-35893c830c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2029929475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2029929475
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.8583610
Short name T41
Test name
Test status
Simulation time 4494364074 ps
CPU time 10.16 seconds
Started Aug 05 05:16:17 PM PDT 24
Finished Aug 05 05:16:27 PM PDT 24
Peak memory 198772 kb
Host smart-c7e8902e-0faf-4138-8733-9a4fe67ef586
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=8583610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.8583610
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3244784781
Short name T442
Test name
Test status
Simulation time 83299366583 ps
CPU time 13.26 seconds
Started Aug 05 05:16:16 PM PDT 24
Finished Aug 05 05:16:30 PM PDT 24
Peak memory 199712 kb
Host smart-8437215a-2d5e-4b69-bf8e-f0668254a3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244784781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3244784781
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3354900306
Short name T555
Test name
Test status
Simulation time 1855154169 ps
CPU time 3.57 seconds
Started Aug 05 05:16:14 PM PDT 24
Finished Aug 05 05:16:17 PM PDT 24
Peak memory 195552 kb
Host smart-0ee91be1-b8f9-441a-8336-ab1ddc977178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354900306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3354900306
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2603445079
Short name T405
Test name
Test status
Simulation time 317797294 ps
CPU time 1.3 seconds
Started Aug 05 05:16:16 PM PDT 24
Finished Aug 05 05:16:18 PM PDT 24
Peak memory 198692 kb
Host smart-291e317e-e870-47e7-8b0e-593d3dd2116b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603445079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2603445079
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2561129383
Short name T533
Test name
Test status
Simulation time 343124132059 ps
CPU time 54.22 seconds
Started Aug 05 05:16:21 PM PDT 24
Finished Aug 05 05:17:15 PM PDT 24
Peak memory 215660 kb
Host smart-a8fdabb5-17d4-4ac5-9eea-4157a47ad438
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561129383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2561129383
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3852281004
Short name T393
Test name
Test status
Simulation time 794111481 ps
CPU time 1.58 seconds
Started Aug 05 05:16:13 PM PDT 24
Finished Aug 05 05:16:15 PM PDT 24
Peak memory 198596 kb
Host smart-f75e696b-7649-4a1d-b904-98afca79cfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852281004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3852281004
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1406443895
Short name T577
Test name
Test status
Simulation time 11296995606 ps
CPU time 4.83 seconds
Started Aug 05 05:16:15 PM PDT 24
Finished Aug 05 05:16:20 PM PDT 24
Peak memory 196472 kb
Host smart-14e4763b-6ded-443f-a785-fae75aed6257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406443895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1406443895
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2179126223
Short name T516
Test name
Test status
Simulation time 35135235 ps
CPU time 0.57 seconds
Started Aug 05 05:16:30 PM PDT 24
Finished Aug 05 05:16:31 PM PDT 24
Peak memory 195288 kb
Host smart-bfca5c3a-ae25-494e-b855-f47ac1f69c1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179126223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2179126223
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2342999935
Short name T1127
Test name
Test status
Simulation time 14610348906 ps
CPU time 21.3 seconds
Started Aug 05 05:16:23 PM PDT 24
Finished Aug 05 05:16:44 PM PDT 24
Peak memory 199780 kb
Host smart-8bd4e28e-dc7f-4e60-9c65-fe40b84a3be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342999935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2342999935
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2511839279
Short name T912
Test name
Test status
Simulation time 15633299847 ps
CPU time 37.57 seconds
Started Aug 05 05:16:18 PM PDT 24
Finished Aug 05 05:16:55 PM PDT 24
Peak memory 199968 kb
Host smart-9825a3ae-db52-49d7-9102-a1e67802c98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511839279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2511839279
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.4038468569
Short name T229
Test name
Test status
Simulation time 128095749571 ps
CPU time 187.59 seconds
Started Aug 05 05:16:23 PM PDT 24
Finished Aug 05 05:19:30 PM PDT 24
Peak memory 199972 kb
Host smart-47dc78ce-78ce-4044-b198-e0078d23334d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038468569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.4038468569
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3845157602
Short name T316
Test name
Test status
Simulation time 8738651125 ps
CPU time 12.95 seconds
Started Aug 05 05:16:19 PM PDT 24
Finished Aug 05 05:16:32 PM PDT 24
Peak memory 196860 kb
Host smart-583c64a2-ee3b-45bc-8442-c732fc459990
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845157602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3845157602
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.4107324508
Short name T394
Test name
Test status
Simulation time 62253663790 ps
CPU time 348.54 seconds
Started Aug 05 05:16:19 PM PDT 24
Finished Aug 05 05:22:08 PM PDT 24
Peak memory 199964 kb
Host smart-65c63463-8921-459c-89d6-4888ffbfd7bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4107324508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.4107324508
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1923912014
Short name T676
Test name
Test status
Simulation time 1325990359 ps
CPU time 4.04 seconds
Started Aug 05 05:16:18 PM PDT 24
Finished Aug 05 05:16:22 PM PDT 24
Peak memory 198484 kb
Host smart-90595ea4-97e7-4438-8bee-652de3e3d9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923912014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1923912014
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1983801597
Short name T365
Test name
Test status
Simulation time 185799495668 ps
CPU time 99.83 seconds
Started Aug 05 05:16:17 PM PDT 24
Finished Aug 05 05:17:57 PM PDT 24
Peak memory 207900 kb
Host smart-24c72e62-110c-4a23-a7d5-06c0c4db5243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983801597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1983801597
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.138447771
Short name T391
Test name
Test status
Simulation time 23993593526 ps
CPU time 1233.01 seconds
Started Aug 05 05:16:21 PM PDT 24
Finished Aug 05 05:36:54 PM PDT 24
Peak memory 199872 kb
Host smart-57164d6b-b5fa-4cd3-94f6-e0c783ed39d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=138447771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.138447771
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1806355843
Short name T1017
Test name
Test status
Simulation time 4217158642 ps
CPU time 35.73 seconds
Started Aug 05 05:16:17 PM PDT 24
Finished Aug 05 05:16:53 PM PDT 24
Peak memory 198128 kb
Host smart-4ced5b3b-e439-48d7-bcdb-e55fdcee7851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1806355843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1806355843
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2760770365
Short name T373
Test name
Test status
Simulation time 20100109782 ps
CPU time 9.21 seconds
Started Aug 05 05:16:20 PM PDT 24
Finished Aug 05 05:16:29 PM PDT 24
Peak memory 199864 kb
Host smart-b19283f2-e69f-40a9-b5e6-95b23fd255fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760770365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2760770365
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3659079446
Short name T518
Test name
Test status
Simulation time 3677199614 ps
CPU time 2.23 seconds
Started Aug 05 05:16:20 PM PDT 24
Finished Aug 05 05:16:22 PM PDT 24
Peak memory 196484 kb
Host smart-77ff7503-4e67-48da-b028-5d33ac2e6255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659079446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3659079446
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.672652352
Short name T300
Test name
Test status
Simulation time 695290955 ps
CPU time 3.59 seconds
Started Aug 05 05:16:19 PM PDT 24
Finished Aug 05 05:16:22 PM PDT 24
Peak memory 199836 kb
Host smart-f318888c-530e-493f-aef9-8ff6bee141c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672652352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.672652352
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.1466680076
Short name T690
Test name
Test status
Simulation time 160766104110 ps
CPU time 205.55 seconds
Started Aug 05 05:16:23 PM PDT 24
Finished Aug 05 05:19:49 PM PDT 24
Peak memory 199908 kb
Host smart-8f0ef7ea-fb28-46c3-8a38-27d7a12f133f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466680076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1466680076
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2013103159
Short name T874
Test name
Test status
Simulation time 68667581061 ps
CPU time 555.43 seconds
Started Aug 05 05:16:17 PM PDT 24
Finished Aug 05 05:25:32 PM PDT 24
Peak memory 216464 kb
Host smart-160df925-f2e3-453e-852d-45be4d99c52e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013103159 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2013103159
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1937851802
Short name T958
Test name
Test status
Simulation time 6230869038 ps
CPU time 16.52 seconds
Started Aug 05 05:16:17 PM PDT 24
Finished Aug 05 05:16:33 PM PDT 24
Peak memory 199216 kb
Host smart-7490bd90-83dd-43a8-8a33-28490a31d686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937851802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1937851802
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.4049326122
Short name T1108
Test name
Test status
Simulation time 50915113122 ps
CPU time 46.05 seconds
Started Aug 05 05:16:23 PM PDT 24
Finished Aug 05 05:17:09 PM PDT 24
Peak memory 199992 kb
Host smart-c1c1c8b3-4747-4c5a-a10d-148f5d96e335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049326122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.4049326122
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.2802256559
Short name T810
Test name
Test status
Simulation time 15738807 ps
CPU time 0.53 seconds
Started Aug 05 05:16:34 PM PDT 24
Finished Aug 05 05:16:35 PM PDT 24
Peak memory 194188 kb
Host smart-6376d4d3-dcdb-43e5-9c76-120afac89e20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802256559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2802256559
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3333129860
Short name T955
Test name
Test status
Simulation time 35271218675 ps
CPU time 51.93 seconds
Started Aug 05 05:16:27 PM PDT 24
Finished Aug 05 05:17:19 PM PDT 24
Peak memory 199940 kb
Host smart-b54d30d2-32e6-44a3-b0c9-9ba372ea51db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333129860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3333129860
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1134497595
Short name T614
Test name
Test status
Simulation time 130857591873 ps
CPU time 75.97 seconds
Started Aug 05 05:16:25 PM PDT 24
Finished Aug 05 05:17:41 PM PDT 24
Peak memory 199952 kb
Host smart-91ad6cfe-b445-47de-970d-771b94346a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134497595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1134497595
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.363699602
Short name T1176
Test name
Test status
Simulation time 55269227618 ps
CPU time 93.87 seconds
Started Aug 05 05:16:24 PM PDT 24
Finished Aug 05 05:17:58 PM PDT 24
Peak memory 199912 kb
Host smart-fd8536ab-f704-4fe7-a9fa-008ecb79249e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363699602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.363699602
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1299082243
Short name T464
Test name
Test status
Simulation time 8338243031 ps
CPU time 16.55 seconds
Started Aug 05 05:16:24 PM PDT 24
Finished Aug 05 05:16:40 PM PDT 24
Peak memory 199876 kb
Host smart-c28ff36f-a397-4a58-a468-ce8c0d013e08
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299082243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1299082243
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2299651194
Short name T47
Test name
Test status
Simulation time 68740249913 ps
CPU time 418.27 seconds
Started Aug 05 05:16:33 PM PDT 24
Finished Aug 05 05:23:31 PM PDT 24
Peak memory 199924 kb
Host smart-cdb10462-5643-4f06-9e4a-daadce0442c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2299651194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2299651194
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1547175176
Short name T755
Test name
Test status
Simulation time 6231983834 ps
CPU time 5.87 seconds
Started Aug 05 05:16:24 PM PDT 24
Finished Aug 05 05:16:30 PM PDT 24
Peak memory 198560 kb
Host smart-8144fc9e-fc6c-40ae-a617-02aaad7a298c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547175176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1547175176
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.806057457
Short name T513
Test name
Test status
Simulation time 104001493204 ps
CPU time 186.52 seconds
Started Aug 05 05:16:24 PM PDT 24
Finished Aug 05 05:19:31 PM PDT 24
Peak memory 200104 kb
Host smart-4e347f86-e4b0-4cdf-bee7-dd9c45766229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806057457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.806057457
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.4164978010
Short name T630
Test name
Test status
Simulation time 11199671016 ps
CPU time 659.63 seconds
Started Aug 05 05:16:25 PM PDT 24
Finished Aug 05 05:27:25 PM PDT 24
Peak memory 199876 kb
Host smart-5a016b92-640a-48ee-96c1-0eb84a86c243
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164978010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.4164978010
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3380113317
Short name T975
Test name
Test status
Simulation time 6231274835 ps
CPU time 59.91 seconds
Started Aug 05 05:16:33 PM PDT 24
Finished Aug 05 05:17:33 PM PDT 24
Peak memory 198060 kb
Host smart-ecd31909-edde-425c-acad-c651dba002df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3380113317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3380113317
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3487562339
Short name T936
Test name
Test status
Simulation time 234912866599 ps
CPU time 118.07 seconds
Started Aug 05 05:16:29 PM PDT 24
Finished Aug 05 05:18:27 PM PDT 24
Peak memory 199852 kb
Host smart-8e18e94b-02c0-4fb7-90d3-360e76c8587b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487562339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3487562339
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2281960261
Short name T277
Test name
Test status
Simulation time 4133954661 ps
CPU time 2.52 seconds
Started Aug 05 05:16:28 PM PDT 24
Finished Aug 05 05:16:31 PM PDT 24
Peak memory 196064 kb
Host smart-f0a7c310-85c6-43c8-b50d-065206ab8025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281960261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2281960261
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3858447950
Short name T398
Test name
Test status
Simulation time 469692893 ps
CPU time 1.67 seconds
Started Aug 05 05:16:27 PM PDT 24
Finished Aug 05 05:16:28 PM PDT 24
Peak memory 198140 kb
Host smart-d4b0922c-6aa5-459c-8b77-5eb11d2a2106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858447950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3858447950
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1818862923
Short name T173
Test name
Test status
Simulation time 369308694595 ps
CPU time 556.2 seconds
Started Aug 05 05:16:22 PM PDT 24
Finished Aug 05 05:25:39 PM PDT 24
Peak memory 216412 kb
Host smart-42626108-25e4-4843-a0ec-4549d0bb56ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818862923 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1818862923
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3604513143
Short name T545
Test name
Test status
Simulation time 6686787540 ps
CPU time 9.97 seconds
Started Aug 05 05:16:24 PM PDT 24
Finished Aug 05 05:16:34 PM PDT 24
Peak memory 199600 kb
Host smart-6b1c42bd-cf31-48e1-aa93-1234019c3b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604513143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3604513143
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1663750683
Short name T465
Test name
Test status
Simulation time 99708801213 ps
CPU time 88.81 seconds
Started Aug 05 05:16:25 PM PDT 24
Finished Aug 05 05:17:54 PM PDT 24
Peak memory 199944 kb
Host smart-63c0caf6-f1cb-4dc0-af63-35103d5e1c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663750683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1663750683
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3587213938
Short name T967
Test name
Test status
Simulation time 37995048 ps
CPU time 0.58 seconds
Started Aug 05 05:16:37 PM PDT 24
Finished Aug 05 05:16:38 PM PDT 24
Peak memory 195348 kb
Host smart-3953ae5b-83a9-4298-bd91-d9ccac0dee8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587213938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3587213938
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2831292494
Short name T1063
Test name
Test status
Simulation time 36406407001 ps
CPU time 69.12 seconds
Started Aug 05 05:16:33 PM PDT 24
Finished Aug 05 05:17:42 PM PDT 24
Peak memory 199880 kb
Host smart-23f1b476-3bbb-4aca-add1-d31707ee9de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831292494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2831292494
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.469763154
Short name T392
Test name
Test status
Simulation time 83334120451 ps
CPU time 130.17 seconds
Started Aug 05 05:16:34 PM PDT 24
Finished Aug 05 05:18:44 PM PDT 24
Peak memory 199924 kb
Host smart-52d37ad9-c547-4171-b201-7782ff28b7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469763154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.469763154
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1847492829
Short name T145
Test name
Test status
Simulation time 11358234080 ps
CPU time 19.68 seconds
Started Aug 05 05:16:33 PM PDT 24
Finished Aug 05 05:16:53 PM PDT 24
Peak memory 199972 kb
Host smart-3a16226b-3a5e-428f-b385-1c2a144b0fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847492829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1847492829
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2572637610
Short name T411
Test name
Test status
Simulation time 20588405122 ps
CPU time 9.24 seconds
Started Aug 05 05:16:32 PM PDT 24
Finished Aug 05 05:16:41 PM PDT 24
Peak memory 198640 kb
Host smart-3719d483-2959-4e00-8011-c9aa2008f167
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572637610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2572637610
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1725999678
Short name T584
Test name
Test status
Simulation time 192542301644 ps
CPU time 1080.73 seconds
Started Aug 05 05:16:37 PM PDT 24
Finished Aug 05 05:34:38 PM PDT 24
Peak memory 199972 kb
Host smart-fb56532b-b3fc-42a6-9455-65a117f796cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1725999678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1725999678
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1226558013
Short name T593
Test name
Test status
Simulation time 773822909 ps
CPU time 1.64 seconds
Started Aug 05 05:16:33 PM PDT 24
Finished Aug 05 05:16:34 PM PDT 24
Peak memory 195420 kb
Host smart-328c34be-8604-4971-a5d1-f588c5cdfc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226558013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1226558013
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.4113007028
Short name T352
Test name
Test status
Simulation time 12052957463 ps
CPU time 19.95 seconds
Started Aug 05 05:16:33 PM PDT 24
Finished Aug 05 05:16:53 PM PDT 24
Peak memory 198380 kb
Host smart-063ce3e5-b5f6-47b9-bdc6-d8aeabe2c477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113007028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.4113007028
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1110430394
Short name T514
Test name
Test status
Simulation time 20890371813 ps
CPU time 268.41 seconds
Started Aug 05 05:16:30 PM PDT 24
Finished Aug 05 05:20:58 PM PDT 24
Peak memory 199916 kb
Host smart-895973f1-628c-462b-92d2-22d6225c675b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1110430394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1110430394
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1848124167
Short name T364
Test name
Test status
Simulation time 2343721526 ps
CPU time 1.43 seconds
Started Aug 05 05:16:34 PM PDT 24
Finished Aug 05 05:16:36 PM PDT 24
Peak memory 197812 kb
Host smart-56a8beec-36c4-41bc-a20c-e4f057964d75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1848124167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1848124167
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2484583194
Short name T152
Test name
Test status
Simulation time 112703247354 ps
CPU time 30.51 seconds
Started Aug 05 05:16:34 PM PDT 24
Finished Aug 05 05:17:05 PM PDT 24
Peak memory 199860 kb
Host smart-b2ab3bc7-9733-431d-9255-590561bc2c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484583194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2484583194
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1796780122
Short name T434
Test name
Test status
Simulation time 79596454942 ps
CPU time 31.73 seconds
Started Aug 05 05:16:34 PM PDT 24
Finished Aug 05 05:17:06 PM PDT 24
Peak memory 196236 kb
Host smart-1f6d31c3-aec9-4107-ac78-1e2d4dff4198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796780122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1796780122
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3737352085
Short name T368
Test name
Test status
Simulation time 6073955303 ps
CPU time 11.46 seconds
Started Aug 05 05:16:31 PM PDT 24
Finished Aug 05 05:16:42 PM PDT 24
Peak memory 199488 kb
Host smart-0ef0b0bb-b3d9-46f5-823a-977208e04987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737352085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3737352085
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.731278947
Short name T819
Test name
Test status
Simulation time 209966157323 ps
CPU time 79.45 seconds
Started Aug 05 05:16:40 PM PDT 24
Finished Aug 05 05:18:00 PM PDT 24
Peak memory 199948 kb
Host smart-f2afd41b-5c09-419d-9af8-d43ca5348ade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731278947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.731278947
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3225708010
Short name T65
Test name
Test status
Simulation time 108860789316 ps
CPU time 634.41 seconds
Started Aug 05 05:16:39 PM PDT 24
Finished Aug 05 05:27:14 PM PDT 24
Peak memory 216352 kb
Host smart-42c232df-6b26-437e-aade-bc3bbd40e526
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225708010 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3225708010
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1320650275
Short name T499
Test name
Test status
Simulation time 829867749 ps
CPU time 4.01 seconds
Started Aug 05 05:16:31 PM PDT 24
Finished Aug 05 05:16:35 PM PDT 24
Peak memory 198956 kb
Host smart-cc26caba-a7e7-49e0-be3c-16e186db90b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320650275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1320650275
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.52337182
Short name T600
Test name
Test status
Simulation time 29936665735 ps
CPU time 54.04 seconds
Started Aug 05 05:16:34 PM PDT 24
Finished Aug 05 05:17:29 PM PDT 24
Peak memory 199984 kb
Host smart-551aa982-4580-4d20-8e74-c2c93681669b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52337182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.52337182
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1776109869
Short name T22
Test name
Test status
Simulation time 47884729 ps
CPU time 0.59 seconds
Started Aug 05 05:16:42 PM PDT 24
Finished Aug 05 05:16:42 PM PDT 24
Peak memory 195288 kb
Host smart-693e77d2-0025-42ab-812a-753bfc04e4ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776109869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1776109869
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.260533109
Short name T162
Test name
Test status
Simulation time 45334430079 ps
CPU time 37.46 seconds
Started Aug 05 05:16:38 PM PDT 24
Finished Aug 05 05:17:16 PM PDT 24
Peak memory 199988 kb
Host smart-e9e0d1e8-d055-4404-94c5-f719f5dd9f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260533109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.260533109
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1718347856
Short name T890
Test name
Test status
Simulation time 262696428245 ps
CPU time 103.67 seconds
Started Aug 05 05:16:38 PM PDT 24
Finished Aug 05 05:18:22 PM PDT 24
Peak memory 199976 kb
Host smart-fc915ffe-7e95-45ee-9461-e2ad947bf132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718347856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1718347856
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1089411988
Short name T889
Test name
Test status
Simulation time 19043649259 ps
CPU time 16.78 seconds
Started Aug 05 05:16:38 PM PDT 24
Finished Aug 05 05:16:55 PM PDT 24
Peak memory 199848 kb
Host smart-cd263179-a023-446d-b35f-902ef943a1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089411988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1089411988
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1466229716
Short name T415
Test name
Test status
Simulation time 9505442282 ps
CPU time 5.01 seconds
Started Aug 05 05:16:38 PM PDT 24
Finished Aug 05 05:16:43 PM PDT 24
Peak memory 199936 kb
Host smart-05b1050e-5ee6-4712-8212-7cdf0194b7dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466229716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1466229716
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1853690682
Short name T714
Test name
Test status
Simulation time 94079704301 ps
CPU time 423.54 seconds
Started Aug 05 05:16:44 PM PDT 24
Finished Aug 05 05:23:47 PM PDT 24
Peak memory 199896 kb
Host smart-6e6b88c9-6505-4aec-a1a9-c282bc15806c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853690682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1853690682
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3302992257
Short name T360
Test name
Test status
Simulation time 4080547276 ps
CPU time 6.93 seconds
Started Aug 05 05:16:51 PM PDT 24
Finished Aug 05 05:16:58 PM PDT 24
Peak memory 199948 kb
Host smart-89981422-0643-4fe5-8d61-6da018e593b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302992257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3302992257
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.544923474
Short name T942
Test name
Test status
Simulation time 105250280681 ps
CPU time 45.96 seconds
Started Aug 05 05:16:35 PM PDT 24
Finished Aug 05 05:17:21 PM PDT 24
Peak memory 199324 kb
Host smart-f4192830-2074-43eb-9b03-6cba82ce4d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544923474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.544923474
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2657906165
Short name T743
Test name
Test status
Simulation time 11233488370 ps
CPU time 306.08 seconds
Started Aug 05 05:16:42 PM PDT 24
Finished Aug 05 05:21:48 PM PDT 24
Peak memory 199976 kb
Host smart-0a4384d3-ba6e-44ea-a7f1-7b87ca060f89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2657906165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2657906165
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3037639355
Short name T1033
Test name
Test status
Simulation time 1168265376 ps
CPU time 2.58 seconds
Started Aug 05 05:16:39 PM PDT 24
Finished Aug 05 05:16:42 PM PDT 24
Peak memory 196812 kb
Host smart-baf156c7-2e86-4362-8760-c4dae1ad65a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3037639355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3037639355
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1679638514
Short name T717
Test name
Test status
Simulation time 288722023811 ps
CPU time 92.07 seconds
Started Aug 05 05:16:39 PM PDT 24
Finished Aug 05 05:18:11 PM PDT 24
Peak memory 199896 kb
Host smart-1536cb3c-698f-4ce4-a9d1-773a301f7714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679638514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1679638514
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1057231303
Short name T448
Test name
Test status
Simulation time 2353893002 ps
CPU time 1.56 seconds
Started Aug 05 05:16:36 PM PDT 24
Finished Aug 05 05:16:38 PM PDT 24
Peak memory 195644 kb
Host smart-a91a2eae-f2fc-478a-88a4-14943a57a555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057231303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1057231303
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3055272007
Short name T350
Test name
Test status
Simulation time 467872289 ps
CPU time 2.21 seconds
Started Aug 05 05:16:38 PM PDT 24
Finished Aug 05 05:16:40 PM PDT 24
Peak memory 199644 kb
Host smart-ee862a15-18af-42e9-ae9c-852a2ba68de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055272007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3055272007
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.4222398314
Short name T1154
Test name
Test status
Simulation time 27969618328 ps
CPU time 32.13 seconds
Started Aug 05 05:16:45 PM PDT 24
Finished Aug 05 05:17:17 PM PDT 24
Peak memory 199976 kb
Host smart-0b0acd75-2009-4959-93e8-f3ceca98cb59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222398314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.4222398314
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1292531920
Short name T1093
Test name
Test status
Simulation time 57172375695 ps
CPU time 196.66 seconds
Started Aug 05 05:16:48 PM PDT 24
Finished Aug 05 05:20:05 PM PDT 24
Peak memory 216320 kb
Host smart-f208d744-a5b0-4eb4-a362-b45cdb31c062
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292531920 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1292531920
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1693793275
Short name T560
Test name
Test status
Simulation time 1001363062 ps
CPU time 3.49 seconds
Started Aug 05 05:16:38 PM PDT 24
Finished Aug 05 05:16:42 PM PDT 24
Peak memory 198876 kb
Host smart-7feed1c2-ce0a-41d1-abcf-db8d0d2a35ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693793275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1693793275
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1064564696
Short name T366
Test name
Test status
Simulation time 49285656523 ps
CPU time 82.1 seconds
Started Aug 05 05:16:38 PM PDT 24
Finished Aug 05 05:18:00 PM PDT 24
Peak memory 199976 kb
Host smart-7fe46d15-617e-4a31-b157-339a0110fb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064564696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1064564696
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.256860685
Short name T677
Test name
Test status
Simulation time 37399161 ps
CPU time 0.58 seconds
Started Aug 05 05:13:48 PM PDT 24
Finished Aug 05 05:13:48 PM PDT 24
Peak memory 195572 kb
Host smart-6f2de2de-ba0a-4c3e-9bd2-eb6a95671642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256860685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.256860685
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3489410423
Short name T142
Test name
Test status
Simulation time 208603872735 ps
CPU time 156.01 seconds
Started Aug 05 05:13:36 PM PDT 24
Finished Aug 05 05:16:12 PM PDT 24
Peak memory 200000 kb
Host smart-f2039d19-414d-4857-9e43-31875ef423e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489410423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3489410423
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.2778278856
Short name T960
Test name
Test status
Simulation time 72324884322 ps
CPU time 135.92 seconds
Started Aug 05 05:13:40 PM PDT 24
Finished Aug 05 05:15:56 PM PDT 24
Peak memory 199308 kb
Host smart-2b6ba5bc-2f98-4e66-8718-26f4f709b314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778278856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2778278856
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1382498780
Short name T673
Test name
Test status
Simulation time 117316821240 ps
CPU time 51.53 seconds
Started Aug 05 05:13:37 PM PDT 24
Finished Aug 05 05:14:29 PM PDT 24
Peak memory 199956 kb
Host smart-9ad38d61-e848-4f0a-b4a1-2eee1e384063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382498780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1382498780
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2410782914
Short name T847
Test name
Test status
Simulation time 92915827891 ps
CPU time 139.28 seconds
Started Aug 05 05:13:39 PM PDT 24
Finished Aug 05 05:15:59 PM PDT 24
Peak memory 199908 kb
Host smart-c6a1e845-b9d5-4ca7-84e5-88821729d88a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410782914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2410782914
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.523259404
Short name T826
Test name
Test status
Simulation time 161205403817 ps
CPU time 1136.22 seconds
Started Aug 05 05:13:43 PM PDT 24
Finished Aug 05 05:32:39 PM PDT 24
Peak memory 199892 kb
Host smart-0de9fa85-b81a-48db-b7ab-7f84fd39f25e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=523259404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.523259404
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.827750514
Short name T115
Test name
Test status
Simulation time 11209574086 ps
CPU time 5.63 seconds
Started Aug 05 05:13:39 PM PDT 24
Finished Aug 05 05:13:45 PM PDT 24
Peak memory 199648 kb
Host smart-37bb144f-bcc2-45f9-a4b3-eae554581d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827750514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.827750514
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2482023917
Short name T682
Test name
Test status
Simulation time 19868712710 ps
CPU time 19 seconds
Started Aug 05 05:13:39 PM PDT 24
Finished Aug 05 05:13:58 PM PDT 24
Peak memory 198136 kb
Host smart-15402734-e959-434c-8ffa-57814e6de45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482023917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2482023917
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3133653110
Short name T83
Test name
Test status
Simulation time 24023018799 ps
CPU time 240.69 seconds
Started Aug 05 05:13:36 PM PDT 24
Finished Aug 05 05:17:37 PM PDT 24
Peak memory 199912 kb
Host smart-df5650b1-8dae-420c-bb77-23124bddc7da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3133653110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3133653110
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.730256826
Short name T789
Test name
Test status
Simulation time 3365295811 ps
CPU time 23.94 seconds
Started Aug 05 05:13:37 PM PDT 24
Finished Aug 05 05:14:01 PM PDT 24
Peak memory 197960 kb
Host smart-9d0ee806-7e94-4727-9775-9e0d26fffdb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=730256826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.730256826
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.3834223584
Short name T692
Test name
Test status
Simulation time 155293056424 ps
CPU time 163.68 seconds
Started Aug 05 05:13:37 PM PDT 24
Finished Aug 05 05:16:21 PM PDT 24
Peak memory 199988 kb
Host smart-b88971db-29ad-49c4-bbd9-1b3b5fd4d1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834223584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3834223584
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2848605825
Short name T978
Test name
Test status
Simulation time 3369202897 ps
CPU time 2.01 seconds
Started Aug 05 05:13:40 PM PDT 24
Finished Aug 05 05:13:42 PM PDT 24
Peak memory 196464 kb
Host smart-04df6ad2-bb8e-47c6-ae6d-aec4179e0b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848605825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2848605825
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.971731864
Short name T26
Test name
Test status
Simulation time 36137754 ps
CPU time 0.78 seconds
Started Aug 05 05:13:42 PM PDT 24
Finished Aug 05 05:13:43 PM PDT 24
Peak memory 218328 kb
Host smart-52401ce6-cc5d-413d-ab2d-b99ccc7503ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971731864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.971731864
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3887704137
Short name T587
Test name
Test status
Simulation time 6213835822 ps
CPU time 13.01 seconds
Started Aug 05 05:13:40 PM PDT 24
Finished Aug 05 05:13:53 PM PDT 24
Peak memory 199388 kb
Host smart-5d5954d0-6387-4a28-bedc-0ad41aea5d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887704137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3887704137
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1062186002
Short name T647
Test name
Test status
Simulation time 8322148636 ps
CPU time 79.4 seconds
Started Aug 05 05:13:44 PM PDT 24
Finished Aug 05 05:15:03 PM PDT 24
Peak memory 208208 kb
Host smart-b12a6eee-0909-4661-9fa2-8805a7db1d4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062186002 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1062186002
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3841062808
Short name T14
Test name
Test status
Simulation time 2296763470 ps
CPU time 2.64 seconds
Started Aug 05 05:13:39 PM PDT 24
Finished Aug 05 05:13:42 PM PDT 24
Peak memory 198568 kb
Host smart-6b3909a7-2aed-4ca2-99e8-61ce81c5c7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841062808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3841062808
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2100986051
Short name T836
Test name
Test status
Simulation time 64554753276 ps
CPU time 56 seconds
Started Aug 05 05:13:40 PM PDT 24
Finished Aug 05 05:14:36 PM PDT 24
Peak memory 199912 kb
Host smart-e7c7217d-6b82-4e60-9792-cfa855a57aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100986051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2100986051
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2307978517
Short name T1096
Test name
Test status
Simulation time 50677827 ps
CPU time 0.59 seconds
Started Aug 05 05:16:52 PM PDT 24
Finished Aug 05 05:16:52 PM PDT 24
Peak memory 195624 kb
Host smart-77a84bd7-d3e1-4701-a4d5-de4405752687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307978517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2307978517
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.332906834
Short name T1112
Test name
Test status
Simulation time 91913877312 ps
CPU time 207.8 seconds
Started Aug 05 05:16:48 PM PDT 24
Finished Aug 05 05:20:16 PM PDT 24
Peak memory 199960 kb
Host smart-3a2594fd-9038-49fe-94f3-67099849ade6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332906834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.332906834
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.971092883
Short name T261
Test name
Test status
Simulation time 7355466843 ps
CPU time 15.86 seconds
Started Aug 05 05:16:43 PM PDT 24
Finished Aug 05 05:16:59 PM PDT 24
Peak memory 199832 kb
Host smart-48fc4ab4-a946-474e-9c3c-8dac45665d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971092883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.971092883
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.441773902
Short name T271
Test name
Test status
Simulation time 115293188448 ps
CPU time 46.69 seconds
Started Aug 05 05:16:48 PM PDT 24
Finished Aug 05 05:17:35 PM PDT 24
Peak memory 199928 kb
Host smart-616f439a-8007-4cb6-957a-4b9dff346790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441773902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.441773902
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2083277663
Short name T604
Test name
Test status
Simulation time 26933470308 ps
CPU time 8.86 seconds
Started Aug 05 05:16:43 PM PDT 24
Finished Aug 05 05:16:52 PM PDT 24
Peak memory 199628 kb
Host smart-99761d00-a2b4-46cd-9a45-ea1a49e1c7b6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083277663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2083277663
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2294822066
Short name T966
Test name
Test status
Simulation time 266929197993 ps
CPU time 449.28 seconds
Started Aug 05 05:16:50 PM PDT 24
Finished Aug 05 05:24:20 PM PDT 24
Peak memory 199904 kb
Host smart-94b2d9f9-df45-488e-b2ff-f4e056564b29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2294822066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2294822066
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.1352137333
Short name T345
Test name
Test status
Simulation time 5666081557 ps
CPU time 9.85 seconds
Started Aug 05 05:16:49 PM PDT 24
Finished Aug 05 05:16:59 PM PDT 24
Peak memory 199600 kb
Host smart-b2b7e227-3612-4a52-aede-f56fc1958d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352137333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1352137333
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.3511447520
Short name T863
Test name
Test status
Simulation time 80721208263 ps
CPU time 67.25 seconds
Started Aug 05 05:16:44 PM PDT 24
Finished Aug 05 05:17:52 PM PDT 24
Peak memory 199008 kb
Host smart-c6cf7f08-67d2-4e20-91da-beb94a7a4841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511447520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.3511447520
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.634683017
Short name T422
Test name
Test status
Simulation time 26255764528 ps
CPU time 309.48 seconds
Started Aug 05 05:16:52 PM PDT 24
Finished Aug 05 05:22:02 PM PDT 24
Peak memory 199872 kb
Host smart-602b4323-46de-4dfb-94d8-18c61e6210ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=634683017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.634683017
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2627957802
Short name T409
Test name
Test status
Simulation time 2653500992 ps
CPU time 3.11 seconds
Started Aug 05 05:16:43 PM PDT 24
Finished Aug 05 05:16:46 PM PDT 24
Peak memory 198452 kb
Host smart-20b34def-91b2-4579-8faf-395674cebcd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627957802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2627957802
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3171724538
Short name T681
Test name
Test status
Simulation time 93479062042 ps
CPU time 175.25 seconds
Started Aug 05 05:16:42 PM PDT 24
Finished Aug 05 05:19:37 PM PDT 24
Peak memory 199912 kb
Host smart-2b2c8ccb-1703-43e6-b165-500769d6c912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171724538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3171724538
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2821062981
Short name T1142
Test name
Test status
Simulation time 34554225250 ps
CPU time 13.6 seconds
Started Aug 05 05:16:46 PM PDT 24
Finished Aug 05 05:16:59 PM PDT 24
Peak memory 196072 kb
Host smart-23127a34-7a86-415a-8a89-239fcb3f494b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821062981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2821062981
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2904527069
Short name T1159
Test name
Test status
Simulation time 277104580 ps
CPU time 1.29 seconds
Started Aug 05 05:16:44 PM PDT 24
Finished Aug 05 05:16:45 PM PDT 24
Peak memory 199536 kb
Host smart-5fce6261-0c96-4982-a636-8742500d885c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904527069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2904527069
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3709662390
Short name T872
Test name
Test status
Simulation time 227742186007 ps
CPU time 846.51 seconds
Started Aug 05 05:16:50 PM PDT 24
Finished Aug 05 05:30:56 PM PDT 24
Peak memory 199980 kb
Host smart-fcaf73fd-6c18-4fa9-b641-7126737ab493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709662390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3709662390
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.102631069
Short name T1160
Test name
Test status
Simulation time 19321721740 ps
CPU time 188.12 seconds
Started Aug 05 05:16:51 PM PDT 24
Finished Aug 05 05:19:59 PM PDT 24
Peak memory 216012 kb
Host smart-724e394e-f4f9-4322-881e-58a1021a2385
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102631069 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.102631069
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2014483285
Short name T913
Test name
Test status
Simulation time 300639814 ps
CPU time 1.19 seconds
Started Aug 05 05:16:50 PM PDT 24
Finished Aug 05 05:16:51 PM PDT 24
Peak memory 197004 kb
Host smart-ba5f54bb-c19f-4709-b9b3-5855d605f9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014483285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2014483285
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.461400628
Short name T326
Test name
Test status
Simulation time 31068046260 ps
CPU time 28.24 seconds
Started Aug 05 05:16:46 PM PDT 24
Finished Aug 05 05:17:15 PM PDT 24
Peak memory 199988 kb
Host smart-4f8ce6a6-9f85-4498-9325-71c44261b958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461400628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.461400628
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2683920604
Short name T367
Test name
Test status
Simulation time 85834445 ps
CPU time 0.6 seconds
Started Aug 05 05:16:58 PM PDT 24
Finished Aug 05 05:16:59 PM PDT 24
Peak memory 194264 kb
Host smart-a7619566-d321-4e07-9ee2-506b89a8a90c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683920604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2683920604
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3640344009
Short name T652
Test name
Test status
Simulation time 36383573898 ps
CPU time 59.48 seconds
Started Aug 05 05:17:02 PM PDT 24
Finished Aug 05 05:18:01 PM PDT 24
Peak memory 199820 kb
Host smart-1b94708c-c47d-44fb-a5b9-1c63562b4d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640344009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3640344009
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.4094905475
Short name T1043
Test name
Test status
Simulation time 44188854198 ps
CPU time 37.83 seconds
Started Aug 05 05:16:50 PM PDT 24
Finished Aug 05 05:17:28 PM PDT 24
Peak memory 199868 kb
Host smart-7c7f6b20-ab5f-4de7-8d00-b9a09c594aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094905475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.4094905475
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.4091606023
Short name T1083
Test name
Test status
Simulation time 31812649339 ps
CPU time 26.82 seconds
Started Aug 05 05:16:51 PM PDT 24
Finished Aug 05 05:17:18 PM PDT 24
Peak memory 199928 kb
Host smart-f7c6e4e4-c9ba-4bef-8842-7a52a8648f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091606023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.4091606023
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1954797214
Short name T455
Test name
Test status
Simulation time 42418176084 ps
CPU time 72.37 seconds
Started Aug 05 05:16:52 PM PDT 24
Finished Aug 05 05:18:05 PM PDT 24
Peak memory 199956 kb
Host smart-e3420371-9a4c-4b53-9127-98155be74df4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954797214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1954797214
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3535194234
Short name T576
Test name
Test status
Simulation time 299915206218 ps
CPU time 430.91 seconds
Started Aug 05 05:16:57 PM PDT 24
Finished Aug 05 05:24:08 PM PDT 24
Peak memory 200000 kb
Host smart-3414e200-5a58-4e1b-bf03-c550e7e07125
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3535194234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3535194234
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.4124347660
Short name T490
Test name
Test status
Simulation time 11048010271 ps
CPU time 8.33 seconds
Started Aug 05 05:16:55 PM PDT 24
Finished Aug 05 05:17:04 PM PDT 24
Peak memory 199880 kb
Host smart-300d3611-a015-4018-b7d2-ca9b24d25904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124347660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.4124347660
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3001045641
Short name T546
Test name
Test status
Simulation time 118143050443 ps
CPU time 119.56 seconds
Started Aug 05 05:16:59 PM PDT 24
Finished Aug 05 05:18:59 PM PDT 24
Peak memory 199236 kb
Host smart-d4536199-496b-408d-a044-0e20b04d8b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001045641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3001045641
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.1018642342
Short name T898
Test name
Test status
Simulation time 1444200307 ps
CPU time 78.36 seconds
Started Aug 05 05:16:58 PM PDT 24
Finished Aug 05 05:18:17 PM PDT 24
Peak memory 199472 kb
Host smart-ec4975c7-93ad-4d96-b2d6-bb3b738022a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018642342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1018642342
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.184333022
Short name T797
Test name
Test status
Simulation time 4522814065 ps
CPU time 17.84 seconds
Started Aug 05 05:16:52 PM PDT 24
Finished Aug 05 05:17:10 PM PDT 24
Peak memory 198064 kb
Host smart-0342c09e-5642-4060-88a2-b08bab83a94f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=184333022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.184333022
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1551831926
Short name T263
Test name
Test status
Simulation time 74986959723 ps
CPU time 113.21 seconds
Started Aug 05 05:16:56 PM PDT 24
Finished Aug 05 05:18:50 PM PDT 24
Peak memory 199796 kb
Host smart-aa107473-e8fc-4ff4-82d7-7da6e90ef211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551831926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1551831926
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3045194760
Short name T684
Test name
Test status
Simulation time 2135525442 ps
CPU time 2.11 seconds
Started Aug 05 05:16:55 PM PDT 24
Finished Aug 05 05:16:58 PM PDT 24
Peak memory 195628 kb
Host smart-4c6cf2b2-b8cc-4f72-b746-bfd84b1ab6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045194760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3045194760
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.130234199
Short name T876
Test name
Test status
Simulation time 6063119362 ps
CPU time 14.83 seconds
Started Aug 05 05:16:53 PM PDT 24
Finished Aug 05 05:17:08 PM PDT 24
Peak memory 199824 kb
Host smart-91cb0def-1185-4fa2-8840-4a3a33a922c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130234199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.130234199
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1727322756
Short name T161
Test name
Test status
Simulation time 175564938150 ps
CPU time 271.5 seconds
Started Aug 05 05:16:56 PM PDT 24
Finished Aug 05 05:21:27 PM PDT 24
Peak memory 199960 kb
Host smart-36c40a45-bc3b-4565-b349-0b1e14c14a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727322756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1727322756
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3679627125
Short name T535
Test name
Test status
Simulation time 209351408935 ps
CPU time 951.48 seconds
Started Aug 05 05:16:58 PM PDT 24
Finished Aug 05 05:32:50 PM PDT 24
Peak memory 216380 kb
Host smart-db02db1e-2b12-4184-a044-ddc23c1d74fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679627125 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3679627125
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2025888017
Short name T519
Test name
Test status
Simulation time 6001365889 ps
CPU time 14.74 seconds
Started Aug 05 05:16:57 PM PDT 24
Finished Aug 05 05:17:12 PM PDT 24
Peak memory 199960 kb
Host smart-bad1cc2e-b0a0-4aa2-8130-45bb3226cbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025888017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2025888017
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3431082125
Short name T1100
Test name
Test status
Simulation time 7091848165 ps
CPU time 3.41 seconds
Started Aug 05 05:16:50 PM PDT 24
Finished Aug 05 05:16:54 PM PDT 24
Peak memory 197880 kb
Host smart-e5c3655b-b42d-4663-a5eb-11eee727e661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431082125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3431082125
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.4117915863
Short name T951
Test name
Test status
Simulation time 57400543 ps
CPU time 0.56 seconds
Started Aug 05 05:16:57 PM PDT 24
Finished Aug 05 05:16:58 PM PDT 24
Peak memory 195620 kb
Host smart-7ba992d4-cede-42ae-a409-4bca399b2cfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117915863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.4117915863
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.276636616
Short name T747
Test name
Test status
Simulation time 84848582869 ps
CPU time 68.28 seconds
Started Aug 05 05:16:56 PM PDT 24
Finished Aug 05 05:18:05 PM PDT 24
Peak memory 200000 kb
Host smart-236e389c-ccf3-43fa-8feb-4d122a4b3195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276636616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.276636616
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.2630545316
Short name T990
Test name
Test status
Simulation time 30778396890 ps
CPU time 47.88 seconds
Started Aug 05 05:16:56 PM PDT 24
Finished Aug 05 05:17:44 PM PDT 24
Peak memory 199856 kb
Host smart-f6f6c2de-34bd-45bb-b61c-b1b2745cfc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630545316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2630545316
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2794366191
Short name T932
Test name
Test status
Simulation time 25200206861 ps
CPU time 20.94 seconds
Started Aug 05 05:16:54 PM PDT 24
Finished Aug 05 05:17:15 PM PDT 24
Peak memory 199928 kb
Host smart-5901a22a-f529-416b-b12a-1a7ebc1ca970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794366191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2794366191
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2105647593
Short name T493
Test name
Test status
Simulation time 182266967472 ps
CPU time 260.4 seconds
Started Aug 05 05:16:58 PM PDT 24
Finished Aug 05 05:21:18 PM PDT 24
Peak memory 199968 kb
Host smart-19232601-4506-4da3-8451-246f3c820aa3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105647593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2105647593
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3857338550
Short name T637
Test name
Test status
Simulation time 60127518373 ps
CPU time 163.02 seconds
Started Aug 05 05:16:59 PM PDT 24
Finished Aug 05 05:19:42 PM PDT 24
Peak memory 199916 kb
Host smart-69715707-be0e-404e-b747-8785840a6612
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3857338550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3857338550
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.237635371
Short name T418
Test name
Test status
Simulation time 2814776431 ps
CPU time 2.05 seconds
Started Aug 05 05:16:59 PM PDT 24
Finished Aug 05 05:17:01 PM PDT 24
Peak memory 197476 kb
Host smart-94988f41-6eb8-4d47-98a0-939a22d9df24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237635371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.237635371
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2384191270
Short name T651
Test name
Test status
Simulation time 66498372424 ps
CPU time 32.08 seconds
Started Aug 05 05:17:00 PM PDT 24
Finished Aug 05 05:17:32 PM PDT 24
Peak memory 200120 kb
Host smart-b1ff7e76-2c14-42f7-99ca-3b9c20dc8ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384191270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2384191270
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1380190011
Short name T481
Test name
Test status
Simulation time 24769524085 ps
CPU time 189.72 seconds
Started Aug 05 05:16:58 PM PDT 24
Finished Aug 05 05:20:07 PM PDT 24
Peak memory 199900 kb
Host smart-eb502378-44a4-4f71-8def-bced89b614be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1380190011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1380190011
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3232095425
Short name T962
Test name
Test status
Simulation time 1480065245 ps
CPU time 5.69 seconds
Started Aug 05 05:16:59 PM PDT 24
Finished Aug 05 05:17:05 PM PDT 24
Peak memory 197948 kb
Host smart-2e2da3fd-93b4-499b-b496-f070d64249d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3232095425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3232095425
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.58220191
Short name T548
Test name
Test status
Simulation time 12345023582 ps
CPU time 8.73 seconds
Started Aug 05 05:16:59 PM PDT 24
Finished Aug 05 05:17:08 PM PDT 24
Peak memory 199276 kb
Host smart-3056bdfd-0882-4381-85f1-c220d6bf3933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58220191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.58220191
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.484997740
Short name T997
Test name
Test status
Simulation time 34445337231 ps
CPU time 49.71 seconds
Started Aug 05 05:17:01 PM PDT 24
Finished Aug 05 05:17:51 PM PDT 24
Peak memory 196264 kb
Host smart-b611b33c-ad80-4e70-87f3-a079b21b1fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484997740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.484997740
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.4200551293
Short name T821
Test name
Test status
Simulation time 5795338773 ps
CPU time 14.29 seconds
Started Aug 05 05:16:57 PM PDT 24
Finished Aug 05 05:17:11 PM PDT 24
Peak memory 199816 kb
Host smart-dab86548-8078-4f01-85f6-da914d762bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200551293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.4200551293
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.603582711
Short name T133
Test name
Test status
Simulation time 102363203066 ps
CPU time 595.1 seconds
Started Aug 05 05:16:57 PM PDT 24
Finished Aug 05 05:26:52 PM PDT 24
Peak memory 199968 kb
Host smart-8b07fc63-2778-48d6-98ae-3499326f1565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603582711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.603582711
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2399787008
Short name T319
Test name
Test status
Simulation time 64242766613 ps
CPU time 581.19 seconds
Started Aug 05 05:17:34 PM PDT 24
Finished Aug 05 05:27:16 PM PDT 24
Peak memory 224488 kb
Host smart-927a5bda-6684-4aee-8fd5-5eadc84a4b5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399787008 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2399787008
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2641375265
Short name T419
Test name
Test status
Simulation time 1431786504 ps
CPU time 1.14 seconds
Started Aug 05 05:17:02 PM PDT 24
Finished Aug 05 05:17:03 PM PDT 24
Peak memory 198068 kb
Host smart-8f43b495-f215-4ded-a84a-2fa15e5e66c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641375265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2641375265
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.616899506
Short name T736
Test name
Test status
Simulation time 34092253083 ps
CPU time 79.29 seconds
Started Aug 05 05:17:35 PM PDT 24
Finished Aug 05 05:18:54 PM PDT 24
Peak memory 199916 kb
Host smart-94ebbe5c-f55e-4213-a882-a7a2dd59e917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616899506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.616899506
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2361177703
Short name T695
Test name
Test status
Simulation time 45027375 ps
CPU time 0.53 seconds
Started Aug 05 05:17:36 PM PDT 24
Finished Aug 05 05:17:36 PM PDT 24
Peak memory 194796 kb
Host smart-5ef0194d-af51-4707-87a3-40b0752b2aba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361177703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2361177703
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1085968527
Short name T40
Test name
Test status
Simulation time 130070129404 ps
CPU time 92.75 seconds
Started Aug 05 05:17:03 PM PDT 24
Finished Aug 05 05:18:36 PM PDT 24
Peak memory 199620 kb
Host smart-132ae811-c48f-4333-aafb-ea98d132a7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085968527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1085968527
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3790355826
Short name T678
Test name
Test status
Simulation time 43361904424 ps
CPU time 36.09 seconds
Started Aug 05 05:16:58 PM PDT 24
Finished Aug 05 05:17:34 PM PDT 24
Peak memory 199980 kb
Host smart-1692df1d-542f-47a2-883e-c00b8dd2d11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790355826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3790355826
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1829434106
Short name T209
Test name
Test status
Simulation time 52671377882 ps
CPU time 20.71 seconds
Started Aug 05 05:16:59 PM PDT 24
Finished Aug 05 05:17:20 PM PDT 24
Peak memory 199788 kb
Host smart-2e726b32-5b9e-4a6c-b985-3247f8582265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829434106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1829434106
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3726512767
Short name T1032
Test name
Test status
Simulation time 40606854493 ps
CPU time 35.08 seconds
Started Aug 05 05:17:04 PM PDT 24
Finished Aug 05 05:17:39 PM PDT 24
Peak memory 199912 kb
Host smart-d66d0e2d-32f5-443e-9435-a2cd64be0447
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726512767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3726512767
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.2323323463
Short name T991
Test name
Test status
Simulation time 127864997401 ps
CPU time 330.46 seconds
Started Aug 05 05:17:04 PM PDT 24
Finished Aug 05 05:22:34 PM PDT 24
Peak memory 199880 kb
Host smart-c5950594-17f3-4cab-8cae-6c3dce319371
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2323323463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2323323463
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.857123292
Short name T403
Test name
Test status
Simulation time 2514038962 ps
CPU time 2.44 seconds
Started Aug 05 05:17:02 PM PDT 24
Finished Aug 05 05:17:05 PM PDT 24
Peak memory 198208 kb
Host smart-c208fba4-e642-41ee-8a03-5d54eccf4317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857123292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.857123292
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.3894455235
Short name T726
Test name
Test status
Simulation time 28456603024 ps
CPU time 15.3 seconds
Started Aug 05 05:17:02 PM PDT 24
Finished Aug 05 05:17:17 PM PDT 24
Peak memory 199260 kb
Host smart-4ad527bd-4dbd-499f-bd87-96b96ffb2b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894455235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3894455235
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.2143860045
Short name T916
Test name
Test status
Simulation time 7251432921 ps
CPU time 338.31 seconds
Started Aug 05 05:17:05 PM PDT 24
Finished Aug 05 05:22:44 PM PDT 24
Peak memory 199912 kb
Host smart-79ede284-e9ae-421d-99f2-a9c83ca6da9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2143860045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2143860045
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.3307247456
Short name T707
Test name
Test status
Simulation time 5268185900 ps
CPU time 38.95 seconds
Started Aug 05 05:17:03 PM PDT 24
Finished Aug 05 05:17:43 PM PDT 24
Peak memory 198124 kb
Host smart-03240252-318d-4d93-ae74-ed8847bfd562
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3307247456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3307247456
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2208570637
Short name T378
Test name
Test status
Simulation time 12949410225 ps
CPU time 22.92 seconds
Started Aug 05 05:17:05 PM PDT 24
Finished Aug 05 05:17:28 PM PDT 24
Peak memory 199908 kb
Host smart-60d52028-096d-4f9a-8106-6678058b44b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208570637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2208570637
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2644005087
Short name T431
Test name
Test status
Simulation time 41868147417 ps
CPU time 15.66 seconds
Started Aug 05 05:17:03 PM PDT 24
Finished Aug 05 05:17:19 PM PDT 24
Peak memory 195992 kb
Host smart-a6c20eff-3027-4b88-81e7-27d68e492ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644005087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2644005087
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3304945090
Short name T355
Test name
Test status
Simulation time 465478488 ps
CPU time 1.21 seconds
Started Aug 05 05:16:58 PM PDT 24
Finished Aug 05 05:16:59 PM PDT 24
Peak memory 199000 kb
Host smart-444d65bd-13bc-4b2e-bf32-15dc2e1d5801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304945090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3304945090
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2916735088
Short name T540
Test name
Test status
Simulation time 102350990134 ps
CPU time 111.75 seconds
Started Aug 05 05:17:04 PM PDT 24
Finished Aug 05 05:18:56 PM PDT 24
Peak memory 199908 kb
Host smart-9aa9caef-9c11-465a-9aef-5018141c38ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916735088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2916735088
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.474994962
Short name T1054
Test name
Test status
Simulation time 45296327775 ps
CPU time 501.09 seconds
Started Aug 05 05:17:04 PM PDT 24
Finished Aug 05 05:25:26 PM PDT 24
Peak memory 216424 kb
Host smart-3f7c04ac-0a94-4092-bca6-3a43b4cc13cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474994962 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.474994962
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3624539919
Short name T371
Test name
Test status
Simulation time 4834541427 ps
CPU time 2 seconds
Started Aug 05 05:17:04 PM PDT 24
Finished Aug 05 05:17:06 PM PDT 24
Peak memory 198988 kb
Host smart-0af38b4f-fb1e-4e67-98d9-9c87d5162bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624539919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3624539919
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3547978517
Short name T551
Test name
Test status
Simulation time 19564146263 ps
CPU time 31.33 seconds
Started Aug 05 05:17:01 PM PDT 24
Finished Aug 05 05:17:33 PM PDT 24
Peak memory 199968 kb
Host smart-5f011afa-88b6-476b-8bb4-1b92e8de9872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547978517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3547978517
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.49832163
Short name T764
Test name
Test status
Simulation time 65921335 ps
CPU time 0.57 seconds
Started Aug 05 05:17:10 PM PDT 24
Finished Aug 05 05:17:11 PM PDT 24
Peak memory 195572 kb
Host smart-4b366684-0faf-429f-8497-5b1bf10c64a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49832163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.49832163
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3213972606
Short name T158
Test name
Test status
Simulation time 107404269625 ps
CPU time 49.64 seconds
Started Aug 05 05:17:03 PM PDT 24
Finished Aug 05 05:17:53 PM PDT 24
Peak memory 199900 kb
Host smart-358d72a6-2c17-4447-b2ae-9f2841417573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213972606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3213972606
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1381644779
Short name T450
Test name
Test status
Simulation time 103503670006 ps
CPU time 188.96 seconds
Started Aug 05 05:17:04 PM PDT 24
Finished Aug 05 05:20:13 PM PDT 24
Peak memory 199740 kb
Host smart-dcc4620c-bcb4-4a15-a745-3f6b8ad87115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381644779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1381644779
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.209848936
Short name T931
Test name
Test status
Simulation time 62543215204 ps
CPU time 81.94 seconds
Started Aug 05 05:17:02 PM PDT 24
Finished Aug 05 05:18:24 PM PDT 24
Peak memory 199872 kb
Host smart-33bc5b1c-1c81-4225-97b7-77c32a29b268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209848936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.209848936
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2392380218
Short name T446
Test name
Test status
Simulation time 14872082844 ps
CPU time 7.31 seconds
Started Aug 05 05:17:10 PM PDT 24
Finished Aug 05 05:17:17 PM PDT 24
Peak memory 198600 kb
Host smart-5725b1fc-1d12-4229-8936-fb3faedbac10
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392380218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2392380218
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1429572726
Short name T775
Test name
Test status
Simulation time 46589672560 ps
CPU time 56.48 seconds
Started Aug 05 05:17:09 PM PDT 24
Finished Aug 05 05:18:05 PM PDT 24
Peak memory 199960 kb
Host smart-e41a733f-c994-4c4e-8f7a-78c8c291c99d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1429572726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1429572726
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1506920972
Short name T1109
Test name
Test status
Simulation time 8461609348 ps
CPU time 4.17 seconds
Started Aug 05 05:17:37 PM PDT 24
Finished Aug 05 05:17:41 PM PDT 24
Peak memory 199696 kb
Host smart-4eb25565-1a30-4268-b57e-eeb12b41df95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506920972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1506920972
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3822143434
Short name T697
Test name
Test status
Simulation time 47281036657 ps
CPU time 22.73 seconds
Started Aug 05 05:17:38 PM PDT 24
Finished Aug 05 05:18:01 PM PDT 24
Peak memory 199416 kb
Host smart-5cede83b-afdd-4f12-8823-b5c025c6c27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822143434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3822143434
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.1222027141
Short name T412
Test name
Test status
Simulation time 7941075714 ps
CPU time 444.58 seconds
Started Aug 05 05:17:08 PM PDT 24
Finished Aug 05 05:24:33 PM PDT 24
Peak memory 199904 kb
Host smart-3fe2bca1-2db6-41dc-aae2-2fd12a6ef925
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1222027141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1222027141
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2648496676
Short name T713
Test name
Test status
Simulation time 7524412785 ps
CPU time 18.54 seconds
Started Aug 05 05:17:12 PM PDT 24
Finished Aug 05 05:17:30 PM PDT 24
Peak memory 198268 kb
Host smart-99733c01-5c27-48a9-8d98-57dfe357d85e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2648496676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2648496676
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1639262697
Short name T521
Test name
Test status
Simulation time 252150275705 ps
CPU time 71.68 seconds
Started Aug 05 05:17:11 PM PDT 24
Finished Aug 05 05:18:23 PM PDT 24
Peak memory 199908 kb
Host smart-d6547df6-7623-4aed-a194-e2317d6e3048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639262697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1639262697
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1908804650
Short name T537
Test name
Test status
Simulation time 1555126226 ps
CPU time 1.28 seconds
Started Aug 05 05:17:15 PM PDT 24
Finished Aug 05 05:17:16 PM PDT 24
Peak memory 195424 kb
Host smart-297e82ee-7c96-4567-8991-95ca62e2e2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908804650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1908804650
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1245733872
Short name T312
Test name
Test status
Simulation time 5479151803 ps
CPU time 14.33 seconds
Started Aug 05 05:17:37 PM PDT 24
Finished Aug 05 05:17:52 PM PDT 24
Peak memory 199108 kb
Host smart-54c065b6-6c8f-468b-af57-9c836647f5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245733872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1245733872
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.3435028058
Short name T1076
Test name
Test status
Simulation time 213130792773 ps
CPU time 442.49 seconds
Started Aug 05 05:17:10 PM PDT 24
Finished Aug 05 05:24:33 PM PDT 24
Peak memory 208288 kb
Host smart-7846711d-cf79-48ad-90a5-86181bd90573
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435028058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3435028058
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2421651619
Short name T505
Test name
Test status
Simulation time 5039900925 ps
CPU time 1.49 seconds
Started Aug 05 05:17:12 PM PDT 24
Finished Aug 05 05:17:13 PM PDT 24
Peak memory 199356 kb
Host smart-7f7450e1-2710-45b6-9a2f-a8e0111d9a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421651619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2421651619
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1779667884
Short name T279
Test name
Test status
Simulation time 62439925521 ps
CPU time 24.36 seconds
Started Aug 05 05:17:03 PM PDT 24
Finished Aug 05 05:17:28 PM PDT 24
Peak memory 199900 kb
Host smart-d1cfed47-af3c-4a29-8655-d54931cd423b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779667884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1779667884
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1789593682
Short name T1119
Test name
Test status
Simulation time 16050407 ps
CPU time 0.55 seconds
Started Aug 05 05:17:24 PM PDT 24
Finished Aug 05 05:17:24 PM PDT 24
Peak memory 194316 kb
Host smart-4c353306-6d53-4d26-a022-60d2dfff722d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789593682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1789593682
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.33322062
Short name T467
Test name
Test status
Simulation time 16386907753 ps
CPU time 6.32 seconds
Started Aug 05 05:17:08 PM PDT 24
Finished Aug 05 05:17:15 PM PDT 24
Peak memory 199996 kb
Host smart-679f1316-182f-4ad0-b833-14a9871b7a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33322062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.33322062
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3625828894
Short name T624
Test name
Test status
Simulation time 116755024305 ps
CPU time 49.04 seconds
Started Aug 05 05:17:10 PM PDT 24
Finished Aug 05 05:17:59 PM PDT 24
Peak memory 199780 kb
Host smart-8f2984b7-b7e4-44a5-8751-2717c2574b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625828894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3625828894
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2746124914
Short name T168
Test name
Test status
Simulation time 43847822896 ps
CPU time 50.04 seconds
Started Aug 05 05:17:36 PM PDT 24
Finished Aug 05 05:18:27 PM PDT 24
Peak memory 199908 kb
Host smart-26ba9d3b-07a0-4f55-abc1-af6d0c547b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746124914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2746124914
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.1385860945
Short name T981
Test name
Test status
Simulation time 302205362140 ps
CPU time 75.59 seconds
Started Aug 05 05:17:16 PM PDT 24
Finished Aug 05 05:18:31 PM PDT 24
Peak memory 199940 kb
Host smart-5ffb13ab-28b7-4358-879c-73cab4238fac
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385860945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1385860945
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.871439387
Short name T675
Test name
Test status
Simulation time 76901381609 ps
CPU time 310.4 seconds
Started Aug 05 05:17:22 PM PDT 24
Finished Aug 05 05:22:33 PM PDT 24
Peak memory 199916 kb
Host smart-691a2b4c-20c0-4416-987f-7802f9fb1fd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=871439387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.871439387
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.3286376255
Short name T1026
Test name
Test status
Simulation time 5111653678 ps
CPU time 10.65 seconds
Started Aug 05 05:17:22 PM PDT 24
Finished Aug 05 05:17:32 PM PDT 24
Peak memory 199988 kb
Host smart-e1e0d1e2-c187-4e1c-b1cf-0058e426f875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286376255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3286376255
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2630525550
Short name T273
Test name
Test status
Simulation time 65394240979 ps
CPU time 113.59 seconds
Started Aug 05 05:17:15 PM PDT 24
Finished Aug 05 05:19:09 PM PDT 24
Peak memory 199732 kb
Host smart-e0074f03-a5ae-4e2a-b203-0d0f7b0fc4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630525550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2630525550
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.2720533314
Short name T534
Test name
Test status
Simulation time 10511380548 ps
CPU time 317.02 seconds
Started Aug 05 05:17:17 PM PDT 24
Finished Aug 05 05:22:34 PM PDT 24
Peak memory 199840 kb
Host smart-db5d814b-3f42-443a-be83-6e34d4d7ea2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2720533314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2720533314
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3441363063
Short name T940
Test name
Test status
Simulation time 3296580051 ps
CPU time 29.92 seconds
Started Aug 05 05:17:37 PM PDT 24
Finished Aug 05 05:18:07 PM PDT 24
Peak memory 197968 kb
Host smart-4dab5563-9104-4b39-ae9f-2394bb6be9a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3441363063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3441363063
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3694898224
Short name T1048
Test name
Test status
Simulation time 86643484159 ps
CPU time 119.66 seconds
Started Aug 05 05:17:18 PM PDT 24
Finished Aug 05 05:19:18 PM PDT 24
Peak memory 199856 kb
Host smart-aa5afc3c-cb47-4940-bfa9-89e2e4eb90a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694898224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3694898224
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.4129804602
Short name T1027
Test name
Test status
Simulation time 3079273156 ps
CPU time 1.63 seconds
Started Aug 05 05:17:16 PM PDT 24
Finished Aug 05 05:17:18 PM PDT 24
Peak memory 196420 kb
Host smart-f39acdac-a5a4-4688-8837-a184185a4204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129804602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.4129804602
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2258635940
Short name T615
Test name
Test status
Simulation time 949145508 ps
CPU time 2.49 seconds
Started Aug 05 05:17:11 PM PDT 24
Finished Aug 05 05:17:14 PM PDT 24
Peak memory 199856 kb
Host smart-dae078cf-c4b1-4dd4-934a-e56442108527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258635940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2258635940
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1742908521
Short name T64
Test name
Test status
Simulation time 196900217079 ps
CPU time 510.37 seconds
Started Aug 05 05:17:15 PM PDT 24
Finished Aug 05 05:25:46 PM PDT 24
Peak memory 216488 kb
Host smart-abdc6c7e-ee45-44bf-bb57-1c5c8ae43fbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742908521 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1742908521
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2576431097
Short name T1087
Test name
Test status
Simulation time 831197842 ps
CPU time 2.08 seconds
Started Aug 05 05:17:17 PM PDT 24
Finished Aug 05 05:17:20 PM PDT 24
Peak memory 198276 kb
Host smart-e4774275-e9cf-4477-a44a-2933589aa276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576431097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2576431097
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_alert_test.198644482
Short name T340
Test name
Test status
Simulation time 32636822 ps
CPU time 0.58 seconds
Started Aug 05 05:17:22 PM PDT 24
Finished Aug 05 05:17:22 PM PDT 24
Peak memory 195320 kb
Host smart-fd6cb2da-7075-42a5-a5ac-0145810c5e1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198644482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.198644482
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2715716050
Short name T426
Test name
Test status
Simulation time 30936067776 ps
CPU time 46.21 seconds
Started Aug 05 05:17:17 PM PDT 24
Finished Aug 05 05:18:04 PM PDT 24
Peak memory 199872 kb
Host smart-d65a6af4-058c-4180-9b1b-8ecc5b572008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715716050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2715716050
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1384911084
Short name T468
Test name
Test status
Simulation time 69733441713 ps
CPU time 28.44 seconds
Started Aug 05 05:17:16 PM PDT 24
Finished Aug 05 05:17:44 PM PDT 24
Peak memory 199912 kb
Host smart-b3062ba3-2fa8-4c0b-b8d5-c8f5dbebc4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384911084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1384911084
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2778198619
Short name T1023
Test name
Test status
Simulation time 7342070639 ps
CPU time 15.91 seconds
Started Aug 05 05:17:23 PM PDT 24
Finished Aug 05 05:17:39 PM PDT 24
Peak memory 199972 kb
Host smart-e22030e3-7c5a-41df-8775-11b131eb6eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778198619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2778198619
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2384260860
Short name T1019
Test name
Test status
Simulation time 26388961554 ps
CPU time 12.19 seconds
Started Aug 05 05:17:22 PM PDT 24
Finished Aug 05 05:17:35 PM PDT 24
Peak memory 199968 kb
Host smart-c4c7934a-e9a2-4b3d-a361-155baadd2fd9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384260860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2384260860
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1939602005
Short name T985
Test name
Test status
Simulation time 182413258176 ps
CPU time 1155.41 seconds
Started Aug 05 05:17:21 PM PDT 24
Finished Aug 05 05:36:37 PM PDT 24
Peak memory 199912 kb
Host smart-48d2b701-427d-4fe0-a5f0-43b04a10c874
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1939602005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1939602005
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.707895405
Short name T1025
Test name
Test status
Simulation time 2476578963 ps
CPU time 1.59 seconds
Started Aug 05 05:17:23 PM PDT 24
Finished Aug 05 05:17:24 PM PDT 24
Peak memory 195800 kb
Host smart-0f8c3626-56e6-4104-ad08-86a65660ddf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707895405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.707895405
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.1496329658
Short name T725
Test name
Test status
Simulation time 350394120178 ps
CPU time 37.02 seconds
Started Aug 05 05:17:20 PM PDT 24
Finished Aug 05 05:17:57 PM PDT 24
Peak memory 198988 kb
Host smart-8dcf4433-5328-4544-8864-93bbe71289e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496329658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1496329658
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.3875663497
Short name T619
Test name
Test status
Simulation time 10338993805 ps
CPU time 115.35 seconds
Started Aug 05 05:17:21 PM PDT 24
Finished Aug 05 05:19:17 PM PDT 24
Peak memory 199916 kb
Host smart-d9c29dda-b625-4f67-9beb-b43c8068c02e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3875663497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3875663497
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.641541940
Short name T1162
Test name
Test status
Simulation time 6326872460 ps
CPU time 13.96 seconds
Started Aug 05 05:17:37 PM PDT 24
Finished Aug 05 05:17:52 PM PDT 24
Peak memory 198108 kb
Host smart-7a157bd0-92ea-4713-8541-32ee70c134de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=641541940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.641541940
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.517453410
Short name T1174
Test name
Test status
Simulation time 42908838175 ps
CPU time 25.32 seconds
Started Aug 05 05:17:22 PM PDT 24
Finished Aug 05 05:17:47 PM PDT 24
Peak memory 199804 kb
Host smart-b00b1db2-056f-46a4-a747-c5523e9b0d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517453410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.517453410
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3458507066
Short name T384
Test name
Test status
Simulation time 5516147343 ps
CPU time 2.9 seconds
Started Aug 05 05:17:22 PM PDT 24
Finished Aug 05 05:17:25 PM PDT 24
Peak memory 196236 kb
Host smart-db3f2a8d-56e7-4156-8a52-7ef8538267ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458507066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3458507066
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2404234338
Short name T406
Test name
Test status
Simulation time 521586787 ps
CPU time 1.58 seconds
Started Aug 05 05:17:23 PM PDT 24
Finished Aug 05 05:17:25 PM PDT 24
Peak memory 198240 kb
Host smart-59622db4-bfc7-4998-bb65-f259ddd99e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404234338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2404234338
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1362929351
Short name T674
Test name
Test status
Simulation time 362695155460 ps
CPU time 145.14 seconds
Started Aug 05 05:17:22 PM PDT 24
Finished Aug 05 05:19:47 PM PDT 24
Peak memory 208252 kb
Host smart-b54cacc7-47cb-4cd9-bf93-1d75fbbef62b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362929351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1362929351
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2896476947
Short name T1035
Test name
Test status
Simulation time 34619019788 ps
CPU time 611 seconds
Started Aug 05 05:17:22 PM PDT 24
Finished Aug 05 05:27:33 PM PDT 24
Peak memory 216532 kb
Host smart-a36d36db-6739-46da-a545-e6277a3a5021
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896476947 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2896476947
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.4274267918
Short name T451
Test name
Test status
Simulation time 892477359 ps
CPU time 2.58 seconds
Started Aug 05 05:17:37 PM PDT 24
Finished Aug 05 05:17:40 PM PDT 24
Peak memory 198812 kb
Host smart-639e2dea-4cea-452d-88c5-7a26f3127c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274267918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.4274267918
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3097943774
Short name T502
Test name
Test status
Simulation time 88450211525 ps
CPU time 19.1 seconds
Started Aug 05 05:17:19 PM PDT 24
Finished Aug 05 05:17:38 PM PDT 24
Peak memory 199904 kb
Host smart-b061f9b6-7a1f-4fbd-bd5d-7b5659c6bd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097943774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3097943774
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3735071661
Short name T523
Test name
Test status
Simulation time 30692172 ps
CPU time 0.53 seconds
Started Aug 05 05:17:35 PM PDT 24
Finished Aug 05 05:17:36 PM PDT 24
Peak memory 195356 kb
Host smart-5b696d5c-ad12-425f-a327-33904f091cb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735071661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3735071661
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1954633097
Short name T620
Test name
Test status
Simulation time 67926216898 ps
CPU time 26.11 seconds
Started Aug 05 05:17:21 PM PDT 24
Finished Aug 05 05:17:47 PM PDT 24
Peak memory 199964 kb
Host smart-ee648379-d0b0-435f-b115-79c0b7a773cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954633097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1954633097
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3221552362
Short name T375
Test name
Test status
Simulation time 120994761667 ps
CPU time 20.66 seconds
Started Aug 05 05:17:39 PM PDT 24
Finished Aug 05 05:18:00 PM PDT 24
Peak memory 199896 kb
Host smart-3249f267-799c-4cfd-8318-37aaaa78e354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221552362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3221552362
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.976623516
Short name T192
Test name
Test status
Simulation time 224142393916 ps
CPU time 111.07 seconds
Started Aug 05 05:17:30 PM PDT 24
Finished Aug 05 05:19:21 PM PDT 24
Peak memory 199812 kb
Host smart-ffed45e8-e4dd-45f6-80c6-dfe3db24c33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976623516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.976623516
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2401726104
Short name T731
Test name
Test status
Simulation time 16161023342 ps
CPU time 11.34 seconds
Started Aug 05 05:17:29 PM PDT 24
Finished Aug 05 05:17:41 PM PDT 24
Peak memory 199872 kb
Host smart-520bb723-eb23-4696-a113-0a0ba8ca8e7f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401726104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2401726104
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2983275872
Short name T476
Test name
Test status
Simulation time 102466187289 ps
CPU time 251.94 seconds
Started Aug 05 05:17:30 PM PDT 24
Finished Aug 05 05:21:42 PM PDT 24
Peak memory 199932 kb
Host smart-89a69a97-f0b8-49f3-a69e-0213c4f429e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2983275872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2983275872
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.513021682
Short name T812
Test name
Test status
Simulation time 6657652345 ps
CPU time 5.74 seconds
Started Aug 05 05:17:28 PM PDT 24
Finished Aug 05 05:17:34 PM PDT 24
Peak memory 199108 kb
Host smart-33aed1cd-1660-418b-ad35-6f036f70e800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513021682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.513021682
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.257956974
Short name T542
Test name
Test status
Simulation time 66029064930 ps
CPU time 75.46 seconds
Started Aug 05 05:17:34 PM PDT 24
Finished Aug 05 05:18:50 PM PDT 24
Peak memory 199376 kb
Host smart-ed96701c-9690-4c66-a30e-a689f289a1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257956974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.257956974
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1569116183
Short name T445
Test name
Test status
Simulation time 7679952568 ps
CPU time 307.22 seconds
Started Aug 05 05:17:29 PM PDT 24
Finished Aug 05 05:22:36 PM PDT 24
Peak memory 199912 kb
Host smart-9e4fbfb3-ce82-4b1e-abb5-0d32d87ffba2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1569116183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1569116183
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1255696991
Short name T487
Test name
Test status
Simulation time 4859581364 ps
CPU time 13.81 seconds
Started Aug 05 05:17:31 PM PDT 24
Finished Aug 05 05:17:45 PM PDT 24
Peak memory 198076 kb
Host smart-c983e48c-95c9-43d7-9ee4-adc15bb24400
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1255696991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1255696991
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.679376603
Short name T738
Test name
Test status
Simulation time 126232592814 ps
CPU time 34.34 seconds
Started Aug 05 05:17:37 PM PDT 24
Finished Aug 05 05:18:12 PM PDT 24
Peak memory 199904 kb
Host smart-d9234429-0337-4c09-b786-9cefaa5c975d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679376603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.679376603
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3147091147
Short name T1133
Test name
Test status
Simulation time 3946846360 ps
CPU time 2.27 seconds
Started Aug 05 05:17:29 PM PDT 24
Finished Aug 05 05:17:31 PM PDT 24
Peak memory 196552 kb
Host smart-d300941f-baf5-4a0f-8b6a-9f3206b8dbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147091147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3147091147
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3884885385
Short name T794
Test name
Test status
Simulation time 6202695349 ps
CPU time 12.5 seconds
Started Aug 05 05:17:22 PM PDT 24
Finished Aug 05 05:17:34 PM PDT 24
Peak memory 199720 kb
Host smart-39130b8c-92c3-4297-8dbb-044bc86e11e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884885385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3884885385
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1863865912
Short name T298
Test name
Test status
Simulation time 230260624417 ps
CPU time 207.83 seconds
Started Aug 05 05:17:37 PM PDT 24
Finished Aug 05 05:21:05 PM PDT 24
Peak memory 199972 kb
Host smart-0244777e-318c-4007-a91b-9cafb5390b4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863865912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1863865912
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1196800830
Short name T1120
Test name
Test status
Simulation time 37391839035 ps
CPU time 245.57 seconds
Started Aug 05 05:17:29 PM PDT 24
Finished Aug 05 05:21:34 PM PDT 24
Peak memory 216432 kb
Host smart-da848744-d244-4e4d-9dc0-c9d801cee548
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196800830 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1196800830
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1285776408
Short name T785
Test name
Test status
Simulation time 1262015929 ps
CPU time 3.73 seconds
Started Aug 05 05:17:28 PM PDT 24
Finished Aug 05 05:17:32 PM PDT 24
Peak memory 198888 kb
Host smart-ad323a0f-d5b9-467e-833f-f322ad87e0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285776408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1285776408
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1761543952
Short name T928
Test name
Test status
Simulation time 75581096048 ps
CPU time 52.04 seconds
Started Aug 05 05:17:23 PM PDT 24
Finished Aug 05 05:18:15 PM PDT 24
Peak memory 199924 kb
Host smart-83091413-ac7d-4cb5-907f-93ec1212f153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761543952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1761543952
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2098238738
Short name T756
Test name
Test status
Simulation time 44827142 ps
CPU time 0.57 seconds
Started Aug 05 05:17:46 PM PDT 24
Finished Aug 05 05:17:47 PM PDT 24
Peak memory 195288 kb
Host smart-946177d6-bfca-4668-8c83-1d8b7984f3a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098238738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2098238738
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3117749807
Short name T592
Test name
Test status
Simulation time 61655575574 ps
CPU time 25.72 seconds
Started Aug 05 05:17:34 PM PDT 24
Finished Aug 05 05:18:00 PM PDT 24
Peak memory 199836 kb
Host smart-12b2292c-e0d3-43e1-b6e2-ef4fd9cafb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117749807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3117749807
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2664238673
Short name T307
Test name
Test status
Simulation time 152154170238 ps
CPU time 85.95 seconds
Started Aug 05 05:17:33 PM PDT 24
Finished Aug 05 05:18:59 PM PDT 24
Peak memory 199936 kb
Host smart-d83a5a50-4ea5-4cce-9499-df3a31fd6e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664238673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2664238673
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2202258105
Short name T613
Test name
Test status
Simulation time 75378273658 ps
CPU time 23.49 seconds
Started Aug 05 05:17:34 PM PDT 24
Finished Aug 05 05:17:58 PM PDT 24
Peak memory 199940 kb
Host smart-b5c7d450-4319-4f98-a221-83f54e874493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202258105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2202258105
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.60814387
Short name T749
Test name
Test status
Simulation time 59406516627 ps
CPU time 97.81 seconds
Started Aug 05 05:17:36 PM PDT 24
Finished Aug 05 05:19:13 PM PDT 24
Peak memory 198880 kb
Host smart-f10494e1-10ae-4ed7-a73d-42489fe12f5a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60814387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.60814387
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1158350899
Short name T811
Test name
Test status
Simulation time 173373314957 ps
CPU time 364.73 seconds
Started Aug 05 05:17:43 PM PDT 24
Finished Aug 05 05:23:47 PM PDT 24
Peak memory 199932 kb
Host smart-6b7069a7-7c76-499a-852d-300408fab1b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1158350899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1158350899
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.4018155725
Short name T458
Test name
Test status
Simulation time 3898816867 ps
CPU time 3.15 seconds
Started Aug 05 05:17:41 PM PDT 24
Finished Aug 05 05:17:45 PM PDT 24
Peak memory 198972 kb
Host smart-e0369326-8da7-4626-990f-9d00cfd7e453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018155725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.4018155725
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2925119503
Short name T401
Test name
Test status
Simulation time 2211057894 ps
CPU time 3.88 seconds
Started Aug 05 05:17:35 PM PDT 24
Finished Aug 05 05:17:39 PM PDT 24
Peak memory 199864 kb
Host smart-d5c4148e-e2bd-4da6-8204-7e2a6fbfe783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925119503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2925119503
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3026878828
Short name T728
Test name
Test status
Simulation time 10822493545 ps
CPU time 51.23 seconds
Started Aug 05 05:17:42 PM PDT 24
Finished Aug 05 05:18:33 PM PDT 24
Peak memory 199976 kb
Host smart-1ee8ae3a-d407-4e2f-ac76-0a65816317e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3026878828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3026878828
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2728131180
Short name T430
Test name
Test status
Simulation time 2028010748 ps
CPU time 2.33 seconds
Started Aug 05 05:17:37 PM PDT 24
Finished Aug 05 05:17:40 PM PDT 24
Peak memory 197948 kb
Host smart-0f9fc523-47e5-473c-a7ff-48549532e245
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2728131180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2728131180
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3786979226
Short name T432
Test name
Test status
Simulation time 267666809633 ps
CPU time 32.47 seconds
Started Aug 05 05:17:35 PM PDT 24
Finished Aug 05 05:18:07 PM PDT 24
Peak memory 199872 kb
Host smart-60efbc30-180e-473f-91fb-df4b0fa075d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786979226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3786979226
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.143924970
Short name T971
Test name
Test status
Simulation time 1819774759 ps
CPU time 3.26 seconds
Started Aug 05 05:17:37 PM PDT 24
Finished Aug 05 05:17:40 PM PDT 24
Peak memory 195664 kb
Host smart-4e3c0c1f-6b98-4add-ae5c-77675ff4796a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143924970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.143924970
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.4040396731
Short name T685
Test name
Test status
Simulation time 889573851 ps
CPU time 3.63 seconds
Started Aug 05 05:17:37 PM PDT 24
Finished Aug 05 05:17:40 PM PDT 24
Peak memory 199612 kb
Host smart-604e1347-bba8-43b6-b2eb-26aeca6d1846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040396731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.4040396731
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1870419874
Short name T610
Test name
Test status
Simulation time 239157573957 ps
CPU time 359.06 seconds
Started Aug 05 05:17:47 PM PDT 24
Finished Aug 05 05:23:46 PM PDT 24
Peak memory 215828 kb
Host smart-5d992109-17e0-4903-b659-35d09716b027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870419874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1870419874
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1820715107
Short name T700
Test name
Test status
Simulation time 410677103586 ps
CPU time 1102.58 seconds
Started Aug 05 05:17:47 PM PDT 24
Finished Aug 05 05:36:10 PM PDT 24
Peak memory 227608 kb
Host smart-f85b5200-6e26-4f6f-8908-ecb76d268eed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820715107 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1820715107
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.46097621
Short name T687
Test name
Test status
Simulation time 1307509667 ps
CPU time 2.57 seconds
Started Aug 05 05:17:41 PM PDT 24
Finished Aug 05 05:17:43 PM PDT 24
Peak memory 198780 kb
Host smart-9b0ed167-e4c6-4338-9fe1-954776391d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46097621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.46097621
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1967405746
Short name T109
Test name
Test status
Simulation time 24203155943 ps
CPU time 44.08 seconds
Started Aug 05 05:17:34 PM PDT 24
Finished Aug 05 05:18:18 PM PDT 24
Peak memory 199988 kb
Host smart-39fadbdf-3966-46ef-a952-9c7dc24ec450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967405746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1967405746
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1591628397
Short name T742
Test name
Test status
Simulation time 19089191 ps
CPU time 0.54 seconds
Started Aug 05 05:18:06 PM PDT 24
Finished Aug 05 05:18:07 PM PDT 24
Peak memory 195356 kb
Host smart-fd17c419-c56a-4358-9038-93e52bb6cf94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591628397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1591628397
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3739636418
Short name T1132
Test name
Test status
Simulation time 21731474206 ps
CPU time 28.8 seconds
Started Aug 05 05:17:54 PM PDT 24
Finished Aug 05 05:18:23 PM PDT 24
Peak memory 199700 kb
Host smart-9efcb198-c359-4446-b9b4-0e090f3187e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739636418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3739636418
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1781323702
Short name T308
Test name
Test status
Simulation time 77073680520 ps
CPU time 73.37 seconds
Started Aug 05 05:17:52 PM PDT 24
Finished Aug 05 05:19:06 PM PDT 24
Peak memory 199976 kb
Host smart-7db55a59-8644-4e89-b7ae-86a9d684b3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781323702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1781323702
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3086422331
Short name T554
Test name
Test status
Simulation time 61791756230 ps
CPU time 7.15 seconds
Started Aug 05 05:17:54 PM PDT 24
Finished Aug 05 05:18:01 PM PDT 24
Peak memory 199900 kb
Host smart-487109ca-6600-43a7-9d6a-2c0612dff540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086422331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3086422331
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3908608808
Short name T421
Test name
Test status
Simulation time 47917317505 ps
CPU time 81.35 seconds
Started Aug 05 05:17:54 PM PDT 24
Finished Aug 05 05:19:15 PM PDT 24
Peak memory 199976 kb
Host smart-6db2d421-7ef0-4768-a568-e85813f0664a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908608808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3908608808
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.4292151018
Short name T483
Test name
Test status
Simulation time 85700601724 ps
CPU time 594.89 seconds
Started Aug 05 05:18:01 PM PDT 24
Finished Aug 05 05:27:56 PM PDT 24
Peak memory 199972 kb
Host smart-dbbac14e-7ea4-4e22-85ec-643e82e70148
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4292151018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.4292151018
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3075511514
Short name T788
Test name
Test status
Simulation time 4643262607 ps
CPU time 5.06 seconds
Started Aug 05 05:17:59 PM PDT 24
Finished Aug 05 05:18:04 PM PDT 24
Peak memory 197864 kb
Host smart-71f6435b-f9e6-448d-b37c-fd7a7f56b77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075511514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3075511514
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.613888377
Short name T582
Test name
Test status
Simulation time 230489947929 ps
CPU time 123.57 seconds
Started Aug 05 05:17:53 PM PDT 24
Finished Aug 05 05:19:56 PM PDT 24
Peak memory 200076 kb
Host smart-b3683c82-3aa7-4d05-8f6c-13fb75173037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613888377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.613888377
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1078539182
Short name T849
Test name
Test status
Simulation time 21830689978 ps
CPU time 134.12 seconds
Started Aug 05 05:17:58 PM PDT 24
Finished Aug 05 05:20:13 PM PDT 24
Peak memory 199936 kb
Host smart-6fcc4451-4872-4d58-b6b5-73b542c9c4c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1078539182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1078539182
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.4282855132
Short name T575
Test name
Test status
Simulation time 4369750364 ps
CPU time 8.02 seconds
Started Aug 05 05:17:58 PM PDT 24
Finished Aug 05 05:18:06 PM PDT 24
Peak memory 198104 kb
Host smart-706bd0c8-d10c-4ca2-84f8-bd0e538eb04a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4282855132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.4282855132
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2429228238
Short name T374
Test name
Test status
Simulation time 47141259516 ps
CPU time 85.31 seconds
Started Aug 05 05:18:00 PM PDT 24
Finished Aug 05 05:19:25 PM PDT 24
Peak memory 199848 kb
Host smart-aaee3825-f597-44be-97ff-526322962a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429228238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2429228238
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2697844917
Short name T353
Test name
Test status
Simulation time 82828240736 ps
CPU time 15.54 seconds
Started Aug 05 05:17:53 PM PDT 24
Finished Aug 05 05:18:09 PM PDT 24
Peak memory 196064 kb
Host smart-207f313f-c351-4d27-88ec-c5da5ed6b270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697844917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2697844917
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1985581857
Short name T868
Test name
Test status
Simulation time 250080927 ps
CPU time 1.52 seconds
Started Aug 05 05:17:47 PM PDT 24
Finished Aug 05 05:17:49 PM PDT 24
Peak memory 198272 kb
Host smart-11c83743-662f-4194-b579-de323712285c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985581857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1985581857
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2213671963
Short name T871
Test name
Test status
Simulation time 114206466042 ps
CPU time 1305.47 seconds
Started Aug 05 05:18:01 PM PDT 24
Finished Aug 05 05:39:47 PM PDT 24
Peak memory 199908 kb
Host smart-6e2869d4-5a12-47b1-ac82-0b4cece26128
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213671963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2213671963
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1927779974
Short name T769
Test name
Test status
Simulation time 29527729440 ps
CPU time 588.79 seconds
Started Aug 05 05:18:00 PM PDT 24
Finished Aug 05 05:27:49 PM PDT 24
Peak memory 216608 kb
Host smart-fd3602d0-4c0f-45be-aa0f-22b56af9d1a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927779974 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1927779974
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2110520844
Short name T631
Test name
Test status
Simulation time 904552754 ps
CPU time 1.38 seconds
Started Aug 05 05:17:51 PM PDT 24
Finished Aug 05 05:17:52 PM PDT 24
Peak memory 198752 kb
Host smart-fc1902cf-77fa-4b27-b19a-4a145b3fc6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110520844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2110520844
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1775644497
Short name T383
Test name
Test status
Simulation time 96426694470 ps
CPU time 37.89 seconds
Started Aug 05 05:17:48 PM PDT 24
Finished Aug 05 05:18:26 PM PDT 24
Peak memory 199904 kb
Host smart-3086e80d-a0cf-4cb7-a4a4-8bf9bf23a55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775644497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1775644497
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.1293613381
Short name T341
Test name
Test status
Simulation time 14416124 ps
CPU time 0.55 seconds
Started Aug 05 05:13:47 PM PDT 24
Finished Aug 05 05:13:47 PM PDT 24
Peak memory 195280 kb
Host smart-b7b88230-3fbe-4e90-b32c-4ff00672a9d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293613381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1293613381
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.4208885845
Short name T1097
Test name
Test status
Simulation time 73583246857 ps
CPU time 35.28 seconds
Started Aug 05 05:13:45 PM PDT 24
Finished Aug 05 05:14:20 PM PDT 24
Peak memory 199932 kb
Host smart-9f6b3085-e938-4e93-9d48-eef34f24e636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208885845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.4208885845
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3587519834
Short name T964
Test name
Test status
Simulation time 79412621611 ps
CPU time 97.07 seconds
Started Aug 05 05:13:50 PM PDT 24
Finished Aug 05 05:15:27 PM PDT 24
Peak memory 199840 kb
Host smart-819f2b14-3632-4b39-9882-6a5b65284866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587519834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3587519834
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3598336889
Short name T222
Test name
Test status
Simulation time 94100224888 ps
CPU time 33.82 seconds
Started Aug 05 05:13:41 PM PDT 24
Finished Aug 05 05:14:15 PM PDT 24
Peak memory 199968 kb
Host smart-bddfb40e-5438-4741-90cb-ec00355981b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598336889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3598336889
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.425950678
Short name T1115
Test name
Test status
Simulation time 38428005646 ps
CPU time 66.16 seconds
Started Aug 05 05:13:42 PM PDT 24
Finished Aug 05 05:14:48 PM PDT 24
Peak memory 199984 kb
Host smart-48bc1582-9dc4-42fa-955f-dec844e84003
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425950678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.425950678
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1024247425
Short name T1141
Test name
Test status
Simulation time 250773305369 ps
CPU time 187.5 seconds
Started Aug 05 05:13:49 PM PDT 24
Finished Aug 05 05:16:57 PM PDT 24
Peak memory 199792 kb
Host smart-58b2076d-45d3-4089-85f1-b79e31648aa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1024247425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1024247425
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2242365608
Short name T1039
Test name
Test status
Simulation time 208257868 ps
CPU time 0.77 seconds
Started Aug 05 05:13:45 PM PDT 24
Finished Aug 05 05:13:46 PM PDT 24
Peak memory 196068 kb
Host smart-ee95c264-d1bd-4871-a4a5-b5024ca561d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242365608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2242365608
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.1739103609
Short name T696
Test name
Test status
Simulation time 43709038683 ps
CPU time 66.03 seconds
Started Aug 05 05:13:43 PM PDT 24
Finished Aug 05 05:14:49 PM PDT 24
Peak memory 198984 kb
Host smart-ee4d7cad-ecde-4442-b855-7dec48496902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739103609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.1739103609
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.1995704045
Short name T671
Test name
Test status
Simulation time 20518220878 ps
CPU time 238.46 seconds
Started Aug 05 05:13:50 PM PDT 24
Finished Aug 05 05:17:48 PM PDT 24
Peak memory 199916 kb
Host smart-02111892-960d-49f4-866b-65ff04f27470
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1995704045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1995704045
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.4148375095
Short name T945
Test name
Test status
Simulation time 2003936964 ps
CPU time 5.09 seconds
Started Aug 05 05:13:46 PM PDT 24
Finished Aug 05 05:13:51 PM PDT 24
Peak memory 198284 kb
Host smart-237020af-8a00-4ba8-9171-dc2fcf9d56d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4148375095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.4148375095
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3963985887
Short name T923
Test name
Test status
Simulation time 87231284049 ps
CPU time 28.48 seconds
Started Aug 05 05:13:44 PM PDT 24
Finished Aug 05 05:14:12 PM PDT 24
Peak memory 199932 kb
Host smart-b7249623-2f95-4460-8b1b-f97c49a8c1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963985887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3963985887
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1192574291
Short name T1145
Test name
Test status
Simulation time 3493729339 ps
CPU time 3.36 seconds
Started Aug 05 05:13:40 PM PDT 24
Finished Aug 05 05:13:43 PM PDT 24
Peak memory 196524 kb
Host smart-fc77d163-8680-4adb-af76-70c85137dca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192574291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1192574291
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.107869860
Short name T605
Test name
Test status
Simulation time 626279377 ps
CPU time 2.78 seconds
Started Aug 05 05:13:42 PM PDT 24
Finished Aug 05 05:13:45 PM PDT 24
Peak memory 198668 kb
Host smart-df0736cf-e7fd-43bc-bff5-9e44492589ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107869860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.107869860
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3926892740
Short name T724
Test name
Test status
Simulation time 232041008873 ps
CPU time 178.72 seconds
Started Aug 05 05:13:49 PM PDT 24
Finished Aug 05 05:16:48 PM PDT 24
Peak memory 199800 kb
Host smart-a1c5bbd8-1e2f-4a2f-a47a-66f35b7cbfda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926892740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3926892740
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2034055862
Short name T1143
Test name
Test status
Simulation time 979413896304 ps
CPU time 1750.1 seconds
Started Aug 05 05:13:50 PM PDT 24
Finished Aug 05 05:43:00 PM PDT 24
Peak memory 232972 kb
Host smart-dc673d1a-8bb7-457c-8c6c-ab4e50479fcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034055862 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2034055862
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3783414123
Short name T303
Test name
Test status
Simulation time 2105799701 ps
CPU time 2.3 seconds
Started Aug 05 05:13:46 PM PDT 24
Finished Aug 05 05:13:48 PM PDT 24
Peak memory 198832 kb
Host smart-e7e19465-4a63-4ef1-848e-dec040cd7683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783414123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3783414123
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1284216727
Short name T553
Test name
Test status
Simulation time 22439367427 ps
CPU time 12.12 seconds
Started Aug 05 05:13:41 PM PDT 24
Finished Aug 05 05:13:53 PM PDT 24
Peak memory 196920 kb
Host smart-ad5c261b-1d07-4435-8d79-b33c0b8e5527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284216727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1284216727
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2448564274
Short name T1125
Test name
Test status
Simulation time 103712159313 ps
CPU time 71.75 seconds
Started Aug 05 05:18:06 PM PDT 24
Finished Aug 05 05:19:18 PM PDT 24
Peak memory 199848 kb
Host smart-a606f4b7-ec69-41f1-b2f2-4206d1c1676c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448564274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2448564274
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1523388971
Short name T1016
Test name
Test status
Simulation time 79922140830 ps
CPU time 267.24 seconds
Started Aug 05 05:18:06 PM PDT 24
Finished Aug 05 05:22:34 PM PDT 24
Peak memory 209260 kb
Host smart-f1546aaf-b1d3-4ae0-af8d-bd8bff99b8f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523388971 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1523388971
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.669463707
Short name T1020
Test name
Test status
Simulation time 43335400966 ps
CPU time 142.89 seconds
Started Aug 05 05:18:06 PM PDT 24
Finished Aug 05 05:20:29 PM PDT 24
Peak memory 199932 kb
Host smart-205cb020-d099-412b-904b-599cc4df7062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669463707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.669463707
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.4159343180
Short name T119
Test name
Test status
Simulation time 103902527353 ps
CPU time 1661.62 seconds
Started Aug 05 05:18:07 PM PDT 24
Finished Aug 05 05:45:49 PM PDT 24
Peak memory 227092 kb
Host smart-b6790d89-01b4-4d32-a248-a96b8d5c0287
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159343180 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.4159343180
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2849416084
Short name T1038
Test name
Test status
Simulation time 65717413525 ps
CPU time 527.73 seconds
Started Aug 05 05:18:14 PM PDT 24
Finished Aug 05 05:27:02 PM PDT 24
Peak memory 216600 kb
Host smart-1316baea-882e-4b6b-8e1c-c3b6cd1b1352
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849416084 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2849416084
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3810181447
Short name T662
Test name
Test status
Simulation time 93303950427 ps
CPU time 704.27 seconds
Started Aug 05 05:18:15 PM PDT 24
Finished Aug 05 05:29:59 PM PDT 24
Peak memory 199832 kb
Host smart-91fb2757-8856-44dc-9889-535694a337cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810181447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3810181447
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2624609545
Short name T800
Test name
Test status
Simulation time 78556805666 ps
CPU time 214.15 seconds
Started Aug 05 05:18:17 PM PDT 24
Finished Aug 05 05:21:52 PM PDT 24
Peak memory 216564 kb
Host smart-10b9a96a-462c-42aa-a9a9-bc63a12fd427
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624609545 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2624609545
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3314844954
Short name T706
Test name
Test status
Simulation time 82884753110 ps
CPU time 37.99 seconds
Started Aug 05 05:18:42 PM PDT 24
Finished Aug 05 05:19:20 PM PDT 24
Peak memory 200024 kb
Host smart-c19fd75b-d13f-463f-b203-72ebbb211d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314844954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3314844954
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2210829542
Short name T563
Test name
Test status
Simulation time 208354642336 ps
CPU time 594.98 seconds
Started Aug 05 05:18:21 PM PDT 24
Finished Aug 05 05:28:17 PM PDT 24
Peak memory 230432 kb
Host smart-8bcca5bb-3e32-4bd1-b620-370938c8a613
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210829542 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2210829542
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.884066516
Short name T727
Test name
Test status
Simulation time 115935550600 ps
CPU time 82.3 seconds
Started Aug 05 05:18:25 PM PDT 24
Finished Aug 05 05:19:47 PM PDT 24
Peak memory 199896 kb
Host smart-3a1ad7f8-c653-4791-b9d5-2973603c8624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884066516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.884066516
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.4247383978
Short name T31
Test name
Test status
Simulation time 79625707843 ps
CPU time 176.43 seconds
Started Aug 05 05:18:23 PM PDT 24
Finished Aug 05 05:21:20 PM PDT 24
Peak memory 208228 kb
Host smart-15779d84-b244-46da-8638-a9cff11ac1ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247383978 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.4247383978
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3709402499
Short name T718
Test name
Test status
Simulation time 113778879704 ps
CPU time 188.5 seconds
Started Aug 05 05:18:21 PM PDT 24
Finished Aug 05 05:21:29 PM PDT 24
Peak memory 199952 kb
Host smart-2d2e486f-6be8-4bbb-a35a-3ee05c115f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709402499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3709402499
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2920445575
Short name T59
Test name
Test status
Simulation time 185702503786 ps
CPU time 2456.48 seconds
Started Aug 05 05:18:22 PM PDT 24
Finished Aug 05 05:59:18 PM PDT 24
Peak memory 232852 kb
Host smart-24e9407a-cf57-4eb6-ad24-a5673fa4b100
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920445575 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2920445575
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1804056401
Short name T656
Test name
Test status
Simulation time 20710666939 ps
CPU time 34.3 seconds
Started Aug 05 05:18:21 PM PDT 24
Finished Aug 05 05:18:55 PM PDT 24
Peak memory 199776 kb
Host smart-1cff9d61-ce61-4c34-b885-d64b00d1066e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804056401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1804056401
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2443554590
Short name T729
Test name
Test status
Simulation time 41358736276 ps
CPU time 698.4 seconds
Started Aug 05 05:18:24 PM PDT 24
Finished Aug 05 05:30:02 PM PDT 24
Peak memory 216496 kb
Host smart-dab7b9f0-5827-4b78-a2f5-d5c2d70fe955
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443554590 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2443554590
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2664678865
Short name T982
Test name
Test status
Simulation time 63686995303 ps
CPU time 27.72 seconds
Started Aug 05 05:18:20 PM PDT 24
Finished Aug 05 05:18:48 PM PDT 24
Peak memory 199844 kb
Host smart-1a5f0bc3-f4c3-46fa-9567-01dedc54bdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664678865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2664678865
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1042051117
Short name T167
Test name
Test status
Simulation time 25237494770 ps
CPU time 145.4 seconds
Started Aug 05 05:18:20 PM PDT 24
Finished Aug 05 05:20:45 PM PDT 24
Peak memory 215500 kb
Host smart-11bbe443-28f4-407b-8ca9-ba26e93d97c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042051117 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1042051117
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2116208182
Short name T1092
Test name
Test status
Simulation time 43437904 ps
CPU time 0.56 seconds
Started Aug 05 05:13:51 PM PDT 24
Finished Aug 05 05:13:52 PM PDT 24
Peak memory 195336 kb
Host smart-5c111c11-7d01-48c5-862a-04734c1c0e2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116208182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2116208182
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3734657896
Short name T926
Test name
Test status
Simulation time 109331344959 ps
CPU time 271.5 seconds
Started Aug 05 05:13:50 PM PDT 24
Finished Aug 05 05:18:22 PM PDT 24
Peak memory 199964 kb
Host smart-356893f6-1cb0-421e-99f5-0f78a2d4bc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734657896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3734657896
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.368323074
Short name T1037
Test name
Test status
Simulation time 41437053770 ps
CPU time 33.7 seconds
Started Aug 05 05:13:50 PM PDT 24
Finished Aug 05 05:14:24 PM PDT 24
Peak memory 199920 kb
Host smart-9aa44992-df6c-4a3c-a5ef-82beb810adfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368323074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.368323074
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2495774794
Short name T1080
Test name
Test status
Simulation time 24970681123 ps
CPU time 40.9 seconds
Started Aug 05 05:13:47 PM PDT 24
Finished Aug 05 05:14:29 PM PDT 24
Peak memory 199872 kb
Host smart-57ac862b-19cc-46be-9c5f-e34f461a8955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495774794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2495774794
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.4193900811
Short name T984
Test name
Test status
Simulation time 3123019183 ps
CPU time 2.8 seconds
Started Aug 05 05:13:49 PM PDT 24
Finished Aug 05 05:13:51 PM PDT 24
Peak memory 199676 kb
Host smart-0318877c-44f1-4c5c-a07a-39dededc17b0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193900811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.4193900811
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3510462212
Short name T680
Test name
Test status
Simulation time 121987506941 ps
CPU time 177 seconds
Started Aug 05 05:13:50 PM PDT 24
Finished Aug 05 05:16:47 PM PDT 24
Peak memory 199916 kb
Host smart-dd307c9a-39fe-4514-a9ae-62c98af9a014
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3510462212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3510462212
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.394972403
Short name T873
Test name
Test status
Simulation time 7679034408 ps
CPU time 24.99 seconds
Started Aug 05 05:13:49 PM PDT 24
Finished Aug 05 05:14:14 PM PDT 24
Peak memory 199388 kb
Host smart-9162b132-44b9-4fa3-b007-b366b490fac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394972403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.394972403
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3831215865
Short name T111
Test name
Test status
Simulation time 120482533024 ps
CPU time 245.44 seconds
Started Aug 05 05:13:48 PM PDT 24
Finished Aug 05 05:17:53 PM PDT 24
Peak memory 208232 kb
Host smart-50c9cc22-5988-4178-a207-a53cfa543729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831215865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3831215865
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.351764349
Short name T486
Test name
Test status
Simulation time 16232226124 ps
CPU time 675.15 seconds
Started Aug 05 05:13:50 PM PDT 24
Finished Aug 05 05:25:05 PM PDT 24
Peak memory 199916 kb
Host smart-9b997383-6a20-4d9c-b0e1-a21686387390
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=351764349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.351764349
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.767681262
Short name T599
Test name
Test status
Simulation time 7363830205 ps
CPU time 70.58 seconds
Started Aug 05 05:13:51 PM PDT 24
Finished Aug 05 05:15:02 PM PDT 24
Peak memory 198124 kb
Host smart-30b87b22-b4b5-46fa-b8d4-e7999dc81ce7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=767681262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.767681262
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.4290487032
Short name T670
Test name
Test status
Simulation time 207213165028 ps
CPU time 26.82 seconds
Started Aug 05 05:13:51 PM PDT 24
Finished Aug 05 05:14:18 PM PDT 24
Peak memory 198640 kb
Host smart-b32b3cd8-1466-4e74-acb0-6f94fd622dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290487032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.4290487032
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.799809891
Short name T795
Test name
Test status
Simulation time 3919078834 ps
CPU time 1.03 seconds
Started Aug 05 05:13:52 PM PDT 24
Finished Aug 05 05:13:53 PM PDT 24
Peak memory 196496 kb
Host smart-60393333-6215-48c0-85b2-7fa5ec20fbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799809891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.799809891
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2158394107
Short name T488
Test name
Test status
Simulation time 5725310914 ps
CPU time 10.01 seconds
Started Aug 05 05:13:52 PM PDT 24
Finished Aug 05 05:14:02 PM PDT 24
Peak memory 199708 kb
Host smart-cb1ba51c-8f20-452b-8120-d9eeadb9b6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158394107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2158394107
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.3760411936
Short name T664
Test name
Test status
Simulation time 270592097119 ps
CPU time 390.99 seconds
Started Aug 05 05:13:51 PM PDT 24
Finished Aug 05 05:20:22 PM PDT 24
Peak memory 199892 kb
Host smart-ba760ce3-c3a3-4685-b465-673675009f4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760411936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3760411936
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2827245933
Short name T634
Test name
Test status
Simulation time 122877775270 ps
CPU time 765.47 seconds
Started Aug 05 05:13:52 PM PDT 24
Finished Aug 05 05:26:38 PM PDT 24
Peak memory 224744 kb
Host smart-95df26e0-fc84-4e63-ab24-017ee43fcc72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827245933 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2827245933
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.898509175
Short name T625
Test name
Test status
Simulation time 716470419 ps
CPU time 2.35 seconds
Started Aug 05 05:13:48 PM PDT 24
Finished Aug 05 05:13:50 PM PDT 24
Peak memory 198868 kb
Host smart-5af41038-9859-40ad-9bf2-72f7c75a6471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898509175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.898509175
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1130925850
Short name T278
Test name
Test status
Simulation time 69419679420 ps
CPU time 28.4 seconds
Started Aug 05 05:13:56 PM PDT 24
Finished Aug 05 05:14:25 PM PDT 24
Peak memory 199764 kb
Host smart-05c271e9-1f67-493b-9b65-a631a82faa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130925850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1130925850
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1722323266
Short name T626
Test name
Test status
Simulation time 80538854535 ps
CPU time 33.8 seconds
Started Aug 05 05:18:21 PM PDT 24
Finished Aug 05 05:18:55 PM PDT 24
Peak memory 199924 kb
Host smart-62e000af-3ea1-4291-9e37-084011e39840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722323266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1722323266
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.944377416
Short name T85
Test name
Test status
Simulation time 43075519500 ps
CPU time 608.64 seconds
Started Aug 05 05:18:25 PM PDT 24
Finished Aug 05 05:28:33 PM PDT 24
Peak memory 212564 kb
Host smart-a1f0b4a1-9373-42a8-a163-9399ef2058b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944377416 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.944377416
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3199570531
Short name T492
Test name
Test status
Simulation time 30640432650 ps
CPU time 49.28 seconds
Started Aug 05 05:18:22 PM PDT 24
Finished Aug 05 05:19:11 PM PDT 24
Peak memory 199932 kb
Host smart-8b74cb6b-e9cc-433c-8d42-fab0e1b8c2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199570531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3199570531
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.629464385
Short name T1103
Test name
Test status
Simulation time 68394189249 ps
CPU time 223.52 seconds
Started Aug 05 05:18:22 PM PDT 24
Finished Aug 05 05:22:06 PM PDT 24
Peak memory 216416 kb
Host smart-fd93121b-b225-4dce-851c-41c0de389cb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629464385 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.629464385
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2867769108
Short name T213
Test name
Test status
Simulation time 151815361785 ps
CPU time 136.96 seconds
Started Aug 05 05:18:19 PM PDT 24
Finished Aug 05 05:20:36 PM PDT 24
Peak memory 199908 kb
Host smart-f1934687-ac07-439a-8112-ada965979d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867769108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2867769108
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1676522710
Short name T61
Test name
Test status
Simulation time 101118284790 ps
CPU time 729.89 seconds
Started Aug 05 05:18:26 PM PDT 24
Finished Aug 05 05:30:36 PM PDT 24
Peak memory 224712 kb
Host smart-28664aca-61db-45f1-ae44-45de0c13da0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676522710 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1676522710
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.4168099577
Short name T246
Test name
Test status
Simulation time 25902966685 ps
CPU time 107.44 seconds
Started Aug 05 05:18:27 PM PDT 24
Finished Aug 05 05:20:15 PM PDT 24
Peak memory 199828 kb
Host smart-22b81dc3-85ca-440f-a773-72132d0b6e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168099577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.4168099577
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3850746487
Short name T1180
Test name
Test status
Simulation time 93749231333 ps
CPU time 600.29 seconds
Started Aug 05 05:18:27 PM PDT 24
Finished Aug 05 05:28:27 PM PDT 24
Peak memory 216656 kb
Host smart-04a328ea-1ff6-4f33-a407-f835862222be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850746487 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3850746487
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.4237656146
Short name T911
Test name
Test status
Simulation time 109866929935 ps
CPU time 57.79 seconds
Started Aug 05 05:18:28 PM PDT 24
Finished Aug 05 05:19:26 PM PDT 24
Peak memory 199932 kb
Host smart-7fcc2ee5-453a-441f-9e2f-1f93c93afb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237656146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.4237656146
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.700510008
Short name T814
Test name
Test status
Simulation time 43739983079 ps
CPU time 240.05 seconds
Started Aug 05 05:18:26 PM PDT 24
Finished Aug 05 05:22:26 PM PDT 24
Peak memory 215224 kb
Host smart-607b7488-6c80-42bc-aa92-7c5b085c4813
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700510008 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.700510008
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.668087523
Short name T807
Test name
Test status
Simulation time 155104762984 ps
CPU time 26.95 seconds
Started Aug 05 05:18:30 PM PDT 24
Finished Aug 05 05:18:57 PM PDT 24
Peak memory 199956 kb
Host smart-69292aff-4be4-4038-b609-bafa385c9d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668087523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.668087523
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.866110126
Short name T708
Test name
Test status
Simulation time 311480104514 ps
CPU time 1055.01 seconds
Started Aug 05 05:18:36 PM PDT 24
Finished Aug 05 05:36:11 PM PDT 24
Peak memory 216648 kb
Host smart-dcc63646-d392-4f26-8723-b5b2b157aa23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866110126 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.866110126
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3983437794
Short name T915
Test name
Test status
Simulation time 150974738384 ps
CPU time 309.95 seconds
Started Aug 05 05:18:34 PM PDT 24
Finished Aug 05 05:23:44 PM PDT 24
Peak memory 199864 kb
Host smart-0529b79e-a965-4523-8efc-1e8d34d02d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983437794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3983437794
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.72399549
Short name T862
Test name
Test status
Simulation time 85285496743 ps
CPU time 348.22 seconds
Started Aug 05 05:18:34 PM PDT 24
Finished Aug 05 05:24:22 PM PDT 24
Peak memory 216564 kb
Host smart-15ab3ab9-6e57-4b9e-9404-c57526cc8e33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72399549 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.72399549
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2703606089
Short name T556
Test name
Test status
Simulation time 17057694374 ps
CPU time 25.47 seconds
Started Aug 05 05:18:32 PM PDT 24
Finished Aug 05 05:18:58 PM PDT 24
Peak memory 199976 kb
Host smart-8ddfba94-ab3f-46c4-b372-c2088fb4b517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703606089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2703606089
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.4114143700
Short name T947
Test name
Test status
Simulation time 24638108988 ps
CPU time 279.7 seconds
Started Aug 05 05:18:33 PM PDT 24
Finished Aug 05 05:23:13 PM PDT 24
Peak memory 216484 kb
Host smart-3470a2af-4d39-41f8-882e-db423d48b59b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114143700 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.4114143700
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3666203039
Short name T925
Test name
Test status
Simulation time 29782088862 ps
CPU time 43.32 seconds
Started Aug 05 05:18:34 PM PDT 24
Finished Aug 05 05:19:17 PM PDT 24
Peak memory 199988 kb
Host smart-d159765a-d8d3-4518-8c07-067471df5d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666203039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3666203039
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.903368478
Short name T1163
Test name
Test status
Simulation time 53875557466 ps
CPU time 275.58 seconds
Started Aug 05 05:18:34 PM PDT 24
Finished Aug 05 05:23:10 PM PDT 24
Peak memory 216468 kb
Host smart-475d1583-811a-4622-b47d-2a78814738c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903368478 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.903368478
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.35023710
Short name T346
Test name
Test status
Simulation time 21835122 ps
CPU time 0.57 seconds
Started Aug 05 05:13:58 PM PDT 24
Finished Aug 05 05:13:59 PM PDT 24
Peak memory 195328 kb
Host smart-7cd0fa5f-86e2-4e1d-978b-103f822bf82b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35023710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.35023710
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2679663285
Short name T853
Test name
Test status
Simulation time 208685639421 ps
CPU time 83.09 seconds
Started Aug 05 05:13:50 PM PDT 24
Finished Aug 05 05:15:13 PM PDT 24
Peak memory 200000 kb
Host smart-eea3dd9c-1ea3-481e-baad-2fae96fae530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679663285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2679663285
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.203127049
Short name T1012
Test name
Test status
Simulation time 21082934345 ps
CPU time 35.26 seconds
Started Aug 05 05:13:49 PM PDT 24
Finished Aug 05 05:14:25 PM PDT 24
Peak memory 199916 kb
Host smart-3efefff1-d7aa-4406-b750-8413f82c4c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203127049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.203127049
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1994827977
Short name T801
Test name
Test status
Simulation time 27058951336 ps
CPU time 14.23 seconds
Started Aug 05 05:13:50 PM PDT 24
Finished Aug 05 05:14:05 PM PDT 24
Peak memory 199896 kb
Host smart-80036bef-7fac-46f3-b291-ea37640c240a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994827977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1994827977
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.4136318817
Short name T1114
Test name
Test status
Simulation time 235870796840 ps
CPU time 187.35 seconds
Started Aug 05 05:13:51 PM PDT 24
Finished Aug 05 05:16:58 PM PDT 24
Peak memory 197476 kb
Host smart-6843305e-729b-4a9d-9637-43bb5419f68c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136318817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.4136318817
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.548663142
Short name T732
Test name
Test status
Simulation time 120542594791 ps
CPU time 632.21 seconds
Started Aug 05 05:13:58 PM PDT 24
Finished Aug 05 05:24:31 PM PDT 24
Peak memory 199884 kb
Host smart-3e4bd034-c227-4cfa-b1ba-5b064bf732ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=548663142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.548663142
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1187392542
Short name T745
Test name
Test status
Simulation time 3893355892 ps
CPU time 13.21 seconds
Started Aug 05 05:13:54 PM PDT 24
Finished Aug 05 05:14:07 PM PDT 24
Peak memory 198272 kb
Host smart-e66dd26f-4029-48d4-bf62-cdddac0be189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187392542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1187392542
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2533123967
Short name T328
Test name
Test status
Simulation time 52100868764 ps
CPU time 82.46 seconds
Started Aug 05 05:13:50 PM PDT 24
Finished Aug 05 05:15:13 PM PDT 24
Peak memory 199432 kb
Host smart-a3bae139-d4ad-419e-8732-9f06b7c4da76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533123967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2533123967
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.3561324681
Short name T438
Test name
Test status
Simulation time 20996564022 ps
CPU time 617.33 seconds
Started Aug 05 05:13:54 PM PDT 24
Finished Aug 05 05:24:12 PM PDT 24
Peak memory 199900 kb
Host smart-9ac0b1e6-fbc9-43e5-a5c1-3b6ac9b305cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561324681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3561324681
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.983309162
Short name T693
Test name
Test status
Simulation time 4373752007 ps
CPU time 38.25 seconds
Started Aug 05 05:13:49 PM PDT 24
Finished Aug 05 05:14:27 PM PDT 24
Peak memory 198600 kb
Host smart-0dd2cf49-9092-4c46-8303-b1b6789723b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=983309162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.983309162
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.942621635
Short name T959
Test name
Test status
Simulation time 192884759753 ps
CPU time 37.75 seconds
Started Aug 05 05:13:57 PM PDT 24
Finished Aug 05 05:14:35 PM PDT 24
Peak memory 199916 kb
Host smart-50cc1e14-ae6e-4234-9f9e-880089be1840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942621635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.942621635
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1146199863
Short name T19
Test name
Test status
Simulation time 2101926472 ps
CPU time 4.13 seconds
Started Aug 05 05:13:55 PM PDT 24
Finished Aug 05 05:13:59 PM PDT 24
Peak memory 195644 kb
Host smart-5f6bf84b-8277-4f61-bee4-c2e663ee42d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146199863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1146199863
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.4010213372
Short name T471
Test name
Test status
Simulation time 300342974 ps
CPU time 1.12 seconds
Started Aug 05 05:13:52 PM PDT 24
Finished Aug 05 05:13:53 PM PDT 24
Peak memory 198496 kb
Host smart-33be4a36-e567-4f20-9131-7eec9042d253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010213372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.4010213372
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.3631799063
Short name T1014
Test name
Test status
Simulation time 50319994091 ps
CPU time 273.41 seconds
Started Aug 05 05:13:55 PM PDT 24
Finished Aug 05 05:18:29 PM PDT 24
Peak memory 199800 kb
Host smart-ba3b31f7-fc26-4db4-9108-5091d31c2f0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631799063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3631799063
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3631605477
Short name T1031
Test name
Test status
Simulation time 52505499749 ps
CPU time 598.64 seconds
Started Aug 05 05:13:55 PM PDT 24
Finished Aug 05 05:23:54 PM PDT 24
Peak memory 216380 kb
Host smart-329b8698-1830-4c6a-acc7-877fa27b1d51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631605477 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3631605477
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2925741725
Short name T616
Test name
Test status
Simulation time 1482229699 ps
CPU time 2.35 seconds
Started Aug 05 05:13:57 PM PDT 24
Finished Aug 05 05:13:59 PM PDT 24
Peak memory 198928 kb
Host smart-4a08ff90-c903-4f8b-b144-e106b2b6dd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925741725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2925741725
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.481616439
Short name T934
Test name
Test status
Simulation time 120866087323 ps
CPU time 272.57 seconds
Started Aug 05 05:13:50 PM PDT 24
Finished Aug 05 05:18:23 PM PDT 24
Peak memory 199528 kb
Host smart-e94a8871-da9d-47b6-b3e8-74ede336ff60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481616439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.481616439
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2974240928
Short name T884
Test name
Test status
Simulation time 52491476428 ps
CPU time 22.24 seconds
Started Aug 05 05:18:33 PM PDT 24
Finished Aug 05 05:18:56 PM PDT 24
Peak memory 199624 kb
Host smart-3145e949-9082-4df0-ac8e-753f702495ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974240928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2974240928
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.624893089
Short name T1121
Test name
Test status
Simulation time 25141799012 ps
CPU time 300.37 seconds
Started Aug 05 05:18:37 PM PDT 24
Finished Aug 05 05:23:37 PM PDT 24
Peak memory 215356 kb
Host smart-2c3cba8b-0d4f-4aca-96f4-e87aa08dcdc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624893089 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.624893089
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1668461411
Short name T1139
Test name
Test status
Simulation time 80656955539 ps
CPU time 53.66 seconds
Started Aug 05 05:18:33 PM PDT 24
Finished Aug 05 05:19:26 PM PDT 24
Peak memory 199848 kb
Host smart-872da690-6ec0-47e2-8c96-a073ccc2d958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668461411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1668461411
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1569846561
Short name T784
Test name
Test status
Simulation time 704748865785 ps
CPU time 540.1 seconds
Started Aug 05 05:18:43 PM PDT 24
Finished Aug 05 05:27:43 PM PDT 24
Peak memory 216420 kb
Host smart-23ea957a-268d-4f78-bfa3-1c8876960675
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569846561 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1569846561
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1822130905
Short name T1015
Test name
Test status
Simulation time 92892363308 ps
CPU time 13.41 seconds
Started Aug 05 05:18:42 PM PDT 24
Finished Aug 05 05:18:55 PM PDT 24
Peak memory 199868 kb
Host smart-eeb56ec4-25a3-4ce1-ba1d-94aa5014a6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822130905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1822130905
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1906949099
Short name T120
Test name
Test status
Simulation time 331556960664 ps
CPU time 1847.82 seconds
Started Aug 05 05:18:43 PM PDT 24
Finished Aug 05 05:49:31 PM PDT 24
Peak memory 231176 kb
Host smart-0f750a33-eb09-4de5-b2c5-de9c21252cdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906949099 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1906949099
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.929681473
Short name T6
Test name
Test status
Simulation time 38959195372 ps
CPU time 33.21 seconds
Started Aug 05 05:18:38 PM PDT 24
Finished Aug 05 05:19:12 PM PDT 24
Peak memory 199968 kb
Host smart-db98b2a8-9e5b-47a4-958a-f09579a38593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929681473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.929681473
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1223197631
Short name T1024
Test name
Test status
Simulation time 64863011011 ps
CPU time 526.11 seconds
Started Aug 05 05:18:43 PM PDT 24
Finished Aug 05 05:27:29 PM PDT 24
Peak memory 216428 kb
Host smart-a9138952-a18a-4c87-bec1-9c9d3545affc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223197631 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1223197631
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.653705753
Short name T1124
Test name
Test status
Simulation time 122300945922 ps
CPU time 41 seconds
Started Aug 05 05:18:38 PM PDT 24
Finished Aug 05 05:19:19 PM PDT 24
Peak memory 199888 kb
Host smart-06721219-54f0-4b7f-be51-ab28693a5466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653705753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.653705753
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3778194486
Short name T58
Test name
Test status
Simulation time 159341704799 ps
CPU time 973.5 seconds
Started Aug 05 05:18:39 PM PDT 24
Finished Aug 05 05:34:52 PM PDT 24
Peak memory 224836 kb
Host smart-7bdd11b2-a707-4c7c-b351-1ac83a9f3d01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778194486 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3778194486
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.354613433
Short name T39
Test name
Test status
Simulation time 43173422329 ps
CPU time 34.79 seconds
Started Aug 05 05:18:41 PM PDT 24
Finished Aug 05 05:19:16 PM PDT 24
Peak memory 199860 kb
Host smart-722b4a42-2b9a-42e8-a4f2-f3115ab41860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354613433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.354613433
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2652447251
Short name T562
Test name
Test status
Simulation time 135151134853 ps
CPU time 163.24 seconds
Started Aug 05 05:18:38 PM PDT 24
Finished Aug 05 05:21:22 PM PDT 24
Peak memory 199924 kb
Host smart-ee4b8da7-27ec-4b46-9fff-6a926a0645ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652447251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2652447251
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3706345060
Short name T55
Test name
Test status
Simulation time 282631834219 ps
CPU time 926.73 seconds
Started Aug 05 05:18:39 PM PDT 24
Finished Aug 05 05:34:06 PM PDT 24
Peak memory 231848 kb
Host smart-7c11cfdd-872d-4679-a1e8-30e399bb6db7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706345060 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3706345060
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.752110726
Short name T861
Test name
Test status
Simulation time 52886038268 ps
CPU time 22.19 seconds
Started Aug 05 05:18:36 PM PDT 24
Finished Aug 05 05:18:59 PM PDT 24
Peak memory 199944 kb
Host smart-7321c92d-a4f5-4cf7-b50a-816a90197a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752110726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.752110726
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1489213792
Short name T550
Test name
Test status
Simulation time 63897750707 ps
CPU time 285.78 seconds
Started Aug 05 05:18:43 PM PDT 24
Finished Aug 05 05:23:29 PM PDT 24
Peak memory 216020 kb
Host smart-12273748-cd35-4d97-87e8-92acedd45fad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489213792 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1489213792
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.818262558
Short name T793
Test name
Test status
Simulation time 156156354578 ps
CPU time 407.49 seconds
Started Aug 05 05:18:40 PM PDT 24
Finished Aug 05 05:25:28 PM PDT 24
Peak memory 199848 kb
Host smart-0eed0e6b-1f21-405c-a495-2ebbc2051277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818262558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.818262558
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2548997746
Short name T897
Test name
Test status
Simulation time 47992678313 ps
CPU time 214.93 seconds
Started Aug 05 05:18:39 PM PDT 24
Finished Aug 05 05:22:14 PM PDT 24
Peak memory 216596 kb
Host smart-d847e427-1da3-4d41-ab5b-83f5008d816e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548997746 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2548997746
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3811941042
Short name T169
Test name
Test status
Simulation time 42809026288 ps
CPU time 8.7 seconds
Started Aug 05 05:18:39 PM PDT 24
Finished Aug 05 05:18:48 PM PDT 24
Peak memory 199844 kb
Host smart-0b82afbb-b059-4146-b3f6-58788d091df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811941042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3811941042
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.874540577
Short name T1089
Test name
Test status
Simulation time 72696939139 ps
CPU time 328.03 seconds
Started Aug 05 05:18:38 PM PDT 24
Finished Aug 05 05:24:06 PM PDT 24
Peak memory 216480 kb
Host smart-8d58dae8-233e-4438-aa77-1e598d63b116
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874540577 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.874540577
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2137600358
Short name T410
Test name
Test status
Simulation time 12712578 ps
CPU time 0.57 seconds
Started Aug 05 05:14:05 PM PDT 24
Finished Aug 05 05:14:06 PM PDT 24
Peak memory 195356 kb
Host smart-bda03e96-84c6-40e7-82d8-752f97dd7f2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137600358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2137600358
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.1304697803
Short name T81
Test name
Test status
Simulation time 120904473890 ps
CPU time 370.95 seconds
Started Aug 05 05:13:54 PM PDT 24
Finished Aug 05 05:20:05 PM PDT 24
Peak memory 199832 kb
Host smart-7d04bf8f-1a4b-426e-8e7d-f9ef3a6262be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304697803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1304697803
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1343394060
Short name T1118
Test name
Test status
Simulation time 70502238893 ps
CPU time 128.65 seconds
Started Aug 05 05:13:56 PM PDT 24
Finished Aug 05 05:16:05 PM PDT 24
Peak memory 199896 kb
Host smart-34614cd8-cc1c-4a4c-b68a-7769324068d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343394060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1343394060
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3904824794
Short name T603
Test name
Test status
Simulation time 61354558701 ps
CPU time 123.89 seconds
Started Aug 05 05:13:57 PM PDT 24
Finished Aug 05 05:16:01 PM PDT 24
Peak memory 199952 kb
Host smart-82063555-ac36-412f-985a-0b88e59c0d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904824794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3904824794
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.2075722066
Short name T723
Test name
Test status
Simulation time 61050002169 ps
CPU time 52.74 seconds
Started Aug 05 05:13:58 PM PDT 24
Finished Aug 05 05:14:51 PM PDT 24
Peak memory 199948 kb
Host smart-2fe9cef0-6970-4c52-9512-374c9c9a2803
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075722066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2075722066
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1277183382
Short name T429
Test name
Test status
Simulation time 81830699599 ps
CPU time 602.2 seconds
Started Aug 05 05:14:03 PM PDT 24
Finished Aug 05 05:24:06 PM PDT 24
Peak memory 199928 kb
Host smart-57707337-561d-41f9-8521-22f1bfbfa060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1277183382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1277183382
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3221101229
Short name T580
Test name
Test status
Simulation time 11927769564 ps
CPU time 6.74 seconds
Started Aug 05 05:13:58 PM PDT 24
Finished Aug 05 05:14:05 PM PDT 24
Peak memory 199864 kb
Host smart-0f3ed06a-5fd8-4244-bfdc-6bfd7575e379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221101229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3221101229
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1607618393
Short name T1122
Test name
Test status
Simulation time 98685445653 ps
CPU time 231.38 seconds
Started Aug 05 05:13:55 PM PDT 24
Finished Aug 05 05:17:46 PM PDT 24
Peak memory 199252 kb
Host smart-a2a53475-4e62-4d28-abb2-c75cb16b963a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607618393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1607618393
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2646185926
Short name T1183
Test name
Test status
Simulation time 9220231022 ps
CPU time 558.31 seconds
Started Aug 05 05:13:57 PM PDT 24
Finished Aug 05 05:23:16 PM PDT 24
Peak memory 199948 kb
Host smart-f48a2c23-1ede-48ae-8a6e-d1240373c70b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2646185926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2646185926
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2721437586
Short name T95
Test name
Test status
Simulation time 2023784397 ps
CPU time 3.58 seconds
Started Aug 05 05:13:57 PM PDT 24
Finished Aug 05 05:14:00 PM PDT 24
Peak memory 198684 kb
Host smart-f1451625-bb39-4662-a8c8-32cdf0606c2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2721437586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2721437586
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.501859437
Short name T1067
Test name
Test status
Simulation time 22946801803 ps
CPU time 32.78 seconds
Started Aug 05 05:13:56 PM PDT 24
Finished Aug 05 05:14:29 PM PDT 24
Peak memory 199928 kb
Host smart-03b51d22-397d-498f-bf56-794f9a278dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501859437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.501859437
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2215861939
Short name T588
Test name
Test status
Simulation time 2783563399 ps
CPU time 2.81 seconds
Started Aug 05 05:13:57 PM PDT 24
Finished Aug 05 05:14:00 PM PDT 24
Peak memory 195840 kb
Host smart-a3dd6647-e3c1-4c3d-b5e8-4054a5ab2d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215861939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2215861939
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3492330697
Short name T423
Test name
Test status
Simulation time 533789705 ps
CPU time 1.06 seconds
Started Aug 05 05:13:57 PM PDT 24
Finished Aug 05 05:13:58 PM PDT 24
Peak memory 199208 kb
Host smart-9603537a-645b-49a1-9c87-e3b636b44a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492330697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3492330697
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.1254654623
Short name T992
Test name
Test status
Simulation time 147507864758 ps
CPU time 57.64 seconds
Started Aug 05 05:14:02 PM PDT 24
Finished Aug 05 05:14:59 PM PDT 24
Peak memory 200116 kb
Host smart-52ce92b4-8d66-471a-9083-55a45a221515
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254654623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1254654623
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.742640510
Short name T798
Test name
Test status
Simulation time 92392812222 ps
CPU time 477.9 seconds
Started Aug 05 05:14:02 PM PDT 24
Finished Aug 05 05:22:00 PM PDT 24
Peak memory 216484 kb
Host smart-ff3a3987-51a2-4a9d-ac2c-b42305a03501
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742640510 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.742640510
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3847093223
Short name T1088
Test name
Test status
Simulation time 1014343813 ps
CPU time 3.81 seconds
Started Aug 05 05:13:55 PM PDT 24
Finished Aug 05 05:13:59 PM PDT 24
Peak memory 198912 kb
Host smart-a9e002cf-8c27-4033-aec1-9fbbe88c893b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847093223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3847093223
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1856397807
Short name T878
Test name
Test status
Simulation time 73063542168 ps
CPU time 50.54 seconds
Started Aug 05 05:13:56 PM PDT 24
Finished Aug 05 05:14:46 PM PDT 24
Peak memory 199984 kb
Host smart-dedbd00e-c6f6-4552-a0aa-92b81847fad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856397807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1856397807
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.4249473958
Short name T424
Test name
Test status
Simulation time 68870796844 ps
CPU time 15.19 seconds
Started Aug 05 05:18:40 PM PDT 24
Finished Aug 05 05:18:55 PM PDT 24
Peak memory 199912 kb
Host smart-72f40700-e7b2-4e20-9998-a689ccc85fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249473958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.4249473958
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3848270675
Short name T831
Test name
Test status
Simulation time 64829297925 ps
CPU time 667.84 seconds
Started Aug 05 05:18:36 PM PDT 24
Finished Aug 05 05:29:44 PM PDT 24
Peak memory 224792 kb
Host smart-37d8d29c-3a18-4e47-8c70-7e3bda51b33f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848270675 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3848270675
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1390924987
Short name T1000
Test name
Test status
Simulation time 26601440823 ps
CPU time 14.57 seconds
Started Aug 05 05:18:44 PM PDT 24
Finished Aug 05 05:18:58 PM PDT 24
Peak memory 199776 kb
Host smart-fe0aaa71-9bd9-459b-82eb-125cb0f01ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390924987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1390924987
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2941541065
Short name T1073
Test name
Test status
Simulation time 50356302608 ps
CPU time 430.45 seconds
Started Aug 05 05:18:45 PM PDT 24
Finished Aug 05 05:25:55 PM PDT 24
Peak memory 216456 kb
Host smart-b9f0d5e2-1968-4512-b7ff-5f632e88ecf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941541065 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2941541065
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2432658271
Short name T257
Test name
Test status
Simulation time 67706209312 ps
CPU time 154.19 seconds
Started Aug 05 05:18:48 PM PDT 24
Finished Aug 05 05:21:22 PM PDT 24
Peak memory 199908 kb
Host smart-e951396e-3adf-418e-9913-e08850e8bc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432658271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2432658271
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3032279990
Short name T118
Test name
Test status
Simulation time 42149400823 ps
CPU time 373.65 seconds
Started Aug 05 05:18:45 PM PDT 24
Finished Aug 05 05:24:59 PM PDT 24
Peak memory 216308 kb
Host smart-c8f21f64-96ed-4d88-9f96-b80297748e8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032279990 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3032279990
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.374157910
Short name T247
Test name
Test status
Simulation time 36488446566 ps
CPU time 26.98 seconds
Started Aug 05 05:18:45 PM PDT 24
Finished Aug 05 05:19:12 PM PDT 24
Peak memory 199792 kb
Host smart-91b350ea-271f-4583-96fa-d8396d62e7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374157910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.374157910
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.676892687
Short name T1022
Test name
Test status
Simulation time 95331192910 ps
CPU time 944.36 seconds
Started Aug 05 05:18:46 PM PDT 24
Finished Aug 05 05:34:30 PM PDT 24
Peak memory 216524 kb
Host smart-cfb34ec1-34da-41b9-93f9-a577c4de085b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676892687 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.676892687
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3537423908
Short name T194
Test name
Test status
Simulation time 110859014733 ps
CPU time 31.14 seconds
Started Aug 05 05:18:45 PM PDT 24
Finished Aug 05 05:19:17 PM PDT 24
Peak memory 199896 kb
Host smart-190283c5-1617-485b-b125-5bf8dab85d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537423908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3537423908
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1754254825
Short name T617
Test name
Test status
Simulation time 124786811671 ps
CPU time 47.58 seconds
Started Aug 05 05:18:47 PM PDT 24
Finished Aug 05 05:19:34 PM PDT 24
Peak memory 199820 kb
Host smart-e9958dba-d7b3-4423-bfaa-2d63c75dd770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754254825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1754254825
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2079231258
Short name T581
Test name
Test status
Simulation time 29287293664 ps
CPU time 334.23 seconds
Started Aug 05 05:18:46 PM PDT 24
Finished Aug 05 05:24:20 PM PDT 24
Peak memory 216576 kb
Host smart-2aaf175e-1d72-4571-9ee6-f2e19cf427a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079231258 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2079231258
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2689025322
Short name T314
Test name
Test status
Simulation time 15288633071 ps
CPU time 21.53 seconds
Started Aug 05 05:18:45 PM PDT 24
Finished Aug 05 05:19:07 PM PDT 24
Peak memory 199988 kb
Host smart-6ba922cd-ff66-4501-9365-5e0001e0f6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689025322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2689025322
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.4011753835
Short name T215
Test name
Test status
Simulation time 120164700202 ps
CPU time 82.24 seconds
Started Aug 05 05:18:46 PM PDT 24
Finished Aug 05 05:20:08 PM PDT 24
Peak memory 199812 kb
Host smart-bf8d35ea-5833-4d2c-a5ed-f44cf7fd3fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011753835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.4011753835
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.872612512
Short name T174
Test name
Test status
Simulation time 96027409805 ps
CPU time 365.53 seconds
Started Aug 05 05:18:46 PM PDT 24
Finished Aug 05 05:24:52 PM PDT 24
Peak memory 216276 kb
Host smart-79b51d25-6676-419b-b638-28af73f7668a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872612512 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.872612512
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2778534194
Short name T527
Test name
Test status
Simulation time 92450414699 ps
CPU time 409.78 seconds
Started Aug 05 05:18:45 PM PDT 24
Finished Aug 05 05:25:35 PM PDT 24
Peak memory 199916 kb
Host smart-32d9eca2-03ea-420d-ba5f-690863c66b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778534194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2778534194
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2683157360
Short name T1059
Test name
Test status
Simulation time 146632248225 ps
CPU time 620.66 seconds
Started Aug 05 05:18:50 PM PDT 24
Finished Aug 05 05:29:11 PM PDT 24
Peak memory 216472 kb
Host smart-dc2ac510-4cc8-4d41-9eed-99fc0b775ff0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683157360 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2683157360
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.610239905
Short name T287
Test name
Test status
Simulation time 21819602087 ps
CPU time 11.73 seconds
Started Aug 05 05:18:52 PM PDT 24
Finished Aug 05 05:19:03 PM PDT 24
Peak memory 199896 kb
Host smart-922b63a8-3cb3-4a6c-9941-f6f464e3986e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610239905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.610239905
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.131782337
Short name T60
Test name
Test status
Simulation time 335496743211 ps
CPU time 1710.74 seconds
Started Aug 05 05:18:52 PM PDT 24
Finished Aug 05 05:47:23 PM PDT 24
Peak memory 230188 kb
Host smart-256cfe7a-192a-4506-b216-7951d4b57f9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131782337 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.131782337
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1857531149
Short name T338
Test name
Test status
Simulation time 46373755 ps
CPU time 0.57 seconds
Started Aug 05 05:14:00 PM PDT 24
Finished Aug 05 05:14:01 PM PDT 24
Peak memory 195324 kb
Host smart-d72648e0-14a8-4896-a61d-bb8b4ffb458d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857531149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1857531149
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.213227754
Short name T830
Test name
Test status
Simulation time 82896488655 ps
CPU time 203.73 seconds
Started Aug 05 05:14:05 PM PDT 24
Finished Aug 05 05:17:29 PM PDT 24
Peak memory 199984 kb
Host smart-b2d4327f-e08b-4918-b2fe-973b15d6eab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213227754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.213227754
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.3209626397
Short name T176
Test name
Test status
Simulation time 50418964780 ps
CPU time 34.79 seconds
Started Aug 05 05:14:03 PM PDT 24
Finished Aug 05 05:14:38 PM PDT 24
Peak memory 199976 kb
Host smart-4ad4c762-f9ee-41e8-a345-7fe32bc4364b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209626397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3209626397
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2837232804
Short name T181
Test name
Test status
Simulation time 91334896097 ps
CPU time 72.09 seconds
Started Aug 05 05:14:04 PM PDT 24
Finished Aug 05 05:15:17 PM PDT 24
Peak memory 199892 kb
Host smart-485e50ff-4cff-4a52-bdec-2c142c99a1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837232804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2837232804
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1328836409
Short name T1047
Test name
Test status
Simulation time 2219935424 ps
CPU time 8.79 seconds
Started Aug 05 05:14:02 PM PDT 24
Finished Aug 05 05:14:11 PM PDT 24
Peak memory 199260 kb
Host smart-fe26fc49-b624-40d0-afb1-ca42e8796cdf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328836409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1328836409
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1798125310
Short name T49
Test name
Test status
Simulation time 96138470243 ps
CPU time 871.65 seconds
Started Aug 05 05:14:01 PM PDT 24
Finished Aug 05 05:28:33 PM PDT 24
Peak memory 200156 kb
Host smart-2af1c90c-5254-4dd6-a99d-08fafc43b650
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1798125310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1798125310
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.3913615754
Short name T969
Test name
Test status
Simulation time 3934270215 ps
CPU time 3.43 seconds
Started Aug 05 05:14:01 PM PDT 24
Finished Aug 05 05:14:04 PM PDT 24
Peak memory 198436 kb
Host smart-61c79eee-7f6d-47d4-adc3-f1bb2634ee76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913615754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3913615754
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.15724024
Short name T935
Test name
Test status
Simulation time 6635912710 ps
CPU time 11.49 seconds
Started Aug 05 05:14:03 PM PDT 24
Finished Aug 05 05:14:15 PM PDT 24
Peak memory 195940 kb
Host smart-9e73492f-e5bc-4d1f-9027-65d60e187f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15724024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.15724024
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.2870342194
Short name T313
Test name
Test status
Simulation time 23161797095 ps
CPU time 59.16 seconds
Started Aug 05 05:14:01 PM PDT 24
Finished Aug 05 05:15:00 PM PDT 24
Peak memory 199912 kb
Host smart-ac6fd210-488a-4079-a2c1-2b51305a3cc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2870342194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2870342194
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.3099935482
Short name T37
Test name
Test status
Simulation time 6151016191 ps
CPU time 47.75 seconds
Started Aug 05 05:14:04 PM PDT 24
Finished Aug 05 05:14:52 PM PDT 24
Peak memory 199368 kb
Host smart-edcd8497-14b4-4c29-9458-01047b88ae41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3099935482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3099935482
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3770405982
Short name T1149
Test name
Test status
Simulation time 48797087327 ps
CPU time 12.78 seconds
Started Aug 05 05:14:05 PM PDT 24
Finished Aug 05 05:14:18 PM PDT 24
Peak memory 199492 kb
Host smart-3eadd136-a2d2-4245-9531-f9926b79395b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770405982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3770405982
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3265415650
Short name T659
Test name
Test status
Simulation time 3401780442 ps
CPU time 1.82 seconds
Started Aug 05 05:14:01 PM PDT 24
Finished Aug 05 05:14:03 PM PDT 24
Peak memory 196108 kb
Host smart-fbe1a2f6-e7e9-4ba3-ab4a-795b0a18a53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265415650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3265415650
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.54186392
Short name T1030
Test name
Test status
Simulation time 5628760609 ps
CPU time 20.92 seconds
Started Aug 05 05:14:04 PM PDT 24
Finished Aug 05 05:14:25 PM PDT 24
Peak memory 199432 kb
Host smart-067c2f2d-c680-438c-8978-330cdd4a18db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54186392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.54186392
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.2491772241
Short name T127
Test name
Test status
Simulation time 8217851543 ps
CPU time 15.7 seconds
Started Aug 05 05:14:03 PM PDT 24
Finished Aug 05 05:14:19 PM PDT 24
Peak memory 199920 kb
Host smart-50275831-1095-4dbb-94c0-341a33ecfb3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491772241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2491772241
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3890103352
Short name T910
Test name
Test status
Simulation time 49385986176 ps
CPU time 682.31 seconds
Started Aug 05 05:14:02 PM PDT 24
Finished Aug 05 05:25:25 PM PDT 24
Peak memory 216480 kb
Host smart-334f3717-d4f9-42d9-a089-27abc77b245e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890103352 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3890103352
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1176787113
Short name T894
Test name
Test status
Simulation time 1263470765 ps
CPU time 2.22 seconds
Started Aug 05 05:14:03 PM PDT 24
Finished Aug 05 05:14:06 PM PDT 24
Peak memory 199460 kb
Host smart-ae5a518c-8664-4ba7-beb3-0f0b2ca72ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176787113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1176787113
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.927120565
Short name T568
Test name
Test status
Simulation time 241969941814 ps
CPU time 52.71 seconds
Started Aug 05 05:14:05 PM PDT 24
Finished Aug 05 05:14:58 PM PDT 24
Peak memory 199988 kb
Host smart-f5ae5a5f-23fa-4dcd-902d-61a86af8ce33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927120565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.927120565
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3136725940
Short name T1010
Test name
Test status
Simulation time 42551644542 ps
CPU time 69.9 seconds
Started Aug 05 05:18:51 PM PDT 24
Finished Aug 05 05:20:01 PM PDT 24
Peak memory 199900 kb
Host smart-80779eb1-36ee-457f-a35a-9455d3fbc614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136725940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3136725940
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3480067909
Short name T596
Test name
Test status
Simulation time 154867052213 ps
CPU time 1372.05 seconds
Started Aug 05 05:18:53 PM PDT 24
Finished Aug 05 05:41:46 PM PDT 24
Peak memory 216452 kb
Host smart-5898474f-45f7-48a2-9e3c-42c86f6921a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480067909 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3480067909
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1104772493
Short name T1082
Test name
Test status
Simulation time 148563799854 ps
CPU time 443.64 seconds
Started Aug 05 05:18:55 PM PDT 24
Finished Aug 05 05:26:19 PM PDT 24
Peak memory 226156 kb
Host smart-22fb7397-28f1-498e-bf67-1bf3d84ee610
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104772493 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1104772493
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.626094927
Short name T180
Test name
Test status
Simulation time 126880260730 ps
CPU time 32.55 seconds
Started Aug 05 05:18:57 PM PDT 24
Finished Aug 05 05:19:29 PM PDT 24
Peak memory 199784 kb
Host smart-abcbaff9-6efc-4c75-94cc-1b3b7297a0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626094927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.626094927
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2513347694
Short name T453
Test name
Test status
Simulation time 67178141865 ps
CPU time 434.09 seconds
Started Aug 05 05:18:57 PM PDT 24
Finished Aug 05 05:26:12 PM PDT 24
Peak memory 216504 kb
Host smart-2e3af521-3976-42d2-9d4b-fc3cc1aca53e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513347694 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2513347694
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1589948263
Short name T841
Test name
Test status
Simulation time 25510793402 ps
CPU time 341.42 seconds
Started Aug 05 05:18:57 PM PDT 24
Finished Aug 05 05:24:39 PM PDT 24
Peak memory 216616 kb
Host smart-83418616-b9ab-45b5-9673-f04af40f111c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589948263 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1589948263
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3299536745
Short name T946
Test name
Test status
Simulation time 82748704249 ps
CPU time 138.34 seconds
Started Aug 05 05:18:57 PM PDT 24
Finished Aug 05 05:21:16 PM PDT 24
Peak memory 199884 kb
Host smart-1ca1eb96-94ed-42df-bac4-6bedb72e0d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299536745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3299536745
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.34230602
Short name T165
Test name
Test status
Simulation time 137360652387 ps
CPU time 410.86 seconds
Started Aug 05 05:18:56 PM PDT 24
Finished Aug 05 05:25:47 PM PDT 24
Peak memory 226768 kb
Host smart-75023707-e6a6-4a09-881e-b3d188c55262
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34230602 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.34230602
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.4264923855
Short name T205
Test name
Test status
Simulation time 16461659243 ps
CPU time 25.89 seconds
Started Aug 05 05:19:04 PM PDT 24
Finished Aug 05 05:19:30 PM PDT 24
Peak memory 199944 kb
Host smart-f584be7d-feee-409f-96b8-0a470f95bcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264923855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.4264923855
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3867886350
Short name T716
Test name
Test status
Simulation time 58011519524 ps
CPU time 1178.25 seconds
Started Aug 05 05:19:04 PM PDT 24
Finished Aug 05 05:38:42 PM PDT 24
Peak memory 216340 kb
Host smart-26d8c5a0-93a5-4653-a0ba-d35c5744d223
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867886350 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3867886350
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.167565305
Short name T1018
Test name
Test status
Simulation time 293644328768 ps
CPU time 26.63 seconds
Started Aug 05 05:19:05 PM PDT 24
Finished Aug 05 05:19:31 PM PDT 24
Peak memory 199844 kb
Host smart-86a1192e-20f8-444c-9472-ba16a79d8e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167565305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.167565305
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3607856429
Short name T27
Test name
Test status
Simulation time 67756678747 ps
CPU time 1025.54 seconds
Started Aug 05 05:19:04 PM PDT 24
Finished Aug 05 05:36:10 PM PDT 24
Peak memory 214756 kb
Host smart-4a3120a3-0ff4-40aa-8495-51d1af324867
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607856429 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3607856429
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.743537772
Short name T255
Test name
Test status
Simulation time 168676673432 ps
CPU time 62.46 seconds
Started Aug 05 05:19:03 PM PDT 24
Finished Aug 05 05:20:05 PM PDT 24
Peak memory 199884 kb
Host smart-17e8783f-6782-4895-b78a-1d78964a9784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743537772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.743537772
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1313313554
Short name T235
Test name
Test status
Simulation time 416901018691 ps
CPU time 815.18 seconds
Started Aug 05 05:19:02 PM PDT 24
Finished Aug 05 05:32:37 PM PDT 24
Peak memory 224804 kb
Host smart-47fb3665-0d06-4e76-8f73-90fae346ed64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313313554 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1313313554
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3196638530
Short name T288
Test name
Test status
Simulation time 19870815779 ps
CPU time 44.19 seconds
Started Aug 05 05:19:02 PM PDT 24
Finished Aug 05 05:19:47 PM PDT 24
Peak memory 199892 kb
Host smart-381da150-dad3-4073-8e7b-99b4b261b888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196638530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3196638530
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.528308784
Short name T320
Test name
Test status
Simulation time 46128467314 ps
CPU time 677.72 seconds
Started Aug 05 05:19:09 PM PDT 24
Finished Aug 05 05:30:27 PM PDT 24
Peak memory 216504 kb
Host smart-bba8736c-5e6d-4cb2-8d73-d6b1b1a6245e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528308784 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.528308784
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2956271280
Short name T796
Test name
Test status
Simulation time 27608388236 ps
CPU time 12.76 seconds
Started Aug 05 05:19:09 PM PDT 24
Finished Aug 05 05:19:22 PM PDT 24
Peak memory 199856 kb
Host smart-bc25c8db-7a51-465f-9e77-fb20b09c2e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956271280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2956271280
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.4133408829
Short name T833
Test name
Test status
Simulation time 66786281465 ps
CPU time 421.79 seconds
Started Aug 05 05:19:08 PM PDT 24
Finished Aug 05 05:26:10 PM PDT 24
Peak memory 216512 kb
Host smart-957cfec1-cafd-4ace-9dbb-624b402404e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133408829 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.4133408829
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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