Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	116252	1			T2	2		T3	52		T4	1475
all_values[1]	116252	1			T2	2		T3	52		T4	1475
all_values[2]	116252	1			T2	2		T3	52		T4	1475
all_values[3]	116252	1			T2	2		T3	52		T4	1475
all_values[4]	116252	1			T2	2		T3	52		T4	1475
all_values[5]	116252	1			T2	2		T3	52		T4	1475
all_values[6]	116252	1			T2	2		T3	52		T4	1475
all_values[7]	116252	1			T2	2		T3	52		T4	1475
all_values[8]	116252	1			T2	2		T3	52		T4	1475

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

538364

1

T2

18

T3

193

T4

6235

auto[1]

507904

1

T3

275

T4

7040

T5

210

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

950901

1

T2

13

T3

422

T4

12192

auto[1]

95367

1

T2

5

T3

46

T4

1083

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	36833	1			T3	37		T4	445		T5	12
all_values[0]	auto[0]	auto[1]	24830	1			T2	2		T3	3		T4	262
all_values[0]	auto[1]	auto[0]	31268	1			T4	294		T5	5		T6	6
all_values[0]	auto[1]	auto[1]	23321	1			T3	12		T4	474		T5	12
all_values[1]	auto[0]	auto[0]	61501	1			T2	2		T3	3		T4	481
all_values[1]	auto[0]	auto[1]	1732	1			T3	9		T7	4		T9	2
all_values[1]	auto[1]	auto[0]	51219	1			T3	39		T4	994		T5	31
all_values[1]	auto[1]	auto[1]	1800	1			T3	1		T6	1		T7	5
all_values[2]	auto[0]	auto[0]	54600	1			T2	1		T3	8		T4	848
all_values[2]	auto[0]	auto[1]	2911	1			T2	1		T3	5		T4	3
all_values[2]	auto[1]	auto[0]	56266	1			T3	38		T4	621		T5	12
all_values[2]	auto[1]	auto[1]	2475	1			T3	1		T4	3		T5	1
all_values[3]	auto[0]	auto[0]	61306	1			T2	2		T3	5		T4	687
all_values[3]	auto[0]	auto[1]	348	1			T7	3		T9	2		T11	2
all_values[3]	auto[1]	auto[0]	54297	1			T3	47		T4	788		T5	29
all_values[3]	auto[1]	auto[1]	301	1			T7	1		T9	4		T115	2
all_values[4]	auto[0]	auto[0]	59806	1			T2	2		T3	4		T4	492
all_values[4]	auto[0]	auto[1]	505	1			T7	1		T11	1		T13	5
all_values[4]	auto[1]	auto[0]	55447	1			T3	48		T4	983		T5	19
all_values[4]	auto[1]	auto[1]	494	1			T7	3		T9	1		T11	1
all_values[5]	auto[0]	auto[0]	59988	1			T2	2		T3	6		T4	203
all_values[5]	auto[0]	auto[1]	168	1			T7	3		T9	3		T29	1
all_values[5]	auto[1]	auto[0]	55890	1			T3	46		T4	1272		T5	26
all_values[5]	auto[1]	auto[1]	206	1			T7	5		T9	1		T29	3
all_values[6]	auto[0]	auto[0]	58628	1			T2	2		T3	49		T4	898
all_values[6]	auto[0]	auto[1]	187	1			T7	4		T9	1		T29	4
all_values[6]	auto[1]	auto[0]	57262	1			T3	3		T4	577		T5	31
all_values[6]	auto[1]	auto[1]	175	1			T7	1		T19	4		T30	3
all_values[7]	auto[0]	auto[0]	55317	1			T2	2		T3	12		T4	641
all_values[7]	auto[0]	auto[1]	338	1			T7	2		T9	1		T117	4
all_values[7]	auto[1]	auto[0]	60243	1			T3	40		T4	834		T5	14
all_values[7]	auto[1]	auto[1]	354	1			T5	5		T7	5		T9	2
all_values[8]	auto[0]	auto[0]	40105	1			T3	37		T4	938		T5	1
all_values[8]	auto[0]	auto[1]	19261	1			T2	2		T3	15		T4	337
all_values[8]	auto[1]	auto[0]	40925	1			T4	196		T5	16		T6	3
all_values[8]	auto[1]	auto[1]	15961	1			T4	4		T5	9		T6	1