Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2421	1			T2	1		T3	1		T5	2
auto[BaudRate115200]	2027	1			T3	1		T4	3		T6	2
auto[BaudRate230400]	2062	1			T3	1		T4	2		T5	1
auto[BaudRate128Kbps]	2109	1			T2	1		T4	1		T5	2
auto[BaudRate256Kbps]	2191	1			T3	3		T4	1		T5	1
auto[BaudRate1Mbps]	1911	1			T3	2		T4	1		T5	2
auto[BaudRate1p5Mbps]	1303	1			T4	2		T7	3		T8	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1471	1			T35	9		T36	12		T116	5
freqs[25]	1756	1			T2	2		T6	6		T115	9
freqs[48]	755	1			T10	5		T21	60		T41	5
freqs[50]	679	1			T14	2		T16	2		T49	18
freqs[100]	973	1			T8	9		T11	2		T22	3

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	239	1			T36	4		T252	12		T336	1
auto[BaudRate9600]	freqs[25]	275	1			T2	1		T6	2		T115	1
auto[BaudRate9600]	freqs[48]	96	1			T10	1		T43	2		T337	19
auto[BaudRate9600]	freqs[50]	122	1			T16	1		T49	4		T98	2
auto[BaudRate9600]	freqs[100]	180	1			T8	1		T11	1		T22	3
auto[BaudRate115200]	freqs[24]	223	1			T35	1		T36	2		T116	1
auto[BaudRate115200]	freqs[25]	303	1			T6	2		T115	3		T266	2
auto[BaudRate115200]	freqs[48]	97	1			T43	1		T130	4		T335	4
auto[BaudRate115200]	freqs[50]	80	1			T49	3		T290	1		T98	3
auto[BaudRate115200]	freqs[100]	129	1			T8	1		T11	1		T29	2
auto[BaudRate230400]	freqs[24]	194	1			T35	1		T36	1		T47	1
auto[BaudRate230400]	freqs[25]	250	1			T266	3		T117	1		T120	1
auto[BaudRate230400]	freqs[48]	129	1			T10	1		T21	9		T41	1
auto[BaudRate230400]	freqs[50]	95	1			T14	1		T49	2		T338	3
auto[BaudRate230400]	freqs[100]	118	1			T8	3		T29	3		T177	3
auto[BaudRate128Kbps]	freqs[24]	211	1			T35	1		T36	4		T116	1
auto[BaudRate128Kbps]	freqs[25]	253	1			T2	1		T115	2		T266	2
auto[BaudRate128Kbps]	freqs[48]	100	1			T10	2		T21	12		T41	1
auto[BaudRate128Kbps]	freqs[50]	101	1			T49	2		T290	1		T98	4
auto[BaudRate128Kbps]	freqs[100]	144	1			T29	4		T32	1		T128	1
auto[BaudRate256Kbps]	freqs[24]	254	1			T35	2		T36	1		T116	1
auto[BaudRate256Kbps]	freqs[25]	245	1			T6	2		T120	1		T51	1
auto[BaudRate256Kbps]	freqs[48]	117	1			T21	12		T43	5		T130	1
auto[BaudRate256Kbps]	freqs[50]	78	1			T49	1		T290	1		T98	2
auto[BaudRate256Kbps]	freqs[100]	119	1			T8	1		T29	1		T50	1
auto[BaudRate1Mbps]	freqs[24]	226	1			T35	3		T116	2		T260	1
auto[BaudRate1Mbps]	freqs[25]	276	1			T115	3		T266	3		T117	3
auto[BaudRate1Mbps]	freqs[48]	107	1			T10	1		T21	6		T41	2
auto[BaudRate1Mbps]	freqs[50]	101	1			T16	1		T49	3		T290	1
auto[BaudRate1Mbps]	freqs[100]	145	1			T8	1		T29	8		T177	2
auto[BaudRate1p5Mbps]	freqs[25]	154	1			T48	1		T261	2		T256	1
auto[BaudRate1p5Mbps]	freqs[48]	109	1			T21	21		T41	1		T130	1
auto[BaudRate1p5Mbps]	freqs[50]	102	1			T14	1		T49	3		T338	3
auto[BaudRate1p5Mbps]	freqs[100]	138	1			T8	2		T29	4		T50	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded