Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	11	119	91.54

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	11	119	91.54	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	31914640	1			T3	105		T4	629737		T5	88
all_levels[1]	187710	1			T3	50		T4	261		T5	11
all_levels[2]	2507	1			T3	20		T5	10		T7	1
all_levels[3]	1134	1			T3	6		T5	4		T6	1
all_levels[4]	737	1			T3	3		T5	3		T9	2
all_levels[5]	542	1			T5	1		T9	2		T34	1
all_levels[6]	432	1			T5	2		T7	1		T8	2
all_levels[7]	346	1			T5	1		T9	1		T34	1
all_levels[8]	300	1			T9	2		T36	1		T38	1
all_levels[9]	274	1			T8	1		T9	2		T36	1
all_levels[10]	215	1			T7	1		T10	1		T34	1
all_levels[11]	204	1			T3	1		T9	1		T114	1
all_levels[12]	187	1			T10	12		T34	1		T38	1
all_levels[13]	129	1			T114	2		T13	1		T41	1
all_levels[14]	136	1			T3	1		T8	1		T9	1
all_levels[15]	108	1			T115	1		T42	1		T47	4
all_levels[16]	103	1			T3	1		T115	1		T38	3
all_levels[17]	90	1			T115	1		T114	1		T42	3
all_levels[18]	108	1			T3	1		T13	1		T116	1
all_levels[19]	83	1			T12	1		T13	1		T42	1
all_levels[20]	84	1			T115	3		T41	1		T117	1
all_levels[21]	65	1			T20	1		T13	1		T42	2
all_levels[22]	84	1			T114	1		T13	1		T30	1
all_levels[23]	56	1			T115	2		T47	1		T118	1
all_levels[24]	56	1			T42	1		T47	2		T119	1
all_levels[25]	53	1			T8	1		T114	1		T13	1
all_levels[26]	43	1			T114	2		T44	1		T118	1
all_levels[27]	46	1			T3	2		T12	1		T116	1
all_levels[28]	57	1			T34	1		T114	1		T116	1
all_levels[29]	30	1			T20	1		T42	1		T44	1
all_levels[30]	45	1			T8	2		T120	1		T47	1
all_levels[31]	39	1			T3	1		T98	1		T121	1
all_levels[32]	38	1			T115	2		T44	2		T122	2
all_levels[33]	41	1			T3	1		T12	1		T123	1
all_levels[34]	30	1			T117	1		T32	1		T121	2
all_levels[35]	28	1			T7	1		T91	1		T124	2
all_levels[36]	14	1			T34	1		T125	1		T126	1
all_levels[37]	28	1			T3	1		T108	1		T127	1
all_levels[38]	20	1			T34	1		T128	2		T122	1
all_levels[39]	13	1			T30	1		T129	2		T102	1
all_levels[40]	17	1			T116	1		T130	1		T108	1
all_levels[41]	14	1			T131	2		T132	1		T133	1
all_levels[42]	10	1			T134	1		T135	1		T136	2
all_levels[43]	17	1			T12	1		T42	1		T137	1
all_levels[44]	10	1			T138	1		T139	1		T140	1
all_levels[45]	19	1			T13	1		T141	1		T142	2
all_levels[46]	11	1			T108	1		T141	1		T143	1
all_levels[47]	9	1			T144	1		T145	1		T146	1
all_levels[48]	17	1			T147	2		T91	1		T148	2
all_levels[49]	20	1			T6	1		T42	1		T149	1
all_levels[50]	9	1			T150	2		T151	3		T152	1
all_levels[51]	11	1			T44	1		T153	1		T154	1
all_levels[52]	10	1			T155	1		T156	1		T157	1
all_levels[53]	12	1			T5	1		T158	1		T159	1
all_levels[54]	10	1			T138	1		T143	3		T160	1
all_levels[55]	9	1			T47	1		T161	1		T140	1
all_levels[56]	14	1			T162	1		T140	1		T163	1
all_levels[57]	6	1			T7	1		T164	1		T165	1
all_levels[58]	4	1			T6	1		T166	2		T102	1
all_levels[59]	5	1			T167	1		T168	1		T165	1
all_levels[60]	13	1			T34	1		T20	1		T169	1
all_levels[61]	3	1			T170	1		T171	1		T172	1
all_levels[62]	5	1			T20	2		T173	1		T153	1
all_levels[63]	7	1			T174	1		T175	1		T176	1
all_levels[64]	115	1			T7	2		T12	2		T20	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32106187

1

T3

186

T4

629998

T5

121

auto[1]

5045

1

T3

7

T8

3

T9

11

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	11	119	91.54	11

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[36]]	[auto[1]]	0	1	1
[all_levels[40]]	[auto[1]]	0	1	1
[all_levels[44]]	[auto[1]]	0	1	1
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[55]]	[auto[1]]	0	1	1
[all_levels[57] , all_levels[58] , all_levels[59] , all_levels[60] , all_levels[61] , all_levels[62]]	[auto[1]]	--	--	6

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	31910082	1			T3	99		T4	629737		T5	88
all_levels[0]	auto[1]	4558	1			T3	6		T8	3		T9	11
all_levels[1]	auto[0]	187646	1			T3	49		T4	261		T5	11
all_levels[1]	auto[1]	64	1			T3	1		T177	1		T178	1
all_levels[2]	auto[0]	2461	1			T3	20		T5	10		T7	1
all_levels[2]	auto[1]	46	1			T34	1		T115	1		T179	2
all_levels[3]	auto[0]	1111	1			T3	6		T5	4		T6	1
all_levels[3]	auto[1]	23	1			T177	1		T180	3		T131	2
all_levels[4]	auto[0]	716	1			T3	3		T5	3		T9	2
all_levels[4]	auto[1]	21	1			T47	1		T178	4		T181	2
all_levels[5]	auto[0]	529	1			T5	1		T9	2		T34	1
all_levels[5]	auto[1]	13	1			T131	1		T182	1		T148	1
all_levels[6]	auto[0]	415	1			T5	2		T7	1		T8	2
all_levels[6]	auto[1]	17	1			T115	3		T127	1		T149	2
all_levels[7]	auto[0]	324	1			T5	1		T9	1		T34	1
all_levels[7]	auto[1]	22	1			T183	2		T184	1		T185	2
all_levels[8]	auto[0]	281	1			T9	2		T36	1		T38	1
all_levels[8]	auto[1]	19	1			T186	1		T91	2		T93	1
all_levels[9]	auto[0]	251	1			T8	1		T9	2		T36	1
all_levels[9]	auto[1]	23	1			T127	1		T141	2		T187	1
all_levels[10]	auto[0]	209	1			T7	1		T10	1		T34	1
all_levels[10]	auto[1]	6	1			T188	1		T189	2		T190	1
all_levels[11]	auto[0]	196	1			T3	1		T9	1		T114	1
all_levels[11]	auto[1]	8	1			T191	2		T192	2		T193	1
all_levels[12]	auto[0]	177	1			T10	11		T34	1		T38	1
all_levels[12]	auto[1]	10	1			T10	1		T141	1		T194	1
all_levels[13]	auto[0]	121	1			T114	1		T13	1		T41	1
all_levels[13]	auto[1]	8	1			T114	1		T179	4		T195	1
all_levels[14]	auto[0]	120	1			T3	1		T8	1		T9	1
all_levels[14]	auto[1]	16	1			T186	1		T51	2		T196	1
all_levels[15]	auto[0]	101	1			T115	1		T42	1		T47	1
all_levels[15]	auto[1]	7	1			T47	3		T197	1		T198	1
all_levels[16]	auto[0]	96	1			T3	1		T115	1		T38	1
all_levels[16]	auto[1]	7	1			T38	2		T199	3		T200	2
all_levels[17]	auto[0]	84	1			T115	1		T114	1		T42	3
all_levels[17]	auto[1]	6	1			T161	2		T166	1		T201	1
all_levels[18]	auto[0]	95	1			T3	1		T13	1		T116	1
all_levels[18]	auto[1]	13	1			T51	1		T202	1		T203	2
all_levels[19]	auto[0]	75	1			T12	1		T13	1		T42	1
all_levels[19]	auto[1]	8	1			T91	1		T204	1		T205	4
all_levels[20]	auto[0]	82	1			T115	3		T41	1		T117	1
all_levels[20]	auto[1]	2	1			T206	1		T207	1		-	-
all_levels[21]	auto[0]	60	1			T20	1		T13	1		T42	2
all_levels[21]	auto[1]	5	1			T50	2		T208	1		T209	1
all_levels[22]	auto[0]	71	1			T114	1		T13	1		T30	1
all_levels[22]	auto[1]	13	1			T194	1		T210	5		T211	2
all_levels[23]	auto[0]	52	1			T115	1		T47	1		T118	1
all_levels[23]	auto[1]	4	1			T115	1		T212	1		T213	2
all_levels[24]	auto[0]	52	1			T42	1		T47	1		T119	1
all_levels[24]	auto[1]	4	1			T47	1		T214	1		T165	1
all_levels[25]	auto[0]	41	1			T8	1		T114	1		T13	1
all_levels[25]	auto[1]	12	1			T215	1		T216	2		T217	4
all_levels[26]	auto[0]	41	1			T114	1		T44	1		T118	1
all_levels[26]	auto[1]	2	1			T114	1		T217	1		-	-
all_levels[27]	auto[0]	42	1			T3	2		T12	1		T116	1
all_levels[27]	auto[1]	4	1			T211	1		T218	1		T219	1
all_levels[28]	auto[0]	52	1			T34	1		T114	1		T116	1
all_levels[28]	auto[1]	5	1			T120	1		T220	1		T221	1
all_levels[29]	auto[0]	29	1			T20	1		T42	1		T44	1
all_levels[29]	auto[1]	1	1			T209	1		-	-		-	-
all_levels[30]	auto[0]	38	1			T8	2		T120	1		T47	1
all_levels[30]	auto[1]	7	1			T222	2		T223	1		T224	2
all_levels[31]	auto[0]	31	1			T3	1		T98	1		T121	1
all_levels[31]	auto[1]	8	1			T225	2		T226	2		T152	1
all_levels[32]	auto[0]	33	1			T115	1		T44	1		T122	1
all_levels[32]	auto[1]	5	1			T115	1		T44	1		T122	1
all_levels[33]	auto[0]	31	1			T3	1		T12	1		T123	1
all_levels[33]	auto[1]	10	1			T227	2		T228	1		T203	2
all_levels[34]	auto[0]	27	1			T117	1		T32	1		T121	1
all_levels[34]	auto[1]	3	1			T121	1		T227	1		T229	1
all_levels[35]	auto[0]	25	1			T7	1		T91	1		T124	1
all_levels[35]	auto[1]	3	1			T124	1		T230	2		-	-
all_levels[36]	auto[0]	14	1			T34	1		T125	1		T126	1
all_levels[37]	auto[0]	27	1			T3	1		T108	1		T127	1
all_levels[37]	auto[1]	1	1			T231	1		-	-		-	-
all_levels[38]	auto[0]	16	1			T34	1		T128	2		T122	1
all_levels[38]	auto[1]	4	1			T232	1		T233	3		-	-
all_levels[39]	auto[0]	12	1			T30	1		T129	1		T102	1
all_levels[39]	auto[1]	1	1			T129	1		-	-		-	-
all_levels[40]	auto[0]	17	1			T116	1		T130	1		T108	1
all_levels[41]	auto[0]	11	1			T131	1		T132	1		T133	1
all_levels[41]	auto[1]	3	1			T131	1		T234	1		T235	1
all_levels[42]	auto[0]	9	1			T134	1		T135	1		T136	2
all_levels[42]	auto[1]	1	1			T236	1		-	-		-	-
all_levels[43]	auto[0]	14	1			T12	1		T42	1		T137	1
all_levels[43]	auto[1]	3	1			T237	2		T238	1		-	-
all_levels[44]	auto[0]	10	1			T138	1		T139	1		T140	1
all_levels[45]	auto[0]	16	1			T13	1		T141	1		T142	2
all_levels[45]	auto[1]	3	1			T239	2		T230	1		-	-
all_levels[46]	auto[0]	11	1			T108	1		T141	1		T143	1
all_levels[47]	auto[0]	8	1			T144	1		T145	1		T146	1
all_levels[47]	auto[1]	1	1			T240	1		-	-		-	-
all_levels[48]	auto[0]	13	1			T147	1		T91	1		T148	1
all_levels[48]	auto[1]	4	1			T147	1		T148	1		T241	1
all_levels[49]	auto[0]	17	1			T6	1		T42	1		T149	1
all_levels[49]	auto[1]	3	1			T122	1		T242	1		T243	1
all_levels[50]	auto[0]	7	1			T150	2		T151	1		T152	1
all_levels[50]	auto[1]	2	1			T151	2		-	-		-	-
all_levels[51]	auto[0]	10	1			T44	1		T153	1		T154	1
all_levels[51]	auto[1]	1	1			T209	1		-	-		-	-
all_levels[52]	auto[0]	8	1			T155	1		T156	1		T157	1
all_levels[52]	auto[1]	2	1			T244	2		-	-		-	-
all_levels[53]	auto[0]	8	1			T5	1		T158	1		T159	1
all_levels[53]	auto[1]	4	1			T245	4		-	-		-	-
all_levels[54]	auto[0]	8	1			T138	1		T143	1		T160	1
all_levels[54]	auto[1]	2	1			T143	2		-	-		-	-
all_levels[55]	auto[0]	9	1			T47	1		T161	1		T140	1
all_levels[56]	auto[0]	8	1			T162	1		T140	1		T163	1
all_levels[56]	auto[1]	6	1			T246	6		-	-		-	-
all_levels[57]	auto[0]	6	1			T7	1		T164	1		T165	1
all_levels[58]	auto[0]	4	1			T6	1		T166	2		T102	1
all_levels[59]	auto[0]	5	1			T167	1		T168	1		T165	1
all_levels[60]	auto[0]	13	1			T34	1		T20	1		T169	1
all_levels[61]	auto[0]	3	1			T170	1		T171	1		T172	1
all_levels[62]	auto[0]	5	1			T20	2		T173	1		T153	1
all_levels[63]	auto[0]	6	1			T174	1		T175	1		T176	1
all_levels[63]	auto[1]	1	1			T247	1		-	-		-	-
all_levels[64]	auto[0]	95	1			T7	2		T12	1		T20	1
all_levels[64]	auto[1]	20	1			T12	1		T248	1		T121	1