Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	116252	1			T2	2		T3	52		T4	1475
all_pins[1]	116252	1			T2	2		T3	52		T4	1475
all_pins[2]	116252	1			T2	2		T3	52		T4	1475
all_pins[3]	116252	1			T2	2		T3	52		T4	1475
all_pins[4]	116252	1			T2	2		T3	52		T4	1475
all_pins[5]	116252	1			T2	2		T3	52		T4	1475
all_pins[6]	116252	1			T2	2		T3	52		T4	1475
all_pins[7]	116252	1			T2	2		T3	52		T4	1475
all_pins[8]	116252	1			T2	2		T3	52		T4	1475

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1000198	1			T2	18		T3	454		T4	12794
values[0x1]	46070	1			T3	14		T4	481		T5	28
transitions[0x0=>0x1]	37805	1			T3	14		T4	478		T5	19
transitions[0x1=>0x0]	37607	1			T3	14		T4	478		T5	18

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	92833	1			T2	2		T3	40		T4	1001
all_pins[0]	values[0x1]	23419	1			T3	12		T4	474		T5	12
all_pins[0]	transitions[0x0=>0x1]	22707	1			T3	12		T4	474		T5	12
all_pins[0]	transitions[0x1=>0x0]	1093	1			T3	1		T7	4		T9	1
all_pins[1]	values[0x0]	114447	1			T2	2		T3	51		T4	1475
all_pins[1]	values[0x1]	1805	1			T3	1		T6	1		T7	5
all_pins[1]	transitions[0x0=>0x1]	1709	1			T3	1		T7	5		T9	1
all_pins[1]	transitions[0x1=>0x0]	2448	1			T3	1		T4	3		T5	1
all_pins[2]	values[0x0]	113708	1			T2	2		T3	51		T4	1472
all_pins[2]	values[0x1]	2544	1			T3	1		T4	3		T5	1
all_pins[2]	transitions[0x0=>0x1]	2477	1			T3	1		T4	3		T5	1
all_pins[2]	transitions[0x1=>0x0]	234	1			T7	1		T9	2		T20	1
all_pins[3]	values[0x0]	115951	1			T2	2		T3	52		T4	1475
all_pins[3]	values[0x1]	301	1			T7	1		T9	4		T115	2
all_pins[3]	transitions[0x0=>0x1]	247	1			T7	1		T9	3		T115	2
all_pins[3]	transitions[0x1=>0x0]	439	1			T7	3		T11	1		T19	1
all_pins[4]	values[0x0]	115759	1			T2	2		T3	52		T4	1475
all_pins[4]	values[0x1]	493	1			T7	3		T9	1		T11	1
all_pins[4]	transitions[0x0=>0x1]	405	1			T7	1		T11	1		T17	11
all_pins[4]	transitions[0x1=>0x0]	178	1			T7	3		T13	1		T29	3
all_pins[5]	values[0x0]	115986	1			T2	2		T3	52		T4	1475
all_pins[5]	values[0x1]	266	1			T7	5		T9	1		T13	1
all_pins[5]	transitions[0x0=>0x1]	221	1			T7	4		T9	1		T13	1
all_pins[5]	transitions[0x1=>0x0]	815	1			T5	1		T10	1		T11	2
all_pins[6]	values[0x0]	115392	1			T2	2		T3	52		T4	1475
all_pins[6]	values[0x1]	860	1			T5	1		T7	1		T10	1
all_pins[6]	transitions[0x0=>0x1]	804	1			T7	1		T10	1		T11	2
all_pins[6]	transitions[0x1=>0x0]	298	1			T5	4		T7	5		T9	2
all_pins[7]	values[0x0]	115898	1			T2	2		T3	52		T4	1475
all_pins[7]	values[0x1]	354	1			T5	5		T7	5		T9	2
all_pins[7]	transitions[0x0=>0x1]	188	1			T5	5		T7	4		T9	2
all_pins[7]	transitions[0x1=>0x0]	15862	1			T4	4		T5	9		T6	1
all_pins[8]	values[0x0]	100224	1			T2	2		T3	52		T4	1471
all_pins[8]	values[0x1]	16028	1			T4	4		T5	9		T6	1
all_pins[8]	transitions[0x0=>0x1]	9047	1			T4	1		T5	1		T7	3
all_pins[8]	transitions[0x1=>0x0]	16240	1			T3	12		T4	471		T5	3