Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7804507	1			T3	11		T4	188036		T5	43
all_levels[1]	1956626	1			T4	17986		T5	2		T6	2
all_levels[2]	492412	1			T4	5805		T5	1		T6	1
all_levels[3]	328130	1			T4	5794		T5	1		T6	1
all_levels[4]	287511	1			T4	5807		T5	1		T7	99
all_levels[5]	306778	1			T4	5836		T5	1		T7	108
all_levels[6]	396620	1			T4	5836		T7	99		T8	2
all_levels[7]	245316	1			T4	5787		T5	1		T7	95
all_levels[8]	347746	1			T3	2		T4	5803		T7	117
all_levels[9]	429134	1			T4	5860		T7	95		T8	7
all_levels[10]	424501	1			T4	7854		T6	2		T7	108
all_levels[11]	734150	1			T3	2		T4	7881		T7	107
all_levels[12]	204510	1			T3	1		T4	7874		T7	111
all_levels[13]	334069	1			T4	93918		T7	104		T8	6
all_levels[14]	537617	1			T4	7757		T5	2		T7	92
all_levels[15]	226730	1			T4	5798		T7	126		T37	295
all_levels[16]	613304	1			T4	1805		T5	1		T7	100
all_levels[17]	523535	1			T4	1816		T7	88		T8	3
all_levels[18]	186372	1			T4	1816		T7	94		T8	5
all_levels[19]	269771	1			T4	1807		T7	123		T8	2
all_levels[20]	538681	1			T4	1818		T7	96		T8	2
all_levels[21]	285067	1			T4	1811		T7	105		T8	1
all_levels[22]	224607	1			T4	1821		T7	99		T8	6
all_levels[23]	237794	1			T3	2		T4	1811		T5	1
all_levels[24]	201601	1			T4	1785		T7	111		T8	4
all_levels[25]	627687	1			T4	1784		T6	52		T7	108
all_levels[26]	174466	1			T4	1804		T7	96		T8	1
all_levels[27]	229472	1			T3	2		T4	1818		T7	115
all_levels[28]	270685	1			T4	1817		T5	2		T7	98
all_levels[29]	214960	1			T3	1		T4	1816		T6	2
all_levels[30]	459778	1			T4	1815		T5	57		T7	91
all_levels[31]	454901	1			T3	2		T4	3807		T7	2378
all_levels[32]	11541723	1			T3	170		T4	215416		T5	9

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32106187

1

T3

186

T4

629998

T5

121

auto[1]

4574

1

T3

7

T4

1

T5

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7801892	1			T3	7		T4	188036		T5	43
all_levels[0]	auto[1]	2615	1			T3	4		T8	1		T9	3
all_levels[1]	auto[0]	1956327	1			T4	17986		T5	2		T6	2
all_levels[1]	auto[1]	299	1			T8	1		T37	1		T120	1
all_levels[2]	auto[0]	492366	1			T4	5805		T5	1		T6	1
all_levels[2]	auto[1]	46	1			T186	1		T284	3		T93	1
all_levels[3]	auto[0]	327995	1			T4	5794		T5	1		T6	1
all_levels[3]	auto[1]	135	1			T44	1		T177	1		T291	10
all_levels[4]	auto[0]	287468	1			T4	5807		T5	1		T7	99
all_levels[4]	auto[1]	43	1			T34	2		T177	2		T272	3
all_levels[5]	auto[0]	306749	1			T4	5836		T5	1		T7	108
all_levels[5]	auto[1]	29	1			T48	1		T180	1		T334	1
all_levels[6]	auto[0]	396600	1			T4	5836		T7	99		T8	2
all_levels[6]	auto[1]	20	1			T47	1		T141	1		T332	1
all_levels[7]	auto[0]	245199	1			T4	5787		T5	1		T7	95
all_levels[7]	auto[1]	117	1			T269	1		T340	1		T97	8
all_levels[8]	auto[0]	347715	1			T3	1		T4	5803		T7	117
all_levels[8]	auto[1]	31	1			T3	1		T8	1		T35	1
all_levels[9]	auto[0]	429098	1			T4	5860		T7	95		T8	6
all_levels[9]	auto[1]	36	1			T8	1		T161	2		T93	1
all_levels[10]	auto[0]	424457	1			T4	7854		T6	2		T7	108
all_levels[10]	auto[1]	44	1			T8	1		T12	1		T114	1
all_levels[11]	auto[0]	734128	1			T3	2		T4	7881		T7	107
all_levels[11]	auto[1]	22	1			T248	1		T341	1		T323	2
all_levels[12]	auto[0]	204481	1			T3	1		T4	7874		T7	111
all_levels[12]	auto[1]	29	1			T114	2		T202	1		T149	1
all_levels[13]	auto[0]	334043	1			T4	93918		T7	104		T8	5
all_levels[13]	auto[1]	26	1			T8	1		T342	1		T343	1
all_levels[14]	auto[0]	537591	1			T4	7757		T5	2		T7	92
all_levels[14]	auto[1]	26	1			T38	2		T42	1		T179	2
all_levels[15]	auto[0]	226518	1			T4	5798		T7	126		T37	295
all_levels[15]	auto[1]	212	1			T118	1		T286	1		T109	1
all_levels[16]	auto[0]	613280	1			T4	1805		T5	1		T7	100
all_levels[16]	auto[1]	24	1			T10	2		T259	3		T89	1
all_levels[17]	auto[0]	523510	1			T4	1816		T7	88		T8	3
all_levels[17]	auto[1]	25	1			T272	1		T334	1		T344	1
all_levels[18]	auto[0]	186351	1			T4	1816		T7	94		T8	5
all_levels[18]	auto[1]	21	1			T179	2		T45	1		T93	2
all_levels[19]	auto[0]	269747	1			T4	1807		T7	123		T8	2
all_levels[19]	auto[1]	24	1			T38	2		T215	1		T314	1
all_levels[20]	auto[0]	538657	1			T4	1818		T7	96		T8	2
all_levels[20]	auto[1]	24	1			T115	1		T313	1		T325	1
all_levels[21]	auto[0]	285050	1			T4	1811		T7	105		T8	1
all_levels[21]	auto[1]	17	1			T180	2		T91	2		T144	1
all_levels[22]	auto[0]	224586	1			T4	1821		T7	99		T8	6
all_levels[22]	auto[1]	21	1			T272	1		T99	1		T264	1
all_levels[23]	auto[0]	237773	1			T3	2		T4	1811		T5	1
all_levels[23]	auto[1]	21	1			T266	1		T109	1		T345	2
all_levels[24]	auto[0]	201579	1			T4	1785		T7	111		T8	4
all_levels[24]	auto[1]	22	1			T115	1		T166	3		T234	1
all_levels[25]	auto[0]	627674	1			T4	1784		T6	52		T7	108
all_levels[25]	auto[1]	13	1			T49	1		T252	1		T346	1
all_levels[26]	auto[0]	174446	1			T4	1804		T7	96		T8	1
all_levels[26]	auto[1]	20	1			T45	1		T264	1		T347	1
all_levels[27]	auto[0]	229456	1			T3	2		T4	1818		T7	115
all_levels[27]	auto[1]	16	1			T45	1		T99	1		T341	1
all_levels[28]	auto[0]	270674	1			T4	1817		T5	2		T7	98
all_levels[28]	auto[1]	11	1			T89	1		T323	1		T348	1
all_levels[29]	auto[0]	214944	1			T3	1		T4	1816		T6	2
all_levels[29]	auto[1]	16	1			T8	2		T93	1		T308	2
all_levels[30]	auto[0]	459754	1			T4	1815		T5	57		T7	91
all_levels[30]	auto[1]	24	1			T318	1		T178	1		T324	1
all_levels[31]	auto[0]	454878	1			T3	2		T4	3807		T7	2378
all_levels[31]	auto[1]	23	1			T349	1		T309	2		T330	1
all_levels[32]	auto[0]	11541201	1			T3	168		T4	215415		T5	8
all_levels[32]	auto[1]	522	1			T3	2		T4	1		T5	1