Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	852	1			T7	11		T9	8		T29	4
all_values[1]	852	1			T7	11		T9	8		T29	4
all_values[2]	852	1			T7	11		T9	8		T29	4
all_values[3]	852	1			T7	11		T9	8		T29	4
all_values[4]	852	1			T7	11		T9	8		T29	4
all_values[5]	852	1			T7	11		T9	8		T29	4
all_values[6]	852	1			T7	11		T9	8		T29	4
all_values[7]	852	1			T7	11		T9	8		T29	4
all_values[8]	852	1			T7	11		T9	8		T29	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4182

1

T7

54

T9

30

T29

19

auto[1]

3486

1

T7

45

T9

42

T29

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2544

1

T7

34

T9

22

T29

11

auto[1]

5124

1

T7

65

T9

50

T29

25

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4530

1

T7

63

T9

47

T29

22

auto[1]

3138

1

T7

36

T9

25

T29

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	273	1			T7	2		T9	1		T29	1
all_values[0]	auto[0]	auto[1]	auto[1]	227	1			T7	5		T9	6		T29	2
all_values[0]	auto[1]	auto[0]	auto[1]	203	1			T7	2		T9	1		T19	1
all_values[0]	auto[1]	auto[1]	auto[1]	149	1			T7	2		T29	1		T19	2
all_values[1]	auto[0]	auto[0]	auto[0]	291	1			T7	6		T9	1		T29	1
all_values[1]	auto[0]	auto[1]	auto[0]	221	1			T7	3		T9	3		T29	3
all_values[1]	auto[1]	auto[0]	auto[1]	186	1			T9	2		T30	3		T31	2
all_values[1]	auto[1]	auto[1]	auto[1]	154	1			T7	2		T9	2		T19	1
all_values[2]	auto[0]	auto[0]	auto[0]	167	1			T7	2		T30	1		T33	1
all_values[2]	auto[0]	auto[0]	auto[1]	82	1			T7	3		T9	2		T30	1
all_values[2]	auto[0]	auto[1]	auto[0]	148	1			T7	1		T9	1		T19	2
all_values[2]	auto[0]	auto[1]	auto[1]	94	1			T9	1		T29	1		T30	5
all_values[2]	auto[1]	auto[0]	auto[1]	199	1			T7	3		T9	1		T29	2
all_values[2]	auto[1]	auto[1]	auto[1]	162	1			T7	2		T9	3		T29	1
all_values[3]	auto[0]	auto[0]	auto[0]	183	1			T7	5		T9	1		T29	1
all_values[3]	auto[0]	auto[0]	auto[1]	95	1			T7	2		T9	2		T30	1
all_values[3]	auto[0]	auto[1]	auto[0]	139	1			T7	1		T19	5		T30	3
all_values[3]	auto[0]	auto[1]	auto[1]	81	1			T9	1		T29	2		T30	2
all_values[3]	auto[1]	auto[0]	auto[1]	215	1			T7	3		T29	1		T30	2
all_values[3]	auto[1]	auto[1]	auto[1]	139	1			T9	4		T19	1		T30	3
all_values[4]	auto[0]	auto[0]	auto[0]	208	1			T7	5		T9	2		T29	2
all_values[4]	auto[0]	auto[0]	auto[1]	84	1			T9	1		T30	1		T104	1
all_values[4]	auto[0]	auto[1]	auto[0]	136	1			T7	2		T9	3		T19	2
all_values[4]	auto[0]	auto[1]	auto[1]	73	1			T7	2		T30	2		T33	1
all_values[4]	auto[1]	auto[0]	auto[1]	197	1			T7	1		T9	1		T29	2
all_values[4]	auto[1]	auto[1]	auto[1]	154	1			T7	1		T9	1		T19	2
all_values[5]	auto[0]	auto[0]	auto[0]	195	1			T9	1		T19	1		T30	4
all_values[5]	auto[0]	auto[0]	auto[1]	71	1			T9	2		T30	1		T31	1
all_values[5]	auto[0]	auto[1]	auto[0]	158	1			T7	1		T9	2		T19	2
all_values[5]	auto[0]	auto[1]	auto[1]	87	1			T7	3		T29	1		T33	1
all_values[5]	auto[1]	auto[0]	auto[1]	172	1			T7	4		T9	1		T29	2
all_values[5]	auto[1]	auto[1]	auto[1]	169	1			T7	3		T9	2		T29	1
all_values[6]	auto[0]	auto[0]	auto[0]	205	1			T7	2		T9	2		T19	1
all_values[6]	auto[0]	auto[0]	auto[1]	79	1			T7	3		T9	1		T29	1
all_values[6]	auto[0]	auto[1]	auto[0]	172	1			T7	2		T9	4		T19	1
all_values[6]	auto[0]	auto[1]	auto[1]	65	1			T7	1		T19	2		T30	2
all_values[6]	auto[1]	auto[0]	auto[1]	173	1			T7	2		T9	1		T29	3
all_values[6]	auto[1]	auto[1]	auto[1]	158	1			T7	1		T19	2		T30	4
all_values[7]	auto[0]	auto[0]	auto[0]	180	1			T9	1		T29	2		T19	3
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T7	1		T9	1		T33	1
all_values[7]	auto[0]	auto[1]	auto[0]	141	1			T7	4		T9	1		T29	2
all_values[7]	auto[0]	auto[1]	auto[1]	92	1			T7	1		T9	1		T19	1
all_values[7]	auto[1]	auto[0]	auto[1]	212	1			T7	1		T9	1		T19	3
all_values[7]	auto[1]	auto[1]	auto[1]	150	1			T7	4		T9	3		T30	1
all_values[8]	auto[0]	auto[0]	auto[1]	245	1			T7	4		T9	3		T29	1
all_values[8]	auto[0]	auto[1]	auto[1]	261	1			T7	2		T9	3		T29	2
all_values[8]	auto[1]	auto[0]	auto[1]	190	1			T7	3		T9	1		T19	2
all_values[8]	auto[1]	auto[1]	auto[1]	156	1			T7	2		T9	1		T29	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal