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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.53


Total test records in report: 1317
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T1257 /workspace/coverage/cover_reg_top/33.uart_intr_test.2677853765 Aug 06 04:26:50 PM PDT 24 Aug 06 04:26:50 PM PDT 24 11046288 ps
T1258 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2747387840 Aug 06 04:26:14 PM PDT 24 Aug 06 04:26:15 PM PDT 24 74809652 ps
T79 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2933181255 Aug 06 04:26:23 PM PDT 24 Aug 06 04:26:24 PM PDT 24 365541371 ps
T1259 /workspace/coverage/cover_reg_top/16.uart_intr_test.1917104473 Aug 06 04:25:49 PM PDT 24 Aug 06 04:25:49 PM PDT 24 76577433 ps
T84 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.56110076 Aug 06 04:27:11 PM PDT 24 Aug 06 04:27:13 PM PDT 24 394009177 ps
T1260 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2707160586 Aug 06 04:25:58 PM PDT 24 Aug 06 04:25:58 PM PDT 24 58213651 ps
T1261 /workspace/coverage/cover_reg_top/8.uart_intr_test.2842020613 Aug 06 04:27:05 PM PDT 24 Aug 06 04:27:06 PM PDT 24 11189786 ps
T1262 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3003843657 Aug 06 04:26:13 PM PDT 24 Aug 06 04:26:13 PM PDT 24 123239042 ps
T1263 /workspace/coverage/cover_reg_top/16.uart_csr_rw.935684054 Aug 06 04:27:11 PM PDT 24 Aug 06 04:27:11 PM PDT 24 20890370 ps
T1264 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1045096915 Aug 06 04:26:38 PM PDT 24 Aug 06 04:26:39 PM PDT 24 86855813 ps
T1265 /workspace/coverage/cover_reg_top/9.uart_tl_errors.1806694801 Aug 06 04:26:12 PM PDT 24 Aug 06 04:26:14 PM PDT 24 61034510 ps
T1266 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.527560670 Aug 06 04:28:07 PM PDT 24 Aug 06 04:28:09 PM PDT 24 90146657 ps
T1267 /workspace/coverage/cover_reg_top/17.uart_tl_errors.758648102 Aug 06 04:28:02 PM PDT 24 Aug 06 04:28:03 PM PDT 24 56974961 ps
T1268 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.562917723 Aug 06 04:27:10 PM PDT 24 Aug 06 04:27:11 PM PDT 24 60438914 ps
T1269 /workspace/coverage/cover_reg_top/4.uart_tl_errors.3113388620 Aug 06 04:25:59 PM PDT 24 Aug 06 04:26:01 PM PDT 24 356351882 ps
T1270 /workspace/coverage/cover_reg_top/37.uart_intr_test.3487953957 Aug 06 04:26:51 PM PDT 24 Aug 06 04:26:52 PM PDT 24 54025063 ps
T1271 /workspace/coverage/cover_reg_top/35.uart_intr_test.2511931754 Aug 06 04:26:16 PM PDT 24 Aug 06 04:26:17 PM PDT 24 15550363 ps
T1272 /workspace/coverage/cover_reg_top/27.uart_intr_test.1766986979 Aug 06 04:27:46 PM PDT 24 Aug 06 04:27:47 PM PDT 24 26976158 ps
T1273 /workspace/coverage/cover_reg_top/17.uart_csr_rw.3269079280 Aug 06 04:27:42 PM PDT 24 Aug 06 04:27:43 PM PDT 24 38794582 ps
T1274 /workspace/coverage/cover_reg_top/7.uart_csr_rw.3406836949 Aug 06 04:25:41 PM PDT 24 Aug 06 04:25:42 PM PDT 24 29628075 ps
T1275 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2224833897 Aug 06 04:27:06 PM PDT 24 Aug 06 04:27:06 PM PDT 24 23866020 ps
T1276 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3920812815 Aug 06 04:25:54 PM PDT 24 Aug 06 04:25:55 PM PDT 24 56895444 ps
T1277 /workspace/coverage/cover_reg_top/18.uart_intr_test.3000835561 Aug 06 04:27:59 PM PDT 24 Aug 06 04:28:00 PM PDT 24 36434171 ps
T1278 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1638982961 Aug 06 04:26:11 PM PDT 24 Aug 06 04:26:13 PM PDT 24 120952076 ps
T1279 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2532915285 Aug 06 04:26:23 PM PDT 24 Aug 06 04:26:24 PM PDT 24 22826156 ps
T1280 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3464266074 Aug 06 04:26:15 PM PDT 24 Aug 06 04:26:16 PM PDT 24 25405861 ps
T1281 /workspace/coverage/cover_reg_top/7.uart_tl_errors.1461902341 Aug 06 04:26:39 PM PDT 24 Aug 06 04:26:40 PM PDT 24 62276340 ps
T1282 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3644897722 Aug 06 04:26:41 PM PDT 24 Aug 06 04:26:42 PM PDT 24 13271200 ps
T85 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3963910817 Aug 06 04:27:42 PM PDT 24 Aug 06 04:27:43 PM PDT 24 314260484 ps
T1283 /workspace/coverage/cover_reg_top/13.uart_intr_test.3743503082 Aug 06 04:27:05 PM PDT 24 Aug 06 04:27:06 PM PDT 24 41483615 ps
T1284 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1015991217 Aug 06 04:27:55 PM PDT 24 Aug 06 04:27:56 PM PDT 24 78085171 ps
T1285 /workspace/coverage/cover_reg_top/0.uart_intr_test.4001521313 Aug 06 04:26:03 PM PDT 24 Aug 06 04:26:04 PM PDT 24 12890817 ps
T1286 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3274640927 Aug 06 04:26:26 PM PDT 24 Aug 06 04:26:27 PM PDT 24 59769463 ps
T1287 /workspace/coverage/cover_reg_top/30.uart_intr_test.2971786857 Aug 06 04:26:17 PM PDT 24 Aug 06 04:26:18 PM PDT 24 15564412 ps
T1288 /workspace/coverage/cover_reg_top/9.uart_csr_rw.914452578 Aug 06 04:26:12 PM PDT 24 Aug 06 04:26:13 PM PDT 24 37761458 ps
T1289 /workspace/coverage/cover_reg_top/10.uart_tl_errors.2264121791 Aug 06 04:25:26 PM PDT 24 Aug 06 04:25:28 PM PDT 24 134791385 ps
T1290 /workspace/coverage/cover_reg_top/45.uart_intr_test.2995080274 Aug 06 04:27:46 PM PDT 24 Aug 06 04:27:46 PM PDT 24 16190723 ps
T1291 /workspace/coverage/cover_reg_top/10.uart_csr_rw.808717308 Aug 06 04:25:55 PM PDT 24 Aug 06 04:25:56 PM PDT 24 18594176 ps
T1292 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1607128401 Aug 06 04:27:54 PM PDT 24 Aug 06 04:27:55 PM PDT 24 101833494 ps
T1293 /workspace/coverage/cover_reg_top/14.uart_intr_test.2974761944 Aug 06 04:26:28 PM PDT 24 Aug 06 04:26:29 PM PDT 24 45601089 ps
T1294 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4026783279 Aug 06 04:25:26 PM PDT 24 Aug 06 04:25:27 PM PDT 24 42848054 ps
T1295 /workspace/coverage/cover_reg_top/11.uart_intr_test.504416295 Aug 06 04:28:03 PM PDT 24 Aug 06 04:28:04 PM PDT 24 17333244 ps
T1296 /workspace/coverage/cover_reg_top/4.uart_csr_rw.4273536809 Aug 06 04:26:15 PM PDT 24 Aug 06 04:26:16 PM PDT 24 44900208 ps
T1297 /workspace/coverage/cover_reg_top/11.uart_csr_rw.3604085594 Aug 06 04:28:08 PM PDT 24 Aug 06 04:28:08 PM PDT 24 42529633 ps
T1298 /workspace/coverage/cover_reg_top/41.uart_intr_test.3078424377 Aug 06 04:26:47 PM PDT 24 Aug 06 04:26:48 PM PDT 24 14671259 ps
T1299 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1341873476 Aug 06 04:26:13 PM PDT 24 Aug 06 04:26:16 PM PDT 24 2090723354 ps
T64 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1409959059 Aug 06 04:26:26 PM PDT 24 Aug 06 04:26:27 PM PDT 24 125995136 ps
T1300 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2371595205 Aug 06 04:26:05 PM PDT 24 Aug 06 04:26:06 PM PDT 24 200076875 ps
T1301 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1663914597 Aug 06 04:27:52 PM PDT 24 Aug 06 04:27:53 PM PDT 24 21497279 ps
T1302 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2235216205 Aug 06 04:27:42 PM PDT 24 Aug 06 04:27:43 PM PDT 24 15900593 ps
T1303 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3931443475 Aug 06 04:27:11 PM PDT 24 Aug 06 04:27:11 PM PDT 24 121411577 ps
T1304 /workspace/coverage/cover_reg_top/36.uart_intr_test.3855435609 Aug 06 04:26:14 PM PDT 24 Aug 06 04:26:14 PM PDT 24 23859933 ps
T1305 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2320501257 Aug 06 04:27:11 PM PDT 24 Aug 06 04:27:12 PM PDT 24 25007947 ps
T111 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2971135094 Aug 06 04:28:18 PM PDT 24 Aug 06 04:28:19 PM PDT 24 84142328 ps
T1306 /workspace/coverage/cover_reg_top/15.uart_tl_errors.3999959215 Aug 06 04:27:11 PM PDT 24 Aug 06 04:27:13 PM PDT 24 137869163 ps
T1307 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.4264232041 Aug 06 04:27:56 PM PDT 24 Aug 06 04:27:57 PM PDT 24 257934367 ps
T1308 /workspace/coverage/cover_reg_top/3.uart_tl_errors.1582059264 Aug 06 04:26:14 PM PDT 24 Aug 06 04:26:16 PM PDT 24 93786776 ps
T1309 /workspace/coverage/cover_reg_top/3.uart_intr_test.3022967756 Aug 06 04:26:14 PM PDT 24 Aug 06 04:26:15 PM PDT 24 28013573 ps
T1310 /workspace/coverage/cover_reg_top/1.uart_intr_test.2142098552 Aug 06 04:27:42 PM PDT 24 Aug 06 04:27:43 PM PDT 24 11960706 ps
T1311 /workspace/coverage/cover_reg_top/1.uart_tl_errors.3611123702 Aug 06 04:25:50 PM PDT 24 Aug 06 04:25:51 PM PDT 24 73971738 ps
T112 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.4061759753 Aug 06 04:26:03 PM PDT 24 Aug 06 04:26:04 PM PDT 24 143266424 ps
T1312 /workspace/coverage/cover_reg_top/6.uart_csr_rw.652702150 Aug 06 04:26:37 PM PDT 24 Aug 06 04:26:38 PM PDT 24 32192674 ps
T1313 /workspace/coverage/cover_reg_top/40.uart_intr_test.1831591014 Aug 06 04:26:49 PM PDT 24 Aug 06 04:26:50 PM PDT 24 26414065 ps
T1314 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3305253495 Aug 06 04:27:40 PM PDT 24 Aug 06 04:27:42 PM PDT 24 362971405 ps
T1315 /workspace/coverage/cover_reg_top/2.uart_tl_errors.3651824461 Aug 06 04:27:53 PM PDT 24 Aug 06 04:27:54 PM PDT 24 32614914 ps
T1316 /workspace/coverage/cover_reg_top/13.uart_tl_errors.1973850109 Aug 06 04:25:37 PM PDT 24 Aug 06 04:25:39 PM PDT 24 50478696 ps
T1317 /workspace/coverage/cover_reg_top/18.uart_csr_rw.1383755172 Aug 06 04:26:04 PM PDT 24 Aug 06 04:26:04 PM PDT 24 59357447 ps

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3299949845
Short name T9
Test name
Test status
Simulation time 102337717883 ps
CPU time 259.04 seconds
Started Aug 06 04:28:12 PM PDT 24
Finished Aug 06 04:32:31 PM PDT 24
Peak memory 215300 kb
Host smart-13edb036-e82f-4b0a-a95f-13366b29196b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299949845 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3299949845
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all.3933574424
Short name T42
Test name
Test status
Simulation time 180070340821 ps
CPU time 607.52 seconds
Started Aug 06 04:29:29 PM PDT 24
Finished Aug 06 04:39:37 PM PDT 24
Peak memory 199820 kb
Host smart-5e25148c-915b-45e5-85b2-6cf82b459f30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933574424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3933574424
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1532848588
Short name T8
Test name
Test status
Simulation time 83097826342 ps
CPU time 155.21 seconds
Started Aug 06 04:30:57 PM PDT 24
Finished Aug 06 04:33:32 PM PDT 24
Peak memory 199212 kb
Host smart-4b3ab904-a62a-4520-b5ab-d74240d19315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532848588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1532848588
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.2612217313
Short name T19
Test name
Test status
Simulation time 157814565041 ps
CPU time 691.2 seconds
Started Aug 06 04:30:38 PM PDT 24
Finished Aug 06 04:42:10 PM PDT 24
Peak memory 224544 kb
Host smart-da6d7ab4-2454-4916-bf82-93311d968ce3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612217313 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.2612217313
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.5815652
Short name T18
Test name
Test status
Simulation time 56665192512 ps
CPU time 907.04 seconds
Started Aug 06 04:30:28 PM PDT 24
Finished Aug 06 04:45:35 PM PDT 24
Peak memory 215820 kb
Host smart-5a25f137-37d2-4f08-bab8-66f2bb9e42d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5815652 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.5815652
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all.2899941217
Short name T252
Test name
Test status
Simulation time 274763750026 ps
CPU time 216.46 seconds
Started Aug 06 04:28:33 PM PDT 24
Finished Aug 06 04:32:09 PM PDT 24
Peak memory 199660 kb
Host smart-0afbab67-cbce-4e90-8a24-2277bc55d75e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899941217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2899941217
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all.2429771217
Short name T174
Test name
Test status
Simulation time 220425650297 ps
CPU time 352.86 seconds
Started Aug 06 04:29:33 PM PDT 24
Finished Aug 06 04:35:26 PM PDT 24
Peak memory 199672 kb
Host smart-bb9e9708-11a0-4b56-b806-7364699c8146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429771217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2429771217
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1196189471
Short name T30
Test name
Test status
Simulation time 45263131786 ps
CPU time 643.66 seconds
Started Aug 06 04:29:12 PM PDT 24
Finished Aug 06 04:39:56 PM PDT 24
Peak memory 216368 kb
Host smart-58df51c6-8095-46b4-b068-f6780a99e750
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196189471 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1196189471
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1235193847
Short name T115
Test name
Test status
Simulation time 125051541688 ps
CPU time 48.91 seconds
Started Aug 06 04:31:14 PM PDT 24
Finished Aug 06 04:32:03 PM PDT 24
Peak memory 199712 kb
Host smart-4eac3dba-8739-4f69-94dc-4860fee5822a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235193847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1235193847
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all.2987498818
Short name T7
Test name
Test status
Simulation time 104249389134 ps
CPU time 368.06 seconds
Started Aug 06 04:28:49 PM PDT 24
Finished Aug 06 04:34:58 PM PDT 24
Peak memory 199716 kb
Host smart-59fb7f30-91b2-4fb5-ae4e-b1148f04503f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987498818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2987498818
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2859882396
Short name T28
Test name
Test status
Simulation time 147534561 ps
CPU time 0.79 seconds
Started Aug 06 04:28:10 PM PDT 24
Finished Aug 06 04:28:11 PM PDT 24
Peak memory 218188 kb
Host smart-c282d7f7-b9a3-4963-95f9-e860b1ad5bf9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859882396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2859882396
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/10.uart_alert_test.129972292
Short name T357
Test name
Test status
Simulation time 41539778 ps
CPU time 0.56 seconds
Started Aug 06 04:28:41 PM PDT 24
Finished Aug 06 04:28:42 PM PDT 24
Peak memory 195092 kb
Host smart-d993cb2f-9a4c-4f3f-b479-2bf02463c331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129972292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.129972292
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.2184399815
Short name T254
Test name
Test status
Simulation time 78948209311 ps
CPU time 119.72 seconds
Started Aug 06 04:30:01 PM PDT 24
Finished Aug 06 04:32:00 PM PDT 24
Peak memory 199860 kb
Host smart-79aa227a-819c-46e0-8489-60ab05a56cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184399815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2184399815
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3579377618
Short name T288
Test name
Test status
Simulation time 92150514157 ps
CPU time 1110.67 seconds
Started Aug 06 04:30:11 PM PDT 24
Finished Aug 06 04:48:42 PM PDT 24
Peak memory 225960 kb
Host smart-fe789c6f-a288-406f-943e-f12163a0c530
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579377618 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3579377618
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.281622701
Short name T259
Test name
Test status
Simulation time 124451015165 ps
CPU time 26.41 seconds
Started Aug 06 04:30:57 PM PDT 24
Finished Aug 06 04:31:23 PM PDT 24
Peak memory 199740 kb
Host smart-755f517b-3d12-482f-a298-6a0ac5a7d742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281622701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.281622701
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all.2976258694
Short name T104
Test name
Test status
Simulation time 253266734142 ps
CPU time 199.35 seconds
Started Aug 06 04:29:01 PM PDT 24
Finished Aug 06 04:32:20 PM PDT 24
Peak memory 208116 kb
Host smart-a78dd65c-7c63-4cd6-a0cb-60d9ffe60689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976258694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2976258694
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3376896953
Short name T41
Test name
Test status
Simulation time 15486129517 ps
CPU time 21.4 seconds
Started Aug 06 04:28:52 PM PDT 24
Finished Aug 06 04:29:13 PM PDT 24
Peak memory 199628 kb
Host smart-6cda86c5-2bec-4e5a-9a2a-b61509989f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376896953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3376896953
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.823160058
Short name T32
Test name
Test status
Simulation time 37476488035 ps
CPU time 1431.63 seconds
Started Aug 06 04:28:20 PM PDT 24
Finished Aug 06 04:52:11 PM PDT 24
Peak memory 216384 kb
Host smart-1cb03cf7-1f50-4459-9fce-55f79a078db1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823160058 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.823160058
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2705328768
Short name T29
Test name
Test status
Simulation time 35941868599 ps
CPU time 265.59 seconds
Started Aug 06 04:31:21 PM PDT 24
Finished Aug 06 04:35:47 PM PDT 24
Peak memory 215240 kb
Host smart-3efaa317-3d37-480c-996d-e43b6478f057
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705328768 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2705328768
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3036466220
Short name T138
Test name
Test status
Simulation time 494412254893 ps
CPU time 45.99 seconds
Started Aug 06 04:28:58 PM PDT 24
Finished Aug 06 04:29:45 PM PDT 24
Peak memory 197996 kb
Host smart-0cbe5c5f-af93-4159-8812-166a5ac6ff35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036466220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3036466220
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3643543221
Short name T80
Test name
Test status
Simulation time 70289232 ps
CPU time 1.11 seconds
Started Aug 06 04:26:13 PM PDT 24
Finished Aug 06 04:26:15 PM PDT 24
Peak memory 199376 kb
Host smart-5e9923ba-b22c-4ccf-a977-8e34bcdeded0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643543221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3643543221
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1938471422
Short name T131
Test name
Test status
Simulation time 212591890920 ps
CPU time 149.36 seconds
Started Aug 06 04:30:56 PM PDT 24
Finished Aug 06 04:33:26 PM PDT 24
Peak memory 199660 kb
Host smart-33576060-9533-491f-a05c-a3667894eefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938471422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1938471422
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3156194835
Short name T46
Test name
Test status
Simulation time 96500871156 ps
CPU time 202.24 seconds
Started Aug 06 04:29:46 PM PDT 24
Finished Aug 06 04:33:08 PM PDT 24
Peak memory 208104 kb
Host smart-529a6b2e-1be4-4b7a-857c-d3a104ac6db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156194835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3156194835
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2210805552
Short name T62
Test name
Test status
Simulation time 12740709 ps
CPU time 0.62 seconds
Started Aug 06 04:26:10 PM PDT 24
Finished Aug 06 04:26:11 PM PDT 24
Peak memory 194920 kb
Host smart-6ad2dcac-6741-408f-87bc-953467c2516b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210805552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2210805552
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1509213612
Short name T43
Test name
Test status
Simulation time 105512743877 ps
CPU time 95.14 seconds
Started Aug 06 04:28:30 PM PDT 24
Finished Aug 06 04:30:05 PM PDT 24
Peak memory 199796 kb
Host smart-c553ddaa-54f6-4c20-91ab-59b1dcb2912d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509213612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1509213612
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.76220758
Short name T139
Test name
Test status
Simulation time 127962724362 ps
CPU time 85.37 seconds
Started Aug 06 04:28:13 PM PDT 24
Finished Aug 06 04:29:39 PM PDT 24
Peak memory 199644 kb
Host smart-28a67ea2-86a2-4d3a-9139-bb234ead6c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76220758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.76220758
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.252624719
Short name T94
Test name
Test status
Simulation time 224934650538 ps
CPU time 777.21 seconds
Started Aug 06 04:30:26 PM PDT 24
Finished Aug 06 04:43:23 PM PDT 24
Peak memory 224596 kb
Host smart-50f43c03-11e3-4dc5-b315-31608a333279
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252624719 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.252624719
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3743994006
Short name T102
Test name
Test status
Simulation time 116483123346 ps
CPU time 654.57 seconds
Started Aug 06 04:29:58 PM PDT 24
Finished Aug 06 04:40:53 PM PDT 24
Peak memory 216368 kb
Host smart-e09456f6-eec9-4e91-a409-d00d00fc8110
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743994006 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3743994006
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3321624274
Short name T178
Test name
Test status
Simulation time 39613995317 ps
CPU time 54.66 seconds
Started Aug 06 04:31:16 PM PDT 24
Finished Aug 06 04:32:10 PM PDT 24
Peak memory 199596 kb
Host smart-7276a7a3-be4f-462c-8da1-daa4b20840fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321624274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3321624274
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all.1493523910
Short name T162
Test name
Test status
Simulation time 490499260249 ps
CPU time 270.47 seconds
Started Aug 06 04:29:57 PM PDT 24
Finished Aug 06 04:34:28 PM PDT 24
Peak memory 208232 kb
Host smart-e062d1d5-3198-4b97-8474-e3dc4a997890
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493523910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1493523910
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2839262098
Short name T114
Test name
Test status
Simulation time 95538954959 ps
CPU time 158.88 seconds
Started Aug 06 04:30:39 PM PDT 24
Finished Aug 06 04:33:18 PM PDT 24
Peak memory 199736 kb
Host smart-70d116f4-2889-47a0-8eb5-8a43d23fcd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839262098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2839262098
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3749042045
Short name T156
Test name
Test status
Simulation time 127426705133 ps
CPU time 192.61 seconds
Started Aug 06 04:29:36 PM PDT 24
Finished Aug 06 04:32:49 PM PDT 24
Peak memory 199712 kb
Host smart-25eafb3d-9354-4810-88bf-42a1d5742719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749042045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3749042045
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1997640037
Short name T209
Test name
Test status
Simulation time 267000049486 ps
CPU time 795.81 seconds
Started Aug 06 04:29:57 PM PDT 24
Finished Aug 06 04:43:13 PM PDT 24
Peak memory 224584 kb
Host smart-ed54951f-efda-4736-913c-47b5346e09d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997640037 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1997640037
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3963910817
Short name T85
Test name
Test status
Simulation time 314260484 ps
CPU time 1.35 seconds
Started Aug 06 04:27:42 PM PDT 24
Finished Aug 06 04:27:43 PM PDT 24
Peak memory 197680 kb
Host smart-6ad19a16-5f52-4c90-963b-084684fec2eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963910817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3963910817
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2260403482
Short name T293
Test name
Test status
Simulation time 138552224326 ps
CPU time 62.07 seconds
Started Aug 06 04:28:18 PM PDT 24
Finished Aug 06 04:29:20 PM PDT 24
Peak memory 208096 kb
Host smart-42c6d29c-ee3a-4bb7-9e55-df5dc2a6abe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260403482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2260403482
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1579465112
Short name T225
Test name
Test status
Simulation time 189913215297 ps
CPU time 247.82 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:34:48 PM PDT 24
Peak memory 199768 kb
Host smart-0369341a-af11-4300-8e9f-bdfb3f4a2d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579465112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1579465112
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.723039348
Short name T264
Test name
Test status
Simulation time 93944426068 ps
CPU time 506.23 seconds
Started Aug 06 04:29:34 PM PDT 24
Finished Aug 06 04:38:00 PM PDT 24
Peak memory 216484 kb
Host smart-806631e4-c348-418b-bd1c-c570a50f192e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723039348 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.723039348
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3603625322
Short name T108
Test name
Test status
Simulation time 36469406054 ps
CPU time 48.85 seconds
Started Aug 06 04:28:54 PM PDT 24
Finished Aug 06 04:29:44 PM PDT 24
Peak memory 199744 kb
Host smart-467276d8-3414-40f7-9c60-63291bd451bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603625322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3603625322
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1515318513
Short name T205
Test name
Test status
Simulation time 68237079712 ps
CPU time 247.23 seconds
Started Aug 06 04:30:58 PM PDT 24
Finished Aug 06 04:35:06 PM PDT 24
Peak memory 199672 kb
Host smart-ecfeacfa-0c69-4696-b994-df3d813c3921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515318513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1515318513
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.714079170
Short name T122
Test name
Test status
Simulation time 138299548356 ps
CPU time 99.49 seconds
Started Aug 06 04:31:31 PM PDT 24
Finished Aug 06 04:33:10 PM PDT 24
Peak memory 199752 kb
Host smart-8db48d88-b57b-412c-b512-2e88b7c45ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714079170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.714079170
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3033024028
Short name T240
Test name
Test status
Simulation time 60029115175 ps
CPU time 717.02 seconds
Started Aug 06 04:28:13 PM PDT 24
Finished Aug 06 04:40:10 PM PDT 24
Peak memory 216348 kb
Host smart-1b02ff22-0581-44b7-9f61-d3339bcb3ece
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033024028 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3033024028
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2542625027
Short name T922
Test name
Test status
Simulation time 17883971439 ps
CPU time 26.74 seconds
Started Aug 06 04:30:37 PM PDT 24
Finished Aug 06 04:31:04 PM PDT 24
Peak memory 199628 kb
Host smart-b623a747-1259-4470-8672-07fd48dbe541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542625027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2542625027
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1533665329
Short name T49
Test name
Test status
Simulation time 144948303323 ps
CPU time 188.86 seconds
Started Aug 06 04:28:29 PM PDT 24
Finished Aug 06 04:31:38 PM PDT 24
Peak memory 199980 kb
Host smart-a9f8c109-9e2b-4c76-9ebb-024835a3397c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533665329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1533665329
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3258072082
Short name T228
Test name
Test status
Simulation time 160598661193 ps
CPU time 194.26 seconds
Started Aug 06 04:30:42 PM PDT 24
Finished Aug 06 04:33:56 PM PDT 24
Peak memory 199772 kb
Host smart-754c6793-c1e3-451e-a8d1-b11fea57ffc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258072082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3258072082
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all.2171445916
Short name T109
Test name
Test status
Simulation time 289906174721 ps
CPU time 565.18 seconds
Started Aug 06 04:28:11 PM PDT 24
Finished Aug 06 04:37:36 PM PDT 24
Peak memory 199664 kb
Host smart-e4d43682-82fb-4c5e-825c-c76f23801a1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171445916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2171445916
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1054648521
Short name T158
Test name
Test status
Simulation time 133994881690 ps
CPU time 103 seconds
Started Aug 06 04:30:58 PM PDT 24
Finished Aug 06 04:32:41 PM PDT 24
Peak memory 199760 kb
Host smart-55f812e3-2556-4d90-a1b5-10d1768d0742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054648521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1054648521
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3841369313
Short name T165
Test name
Test status
Simulation time 17960187698 ps
CPU time 24.34 seconds
Started Aug 06 04:31:36 PM PDT 24
Finished Aug 06 04:32:01 PM PDT 24
Peak memory 199672 kb
Host smart-00f840d5-3a6d-4005-b6f6-9ac9ecd59498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841369313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3841369313
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3942164669
Short name T121
Test name
Test status
Simulation time 11855956037 ps
CPU time 12.92 seconds
Started Aug 06 04:29:53 PM PDT 24
Finished Aug 06 04:30:06 PM PDT 24
Peak memory 199744 kb
Host smart-7b9f1c9f-381e-4ccb-9b1f-e0506b458da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942164669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3942164669
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2976044868
Short name T789
Test name
Test status
Simulation time 111355232959 ps
CPU time 91.59 seconds
Started Aug 06 04:30:46 PM PDT 24
Finished Aug 06 04:32:17 PM PDT 24
Peak memory 199632 kb
Host smart-9d2ba9b9-beff-4559-9fa4-f96805169e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976044868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2976044868
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3095745272
Short name T170
Test name
Test status
Simulation time 56375086830 ps
CPU time 86.77 seconds
Started Aug 06 04:31:14 PM PDT 24
Finished Aug 06 04:32:41 PM PDT 24
Peak memory 199752 kb
Host smart-aa981b8e-77f5-4677-99f3-a7291068e71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095745272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3095745272
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2434595501
Short name T180
Test name
Test status
Simulation time 132095908072 ps
CPU time 188.4 seconds
Started Aug 06 04:31:16 PM PDT 24
Finished Aug 06 04:34:24 PM PDT 24
Peak memory 199688 kb
Host smart-71cd89a8-8340-49be-9474-ad7ea1c2eb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434595501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2434595501
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_stress_all.1567022145
Short name T157
Test name
Test status
Simulation time 577040597836 ps
CPU time 1110.45 seconds
Started Aug 06 04:30:56 PM PDT 24
Finished Aug 06 04:49:27 PM PDT 24
Peak memory 199516 kb
Host smart-37d74c5e-3df3-4282-a7ea-eb092ed8b39c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567022145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1567022145
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3057305502
Short name T188
Test name
Test status
Simulation time 75433444017 ps
CPU time 119.62 seconds
Started Aug 06 04:30:46 PM PDT 24
Finished Aug 06 04:32:46 PM PDT 24
Peak memory 199724 kb
Host smart-d4aa8bc6-b25d-4484-b382-0ec41947fc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057305502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3057305502
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.4167735238
Short name T323
Test name
Test status
Simulation time 72178308376 ps
CPU time 24.14 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:31:04 PM PDT 24
Peak memory 199764 kb
Host smart-294af00c-6a49-40f5-b6aa-ebd2bbffcfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167735238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.4167735238
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2771275214
Short name T230
Test name
Test status
Simulation time 68818966575 ps
CPU time 28.36 seconds
Started Aug 06 04:30:39 PM PDT 24
Finished Aug 06 04:31:08 PM PDT 24
Peak memory 199596 kb
Host smart-9d12f932-d7c1-4eda-ad46-7aa9a72304a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771275214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2771275214
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_stress_all.3561950883
Short name T207
Test name
Test status
Simulation time 199131285066 ps
CPU time 165.02 seconds
Started Aug 06 04:28:36 PM PDT 24
Finished Aug 06 04:31:21 PM PDT 24
Peak memory 208116 kb
Host smart-72490b9c-70e2-4a3b-aa3a-356815c792c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561950883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3561950883
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_intr.3916634684
Short name T289
Test name
Test status
Simulation time 80675702715 ps
CPU time 58.92 seconds
Started Aug 06 04:28:51 PM PDT 24
Finished Aug 06 04:29:50 PM PDT 24
Peak memory 199652 kb
Host smart-1890faa6-965a-4ee4-8f6b-f3cf7face6a7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916634684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3916634684
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3031760021
Short name T173
Test name
Test status
Simulation time 43327586845 ps
CPU time 18.54 seconds
Started Aug 06 04:30:42 PM PDT 24
Finished Aug 06 04:31:01 PM PDT 24
Peak memory 199708 kb
Host smart-980bb81c-1cbf-414f-89a1-e93797e35458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031760021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3031760021
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1759942317
Short name T237
Test name
Test status
Simulation time 24668533150 ps
CPU time 35.52 seconds
Started Aug 06 04:30:46 PM PDT 24
Finished Aug 06 04:31:22 PM PDT 24
Peak memory 198400 kb
Host smart-03941f3c-f224-4975-bd41-31524f81024e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759942317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1759942317
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.320785019
Short name T166
Test name
Test status
Simulation time 19163070475 ps
CPU time 26.17 seconds
Started Aug 06 04:30:55 PM PDT 24
Finished Aug 06 04:31:22 PM PDT 24
Peak memory 199600 kb
Host smart-50eb17a6-c35e-4f79-b96c-05cf1d548000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320785019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.320785019
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1307236848
Short name T51
Test name
Test status
Simulation time 45036625096 ps
CPU time 24.45 seconds
Started Aug 06 04:30:57 PM PDT 24
Finished Aug 06 04:31:21 PM PDT 24
Peak memory 199532 kb
Host smart-64c36501-4357-49ef-a222-84844eb366e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307236848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1307236848
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3743437515
Short name T38
Test name
Test status
Simulation time 28291708845 ps
CPU time 24.18 seconds
Started Aug 06 04:31:18 PM PDT 24
Finished Aug 06 04:31:42 PM PDT 24
Peak memory 199752 kb
Host smart-6b850352-723b-46fb-be61-489a1e160b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743437515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3743437515
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.4272009926
Short name T192
Test name
Test status
Simulation time 175704166032 ps
CPU time 281.3 seconds
Started Aug 06 04:31:40 PM PDT 24
Finished Aug 06 04:36:21 PM PDT 24
Peak memory 199772 kb
Host smart-da80d336-99f5-4ae8-a9a5-8b28a1c17183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272009926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.4272009926
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3732463542
Short name T223
Test name
Test status
Simulation time 70911554682 ps
CPU time 27.02 seconds
Started Aug 06 04:30:25 PM PDT 24
Finished Aug 06 04:30:52 PM PDT 24
Peak memory 199748 kb
Host smart-5d34a209-399c-424a-be95-b701a4419b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732463542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3732463542
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2971135094
Short name T111
Test name
Test status
Simulation time 84142328 ps
CPU time 1.29 seconds
Started Aug 06 04:28:18 PM PDT 24
Finished Aug 06 04:28:19 PM PDT 24
Peak memory 199080 kb
Host smart-8d9831e4-cfd4-4d98-9a88-6bae0ed646fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971135094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2971135094
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3032588356
Short name T133
Test name
Test status
Simulation time 9367867106 ps
CPU time 15.33 seconds
Started Aug 06 04:30:43 PM PDT 24
Finished Aug 06 04:30:59 PM PDT 24
Peak memory 199692 kb
Host smart-38b024df-77dd-43b3-9406-2775496bf83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032588356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3032588356
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3997750385
Short name T1111
Test name
Test status
Simulation time 65910304050 ps
CPU time 28.85 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:31:09 PM PDT 24
Peak memory 199708 kb
Host smart-d429ecbf-1803-48be-946c-24d106ee9335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997750385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3997750385
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.4280165412
Short name T232
Test name
Test status
Simulation time 190830016338 ps
CPU time 166.21 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:33:27 PM PDT 24
Peak memory 199704 kb
Host smart-1c036681-d9d5-4adc-a1c1-3c8b98ede14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280165412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.4280165412
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1264844444
Short name T47
Test name
Test status
Simulation time 53283167758 ps
CPU time 26.68 seconds
Started Aug 06 04:30:41 PM PDT 24
Finished Aug 06 04:31:07 PM PDT 24
Peak memory 199688 kb
Host smart-c432b4ed-2e27-4dfa-9bfa-e35fee35ab29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264844444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1264844444
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2965297819
Short name T247
Test name
Test status
Simulation time 77542026333 ps
CPU time 173.36 seconds
Started Aug 06 04:30:38 PM PDT 24
Finished Aug 06 04:33:31 PM PDT 24
Peak memory 199748 kb
Host smart-834020ab-84f0-4e59-9374-6894e2724860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965297819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2965297819
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1797606729
Short name T129
Test name
Test status
Simulation time 49920525792 ps
CPU time 20.12 seconds
Started Aug 06 04:30:57 PM PDT 24
Finished Aug 06 04:31:18 PM PDT 24
Peak memory 199708 kb
Host smart-456f4112-908c-4176-8abb-0fc70c63910c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797606729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1797606729
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1910801830
Short name T246
Test name
Test status
Simulation time 44805361931 ps
CPU time 18.23 seconds
Started Aug 06 04:30:56 PM PDT 24
Finished Aug 06 04:31:15 PM PDT 24
Peak memory 199704 kb
Host smart-a4a164f5-3a86-4e44-9fb9-e84ef3222bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910801830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1910801830
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.39987242
Short name T245
Test name
Test status
Simulation time 189856256831 ps
CPU time 31.46 seconds
Started Aug 06 04:31:13 PM PDT 24
Finished Aug 06 04:31:45 PM PDT 24
Peak memory 200156 kb
Host smart-50cb2c7e-5902-4447-9c20-6f4b8aa0e83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39987242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.39987242
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.4172077649
Short name T244
Test name
Test status
Simulation time 8702363671 ps
CPU time 13.29 seconds
Started Aug 06 04:31:18 PM PDT 24
Finished Aug 06 04:31:31 PM PDT 24
Peak memory 199588 kb
Host smart-94ebdce6-4d53-4974-ab42-fb6a252d77f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172077649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.4172077649
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.188253804
Short name T231
Test name
Test status
Simulation time 71748104922 ps
CPU time 32.38 seconds
Started Aug 06 04:31:31 PM PDT 24
Finished Aug 06 04:32:03 PM PDT 24
Peak memory 199732 kb
Host smart-b243e714-84ef-4d40-b8a9-d00508d37e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188253804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.188253804
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.349543583
Short name T236
Test name
Test status
Simulation time 118852950623 ps
CPU time 161.12 seconds
Started Aug 06 04:29:55 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 199748 kb
Host smart-4bf4c87c-2bc9-48bd-b49d-9c4b12325e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349543583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.349543583
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.4183651324
Short name T151
Test name
Test status
Simulation time 116591949251 ps
CPU time 672.49 seconds
Started Aug 06 04:28:17 PM PDT 24
Finished Aug 06 04:39:29 PM PDT 24
Peak memory 216232 kb
Host smart-21903ccf-8870-4636-9a3d-e471bf62bdb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183651324 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.4183651324
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2362133608
Short name T143
Test name
Test status
Simulation time 42312465508 ps
CPU time 41.32 seconds
Started Aug 06 04:30:10 PM PDT 24
Finished Aug 06 04:30:51 PM PDT 24
Peak memory 199740 kb
Host smart-f9d46935-7a7a-4fa4-9728-973d9146bc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362133608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2362133608
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.4264232041
Short name T1307
Test name
Test status
Simulation time 257934367 ps
CPU time 0.77 seconds
Started Aug 06 04:27:56 PM PDT 24
Finished Aug 06 04:27:57 PM PDT 24
Peak memory 196452 kb
Host smart-5821b7b1-0ee0-4fd2-8237-aba019640b83
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264232041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.4264232041
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2885644767
Short name T1187
Test name
Test status
Simulation time 180151109 ps
CPU time 2.31 seconds
Started Aug 06 04:25:49 PM PDT 24
Finished Aug 06 04:25:51 PM PDT 24
Peak memory 197716 kb
Host smart-b00a9bf9-5908-4114-ab28-0beb4791de66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885644767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2885644767
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1940872251
Short name T63
Test name
Test status
Simulation time 19783483 ps
CPU time 0.58 seconds
Started Aug 06 04:28:07 PM PDT 24
Finished Aug 06 04:28:08 PM PDT 24
Peak memory 195500 kb
Host smart-943352cc-02b1-4ec3-a586-c09045b7e701
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940872251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1940872251
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3003843657
Short name T1262
Test name
Test status
Simulation time 123239042 ps
CPU time 0.69 seconds
Started Aug 06 04:26:13 PM PDT 24
Finished Aug 06 04:26:13 PM PDT 24
Peak memory 197936 kb
Host smart-f3eb6f13-d1f9-43a8-8c05-2a9bcbb458f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003843657 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3003843657
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.4246937329
Short name T1228
Test name
Test status
Simulation time 46082672 ps
CPU time 0.61 seconds
Started Aug 06 04:27:54 PM PDT 24
Finished Aug 06 04:27:55 PM PDT 24
Peak memory 194616 kb
Host smart-dbc10242-dad8-459c-a93b-f5df6187b7b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246937329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.4246937329
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.4001521313
Short name T1285
Test name
Test status
Simulation time 12890817 ps
CPU time 0.63 seconds
Started Aug 06 04:26:03 PM PDT 24
Finished Aug 06 04:26:04 PM PDT 24
Peak memory 194548 kb
Host smart-c28585c2-c305-40d3-9d17-7a5e2d1e7095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001521313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.4001521313
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1157434272
Short name T70
Test name
Test status
Simulation time 53633137 ps
CPU time 0.7 seconds
Started Aug 06 04:28:09 PM PDT 24
Finished Aug 06 04:28:10 PM PDT 24
Peak memory 197200 kb
Host smart-f31f6e52-ea02-4a7a-a37b-cb9571515dd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157434272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1157434272
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3917206572
Short name T1204
Test name
Test status
Simulation time 183199407 ps
CPU time 2.25 seconds
Started Aug 06 04:27:54 PM PDT 24
Finished Aug 06 04:27:57 PM PDT 24
Peak memory 198516 kb
Host smart-a9c8c2fd-fb4e-4c9c-8a00-1aebc2aa17e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917206572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3917206572
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2411455837
Short name T113
Test name
Test status
Simulation time 49427093 ps
CPU time 0.9 seconds
Started Aug 06 04:27:53 PM PDT 24
Finished Aug 06 04:27:54 PM PDT 24
Peak memory 198824 kb
Host smart-1ad6cb3a-c837-4f8b-8e5b-75a06b777a18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411455837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2411455837
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1663914597
Short name T1301
Test name
Test status
Simulation time 21497279 ps
CPU time 0.67 seconds
Started Aug 06 04:27:52 PM PDT 24
Finished Aug 06 04:27:53 PM PDT 24
Peak memory 194252 kb
Host smart-2b16e4df-2008-49cc-b02a-7873735d8d33
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663914597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1663914597
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.527560670
Short name T1266
Test name
Test status
Simulation time 90146657 ps
CPU time 1.47 seconds
Started Aug 06 04:28:07 PM PDT 24
Finished Aug 06 04:28:09 PM PDT 24
Peak memory 198076 kb
Host smart-fb674cb0-0c2c-4e90-a048-e2b5daf6bed1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527560670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.527560670
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3644897722
Short name T1282
Test name
Test status
Simulation time 13271200 ps
CPU time 0.59 seconds
Started Aug 06 04:26:41 PM PDT 24
Finished Aug 06 04:26:42 PM PDT 24
Peak memory 195608 kb
Host smart-a43a09e1-622c-4cde-bffe-42fd170d0a8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644897722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3644897722
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1998513107
Short name T1224
Test name
Test status
Simulation time 60484223 ps
CPU time 0.65 seconds
Started Aug 06 04:27:56 PM PDT 24
Finished Aug 06 04:27:57 PM PDT 24
Peak memory 197736 kb
Host smart-c94c996b-8dea-4aa0-90e4-2d9263e015cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998513107 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1998513107
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2030770933
Short name T65
Test name
Test status
Simulation time 42006374 ps
CPU time 0.62 seconds
Started Aug 06 04:27:47 PM PDT 24
Finished Aug 06 04:27:48 PM PDT 24
Peak memory 194520 kb
Host smart-50a68e12-2c79-40bc-b9d8-bf110f5afbe0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030770933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2030770933
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2142098552
Short name T1310
Test name
Test status
Simulation time 11960706 ps
CPU time 0.58 seconds
Started Aug 06 04:27:42 PM PDT 24
Finished Aug 06 04:27:43 PM PDT 24
Peak memory 194368 kb
Host smart-88dcca33-63a0-4539-b592-fd7c0230f565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142098552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2142098552
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1112483022
Short name T1251
Test name
Test status
Simulation time 58586294 ps
CPU time 0.64 seconds
Started Aug 06 04:27:42 PM PDT 24
Finished Aug 06 04:27:43 PM PDT 24
Peak memory 194900 kb
Host smart-c51f81cb-9261-4753-9d35-e0f50d3504ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112483022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1112483022
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3611123702
Short name T1311
Test name
Test status
Simulation time 73971738 ps
CPU time 1.06 seconds
Started Aug 06 04:25:50 PM PDT 24
Finished Aug 06 04:25:51 PM PDT 24
Peak memory 199972 kb
Host smart-331587be-fb4a-4444-9f1e-bcda278f2b6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611123702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3611123702
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2457381634
Short name T82
Test name
Test status
Simulation time 102843897 ps
CPU time 1.34 seconds
Started Aug 06 04:27:54 PM PDT 24
Finished Aug 06 04:27:56 PM PDT 24
Peak memory 197864 kb
Host smart-9541c47c-c58d-4bda-a99d-7edaa77df86f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457381634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2457381634
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2707160586
Short name T1260
Test name
Test status
Simulation time 58213651 ps
CPU time 0.64 seconds
Started Aug 06 04:25:58 PM PDT 24
Finished Aug 06 04:25:58 PM PDT 24
Peak memory 197904 kb
Host smart-91bcacbd-f083-4aa5-91db-3d52721bf897
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707160586 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2707160586
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.808717308
Short name T1291
Test name
Test status
Simulation time 18594176 ps
CPU time 0.64 seconds
Started Aug 06 04:25:55 PM PDT 24
Finished Aug 06 04:25:56 PM PDT 24
Peak memory 195500 kb
Host smart-e937e420-3ce6-41b8-829a-f6d875b93aa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808717308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.808717308
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2566375326
Short name T1184
Test name
Test status
Simulation time 13395263 ps
CPU time 0.57 seconds
Started Aug 06 04:27:48 PM PDT 24
Finished Aug 06 04:27:49 PM PDT 24
Peak memory 194292 kb
Host smart-d5f94596-ff2d-452c-8cf8-1f10a5bb4732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566375326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2566375326
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3931443475
Short name T1303
Test name
Test status
Simulation time 121411577 ps
CPU time 0.6 seconds
Started Aug 06 04:27:11 PM PDT 24
Finished Aug 06 04:27:11 PM PDT 24
Peak memory 195608 kb
Host smart-8d492a61-f22e-4877-9696-4e65694c60a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931443475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3931443475
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2264121791
Short name T1289
Test name
Test status
Simulation time 134791385 ps
CPU time 1.84 seconds
Started Aug 06 04:25:26 PM PDT 24
Finished Aug 06 04:25:28 PM PDT 24
Peak memory 200212 kb
Host smart-0fdf53ff-8198-47a7-8049-323f98b2ea27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264121791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2264121791
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2550621913
Short name T78
Test name
Test status
Simulation time 217762812 ps
CPU time 1.25 seconds
Started Aug 06 04:27:11 PM PDT 24
Finished Aug 06 04:27:12 PM PDT 24
Peak memory 199408 kb
Host smart-eb989cab-e4e6-478b-8f42-4ba3d786ff58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550621913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2550621913
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3419921168
Short name T1246
Test name
Test status
Simulation time 39966190 ps
CPU time 1.31 seconds
Started Aug 06 04:27:54 PM PDT 24
Finished Aug 06 04:28:01 PM PDT 24
Peak memory 200232 kb
Host smart-71b65de2-48bd-4158-91a5-be9b0257218a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419921168 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3419921168
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3604085594
Short name T1297
Test name
Test status
Simulation time 42529633 ps
CPU time 0.55 seconds
Started Aug 06 04:28:08 PM PDT 24
Finished Aug 06 04:28:08 PM PDT 24
Peak memory 195472 kb
Host smart-750a5cd9-94ee-4fa3-95c3-efe16dc3f04f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604085594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3604085594
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.504416295
Short name T1295
Test name
Test status
Simulation time 17333244 ps
CPU time 0.56 seconds
Started Aug 06 04:28:03 PM PDT 24
Finished Aug 06 04:28:04 PM PDT 24
Peak memory 194420 kb
Host smart-adf1c218-8b08-47ed-9ef3-5acd01271026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504416295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.504416295
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2948716467
Short name T1227
Test name
Test status
Simulation time 27279918 ps
CPU time 0.73 seconds
Started Aug 06 04:27:54 PM PDT 24
Finished Aug 06 04:27:55 PM PDT 24
Peak memory 197200 kb
Host smart-782923c7-851e-43f5-8074-75e44506b95c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948716467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2948716467
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3690040269
Short name T1242
Test name
Test status
Simulation time 49575280 ps
CPU time 1.29 seconds
Started Aug 06 04:27:47 PM PDT 24
Finished Aug 06 04:27:49 PM PDT 24
Peak memory 199320 kb
Host smart-6420fa11-7885-4786-beb9-c208eae77999
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690040269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3690040269
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.56110076
Short name T84
Test name
Test status
Simulation time 394009177 ps
CPU time 0.93 seconds
Started Aug 06 04:27:11 PM PDT 24
Finished Aug 06 04:27:13 PM PDT 24
Peak memory 199480 kb
Host smart-c84770a5-fdcd-4e38-83f9-454a61e3a456
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56110076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.56110076
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3167626886
Short name T1256
Test name
Test status
Simulation time 54219615 ps
CPU time 0.69 seconds
Started Aug 06 04:26:28 PM PDT 24
Finished Aug 06 04:26:29 PM PDT 24
Peak memory 198528 kb
Host smart-79841422-9265-47f1-a906-41a873845765
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167626886 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3167626886
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.412641878
Short name T68
Test name
Test status
Simulation time 99552603 ps
CPU time 0.61 seconds
Started Aug 06 04:27:40 PM PDT 24
Finished Aug 06 04:27:41 PM PDT 24
Peak memory 194848 kb
Host smart-80bc47f2-cf11-4c0a-95ba-ef879db4b28b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412641878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.412641878
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2418338735
Short name T1252
Test name
Test status
Simulation time 23894103 ps
CPU time 0.6 seconds
Started Aug 06 04:25:40 PM PDT 24
Finished Aug 06 04:25:40 PM PDT 24
Peak memory 194408 kb
Host smart-be11660d-56b4-45e4-9656-557980ff404a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418338735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2418338735
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.519825352
Short name T1211
Test name
Test status
Simulation time 48435090 ps
CPU time 0.75 seconds
Started Aug 06 04:25:38 PM PDT 24
Finished Aug 06 04:25:39 PM PDT 24
Peak memory 195688 kb
Host smart-785ca608-f818-4c97-a832-9afb1f5d04f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519825352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr
_outstanding.519825352
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2320602015
Short name T1247
Test name
Test status
Simulation time 775780998 ps
CPU time 1.88 seconds
Started Aug 06 04:26:25 PM PDT 24
Finished Aug 06 04:26:27 PM PDT 24
Peak memory 200112 kb
Host smart-58a9b6f0-bf4e-4b35-86b6-1bf89cb00d5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320602015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2320602015
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3305253495
Short name T1314
Test name
Test status
Simulation time 362971405 ps
CPU time 1.16 seconds
Started Aug 06 04:27:40 PM PDT 24
Finished Aug 06 04:27:42 PM PDT 24
Peak memory 198544 kb
Host smart-8b8c6357-d063-4dd5-9bec-43c2afc5e1f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305253495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3305253495
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1607128401
Short name T1292
Test name
Test status
Simulation time 101833494 ps
CPU time 0.83 seconds
Started Aug 06 04:27:54 PM PDT 24
Finished Aug 06 04:27:55 PM PDT 24
Peak memory 199960 kb
Host smart-d9169951-1e4f-4199-98ad-3e01d9eeeed2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607128401 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1607128401
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1380998843
Short name T1210
Test name
Test status
Simulation time 15295763 ps
CPU time 0.61 seconds
Started Aug 06 04:26:05 PM PDT 24
Finished Aug 06 04:26:06 PM PDT 24
Peak memory 195328 kb
Host smart-340b9522-fbc4-46c5-85f1-425638082667
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380998843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1380998843
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3743503082
Short name T1283
Test name
Test status
Simulation time 41483615 ps
CPU time 0.57 seconds
Started Aug 06 04:27:05 PM PDT 24
Finished Aug 06 04:27:06 PM PDT 24
Peak memory 194560 kb
Host smart-62aeffd9-da2d-48cd-bc93-467b352c6e0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743503082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3743503082
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1307048149
Short name T1208
Test name
Test status
Simulation time 31816924 ps
CPU time 0.76 seconds
Started Aug 06 04:27:06 PM PDT 24
Finished Aug 06 04:27:06 PM PDT 24
Peak memory 197256 kb
Host smart-54456229-1375-4586-a7ef-03fa16031bd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307048149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1307048149
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1973850109
Short name T1316
Test name
Test status
Simulation time 50478696 ps
CPU time 1.2 seconds
Started Aug 06 04:25:37 PM PDT 24
Finished Aug 06 04:25:39 PM PDT 24
Peak memory 200148 kb
Host smart-bb2713f0-8f4d-4723-a276-c38f32f33168
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973850109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1973850109
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2371595205
Short name T1300
Test name
Test status
Simulation time 200076875 ps
CPU time 0.94 seconds
Started Aug 06 04:26:05 PM PDT 24
Finished Aug 06 04:26:06 PM PDT 24
Peak memory 199208 kb
Host smart-778c926e-a4db-4889-9571-202e31cdf40e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371595205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2371595205
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2496804197
Short name T1214
Test name
Test status
Simulation time 113875731 ps
CPU time 0.9 seconds
Started Aug 06 04:27:42 PM PDT 24
Finished Aug 06 04:27:43 PM PDT 24
Peak memory 199100 kb
Host smart-9186d692-4204-4a17-adba-dbaa1bfbe7d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496804197 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2496804197
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3774243743
Short name T66
Test name
Test status
Simulation time 55272342 ps
CPU time 0.6 seconds
Started Aug 06 04:26:49 PM PDT 24
Finished Aug 06 04:26:50 PM PDT 24
Peak memory 194812 kb
Host smart-f708dfec-3de3-4eff-bc30-4f72b2656e2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774243743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3774243743
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2974761944
Short name T1293
Test name
Test status
Simulation time 45601089 ps
CPU time 0.59 seconds
Started Aug 06 04:26:28 PM PDT 24
Finished Aug 06 04:26:29 PM PDT 24
Peak memory 194596 kb
Host smart-79866e3c-d483-420d-ba2d-925d5a6d5d32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974761944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2974761944
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3374036276
Short name T74
Test name
Test status
Simulation time 50485596 ps
CPU time 0.64 seconds
Started Aug 06 04:26:27 PM PDT 24
Finished Aug 06 04:26:28 PM PDT 24
Peak memory 195876 kb
Host smart-a6025fae-2b3f-4ef7-a9f2-1956be5127d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374036276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3374036276
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3362534260
Short name T1232
Test name
Test status
Simulation time 102270318 ps
CPU time 2.06 seconds
Started Aug 06 04:27:53 PM PDT 24
Finished Aug 06 04:27:55 PM PDT 24
Peak memory 200208 kb
Host smart-ed8cdbc5-df58-40de-bd02-f8ac18b35ff4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362534260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3362534260
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1504419022
Short name T81
Test name
Test status
Simulation time 175018980 ps
CPU time 0.93 seconds
Started Aug 06 04:26:08 PM PDT 24
Finished Aug 06 04:26:09 PM PDT 24
Peak memory 199184 kb
Host smart-a85f78c2-ebbb-4531-9c47-3bce9fb8411d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504419022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.1504419022
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.562917723
Short name T1268
Test name
Test status
Simulation time 60438914 ps
CPU time 0.78 seconds
Started Aug 06 04:27:10 PM PDT 24
Finished Aug 06 04:27:11 PM PDT 24
Peak memory 199656 kb
Host smart-3d33e9aa-3509-4a81-a1b1-7bd900ee5d2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562917723 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.562917723
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.4285550358
Short name T67
Test name
Test status
Simulation time 18135317 ps
CPU time 0.62 seconds
Started Aug 06 04:27:42 PM PDT 24
Finished Aug 06 04:27:43 PM PDT 24
Peak memory 195352 kb
Host smart-31b64607-53a4-4d7c-a159-65d1dd98c129
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285550358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.4285550358
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.4234056773
Short name T1233
Test name
Test status
Simulation time 12708006 ps
CPU time 0.59 seconds
Started Aug 06 04:25:52 PM PDT 24
Finished Aug 06 04:25:53 PM PDT 24
Peak memory 194596 kb
Host smart-14894dab-1579-46fe-b6f2-83d75bea1720
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234056773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.4234056773
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2320501257
Short name T1305
Test name
Test status
Simulation time 25007947 ps
CPU time 0.75 seconds
Started Aug 06 04:27:11 PM PDT 24
Finished Aug 06 04:27:12 PM PDT 24
Peak memory 198056 kb
Host smart-37cf59c6-4986-40fa-a821-652478fa7afe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320501257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2320501257
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3999959215
Short name T1306
Test name
Test status
Simulation time 137869163 ps
CPU time 2.33 seconds
Started Aug 06 04:27:11 PM PDT 24
Finished Aug 06 04:27:13 PM PDT 24
Peak memory 200156 kb
Host smart-9a220749-93b9-4046-ab42-fe24cc2f5000
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999959215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3999959215
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3920812815
Short name T1276
Test name
Test status
Simulation time 56895444 ps
CPU time 0.95 seconds
Started Aug 06 04:25:54 PM PDT 24
Finished Aug 06 04:25:55 PM PDT 24
Peak memory 199316 kb
Host smart-68d8236e-262e-4876-852b-71502500a9ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920812815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3920812815
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.193157978
Short name T1191
Test name
Test status
Simulation time 17463207 ps
CPU time 0.83 seconds
Started Aug 06 04:26:03 PM PDT 24
Finished Aug 06 04:26:04 PM PDT 24
Peak memory 199028 kb
Host smart-a0a33238-7056-4775-81db-cba14573a813
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193157978 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.193157978
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.935684054
Short name T1263
Test name
Test status
Simulation time 20890370 ps
CPU time 0.57 seconds
Started Aug 06 04:27:11 PM PDT 24
Finished Aug 06 04:27:11 PM PDT 24
Peak memory 195512 kb
Host smart-649ce0b9-bd60-4241-9662-a5963983e32d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935684054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.935684054
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.1917104473
Short name T1259
Test name
Test status
Simulation time 76577433 ps
CPU time 0.59 seconds
Started Aug 06 04:25:49 PM PDT 24
Finished Aug 06 04:25:49 PM PDT 24
Peak memory 194472 kb
Host smart-0e80840b-f9ce-4cc1-8260-3b16ec9ec464
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917104473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1917104473
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1052100432
Short name T1229
Test name
Test status
Simulation time 66880058 ps
CPU time 0.68 seconds
Started Aug 06 04:27:56 PM PDT 24
Finished Aug 06 04:28:02 PM PDT 24
Peak memory 195928 kb
Host smart-0e44735f-2991-4249-9b38-f9a61ab811f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052100432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1052100432
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.2761012592
Short name T1203
Test name
Test status
Simulation time 103031606 ps
CPU time 1.07 seconds
Started Aug 06 04:27:56 PM PDT 24
Finished Aug 06 04:27:57 PM PDT 24
Peak memory 200164 kb
Host smart-c7f158c3-db88-459c-9557-f5acc7646436
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761012592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2761012592
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2594772229
Short name T110
Test name
Test status
Simulation time 47555429 ps
CPU time 0.99 seconds
Started Aug 06 04:25:54 PM PDT 24
Finished Aug 06 04:25:55 PM PDT 24
Peak memory 199388 kb
Host smart-8eeac5ec-3478-41fb-9326-fe424bf176d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594772229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2594772229
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1015991217
Short name T1284
Test name
Test status
Simulation time 78085171 ps
CPU time 1 seconds
Started Aug 06 04:27:55 PM PDT 24
Finished Aug 06 04:27:56 PM PDT 24
Peak memory 200164 kb
Host smart-5e204685-880a-424c-9559-056f4b4d7f17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015991217 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1015991217
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3269079280
Short name T1273
Test name
Test status
Simulation time 38794582 ps
CPU time 0.62 seconds
Started Aug 06 04:27:42 PM PDT 24
Finished Aug 06 04:27:43 PM PDT 24
Peak memory 193848 kb
Host smart-8ea9fa7f-dc3b-47da-af78-8ad14cf8e200
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269079280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3269079280
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2353484290
Short name T1197
Test name
Test status
Simulation time 42419403 ps
CPU time 0.61 seconds
Started Aug 06 04:26:12 PM PDT 24
Finished Aug 06 04:26:13 PM PDT 24
Peak memory 194604 kb
Host smart-93853f12-9b10-4daf-b703-569eadae9349
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353484290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2353484290
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1664468848
Short name T72
Test name
Test status
Simulation time 77214251 ps
CPU time 0.72 seconds
Started Aug 06 04:27:42 PM PDT 24
Finished Aug 06 04:27:43 PM PDT 24
Peak memory 196756 kb
Host smart-533394f7-1107-4e7c-9a8e-f275577e4305
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664468848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1664468848
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.758648102
Short name T1267
Test name
Test status
Simulation time 56974961 ps
CPU time 1.14 seconds
Started Aug 06 04:28:02 PM PDT 24
Finished Aug 06 04:28:03 PM PDT 24
Peak memory 200184 kb
Host smart-6cb17db5-df65-4cd5-bfb9-b9e2b5b47588
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758648102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.758648102
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3870896903
Short name T1238
Test name
Test status
Simulation time 105971945 ps
CPU time 1.5 seconds
Started Aug 06 04:27:57 PM PDT 24
Finished Aug 06 04:27:58 PM PDT 24
Peak memory 200204 kb
Host smart-b393bf39-bcd8-4e6c-a47c-8ab4ecbf2ece
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870896903 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3870896903
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1383755172
Short name T1317
Test name
Test status
Simulation time 59357447 ps
CPU time 0.57 seconds
Started Aug 06 04:26:04 PM PDT 24
Finished Aug 06 04:26:04 PM PDT 24
Peak memory 195328 kb
Host smart-f8bfa948-8d00-43f1-b8d9-29808e3c13b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383755172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1383755172
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3000835561
Short name T1277
Test name
Test status
Simulation time 36434171 ps
CPU time 0.55 seconds
Started Aug 06 04:27:59 PM PDT 24
Finished Aug 06 04:28:00 PM PDT 24
Peak memory 194216 kb
Host smart-802216c2-45c2-417d-a1ff-092077728b5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000835561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3000835561
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3024420472
Short name T1215
Test name
Test status
Simulation time 55921463 ps
CPU time 0.74 seconds
Started Aug 06 04:26:02 PM PDT 24
Finished Aug 06 04:26:03 PM PDT 24
Peak memory 196900 kb
Host smart-e43c86b2-af22-4ebf-875e-86a171273c3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024420472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3024420472
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2066648512
Short name T1194
Test name
Test status
Simulation time 137242812 ps
CPU time 1.85 seconds
Started Aug 06 04:27:42 PM PDT 24
Finished Aug 06 04:27:44 PM PDT 24
Peak memory 198340 kb
Host smart-049f09c6-9966-470b-9dd7-9adefc3c3fa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066648512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2066648512
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.483238157
Short name T1239
Test name
Test status
Simulation time 198576681 ps
CPU time 1.27 seconds
Started Aug 06 04:26:02 PM PDT 24
Finished Aug 06 04:26:04 PM PDT 24
Peak memory 199412 kb
Host smart-e0b22a1d-fcd6-4aed-8f4b-59d252a121c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483238157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.483238157
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2235216205
Short name T1302
Test name
Test status
Simulation time 15900593 ps
CPU time 0.75 seconds
Started Aug 06 04:27:42 PM PDT 24
Finished Aug 06 04:27:43 PM PDT 24
Peak memory 196744 kb
Host smart-5584c6d8-25d7-4e17-8898-04e68aa6107f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235216205 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2235216205
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.23786693
Short name T1188
Test name
Test status
Simulation time 12363271 ps
CPU time 0.61 seconds
Started Aug 06 04:27:42 PM PDT 24
Finished Aug 06 04:27:43 PM PDT 24
Peak memory 195396 kb
Host smart-485fd033-3830-4d8e-b9f5-35bf6721db0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23786693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.23786693
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.141127114
Short name T1255
Test name
Test status
Simulation time 24597670 ps
CPU time 0.6 seconds
Started Aug 06 04:27:42 PM PDT 24
Finished Aug 06 04:27:43 PM PDT 24
Peak memory 194344 kb
Host smart-e043cc2c-9394-47ad-bfc3-7261ea139360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141127114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.141127114
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.4202186989
Short name T73
Test name
Test status
Simulation time 111267848 ps
CPU time 0.71 seconds
Started Aug 06 04:27:48 PM PDT 24
Finished Aug 06 04:27:48 PM PDT 24
Peak memory 197932 kb
Host smart-38bdfdc6-e108-40e9-84fa-737f11980069
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202186989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.4202186989
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.957612245
Short name T1192
Test name
Test status
Simulation time 32426928 ps
CPU time 1.55 seconds
Started Aug 06 04:27:42 PM PDT 24
Finished Aug 06 04:27:44 PM PDT 24
Peak memory 198332 kb
Host smart-f602cc9d-ae3e-4acb-8bcb-6d40d67e9ae4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957612245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.957612245
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1409959059
Short name T64
Test name
Test status
Simulation time 125995136 ps
CPU time 0.77 seconds
Started Aug 06 04:26:26 PM PDT 24
Finished Aug 06 04:26:27 PM PDT 24
Peak memory 196476 kb
Host smart-a79e5183-1bfd-47b7-b022-de738d62469c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409959059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1409959059
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.23396027
Short name T1244
Test name
Test status
Simulation time 221421410 ps
CPU time 1.31 seconds
Started Aug 06 04:26:26 PM PDT 24
Finished Aug 06 04:26:27 PM PDT 24
Peak memory 197760 kb
Host smart-5e79574e-c6f7-4a63-9a83-f89c99aa2035
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23396027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.23396027
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2270062837
Short name T1235
Test name
Test status
Simulation time 11695226 ps
CPU time 0.62 seconds
Started Aug 06 04:26:53 PM PDT 24
Finished Aug 06 04:26:54 PM PDT 24
Peak memory 194640 kb
Host smart-da8de587-bab7-4c33-a682-ca579820dc68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270062837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2270062837
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2747387840
Short name T1258
Test name
Test status
Simulation time 74809652 ps
CPU time 0.63 seconds
Started Aug 06 04:26:14 PM PDT 24
Finished Aug 06 04:26:15 PM PDT 24
Peak memory 197696 kb
Host smart-ab274387-ecad-4794-9cf0-3135c72646d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747387840 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2747387840
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.4123507523
Short name T1222
Test name
Test status
Simulation time 11907168 ps
CPU time 0.56 seconds
Started Aug 06 04:26:14 PM PDT 24
Finished Aug 06 04:26:14 PM PDT 24
Peak memory 194568 kb
Host smart-17251925-d360-4cd3-9251-e63228e86c4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123507523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.4123507523
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2093516461
Short name T1217
Test name
Test status
Simulation time 44311561 ps
CPU time 0.63 seconds
Started Aug 06 04:26:15 PM PDT 24
Finished Aug 06 04:26:16 PM PDT 24
Peak memory 194884 kb
Host smart-b7d7403a-6627-49d4-b457-24d5b36f2efb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093516461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2093516461
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3651824461
Short name T1315
Test name
Test status
Simulation time 32614914 ps
CPU time 1.22 seconds
Started Aug 06 04:27:53 PM PDT 24
Finished Aug 06 04:27:54 PM PDT 24
Peak memory 199916 kb
Host smart-8f540562-edb7-4c46-aa81-2bfb7449ff8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651824461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3651824461
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1919524045
Short name T83
Test name
Test status
Simulation time 48275685 ps
CPU time 0.99 seconds
Started Aug 06 04:27:54 PM PDT 24
Finished Aug 06 04:27:55 PM PDT 24
Peak memory 197776 kb
Host smart-97ab1e9f-4ce3-4dc0-9f9d-7c23533784ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919524045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1919524045
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.94856145
Short name T1202
Test name
Test status
Simulation time 39283860 ps
CPU time 0.54 seconds
Started Aug 06 04:27:46 PM PDT 24
Finished Aug 06 04:27:47 PM PDT 24
Peak memory 194304 kb
Host smart-9f8aaa41-492f-4835-a999-69e5a46f9003
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94856145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.94856145
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.17904654
Short name T1207
Test name
Test status
Simulation time 13484139 ps
CPU time 0.61 seconds
Started Aug 06 04:26:15 PM PDT 24
Finished Aug 06 04:26:16 PM PDT 24
Peak memory 194636 kb
Host smart-51777ae5-5851-4023-971b-4fc9909a0d0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17904654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.17904654
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1594094447
Short name T1234
Test name
Test status
Simulation time 19445107 ps
CPU time 0.53 seconds
Started Aug 06 04:27:47 PM PDT 24
Finished Aug 06 04:27:48 PM PDT 24
Peak memory 194532 kb
Host smart-83cd7ef7-8c92-4376-9857-de3b8dfc3492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594094447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1594094447
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2245941457
Short name T1218
Test name
Test status
Simulation time 32157405 ps
CPU time 0.56 seconds
Started Aug 06 04:26:58 PM PDT 24
Finished Aug 06 04:26:59 PM PDT 24
Peak memory 194552 kb
Host smart-09dd27cf-ab50-4508-a522-9ec7278c6998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245941457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2245941457
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.4162926679
Short name T1213
Test name
Test status
Simulation time 15464981 ps
CPU time 0.61 seconds
Started Aug 06 04:26:16 PM PDT 24
Finished Aug 06 04:26:17 PM PDT 24
Peak memory 194536 kb
Host smart-040e8400-ea8e-4c4e-b108-82e0a2548796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162926679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.4162926679
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1571538831
Short name T1226
Test name
Test status
Simulation time 46472132 ps
CPU time 0.56 seconds
Started Aug 06 04:27:46 PM PDT 24
Finished Aug 06 04:27:47 PM PDT 24
Peak memory 194092 kb
Host smart-63777ca1-a13f-43be-b117-3f04a78379c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571538831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1571538831
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3806735154
Short name T1223
Test name
Test status
Simulation time 12187085 ps
CPU time 0.59 seconds
Started Aug 06 04:26:17 PM PDT 24
Finished Aug 06 04:26:18 PM PDT 24
Peak memory 194552 kb
Host smart-868b264e-5c1c-4458-9262-3593893533fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806735154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3806735154
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1766986979
Short name T1272
Test name
Test status
Simulation time 26976158 ps
CPU time 0.55 seconds
Started Aug 06 04:27:46 PM PDT 24
Finished Aug 06 04:27:47 PM PDT 24
Peak memory 193968 kb
Host smart-3454c861-04da-4516-9cb4-e89566cd507d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766986979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1766986979
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.694330644
Short name T1236
Test name
Test status
Simulation time 49974312 ps
CPU time 0.59 seconds
Started Aug 06 04:26:16 PM PDT 24
Finished Aug 06 04:26:16 PM PDT 24
Peak memory 194616 kb
Host smart-6bce222c-d4ce-414f-a06f-bf9fe1fc15bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694330644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.694330644
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1361307199
Short name T1199
Test name
Test status
Simulation time 144354968 ps
CPU time 0.58 seconds
Started Aug 06 04:27:48 PM PDT 24
Finished Aug 06 04:27:49 PM PDT 24
Peak memory 194424 kb
Host smart-9ad920db-f2a8-4100-b245-de9ab650d078
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361307199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1361307199
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3274640927
Short name T1286
Test name
Test status
Simulation time 59769463 ps
CPU time 0.65 seconds
Started Aug 06 04:26:26 PM PDT 24
Finished Aug 06 04:26:27 PM PDT 24
Peak memory 194980 kb
Host smart-a26df6d8-feb2-44cc-8b23-35e384932395
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274640927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3274640927
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1638982961
Short name T1278
Test name
Test status
Simulation time 120952076 ps
CPU time 1.37 seconds
Started Aug 06 04:26:11 PM PDT 24
Finished Aug 06 04:26:13 PM PDT 24
Peak memory 196952 kb
Host smart-160a2b01-7ae7-4bf1-a163-b7cbf996ca83
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638982961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1638982961
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.305443267
Short name T1231
Test name
Test status
Simulation time 25758572 ps
CPU time 0.58 seconds
Started Aug 06 04:26:11 PM PDT 24
Finished Aug 06 04:26:12 PM PDT 24
Peak memory 194536 kb
Host smart-f457b2ce-4670-44a9-acd3-8cc2263a0f6e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305443267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.305443267
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3276982669
Short name T1221
Test name
Test status
Simulation time 35822348 ps
CPU time 0.93 seconds
Started Aug 06 04:26:15 PM PDT 24
Finished Aug 06 04:26:16 PM PDT 24
Peak memory 200016 kb
Host smart-1db3e46b-e7d8-45f4-88a8-85136872c3de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276982669 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3276982669
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2856298171
Short name T1241
Test name
Test status
Simulation time 13352837 ps
CPU time 0.55 seconds
Started Aug 06 04:26:13 PM PDT 24
Finished Aug 06 04:26:14 PM PDT 24
Peak memory 195792 kb
Host smart-5914e824-06b6-43d2-bef3-c21463389011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856298171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2856298171
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3022967756
Short name T1309
Test name
Test status
Simulation time 28013573 ps
CPU time 0.58 seconds
Started Aug 06 04:26:14 PM PDT 24
Finished Aug 06 04:26:15 PM PDT 24
Peak memory 194568 kb
Host smart-4f89a57d-d806-4d3c-9f64-9cd0b7a342e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022967756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3022967756
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3464266074
Short name T1280
Test name
Test status
Simulation time 25405861 ps
CPU time 0.64 seconds
Started Aug 06 04:26:15 PM PDT 24
Finished Aug 06 04:26:16 PM PDT 24
Peak memory 196060 kb
Host smart-624479f8-97e7-43ae-bf10-b83cfba632c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464266074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3464266074
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1582059264
Short name T1308
Test name
Test status
Simulation time 93786776 ps
CPU time 1.96 seconds
Started Aug 06 04:26:14 PM PDT 24
Finished Aug 06 04:26:16 PM PDT 24
Peak memory 200212 kb
Host smart-a9ab7f1c-28b9-4246-b68a-30434938fab6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582059264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1582059264
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.317745330
Short name T1254
Test name
Test status
Simulation time 45494705 ps
CPU time 0.9 seconds
Started Aug 06 04:26:27 PM PDT 24
Finished Aug 06 04:26:28 PM PDT 24
Peak memory 199100 kb
Host smart-47f4e3f9-b10b-4907-b261-0821f58a48e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317745330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.317745330
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2971786857
Short name T1287
Test name
Test status
Simulation time 15564412 ps
CPU time 0.59 seconds
Started Aug 06 04:26:17 PM PDT 24
Finished Aug 06 04:26:18 PM PDT 24
Peak memory 194532 kb
Host smart-064fcebf-7d48-4e42-bc84-d52903470581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971786857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2971786857
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2367356458
Short name T1248
Test name
Test status
Simulation time 67788124 ps
CPU time 0.65 seconds
Started Aug 06 04:27:35 PM PDT 24
Finished Aug 06 04:27:36 PM PDT 24
Peak memory 193468 kb
Host smart-da9d2926-d257-43bf-bd03-f47d906d16ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367356458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2367356458
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3988335233
Short name T1253
Test name
Test status
Simulation time 13283019 ps
CPU time 0.55 seconds
Started Aug 06 04:27:48 PM PDT 24
Finished Aug 06 04:27:48 PM PDT 24
Peak memory 194516 kb
Host smart-ab78a806-67ee-450f-b8e6-b8ddbb08ea9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988335233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3988335233
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2677853765
Short name T1257
Test name
Test status
Simulation time 11046288 ps
CPU time 0.55 seconds
Started Aug 06 04:26:50 PM PDT 24
Finished Aug 06 04:26:50 PM PDT 24
Peak memory 194564 kb
Host smart-83865380-bfbf-491d-88dd-1cc657f15010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677853765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2677853765
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3103490073
Short name T1195
Test name
Test status
Simulation time 24927114 ps
CPU time 0.58 seconds
Started Aug 06 04:26:43 PM PDT 24
Finished Aug 06 04:26:44 PM PDT 24
Peak memory 194460 kb
Host smart-84fad9a0-b6ca-4c00-a10f-83f71fcb84a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103490073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3103490073
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.2511931754
Short name T1271
Test name
Test status
Simulation time 15550363 ps
CPU time 0.67 seconds
Started Aug 06 04:26:16 PM PDT 24
Finished Aug 06 04:26:17 PM PDT 24
Peak memory 194616 kb
Host smart-35296d55-76f4-4b62-8d07-cdbcd0570675
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511931754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2511931754
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3855435609
Short name T1304
Test name
Test status
Simulation time 23859933 ps
CPU time 0.58 seconds
Started Aug 06 04:26:14 PM PDT 24
Finished Aug 06 04:26:14 PM PDT 24
Peak memory 194600 kb
Host smart-055ac582-0315-4b0a-8588-3a93a227e317
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855435609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3855435609
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.3487953957
Short name T1270
Test name
Test status
Simulation time 54025063 ps
CPU time 0.67 seconds
Started Aug 06 04:26:51 PM PDT 24
Finished Aug 06 04:26:52 PM PDT 24
Peak memory 194584 kb
Host smart-fa4b5200-8c13-478b-be02-37f9a179b2e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487953957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3487953957
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2758493673
Short name T1189
Test name
Test status
Simulation time 84968101 ps
CPU time 0.59 seconds
Started Aug 06 04:27:46 PM PDT 24
Finished Aug 06 04:27:46 PM PDT 24
Peak memory 193512 kb
Host smart-02ef8f6d-7f4d-4122-abf8-e99bcc6b59d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758493673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2758493673
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.914530655
Short name T1190
Test name
Test status
Simulation time 14283768 ps
CPU time 0.57 seconds
Started Aug 06 04:27:58 PM PDT 24
Finished Aug 06 04:27:59 PM PDT 24
Peak memory 194200 kb
Host smart-787942bc-a44f-4212-a09e-de4435880166
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914530655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.914530655
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3026872312
Short name T1220
Test name
Test status
Simulation time 21540329 ps
CPU time 0.63 seconds
Started Aug 06 04:26:26 PM PDT 24
Finished Aug 06 04:26:26 PM PDT 24
Peak memory 195572 kb
Host smart-892c57fe-b90d-4ab6-a01c-98e6025c0721
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026872312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3026872312
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1341873476
Short name T1299
Test name
Test status
Simulation time 2090723354 ps
CPU time 2.36 seconds
Started Aug 06 04:26:13 PM PDT 24
Finished Aug 06 04:26:16 PM PDT 24
Peak memory 197504 kb
Host smart-df3e4fcf-911d-4858-91d3-e8b8c49e1cde
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341873476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1341873476
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1141196021
Short name T61
Test name
Test status
Simulation time 25677303 ps
CPU time 0.62 seconds
Started Aug 06 04:26:12 PM PDT 24
Finished Aug 06 04:26:14 PM PDT 24
Peak memory 194416 kb
Host smart-ee5b22cd-3956-4ff8-8d88-a7cf2b8668e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141196021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1141196021
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1045096915
Short name T1264
Test name
Test status
Simulation time 86855813 ps
CPU time 1.07 seconds
Started Aug 06 04:26:38 PM PDT 24
Finished Aug 06 04:26:39 PM PDT 24
Peak memory 200268 kb
Host smart-2866f586-d9a0-4f34-aaf6-59cf0e85739b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045096915 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1045096915
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.4273536809
Short name T1296
Test name
Test status
Simulation time 44900208 ps
CPU time 0.57 seconds
Started Aug 06 04:26:15 PM PDT 24
Finished Aug 06 04:26:16 PM PDT 24
Peak memory 195612 kb
Host smart-6fca2406-d04d-4e97-b6e9-2650a1b4b0b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273536809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.4273536809
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3235171543
Short name T1240
Test name
Test status
Simulation time 36018326 ps
CPU time 0.59 seconds
Started Aug 06 04:26:26 PM PDT 24
Finished Aug 06 04:26:27 PM PDT 24
Peak memory 194572 kb
Host smart-cc67565d-36b7-4281-a79b-0d5d7d1856f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235171543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3235171543
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2746179002
Short name T69
Test name
Test status
Simulation time 48794791 ps
CPU time 0.73 seconds
Started Aug 06 04:26:26 PM PDT 24
Finished Aug 06 04:26:27 PM PDT 24
Peak memory 196640 kb
Host smart-e9a2e668-02a3-4767-9cd5-25c21509c329
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746179002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2746179002
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3113388620
Short name T1269
Test name
Test status
Simulation time 356351882 ps
CPU time 1.56 seconds
Started Aug 06 04:25:59 PM PDT 24
Finished Aug 06 04:26:01 PM PDT 24
Peak memory 199408 kb
Host smart-6b729bb3-764a-42a5-bb70-78837ce9fd13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113388620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3113388620
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1831591014
Short name T1313
Test name
Test status
Simulation time 26414065 ps
CPU time 0.54 seconds
Started Aug 06 04:26:49 PM PDT 24
Finished Aug 06 04:26:50 PM PDT 24
Peak memory 194472 kb
Host smart-c91e64d0-43c4-4132-a15a-7d55664ed1e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831591014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1831591014
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3078424377
Short name T1298
Test name
Test status
Simulation time 14671259 ps
CPU time 0.61 seconds
Started Aug 06 04:26:47 PM PDT 24
Finished Aug 06 04:26:48 PM PDT 24
Peak memory 194996 kb
Host smart-75f0e028-bd73-4465-8dce-de8a6f24d73e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078424377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3078424377
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3301496457
Short name T1219
Test name
Test status
Simulation time 13208304 ps
CPU time 0.59 seconds
Started Aug 06 04:26:40 PM PDT 24
Finished Aug 06 04:26:40 PM PDT 24
Peak memory 194644 kb
Host smart-45b39ff3-fb63-43f5-aa01-826e11a4236b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301496457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3301496457
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1985663071
Short name T1230
Test name
Test status
Simulation time 15731497 ps
CPU time 0.63 seconds
Started Aug 06 04:27:46 PM PDT 24
Finished Aug 06 04:27:46 PM PDT 24
Peak memory 194036 kb
Host smart-c83e68d0-172d-4c3d-98f1-d89474ab3ce3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985663071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1985663071
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2632440191
Short name T1183
Test name
Test status
Simulation time 13001936 ps
CPU time 0.56 seconds
Started Aug 06 04:28:13 PM PDT 24
Finished Aug 06 04:28:14 PM PDT 24
Peak memory 194516 kb
Host smart-736c432c-dece-4a8e-a1e9-57c44d99d87d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632440191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2632440191
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2995080274
Short name T1290
Test name
Test status
Simulation time 16190723 ps
CPU time 0.61 seconds
Started Aug 06 04:27:46 PM PDT 24
Finished Aug 06 04:27:46 PM PDT 24
Peak memory 193664 kb
Host smart-d0baf88d-d50e-4a84-9b27-aa462b4b8219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995080274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2995080274
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.427445512
Short name T1237
Test name
Test status
Simulation time 22561813 ps
CPU time 0.56 seconds
Started Aug 06 04:26:37 PM PDT 24
Finished Aug 06 04:26:37 PM PDT 24
Peak memory 194560 kb
Host smart-932407ee-c955-4e2c-9940-145c4ce722fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427445512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.427445512
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.4160008873
Short name T1209
Test name
Test status
Simulation time 11075460 ps
CPU time 0.54 seconds
Started Aug 06 04:28:14 PM PDT 24
Finished Aug 06 04:28:14 PM PDT 24
Peak memory 194580 kb
Host smart-f18ba878-698c-4700-80b2-a8715bf01696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160008873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.4160008873
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3328837766
Short name T1250
Test name
Test status
Simulation time 37597236 ps
CPU time 0.57 seconds
Started Aug 06 04:27:58 PM PDT 24
Finished Aug 06 04:27:59 PM PDT 24
Peak memory 194372 kb
Host smart-b238eeb3-f6c0-4681-8ef0-fce485c377c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328837766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3328837766
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.878974725
Short name T1198
Test name
Test status
Simulation time 30015553 ps
CPU time 0.57 seconds
Started Aug 06 04:28:14 PM PDT 24
Finished Aug 06 04:28:14 PM PDT 24
Peak memory 194588 kb
Host smart-3b00b205-f7b7-4da2-9c7d-160dd054b9ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878974725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.878974725
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1838587918
Short name T1196
Test name
Test status
Simulation time 16516164 ps
CPU time 0.65 seconds
Started Aug 06 04:25:31 PM PDT 24
Finished Aug 06 04:25:32 PM PDT 24
Peak memory 197912 kb
Host smart-d1a66409-1153-4f4e-8cc2-a8cbab8c63ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838587918 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1838587918
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1910713753
Short name T1243
Test name
Test status
Simulation time 42512285 ps
CPU time 0.6 seconds
Started Aug 06 04:26:39 PM PDT 24
Finished Aug 06 04:26:39 PM PDT 24
Peak memory 195584 kb
Host smart-bb1b0795-070d-40bf-99ca-48f2aea50a2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910713753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1910713753
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3796968655
Short name T1216
Test name
Test status
Simulation time 53133486 ps
CPU time 0.55 seconds
Started Aug 06 04:26:38 PM PDT 24
Finished Aug 06 04:26:39 PM PDT 24
Peak memory 194572 kb
Host smart-58be19f7-5559-4ab8-a63c-a451fda5fc8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796968655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3796968655
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2629468913
Short name T1212
Test name
Test status
Simulation time 24115352 ps
CPU time 0.67 seconds
Started Aug 06 04:26:38 PM PDT 24
Finished Aug 06 04:26:39 PM PDT 24
Peak memory 195072 kb
Host smart-49e9c809-4f12-4c05-bfbc-9113d82bb537
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629468913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2629468913
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.271080445
Short name T1225
Test name
Test status
Simulation time 127828802 ps
CPU time 2.15 seconds
Started Aug 06 04:27:06 PM PDT 24
Finished Aug 06 04:27:08 PM PDT 24
Peak memory 200036 kb
Host smart-a01e33bf-3046-4110-9c7a-0e1a6b303d4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271080445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.271080445
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.4251352429
Short name T77
Test name
Test status
Simulation time 356410122 ps
CPU time 1.28 seconds
Started Aug 06 04:26:23 PM PDT 24
Finished Aug 06 04:26:25 PM PDT 24
Peak memory 199172 kb
Host smart-73459c42-35e9-4db2-bbef-4ec271a1bc73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251352429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.4251352429
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2750016477
Short name T1245
Test name
Test status
Simulation time 29458690 ps
CPU time 0.78 seconds
Started Aug 06 04:25:15 PM PDT 24
Finished Aug 06 04:25:16 PM PDT 24
Peak memory 198872 kb
Host smart-1b1ca4ff-832c-47da-bd2a-80501d438d7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750016477 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2750016477
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.652702150
Short name T1312
Test name
Test status
Simulation time 32192674 ps
CPU time 0.54 seconds
Started Aug 06 04:26:37 PM PDT 24
Finished Aug 06 04:26:38 PM PDT 24
Peak memory 195592 kb
Host smart-0741b8d5-57a6-4b7f-a213-d742f151b99d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652702150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.652702150
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1271151840
Short name T1206
Test name
Test status
Simulation time 22660157 ps
CPU time 0.61 seconds
Started Aug 06 04:25:05 PM PDT 24
Finished Aug 06 04:25:06 PM PDT 24
Peak memory 194524 kb
Host smart-23262d3d-5c95-44a9-bdc6-ad56792d7d14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271151840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1271151840
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2224833897
Short name T1275
Test name
Test status
Simulation time 23866020 ps
CPU time 0.7 seconds
Started Aug 06 04:27:06 PM PDT 24
Finished Aug 06 04:27:06 PM PDT 24
Peak memory 196852 kb
Host smart-d55231ec-8d7d-49ef-9ce1-46606ac1a5e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224833897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2224833897
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2569442148
Short name T1182
Test name
Test status
Simulation time 262034046 ps
CPU time 2.56 seconds
Started Aug 06 04:25:42 PM PDT 24
Finished Aug 06 04:25:44 PM PDT 24
Peak memory 200280 kb
Host smart-5c7544dd-c4bf-490c-a45f-55827df7e4c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569442148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2569442148
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3148814405
Short name T75
Test name
Test status
Simulation time 64237686 ps
CPU time 1.22 seconds
Started Aug 06 04:26:23 PM PDT 24
Finished Aug 06 04:26:24 PM PDT 24
Peak memory 199112 kb
Host smart-2c42108f-b3f8-4fa4-a110-9c05c59536f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148814405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3148814405
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.950932332
Short name T1185
Test name
Test status
Simulation time 17461270 ps
CPU time 0.71 seconds
Started Aug 06 04:26:23 PM PDT 24
Finished Aug 06 04:26:24 PM PDT 24
Peak memory 197648 kb
Host smart-0c16da9b-6405-4f5d-bb3b-a80cc3bd74e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950932332 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.950932332
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3406836949
Short name T1274
Test name
Test status
Simulation time 29628075 ps
CPU time 0.61 seconds
Started Aug 06 04:25:41 PM PDT 24
Finished Aug 06 04:25:42 PM PDT 24
Peak memory 195656 kb
Host smart-49744513-486a-47ea-bc0b-afc8440de918
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406836949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3406836949
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.647986149
Short name T1201
Test name
Test status
Simulation time 11106041 ps
CPU time 0.57 seconds
Started Aug 06 04:26:38 PM PDT 24
Finished Aug 06 04:26:38 PM PDT 24
Peak memory 194576 kb
Host smart-4f0d6390-2e9f-48dd-a505-3b99b06f0db8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647986149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.647986149
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2532915285
Short name T1279
Test name
Test status
Simulation time 22826156 ps
CPU time 0.6 seconds
Started Aug 06 04:26:23 PM PDT 24
Finished Aug 06 04:26:24 PM PDT 24
Peak memory 195192 kb
Host smart-9c82fe66-e388-44be-9ef6-faf6912fe8b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532915285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2532915285
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1461902341
Short name T1281
Test name
Test status
Simulation time 62276340 ps
CPU time 0.79 seconds
Started Aug 06 04:26:39 PM PDT 24
Finished Aug 06 04:26:40 PM PDT 24
Peak memory 199664 kb
Host smart-417ccd9b-bb73-4cb8-b960-e93752e59a3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461902341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1461902341
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3962396729
Short name T76
Test name
Test status
Simulation time 228046103 ps
CPU time 1.38 seconds
Started Aug 06 04:26:24 PM PDT 24
Finished Aug 06 04:26:25 PM PDT 24
Peak memory 199336 kb
Host smart-f2f6c959-e9d7-4060-a1c2-105001eb62a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962396729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3962396729
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4055043165
Short name T1249
Test name
Test status
Simulation time 54657175 ps
CPU time 0.81 seconds
Started Aug 06 04:27:11 PM PDT 24
Finished Aug 06 04:27:12 PM PDT 24
Peak memory 199720 kb
Host smart-ac7d1b1c-7929-4b7f-8f94-47272b819971
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055043165 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.4055043165
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1784453560
Short name T1205
Test name
Test status
Simulation time 64709708 ps
CPU time 0.59 seconds
Started Aug 06 04:25:07 PM PDT 24
Finished Aug 06 04:25:07 PM PDT 24
Peak memory 195820 kb
Host smart-65d1c4f3-9728-44ee-ab8f-67aaffcecbd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784453560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1784453560
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2842020613
Short name T1261
Test name
Test status
Simulation time 11189786 ps
CPU time 0.58 seconds
Started Aug 06 04:27:05 PM PDT 24
Finished Aug 06 04:27:06 PM PDT 24
Peak memory 194544 kb
Host smart-516dd086-c1e1-4aa2-b9c4-846dfd614cd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842020613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2842020613
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.250811943
Short name T71
Test name
Test status
Simulation time 15678603 ps
CPU time 0.73 seconds
Started Aug 06 04:25:38 PM PDT 24
Finished Aug 06 04:25:38 PM PDT 24
Peak memory 196624 kb
Host smart-21678491-2b7f-451a-ac4f-d20f3c8f61ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250811943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_
outstanding.250811943
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2621713180
Short name T1193
Test name
Test status
Simulation time 187161250 ps
CPU time 1.13 seconds
Started Aug 06 04:27:06 PM PDT 24
Finished Aug 06 04:27:07 PM PDT 24
Peak memory 199800 kb
Host smart-baeae402-b3e4-4b49-bc25-a82e0f5fd4c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621713180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2621713180
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2933181255
Short name T79
Test name
Test status
Simulation time 365541371 ps
CPU time 1.27 seconds
Started Aug 06 04:26:23 PM PDT 24
Finished Aug 06 04:26:24 PM PDT 24
Peak memory 198736 kb
Host smart-79186fc6-f973-4acf-a354-9aed5f7d8518
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933181255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2933181255
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3794628035
Short name T1200
Test name
Test status
Simulation time 32709160 ps
CPU time 1.5 seconds
Started Aug 06 04:25:38 PM PDT 24
Finished Aug 06 04:25:40 PM PDT 24
Peak memory 200156 kb
Host smart-441a510b-2c39-44b1-8347-5676c9371073
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794628035 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3794628035
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.914452578
Short name T1288
Test name
Test status
Simulation time 37761458 ps
CPU time 0.6 seconds
Started Aug 06 04:26:12 PM PDT 24
Finished Aug 06 04:26:13 PM PDT 24
Peak memory 195628 kb
Host smart-3c4c5b88-bc63-4be2-a211-574d8e12fa74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914452578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.914452578
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.300447492
Short name T1186
Test name
Test status
Simulation time 12751985 ps
CPU time 0.58 seconds
Started Aug 06 04:26:25 PM PDT 24
Finished Aug 06 04:26:25 PM PDT 24
Peak memory 194612 kb
Host smart-d737c190-2bdc-4f09-b210-157657332d1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300447492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.300447492
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4026783279
Short name T1294
Test name
Test status
Simulation time 42848054 ps
CPU time 0.73 seconds
Started Aug 06 04:25:26 PM PDT 24
Finished Aug 06 04:25:27 PM PDT 24
Peak memory 196052 kb
Host smart-6bf6c117-0959-4635-8db0-2ee14109a6b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026783279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.4026783279
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1806694801
Short name T1265
Test name
Test status
Simulation time 61034510 ps
CPU time 1.27 seconds
Started Aug 06 04:26:12 PM PDT 24
Finished Aug 06 04:26:14 PM PDT 24
Peak memory 200176 kb
Host smart-b86d9342-ba15-4cc9-97f8-232cb2396c02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806694801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1806694801
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.4061759753
Short name T112
Test name
Test status
Simulation time 143266424 ps
CPU time 1 seconds
Started Aug 06 04:26:03 PM PDT 24
Finished Aug 06 04:26:04 PM PDT 24
Peak memory 199072 kb
Host smart-86edd337-9fb1-472c-81b2-eba0738fe9a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061759753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.4061759753
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.3375076951
Short name T397
Test name
Test status
Simulation time 30484421 ps
CPU time 0.55 seconds
Started Aug 06 04:28:12 PM PDT 24
Finished Aug 06 04:28:13 PM PDT 24
Peak memory 195068 kb
Host smart-208ec5bb-7c21-4f10-b057-0c509aa0134a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375076951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3375076951
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2800962612
Short name T823
Test name
Test status
Simulation time 46819731393 ps
CPU time 16.42 seconds
Started Aug 06 04:28:03 PM PDT 24
Finished Aug 06 04:28:20 PM PDT 24
Peak memory 199668 kb
Host smart-2ab5ac2f-d210-4765-9bc1-45357da0e5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800962612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2800962612
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.2620323452
Short name T1041
Test name
Test status
Simulation time 114242976966 ps
CPU time 174.24 seconds
Started Aug 06 04:28:00 PM PDT 24
Finished Aug 06 04:30:54 PM PDT 24
Peak memory 199736 kb
Host smart-992fa451-a90d-43b8-ad6b-a3122ae199ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620323452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2620323452
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3663790499
Short name T149
Test name
Test status
Simulation time 19297625845 ps
CPU time 32.08 seconds
Started Aug 06 04:28:09 PM PDT 24
Finished Aug 06 04:28:41 PM PDT 24
Peak memory 199628 kb
Host smart-1897cc3a-2df7-4f8e-8175-929e9d01336f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663790499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3663790499
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1766087357
Short name T870
Test name
Test status
Simulation time 46464174435 ps
CPU time 48.01 seconds
Started Aug 06 04:28:00 PM PDT 24
Finished Aug 06 04:28:48 PM PDT 24
Peak memory 199744 kb
Host smart-cd855001-ca43-4637-bb8c-9d690cb1c0c3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766087357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1766087357
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3813622339
Short name T565
Test name
Test status
Simulation time 95866211045 ps
CPU time 83.73 seconds
Started Aug 06 04:27:59 PM PDT 24
Finished Aug 06 04:29:23 PM PDT 24
Peak memory 199672 kb
Host smart-5ff32885-2a3c-4102-a8f3-4874f80facd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3813622339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3813622339
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.4116901344
Short name T1064
Test name
Test status
Simulation time 5428917158 ps
CPU time 10.25 seconds
Started Aug 06 04:28:16 PM PDT 24
Finished Aug 06 04:28:26 PM PDT 24
Peak memory 199440 kb
Host smart-9234ba8a-2a8f-4afc-9eb8-deb982d15570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116901344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.4116901344
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.978554286
Short name T885
Test name
Test status
Simulation time 5523977073 ps
CPU time 317.5 seconds
Started Aug 06 04:28:06 PM PDT 24
Finished Aug 06 04:33:24 PM PDT 24
Peak memory 199640 kb
Host smart-4cde754a-2d3f-4852-8883-8d04a54c99cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=978554286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.978554286
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.782520364
Short name T751
Test name
Test status
Simulation time 2639722892 ps
CPU time 10.89 seconds
Started Aug 06 04:28:09 PM PDT 24
Finished Aug 06 04:28:21 PM PDT 24
Peak memory 197884 kb
Host smart-4e81e0ad-018e-49d2-afac-57030319cbee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=782520364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.782520364
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3778837714
Short name T142
Test name
Test status
Simulation time 187775234190 ps
CPU time 43.55 seconds
Started Aug 06 04:28:09 PM PDT 24
Finished Aug 06 04:28:52 PM PDT 24
Peak memory 199636 kb
Host smart-b968d978-48a2-4a8f-8e04-07080229c5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778837714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3778837714
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1795387805
Short name T426
Test name
Test status
Simulation time 4343286286 ps
CPU time 3.65 seconds
Started Aug 06 04:28:09 PM PDT 24
Finished Aug 06 04:28:13 PM PDT 24
Peak memory 195820 kb
Host smart-8f5e52b4-0ec8-4884-b03d-01df290be0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795387805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1795387805
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.3083395196
Short name T909
Test name
Test status
Simulation time 604508670 ps
CPU time 2.61 seconds
Started Aug 06 04:28:22 PM PDT 24
Finished Aug 06 04:28:25 PM PDT 24
Peak memory 198460 kb
Host smart-e64d27ba-3679-4bb0-8b46-53f60ee7a906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083395196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3083395196
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.2793865632
Short name T815
Test name
Test status
Simulation time 69181393962 ps
CPU time 908.62 seconds
Started Aug 06 04:28:10 PM PDT 24
Finished Aug 06 04:43:19 PM PDT 24
Peak memory 199692 kb
Host smart-1678926c-fcb2-4f5f-9826-a21e0bf44782
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793865632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2793865632
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2500568700
Short name T566
Test name
Test status
Simulation time 2225404743 ps
CPU time 1.74 seconds
Started Aug 06 04:28:10 PM PDT 24
Finished Aug 06 04:28:12 PM PDT 24
Peak memory 196980 kb
Host smart-9ced978f-6285-4943-b709-ffb8d6698f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500568700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2500568700
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.4021656337
Short name T346
Test name
Test status
Simulation time 29560878152 ps
CPU time 24.96 seconds
Started Aug 06 04:28:13 PM PDT 24
Finished Aug 06 04:28:38 PM PDT 24
Peak memory 199740 kb
Host smart-91fc2ecf-360f-49d2-897c-be10570c3fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021656337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.4021656337
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.2846066753
Short name T1141
Test name
Test status
Simulation time 20021985 ps
CPU time 0.54 seconds
Started Aug 06 04:28:09 PM PDT 24
Finished Aug 06 04:28:10 PM PDT 24
Peak memory 195084 kb
Host smart-57df212f-2f3d-4aed-9e9c-ddeac1c01420
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846066753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2846066753
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3125504052
Short name T537
Test name
Test status
Simulation time 25703471789 ps
CPU time 24.24 seconds
Started Aug 06 04:28:16 PM PDT 24
Finished Aug 06 04:28:41 PM PDT 24
Peak memory 199744 kb
Host smart-149299f7-2226-46a3-bfa2-9be23095b7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125504052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3125504052
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2529712697
Short name T622
Test name
Test status
Simulation time 99474855990 ps
CPU time 23.95 seconds
Started Aug 06 04:28:09 PM PDT 24
Finished Aug 06 04:28:33 PM PDT 24
Peak memory 199716 kb
Host smart-881e3502-9bcf-4fff-b60c-07661a1bb941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529712697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2529712697
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3330222080
Short name T1168
Test name
Test status
Simulation time 61492643332 ps
CPU time 56.55 seconds
Started Aug 06 04:28:09 PM PDT 24
Finished Aug 06 04:29:06 PM PDT 24
Peak memory 199640 kb
Host smart-58fb3f41-7b6a-4815-9860-b1c5ce818d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330222080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3330222080
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.130031291
Short name T475
Test name
Test status
Simulation time 238477177370 ps
CPU time 426.94 seconds
Started Aug 06 04:28:07 PM PDT 24
Finished Aug 06 04:35:14 PM PDT 24
Peak memory 199684 kb
Host smart-1197a2a7-2296-4d0d-a47d-55a384905431
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130031291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.130031291
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2108013147
Short name T1033
Test name
Test status
Simulation time 87767376592 ps
CPU time 192.85 seconds
Started Aug 06 04:28:07 PM PDT 24
Finished Aug 06 04:31:20 PM PDT 24
Peak memory 199732 kb
Host smart-031ae21d-9c21-44a0-8447-e1a994e814e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2108013147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2108013147
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.718758193
Short name T443
Test name
Test status
Simulation time 1541099429 ps
CPU time 1.46 seconds
Started Aug 06 04:28:17 PM PDT 24
Finished Aug 06 04:28:18 PM PDT 24
Peak memory 198304 kb
Host smart-5d43c378-c635-49ff-8490-3b0ca44bcab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718758193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.718758193
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.405233282
Short name T868
Test name
Test status
Simulation time 166921569258 ps
CPU time 62.27 seconds
Started Aug 06 04:28:08 PM PDT 24
Finished Aug 06 04:29:10 PM PDT 24
Peak memory 199272 kb
Host smart-7f2b9bb1-cd97-49a9-9180-b336698bca0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405233282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.405233282
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.3170109050
Short name T962
Test name
Test status
Simulation time 4453732520 ps
CPU time 184.12 seconds
Started Aug 06 04:29:06 PM PDT 24
Finished Aug 06 04:32:10 PM PDT 24
Peak memory 199448 kb
Host smart-9c9896e5-da7c-480d-a69d-39633d46a7c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170109050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3170109050
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.593933654
Short name T669
Test name
Test status
Simulation time 4922778210 ps
CPU time 11.89 seconds
Started Aug 06 04:28:10 PM PDT 24
Finished Aug 06 04:28:22 PM PDT 24
Peak memory 198784 kb
Host smart-6be56717-83b6-4282-817a-b81ea00dd4e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=593933654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.593933654
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1517499209
Short name T379
Test name
Test status
Simulation time 29557618809 ps
CPU time 12.61 seconds
Started Aug 06 04:28:11 PM PDT 24
Finished Aug 06 04:28:24 PM PDT 24
Peak memory 199096 kb
Host smart-b202dca6-65cd-431e-8b57-7e9950009b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517499209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1517499209
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1983587877
Short name T759
Test name
Test status
Simulation time 6671760219 ps
CPU time 3.52 seconds
Started Aug 06 04:28:03 PM PDT 24
Finished Aug 06 04:28:07 PM PDT 24
Peak memory 195896 kb
Host smart-376c5aef-f2d4-4f38-924b-bb8179485f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983587877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1983587877
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2050801513
Short name T27
Test name
Test status
Simulation time 259657258 ps
CPU time 0.85 seconds
Started Aug 06 04:28:07 PM PDT 24
Finished Aug 06 04:28:08 PM PDT 24
Peak memory 218008 kb
Host smart-df04066f-99a2-4889-9d2d-12c0babd98fe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050801513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2050801513
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3411018771
Short name T329
Test name
Test status
Simulation time 532656651 ps
CPU time 1.38 seconds
Started Aug 06 04:27:59 PM PDT 24
Finished Aug 06 04:28:00 PM PDT 24
Peak memory 199540 kb
Host smart-b6bab784-c383-4286-a05e-ae4d92bea939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411018771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3411018771
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.152954097
Short name T763
Test name
Test status
Simulation time 78617167377 ps
CPU time 36.1 seconds
Started Aug 06 04:28:11 PM PDT 24
Finished Aug 06 04:28:47 PM PDT 24
Peak memory 199668 kb
Host smart-d178d164-9beb-4970-9e0d-073fc45b2629
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152954097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.152954097
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1219563430
Short name T1098
Test name
Test status
Simulation time 7054315816 ps
CPU time 11.81 seconds
Started Aug 06 04:28:04 PM PDT 24
Finished Aug 06 04:28:16 PM PDT 24
Peak memory 199464 kb
Host smart-6e038ca3-5650-45bc-9a00-5399b075feba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219563430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1219563430
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2919502068
Short name T932
Test name
Test status
Simulation time 164014494862 ps
CPU time 57.72 seconds
Started Aug 06 04:28:08 PM PDT 24
Finished Aug 06 04:29:06 PM PDT 24
Peak memory 199664 kb
Host smart-121195e6-8de6-47b9-b351-c5f23c79e5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919502068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2919502068
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3179941961
Short name T255
Test name
Test status
Simulation time 132173004123 ps
CPU time 176.65 seconds
Started Aug 06 04:28:14 PM PDT 24
Finished Aug 06 04:31:11 PM PDT 24
Peak memory 199656 kb
Host smart-443df317-292a-47f9-9e59-c22649d6cce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179941961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3179941961
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2529295342
Short name T673
Test name
Test status
Simulation time 98889856920 ps
CPU time 152.45 seconds
Started Aug 06 04:28:28 PM PDT 24
Finished Aug 06 04:31:01 PM PDT 24
Peak memory 199680 kb
Host smart-bc31893d-5a46-46c6-897b-e14b618d57b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529295342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2529295342
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.391018384
Short name T1075
Test name
Test status
Simulation time 43504668539 ps
CPU time 29.5 seconds
Started Aug 06 04:29:06 PM PDT 24
Finished Aug 06 04:29:36 PM PDT 24
Peak memory 199372 kb
Host smart-1f3236ff-5554-4394-a3f5-bfd05c3a2663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391018384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.391018384
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.2823126328
Short name T549
Test name
Test status
Simulation time 31671195564 ps
CPU time 15.77 seconds
Started Aug 06 04:28:40 PM PDT 24
Finished Aug 06 04:28:56 PM PDT 24
Peak memory 199612 kb
Host smart-b3d4410b-511c-4184-a721-7af98287ecaf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823126328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2823126328
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1897971809
Short name T474
Test name
Test status
Simulation time 93989120436 ps
CPU time 250.49 seconds
Started Aug 06 04:28:32 PM PDT 24
Finished Aug 06 04:32:42 PM PDT 24
Peak memory 199772 kb
Host smart-dc7e02ff-9b85-4f95-a597-93fc1383cf97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1897971809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1897971809
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2911898573
Short name T938
Test name
Test status
Simulation time 1111648447 ps
CPU time 1.8 seconds
Started Aug 06 04:28:20 PM PDT 24
Finished Aug 06 04:28:22 PM PDT 24
Peak memory 195160 kb
Host smart-4db011be-240e-465f-9813-59fef14601eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911898573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2911898573
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1777640104
Short name T419
Test name
Test status
Simulation time 44800748776 ps
CPU time 92.8 seconds
Started Aug 06 04:28:22 PM PDT 24
Finished Aug 06 04:29:55 PM PDT 24
Peak memory 198936 kb
Host smart-17fbf290-db45-4a04-93b1-2900f14b094e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777640104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1777640104
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.995011420
Short name T265
Test name
Test status
Simulation time 8001031981 ps
CPU time 190.55 seconds
Started Aug 06 04:28:46 PM PDT 24
Finished Aug 06 04:31:56 PM PDT 24
Peak memory 199768 kb
Host smart-339da6ec-4bb0-472f-b544-f4c58991873b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=995011420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.995011420
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.4184448087
Short name T722
Test name
Test status
Simulation time 6493589187 ps
CPU time 14.21 seconds
Started Aug 06 04:28:42 PM PDT 24
Finished Aug 06 04:28:57 PM PDT 24
Peak memory 198912 kb
Host smart-4b6dfc4f-828d-4a36-b26a-3c2726310ce9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4184448087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.4184448087
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2055602287
Short name T804
Test name
Test status
Simulation time 123920591927 ps
CPU time 148.15 seconds
Started Aug 06 04:28:27 PM PDT 24
Finished Aug 06 04:30:56 PM PDT 24
Peak memory 199780 kb
Host smart-8f737ba4-685f-47dd-906a-61143160da85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055602287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2055602287
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1628942202
Short name T1124
Test name
Test status
Simulation time 52392997500 ps
CPU time 6.44 seconds
Started Aug 06 04:28:28 PM PDT 24
Finished Aug 06 04:28:35 PM PDT 24
Peak memory 195532 kb
Host smart-5055f410-f290-4fda-a7a1-7eb64ba4100f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628942202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1628942202
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2969833454
Short name T1153
Test name
Test status
Simulation time 6002783696 ps
CPU time 13.08 seconds
Started Aug 06 04:28:24 PM PDT 24
Finished Aug 06 04:28:37 PM PDT 24
Peak memory 199424 kb
Host smart-92f3f384-621a-473b-beb6-1bc80136e081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969833454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2969833454
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2135061330
Short name T1089
Test name
Test status
Simulation time 498110316336 ps
CPU time 480.54 seconds
Started Aug 06 04:28:31 PM PDT 24
Finished Aug 06 04:36:32 PM PDT 24
Peak memory 216048 kb
Host smart-227d0c4c-4662-42e3-ab98-18cddb2683d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135061330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2135061330
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1727197604
Short name T921
Test name
Test status
Simulation time 31725139631 ps
CPU time 384.15 seconds
Started Aug 06 04:28:46 PM PDT 24
Finished Aug 06 04:35:10 PM PDT 24
Peak memory 216376 kb
Host smart-a034b025-bf1f-446e-b505-51190abdf6fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727197604 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1727197604
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.160846902
Short name T952
Test name
Test status
Simulation time 536103223 ps
CPU time 2.39 seconds
Started Aug 06 04:28:47 PM PDT 24
Finished Aug 06 04:28:49 PM PDT 24
Peak memory 199004 kb
Host smart-1b06066d-502a-4a7f-83e5-c4b729456d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160846902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.160846902
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.888761199
Short name T1021
Test name
Test status
Simulation time 94336298656 ps
CPU time 70.44 seconds
Started Aug 06 04:28:28 PM PDT 24
Finished Aug 06 04:29:39 PM PDT 24
Peak memory 199628 kb
Host smart-cfcb52ac-957a-4f85-b380-d5b0dead8e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888761199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.888761199
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1956908835
Short name T805
Test name
Test status
Simulation time 5391433926 ps
CPU time 8.45 seconds
Started Aug 06 04:30:39 PM PDT 24
Finished Aug 06 04:30:48 PM PDT 24
Peak memory 198772 kb
Host smart-624d3a99-8116-4f04-8b4b-0579a5ed8167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956908835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1956908835
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1019978705
Short name T808
Test name
Test status
Simulation time 140950902657 ps
CPU time 55.12 seconds
Started Aug 06 04:30:44 PM PDT 24
Finished Aug 06 04:31:39 PM PDT 24
Peak memory 199688 kb
Host smart-0d41df5d-85f5-4847-8397-63db0f99cc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019978705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1019978705
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3274564478
Short name T1087
Test name
Test status
Simulation time 216976402786 ps
CPU time 76.69 seconds
Started Aug 06 04:30:44 PM PDT 24
Finished Aug 06 04:32:01 PM PDT 24
Peak memory 199712 kb
Host smart-b16141d3-a10b-443b-8a6c-37c71c1ba9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274564478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3274564478
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3999365559
Short name T1043
Test name
Test status
Simulation time 71870003022 ps
CPU time 169.98 seconds
Started Aug 06 04:30:39 PM PDT 24
Finished Aug 06 04:33:29 PM PDT 24
Peak memory 199636 kb
Host smart-43dae295-f5ea-42a0-8dd2-d13481d20d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999365559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3999365559
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.375559056
Short name T212
Test name
Test status
Simulation time 17508562506 ps
CPU time 24.65 seconds
Started Aug 06 04:30:42 PM PDT 24
Finished Aug 06 04:31:06 PM PDT 24
Peak memory 199748 kb
Host smart-5b49adb2-b365-486c-827f-b80de78ae1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375559056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.375559056
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3828603093
Short name T1156
Test name
Test status
Simulation time 32355557170 ps
CPU time 51.79 seconds
Started Aug 06 04:30:42 PM PDT 24
Finished Aug 06 04:31:34 PM PDT 24
Peak memory 199788 kb
Host smart-f42e27b0-fb27-41c2-a6f7-4b355586ef0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828603093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3828603093
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3752038262
Short name T853
Test name
Test status
Simulation time 21523527 ps
CPU time 0.57 seconds
Started Aug 06 04:28:39 PM PDT 24
Finished Aug 06 04:28:40 PM PDT 24
Peak memory 194596 kb
Host smart-9953ed8c-c5e5-41b5-a638-1593b9e81cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752038262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3752038262
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1886235810
Short name T766
Test name
Test status
Simulation time 25824570984 ps
CPU time 36.48 seconds
Started Aug 06 04:28:54 PM PDT 24
Finished Aug 06 04:29:30 PM PDT 24
Peak memory 199660 kb
Host smart-3d3096ed-b3c6-400c-9cce-5d855b6d6579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886235810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1886235810
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.4061313225
Short name T322
Test name
Test status
Simulation time 351102260968 ps
CPU time 134.83 seconds
Started Aug 06 04:28:44 PM PDT 24
Finished Aug 06 04:30:59 PM PDT 24
Peak memory 199680 kb
Host smart-37086e87-e033-43fc-af24-251f7da8fcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061313225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.4061313225
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1882152545
Short name T593
Test name
Test status
Simulation time 142270522401 ps
CPU time 123.02 seconds
Started Aug 06 04:28:45 PM PDT 24
Finished Aug 06 04:30:49 PM PDT 24
Peak memory 199616 kb
Host smart-896cabfe-1af5-4ed3-a05f-a463994f4e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882152545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1882152545
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3023731230
Short name T648
Test name
Test status
Simulation time 62224163384 ps
CPU time 112.62 seconds
Started Aug 06 04:28:49 PM PDT 24
Finished Aug 06 04:30:42 PM PDT 24
Peak memory 199712 kb
Host smart-5f2d5c03-56d6-473b-8cc4-6dee47f21212
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023731230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3023731230
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.441897110
Short name T801
Test name
Test status
Simulation time 279444681585 ps
CPU time 628.6 seconds
Started Aug 06 04:28:45 PM PDT 24
Finished Aug 06 04:39:14 PM PDT 24
Peak memory 199640 kb
Host smart-f0c5237e-3f13-4cbe-a905-d03de42ca579
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=441897110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.441897110
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1635592881
Short name T987
Test name
Test status
Simulation time 6234453631 ps
CPU time 6.46 seconds
Started Aug 06 04:28:44 PM PDT 24
Finished Aug 06 04:28:51 PM PDT 24
Peak memory 199620 kb
Host smart-b344e08f-f95a-4aa8-ba81-014522aa173b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635592881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1635592881
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.1832718535
Short name T431
Test name
Test status
Simulation time 27260137337 ps
CPU time 371.51 seconds
Started Aug 06 04:28:41 PM PDT 24
Finished Aug 06 04:34:53 PM PDT 24
Peak memory 199724 kb
Host smart-228bb7f3-1de8-45f6-855c-43452003387b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1832718535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1832718535
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1997427445
Short name T977
Test name
Test status
Simulation time 6153663818 ps
CPU time 52.04 seconds
Started Aug 06 04:28:48 PM PDT 24
Finished Aug 06 04:29:40 PM PDT 24
Peak memory 197784 kb
Host smart-3222cd48-4a66-4807-8d57-6ca2061ea455
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1997427445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1997427445
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.527050168
Short name T1070
Test name
Test status
Simulation time 77329199720 ps
CPU time 81.54 seconds
Started Aug 06 04:28:34 PM PDT 24
Finished Aug 06 04:29:55 PM PDT 24
Peak memory 199716 kb
Host smart-2758e7fe-a66c-46c3-b590-e0a498d9ae26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527050168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.527050168
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2672861280
Short name T869
Test name
Test status
Simulation time 717875392 ps
CPU time 1.67 seconds
Started Aug 06 04:28:42 PM PDT 24
Finished Aug 06 04:28:44 PM PDT 24
Peak memory 195460 kb
Host smart-162db7bb-640f-4d47-acb9-7d48ee6069c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672861280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2672861280
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2501415992
Short name T948
Test name
Test status
Simulation time 515851438 ps
CPU time 1.47 seconds
Started Aug 06 04:28:24 PM PDT 24
Finished Aug 06 04:28:26 PM PDT 24
Peak memory 197800 kb
Host smart-87f5d5e6-9b92-43b4-ab69-7c8e466a179f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501415992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2501415992
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.505313618
Short name T539
Test name
Test status
Simulation time 331465149938 ps
CPU time 139.51 seconds
Started Aug 06 04:28:34 PM PDT 24
Finished Aug 06 04:30:54 PM PDT 24
Peak memory 199760 kb
Host smart-9ddadd05-ca50-4812-8c93-085bd9528b0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505313618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.505313618
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3249135665
Short name T1163
Test name
Test status
Simulation time 282194471259 ps
CPU time 1017.93 seconds
Started Aug 06 04:28:40 PM PDT 24
Finished Aug 06 04:45:38 PM PDT 24
Peak memory 224548 kb
Host smart-0e4c69bf-339a-48eb-8fed-5d6196544db1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249135665 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3249135665
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.971436859
Short name T485
Test name
Test status
Simulation time 6466640909 ps
CPU time 15.88 seconds
Started Aug 06 04:28:29 PM PDT 24
Finished Aug 06 04:28:45 PM PDT 24
Peak memory 199572 kb
Host smart-8bbfad73-8ca0-45a7-a2a6-5ef0f9b9dae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971436859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.971436859
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.4083079799
Short name T715
Test name
Test status
Simulation time 79372775251 ps
CPU time 31.75 seconds
Started Aug 06 04:28:47 PM PDT 24
Finished Aug 06 04:29:19 PM PDT 24
Peak memory 199632 kb
Host smart-459751bb-c3d6-4938-9cfe-215344598645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083079799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.4083079799
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.316680367
Short name T702
Test name
Test status
Simulation time 471210425027 ps
CPU time 32.86 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:31:13 PM PDT 24
Peak memory 199648 kb
Host smart-a9883560-41c8-49e3-abb9-badd91bc35f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316680367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.316680367
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3478730284
Short name T857
Test name
Test status
Simulation time 102901471963 ps
CPU time 37.97 seconds
Started Aug 06 04:30:39 PM PDT 24
Finished Aug 06 04:31:17 PM PDT 24
Peak memory 199768 kb
Host smart-8eeabfa7-ccc8-460a-a24a-3e08b8f11a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478730284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3478730284
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.238275708
Short name T731
Test name
Test status
Simulation time 9450454657 ps
CPU time 13.79 seconds
Started Aug 06 04:30:41 PM PDT 24
Finished Aug 06 04:30:55 PM PDT 24
Peak memory 199492 kb
Host smart-4020b8f5-4961-48e0-885f-7ab6b55ccb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238275708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.238275708
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.765213811
Short name T1057
Test name
Test status
Simulation time 138068285352 ps
CPU time 36.42 seconds
Started Aug 06 04:30:47 PM PDT 24
Finished Aug 06 04:31:23 PM PDT 24
Peak memory 199764 kb
Host smart-38ba077f-c729-4c10-9842-4154193d9af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765213811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.765213811
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2718374917
Short name T842
Test name
Test status
Simulation time 25461039081 ps
CPU time 23.88 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:31:04 PM PDT 24
Peak memory 199736 kb
Host smart-73517da4-2b07-4c74-b381-8ca8155468f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718374917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2718374917
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3450404586
Short name T965
Test name
Test status
Simulation time 36842722890 ps
CPU time 9.06 seconds
Started Aug 06 04:30:43 PM PDT 24
Finished Aug 06 04:30:52 PM PDT 24
Peak memory 199696 kb
Host smart-e6557896-a537-49bf-aac8-948e8601df14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450404586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3450404586
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2232647576
Short name T873
Test name
Test status
Simulation time 35423764156 ps
CPU time 49.38 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:31:30 PM PDT 24
Peak memory 199716 kb
Host smart-64d0f731-ad17-4d99-b342-b6390a1e3f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232647576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2232647576
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.1810185772
Short name T886
Test name
Test status
Simulation time 39891326 ps
CPU time 0.53 seconds
Started Aug 06 04:28:41 PM PDT 24
Finished Aug 06 04:28:42 PM PDT 24
Peak memory 194504 kb
Host smart-e35ce61a-0bbf-4411-8bb5-505fcb1e100f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810185772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1810185772
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.787298758
Short name T1154
Test name
Test status
Simulation time 72000313362 ps
CPU time 119.87 seconds
Started Aug 06 04:28:41 PM PDT 24
Finished Aug 06 04:30:41 PM PDT 24
Peak memory 199708 kb
Host smart-78827443-095f-44a2-a755-4f6b77b2d9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787298758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.787298758
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2861195799
Short name T889
Test name
Test status
Simulation time 400277572107 ps
CPU time 57.71 seconds
Started Aug 06 04:28:38 PM PDT 24
Finished Aug 06 04:29:35 PM PDT 24
Peak memory 199732 kb
Host smart-95f83bdc-a8cb-463b-afdd-b42beb569fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861195799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2861195799
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.294390980
Short name T1106
Test name
Test status
Simulation time 115407163763 ps
CPU time 50.52 seconds
Started Aug 06 04:28:27 PM PDT 24
Finished Aug 06 04:29:18 PM PDT 24
Peak memory 199212 kb
Host smart-52944fd7-c567-423d-91c2-4e0d68d34a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294390980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.294390980
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1371475983
Short name T866
Test name
Test status
Simulation time 11593577071 ps
CPU time 17.9 seconds
Started Aug 06 04:28:31 PM PDT 24
Finished Aug 06 04:28:49 PM PDT 24
Peak memory 198988 kb
Host smart-c69c2f61-d36f-496b-a018-344bc428f00a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371475983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1371475983
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2221172192
Short name T580
Test name
Test status
Simulation time 109269355609 ps
CPU time 312.63 seconds
Started Aug 06 04:28:29 PM PDT 24
Finished Aug 06 04:33:42 PM PDT 24
Peak memory 199664 kb
Host smart-f310fa08-26bd-4e2f-b03b-018d23bcc022
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2221172192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2221172192
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.28623894
Short name T800
Test name
Test status
Simulation time 362945578 ps
CPU time 0.74 seconds
Started Aug 06 04:28:40 PM PDT 24
Finished Aug 06 04:28:41 PM PDT 24
Peak memory 195888 kb
Host smart-ade958d0-b757-42e0-b381-5c0c4110a0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28623894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.28623894
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.559786927
Short name T559
Test name
Test status
Simulation time 473323762084 ps
CPU time 96.82 seconds
Started Aug 06 04:28:55 PM PDT 24
Finished Aug 06 04:30:32 PM PDT 24
Peak memory 208024 kb
Host smart-28df9b4d-2254-478d-b150-460756d8d137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559786927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.559786927
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.653362114
Short name T667
Test name
Test status
Simulation time 18905574487 ps
CPU time 173.62 seconds
Started Aug 06 04:28:45 PM PDT 24
Finished Aug 06 04:31:38 PM PDT 24
Peak memory 199668 kb
Host smart-edc2125e-717a-4452-a718-661fab0a321e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=653362114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.653362114
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.2033062981
Short name T543
Test name
Test status
Simulation time 6043433048 ps
CPU time 50.91 seconds
Started Aug 06 04:28:40 PM PDT 24
Finished Aug 06 04:29:31 PM PDT 24
Peak memory 199076 kb
Host smart-8c0df744-066f-4991-8705-a829b2dc6892
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2033062981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2033062981
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1893711722
Short name T765
Test name
Test status
Simulation time 285310246448 ps
CPU time 27.94 seconds
Started Aug 06 04:28:28 PM PDT 24
Finished Aug 06 04:28:56 PM PDT 24
Peak memory 199644 kb
Host smart-c4ebbcf9-254a-4abe-9970-b9d0200a6e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893711722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1893711722
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2042540560
Short name T942
Test name
Test status
Simulation time 47569470568 ps
CPU time 9.27 seconds
Started Aug 06 04:28:39 PM PDT 24
Finished Aug 06 04:28:48 PM PDT 24
Peak memory 195596 kb
Host smart-301eb445-1bb8-41cc-a785-aeb6419b0ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042540560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2042540560
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2714524391
Short name T2
Test name
Test status
Simulation time 6171538569 ps
CPU time 7.69 seconds
Started Aug 06 04:28:36 PM PDT 24
Finished Aug 06 04:28:44 PM PDT 24
Peak memory 199608 kb
Host smart-6a5eee85-2602-417a-88b6-5ff51c9a2206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714524391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2714524391
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2554563675
Short name T988
Test name
Test status
Simulation time 87371780132 ps
CPU time 1031.52 seconds
Started Aug 06 04:28:59 PM PDT 24
Finished Aug 06 04:46:11 PM PDT 24
Peak memory 216312 kb
Host smart-a001e47c-3f51-41cc-8dc3-22f8fd200b1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554563675 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2554563675
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.4258341437
Short name T704
Test name
Test status
Simulation time 1200024207 ps
CPU time 2.18 seconds
Started Aug 06 04:28:32 PM PDT 24
Finished Aug 06 04:28:34 PM PDT 24
Peak memory 198588 kb
Host smart-ec204a95-1c5c-469b-8e47-a5fe2750ad00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258341437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.4258341437
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1024852303
Short name T36
Test name
Test status
Simulation time 171114107185 ps
CPU time 91.54 seconds
Started Aug 06 04:28:55 PM PDT 24
Finished Aug 06 04:30:26 PM PDT 24
Peak memory 199728 kb
Host smart-40538769-9b91-4c2e-a142-e3f986d5b88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024852303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1024852303
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1526977870
Short name T144
Test name
Test status
Simulation time 120955281716 ps
CPU time 60.61 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:31:41 PM PDT 24
Peak memory 199708 kb
Host smart-d2e1c539-557f-491d-9fda-1c5920f6507a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526977870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1526977870
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3263601531
Short name T553
Test name
Test status
Simulation time 169265296991 ps
CPU time 147.59 seconds
Started Aug 06 04:30:36 PM PDT 24
Finished Aug 06 04:33:04 PM PDT 24
Peak memory 199732 kb
Host smart-e60855a5-c626-4991-b6d1-422025faf777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263601531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3263601531
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.4179521144
Short name T516
Test name
Test status
Simulation time 18577113290 ps
CPU time 41.03 seconds
Started Aug 06 04:30:47 PM PDT 24
Finished Aug 06 04:31:28 PM PDT 24
Peak memory 199728 kb
Host smart-34d14307-bd9c-428c-86a7-2643760c5f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179521144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.4179521144
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2148511657
Short name T177
Test name
Test status
Simulation time 7294450991 ps
CPU time 12.92 seconds
Started Aug 06 04:30:41 PM PDT 24
Finished Aug 06 04:30:54 PM PDT 24
Peak memory 199468 kb
Host smart-474af999-a40c-4992-ac1f-a9b7bf4a0a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148511657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2148511657
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1082109340
Short name T1038
Test name
Test status
Simulation time 55350705707 ps
CPU time 44.07 seconds
Started Aug 06 04:30:42 PM PDT 24
Finished Aug 06 04:31:26 PM PDT 24
Peak memory 199668 kb
Host smart-a5ffe29e-ce29-4c02-9d0a-4ec8439bb50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082109340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1082109340
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1081730145
Short name T436
Test name
Test status
Simulation time 16010308886 ps
CPU time 34.22 seconds
Started Aug 06 04:30:42 PM PDT 24
Finished Aug 06 04:31:16 PM PDT 24
Peak memory 199752 kb
Host smart-52f48bda-9e92-45a7-bff6-e49954bf313d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081730145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1081730145
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.773549931
Short name T93
Test name
Test status
Simulation time 60690105677 ps
CPU time 139.66 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:33:00 PM PDT 24
Peak memory 199760 kb
Host smart-26a6573c-8240-40c4-994c-22ee0ee96eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773549931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.773549931
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1302276078
Short name T573
Test name
Test status
Simulation time 37002674629 ps
CPU time 34.13 seconds
Started Aug 06 04:30:39 PM PDT 24
Finished Aug 06 04:31:13 PM PDT 24
Peak memory 199720 kb
Host smart-8929c090-7239-4821-a2d7-3beca54f486d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302276078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1302276078
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2596263366
Short name T760
Test name
Test status
Simulation time 45793378 ps
CPU time 0.56 seconds
Started Aug 06 04:28:43 PM PDT 24
Finished Aug 06 04:28:44 PM PDT 24
Peak memory 195176 kb
Host smart-28f04bce-c2af-41fe-b649-a0db38ea7b70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596263366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2596263366
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2217741449
Short name T437
Test name
Test status
Simulation time 28030334450 ps
CPU time 52.05 seconds
Started Aug 06 04:28:31 PM PDT 24
Finished Aug 06 04:29:23 PM PDT 24
Peak memory 199716 kb
Host smart-c01e3370-c6c4-4994-b766-322bf99a483d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217741449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2217741449
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3679143836
Short name T609
Test name
Test status
Simulation time 67248485560 ps
CPU time 154.15 seconds
Started Aug 06 04:28:32 PM PDT 24
Finished Aug 06 04:31:06 PM PDT 24
Peak memory 199620 kb
Host smart-d772b9e9-7920-43e1-a6d8-95f9ea325900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679143836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3679143836
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2402820199
Short name T699
Test name
Test status
Simulation time 230732298907 ps
CPU time 50.9 seconds
Started Aug 06 04:28:40 PM PDT 24
Finished Aug 06 04:29:31 PM PDT 24
Peak memory 199680 kb
Host smart-9f64592b-6f70-4b01-a9c6-1a26b28ed1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402820199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2402820199
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3266949012
Short name T826
Test name
Test status
Simulation time 35462941804 ps
CPU time 13.82 seconds
Started Aug 06 04:28:57 PM PDT 24
Finished Aug 06 04:29:11 PM PDT 24
Peak memory 199684 kb
Host smart-3fed9cfd-a84a-4ab9-84f5-93b7ab656883
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266949012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3266949012
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3947730653
Short name T306
Test name
Test status
Simulation time 162650624194 ps
CPU time 758.7 seconds
Started Aug 06 04:28:29 PM PDT 24
Finished Aug 06 04:41:08 PM PDT 24
Peak memory 199748 kb
Host smart-cbab6944-b7cf-48b9-bf75-ff7736bdcaf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3947730653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3947730653
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1417681088
Short name T21
Test name
Test status
Simulation time 8057337228 ps
CPU time 8.14 seconds
Started Aug 06 04:28:57 PM PDT 24
Finished Aug 06 04:29:05 PM PDT 24
Peak memory 199684 kb
Host smart-c8d8bff8-32af-44cd-9f07-7782b26354de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417681088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1417681088
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2612558532
Short name T924
Test name
Test status
Simulation time 67955169813 ps
CPU time 126.76 seconds
Started Aug 06 04:28:57 PM PDT 24
Finished Aug 06 04:31:04 PM PDT 24
Peak memory 199404 kb
Host smart-d520b7b6-f579-4c5f-972c-3864e7f5fb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612558532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2612558532
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.1747681044
Short name T513
Test name
Test status
Simulation time 4336263371 ps
CPU time 62.29 seconds
Started Aug 06 04:28:55 PM PDT 24
Finished Aug 06 04:29:57 PM PDT 24
Peak memory 199728 kb
Host smart-ec68a799-d4ca-4996-9c78-68a7577ee97e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1747681044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1747681044
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2209196516
Short name T790
Test name
Test status
Simulation time 4802955211 ps
CPU time 33.59 seconds
Started Aug 06 04:28:45 PM PDT 24
Finished Aug 06 04:29:18 PM PDT 24
Peak memory 198740 kb
Host smart-65f95eb7-be65-44bb-92e9-f2e73e5caa0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2209196516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2209196516
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2873000611
Short name T995
Test name
Test status
Simulation time 33749937036 ps
CPU time 15.58 seconds
Started Aug 06 04:28:44 PM PDT 24
Finished Aug 06 04:28:59 PM PDT 24
Peak memory 199656 kb
Host smart-8b210879-206b-4aba-84ef-af1b654bdc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873000611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2873000611
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3617900914
Short name T432
Test name
Test status
Simulation time 1666046556 ps
CPU time 2.43 seconds
Started Aug 06 04:28:43 PM PDT 24
Finished Aug 06 04:28:45 PM PDT 24
Peak memory 195272 kb
Host smart-a79ef3f2-10cd-427b-b0c7-1357f6ea9aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617900914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3617900914
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3729074307
Short name T638
Test name
Test status
Simulation time 5376337608 ps
CPU time 9.09 seconds
Started Aug 06 04:28:31 PM PDT 24
Finished Aug 06 04:28:40 PM PDT 24
Peak memory 199532 kb
Host smart-2347887c-6b49-4b4b-b02c-e3aec260d72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729074307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3729074307
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3606945059
Short name T530
Test name
Test status
Simulation time 50960483901 ps
CPU time 588.19 seconds
Started Aug 06 04:28:37 PM PDT 24
Finished Aug 06 04:38:26 PM PDT 24
Peak memory 216372 kb
Host smart-ea78b460-4c5b-4668-9721-c2fbf7308525
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606945059 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3606945059
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.4123871591
Short name T803
Test name
Test status
Simulation time 956868713 ps
CPU time 3.33 seconds
Started Aug 06 04:28:43 PM PDT 24
Finished Aug 06 04:28:46 PM PDT 24
Peak memory 198232 kb
Host smart-85149ea6-d23f-4111-b1a2-ad89387947a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123871591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.4123871591
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3128520884
Short name T607
Test name
Test status
Simulation time 63168288485 ps
CPU time 12.64 seconds
Started Aug 06 04:28:35 PM PDT 24
Finished Aug 06 04:28:47 PM PDT 24
Peak memory 197484 kb
Host smart-e13d07b3-ca7d-401a-9e9d-308627e0ea6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128520884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3128520884
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.190227659
Short name T160
Test name
Test status
Simulation time 127018109014 ps
CPU time 197 seconds
Started Aug 06 04:30:47 PM PDT 24
Finished Aug 06 04:34:04 PM PDT 24
Peak memory 199660 kb
Host smart-89788504-5bfe-4e01-9494-bf1a0c5ad4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190227659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.190227659
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.750103629
Short name T219
Test name
Test status
Simulation time 315597267435 ps
CPU time 45.06 seconds
Started Aug 06 04:30:41 PM PDT 24
Finished Aug 06 04:31:26 PM PDT 24
Peak memory 199680 kb
Host smart-31baaec5-5db4-422c-a75a-a1aaca9a4b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750103629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.750103629
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.444347717
Short name T514
Test name
Test status
Simulation time 5924416153 ps
CPU time 9.9 seconds
Started Aug 06 04:30:39 PM PDT 24
Finished Aug 06 04:30:49 PM PDT 24
Peak memory 199748 kb
Host smart-92faab27-6ca7-4efb-a7ee-80aef541e602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444347717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.444347717
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.70427456
Short name T957
Test name
Test status
Simulation time 129399092583 ps
CPU time 33.22 seconds
Started Aug 06 04:30:47 PM PDT 24
Finished Aug 06 04:31:20 PM PDT 24
Peak memory 199828 kb
Host smart-c4beb16a-bdd7-4c71-9531-8e4f5d6324d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70427456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.70427456
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2430953942
Short name T850
Test name
Test status
Simulation time 12181917297 ps
CPU time 19.56 seconds
Started Aug 06 04:30:45 PM PDT 24
Finished Aug 06 04:31:04 PM PDT 24
Peak memory 199692 kb
Host smart-fb168145-11e3-4b1c-8529-42fe35ab3182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430953942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2430953942
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.556464985
Short name T3
Test name
Test status
Simulation time 165235140213 ps
CPU time 111.46 seconds
Started Aug 06 04:30:46 PM PDT 24
Finished Aug 06 04:32:38 PM PDT 24
Peak memory 199616 kb
Host smart-38a5575a-e156-4a52-b705-58e154af1ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556464985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.556464985
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3060709566
Short name T1133
Test name
Test status
Simulation time 77228451530 ps
CPU time 26.56 seconds
Started Aug 06 04:30:39 PM PDT 24
Finished Aug 06 04:31:05 PM PDT 24
Peak memory 199664 kb
Host smart-9b502aaa-0db6-4d03-b958-8f57f58f2e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060709566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3060709566
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.501232567
Short name T227
Test name
Test status
Simulation time 63654913849 ps
CPU time 37.67 seconds
Started Aug 06 04:30:41 PM PDT 24
Finished Aug 06 04:31:19 PM PDT 24
Peak memory 199696 kb
Host smart-e0f2414c-59f7-4ace-9278-f80e34ae53ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501232567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.501232567
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1224263207
Short name T618
Test name
Test status
Simulation time 65653913836 ps
CPU time 45.36 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:31:25 PM PDT 24
Peak memory 199772 kb
Host smart-97efc19f-66f1-44ed-9ff9-34f24f58eaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224263207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1224263207
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1554734835
Short name T900
Test name
Test status
Simulation time 14480332 ps
CPU time 0.6 seconds
Started Aug 06 04:28:48 PM PDT 24
Finished Aug 06 04:28:49 PM PDT 24
Peak memory 195528 kb
Host smart-6bf01fb7-c081-4e3c-ae77-69b1f68ddc3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554734835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1554734835
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2378171047
Short name T670
Test name
Test status
Simulation time 115599850119 ps
CPU time 165.28 seconds
Started Aug 06 04:28:45 PM PDT 24
Finished Aug 06 04:31:31 PM PDT 24
Peak memory 199624 kb
Host smart-a6692c8b-b418-4529-bb53-0f7b41eadc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378171047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2378171047
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2118878769
Short name T1164
Test name
Test status
Simulation time 152338678211 ps
CPU time 55.13 seconds
Started Aug 06 04:28:52 PM PDT 24
Finished Aug 06 04:29:47 PM PDT 24
Peak memory 199780 kb
Host smart-d32c5b39-eff5-4fab-ae19-0c57b4c21161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118878769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2118878769
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.819213386
Short name T556
Test name
Test status
Simulation time 145732486110 ps
CPU time 235 seconds
Started Aug 06 04:28:45 PM PDT 24
Finished Aug 06 04:32:40 PM PDT 24
Peak memory 199160 kb
Host smart-ffc6dd72-c194-4999-9472-d2f929bdb2ae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819213386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.819213386
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3958210460
Short name T40
Test name
Test status
Simulation time 128151784234 ps
CPU time 759.15 seconds
Started Aug 06 04:28:50 PM PDT 24
Finished Aug 06 04:41:29 PM PDT 24
Peak memory 199700 kb
Host smart-e2d5192b-4ee6-4466-b9a3-69daca808c05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3958210460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3958210460
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.1919058813
Short name T412
Test name
Test status
Simulation time 5881139681 ps
CPU time 9.8 seconds
Started Aug 06 04:28:46 PM PDT 24
Finished Aug 06 04:28:56 PM PDT 24
Peak memory 198648 kb
Host smart-030f9efb-0d64-41db-a251-955528018abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919058813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1919058813
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.4082585245
Short name T658
Test name
Test status
Simulation time 50320523696 ps
CPU time 36.13 seconds
Started Aug 06 04:28:28 PM PDT 24
Finished Aug 06 04:29:04 PM PDT 24
Peak memory 198864 kb
Host smart-59e70acf-dc82-4407-bff3-8d12e34015b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082585245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.4082585245
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.1583604134
Short name T271
Test name
Test status
Simulation time 13794451473 ps
CPU time 187 seconds
Started Aug 06 04:28:46 PM PDT 24
Finished Aug 06 04:31:53 PM PDT 24
Peak memory 199728 kb
Host smart-62fc9a21-5b7f-4b73-ac93-5851e30dd8aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1583604134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1583604134
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2013371868
Short name T1090
Test name
Test status
Simulation time 3994762985 ps
CPU time 33.86 seconds
Started Aug 06 04:28:38 PM PDT 24
Finished Aug 06 04:29:13 PM PDT 24
Peak memory 198728 kb
Host smart-743365fd-3ce7-4c0b-975b-bcc2923e1c69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2013371868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2013371868
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.4189561720
Short name T90
Test name
Test status
Simulation time 15483793706 ps
CPU time 31.54 seconds
Started Aug 06 04:28:48 PM PDT 24
Finished Aug 06 04:29:19 PM PDT 24
Peak memory 199656 kb
Host smart-ed59327c-6503-49e7-970f-218cc9db385f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189561720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.4189561720
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.2428377758
Short name T382
Test name
Test status
Simulation time 1083408447 ps
CPU time 2.48 seconds
Started Aug 06 04:28:43 PM PDT 24
Finished Aug 06 04:28:45 PM PDT 24
Peak memory 195208 kb
Host smart-c0e78f1b-cb30-4aef-86f3-3245b494f560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428377758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2428377758
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1082992045
Short name T480
Test name
Test status
Simulation time 5901274505 ps
CPU time 7.68 seconds
Started Aug 06 04:28:30 PM PDT 24
Finished Aug 06 04:28:38 PM PDT 24
Peak memory 199652 kb
Host smart-36b084c6-2b1b-4997-a405-6199f4338e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082992045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1082992045
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1936362856
Short name T155
Test name
Test status
Simulation time 114496478704 ps
CPU time 114.83 seconds
Started Aug 06 04:28:44 PM PDT 24
Finished Aug 06 04:30:39 PM PDT 24
Peak memory 199756 kb
Host smart-4ed53712-a123-42bc-b703-8757d499b0d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936362856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1936362856
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1114543715
Short name T1119
Test name
Test status
Simulation time 178416147843 ps
CPU time 558.61 seconds
Started Aug 06 04:28:48 PM PDT 24
Finished Aug 06 04:38:07 PM PDT 24
Peak memory 216244 kb
Host smart-1c8d5cb4-f432-4105-847d-2b50e3642151
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114543715 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1114543715
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3140230905
Short name T848
Test name
Test status
Simulation time 1132697173 ps
CPU time 2.04 seconds
Started Aug 06 04:28:41 PM PDT 24
Finished Aug 06 04:28:43 PM PDT 24
Peak memory 198820 kb
Host smart-eae66e35-7b95-472e-b359-8254de4e7341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140230905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3140230905
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1992563224
Short name T542
Test name
Test status
Simulation time 2318061071 ps
CPU time 2.45 seconds
Started Aug 06 04:28:40 PM PDT 24
Finished Aug 06 04:28:43 PM PDT 24
Peak memory 197796 kb
Host smart-01ed4c74-a030-433c-8ed8-d37e0fdf8552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992563224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1992563224
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1258111601
Short name T492
Test name
Test status
Simulation time 217705627804 ps
CPU time 162.58 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:33:23 PM PDT 24
Peak memory 199768 kb
Host smart-3f042a35-fcbf-4e91-b2ab-cd408a1523d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258111601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1258111601
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2436549685
Short name T1151
Test name
Test status
Simulation time 148915813385 ps
CPU time 134.06 seconds
Started Aug 06 04:30:43 PM PDT 24
Finished Aug 06 04:32:57 PM PDT 24
Peak memory 199720 kb
Host smart-93601bcf-0f4a-4fee-8a6f-b019e2b5e527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436549685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2436549685
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2459528612
Short name T185
Test name
Test status
Simulation time 99816189099 ps
CPU time 45.42 seconds
Started Aug 06 04:30:44 PM PDT 24
Finished Aug 06 04:31:30 PM PDT 24
Peak memory 199716 kb
Host smart-ed4fc886-0604-4c6c-89bf-f775a0bac25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459528612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2459528612
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2604334469
Short name T1160
Test name
Test status
Simulation time 97745567123 ps
CPU time 17.93 seconds
Started Aug 06 04:30:43 PM PDT 24
Finished Aug 06 04:31:01 PM PDT 24
Peak memory 199384 kb
Host smart-ab2efd57-1207-4b5b-9530-5199cb6373ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604334469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2604334469
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.592003808
Short name T1126
Test name
Test status
Simulation time 15446593555 ps
CPU time 31.7 seconds
Started Aug 06 04:30:41 PM PDT 24
Finished Aug 06 04:31:13 PM PDT 24
Peak memory 199692 kb
Host smart-7d1472bf-d0fa-41de-a695-acaedcad7b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592003808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.592003808
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1966495557
Short name T193
Test name
Test status
Simulation time 25798171266 ps
CPU time 20.84 seconds
Started Aug 06 04:30:43 PM PDT 24
Finished Aug 06 04:31:03 PM PDT 24
Peak memory 199788 kb
Host smart-766da1b3-181f-4607-a520-d108052d0325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966495557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1966495557
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1830034367
Short name T939
Test name
Test status
Simulation time 137392592581 ps
CPU time 210.33 seconds
Started Aug 06 04:30:39 PM PDT 24
Finished Aug 06 04:34:09 PM PDT 24
Peak memory 199596 kb
Host smart-053b3816-beb8-41d8-b5fc-a9eeaad05651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830034367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1830034367
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.108491208
Short name T817
Test name
Test status
Simulation time 126810333058 ps
CPU time 49.23 seconds
Started Aug 06 04:30:47 PM PDT 24
Finished Aug 06 04:31:36 PM PDT 24
Peak memory 199828 kb
Host smart-9bf58d40-e022-43ef-a26e-d7bf7e963afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108491208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.108491208
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1352948464
Short name T167
Test name
Test status
Simulation time 299156458160 ps
CPU time 28.27 seconds
Started Aug 06 04:30:39 PM PDT 24
Finished Aug 06 04:31:07 PM PDT 24
Peak memory 199668 kb
Host smart-f93bb428-02b1-4f81-ab65-9b8cdcddb57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352948464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1352948464
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2286434785
Short name T768
Test name
Test status
Simulation time 191626731603 ps
CPU time 75.32 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:31:55 PM PDT 24
Peak memory 199676 kb
Host smart-5a92250c-2ded-4701-9657-9e573f8c6014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286434785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2286434785
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2139362032
Short name T816
Test name
Test status
Simulation time 11143677 ps
CPU time 0.55 seconds
Started Aug 06 04:28:43 PM PDT 24
Finished Aug 06 04:28:43 PM PDT 24
Peak memory 195096 kb
Host smart-ab8ec58e-fba2-4d15-b65e-a14192210d4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139362032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2139362032
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3997176761
Short name T258
Test name
Test status
Simulation time 122667441772 ps
CPU time 195.74 seconds
Started Aug 06 04:28:54 PM PDT 24
Finished Aug 06 04:32:10 PM PDT 24
Peak memory 199740 kb
Host smart-04df7dc8-db9c-45d5-b106-eaacf77b9078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997176761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3997176761
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.4177329738
Short name T1008
Test name
Test status
Simulation time 37403951800 ps
CPU time 14.96 seconds
Started Aug 06 04:28:50 PM PDT 24
Finished Aug 06 04:29:05 PM PDT 24
Peak memory 199732 kb
Host smart-e7726003-4df1-488c-a19f-2f507b826506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177329738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.4177329738
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2023804602
Short name T469
Test name
Test status
Simulation time 9771218530 ps
CPU time 2.95 seconds
Started Aug 06 04:28:56 PM PDT 24
Finished Aug 06 04:28:59 PM PDT 24
Peak memory 196860 kb
Host smart-3dc13ea0-056f-497a-90a0-d5be8fa4f220
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023804602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2023804602
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1480586290
Short name T1036
Test name
Test status
Simulation time 96149480426 ps
CPU time 1004.5 seconds
Started Aug 06 04:29:01 PM PDT 24
Finished Aug 06 04:45:46 PM PDT 24
Peak memory 199648 kb
Host smart-04a5671b-5270-4069-84f1-7c82b1ac699b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1480586290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1480586290
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.849231972
Short name T601
Test name
Test status
Simulation time 7960298277 ps
CPU time 13.03 seconds
Started Aug 06 04:28:52 PM PDT 24
Finished Aug 06 04:29:05 PM PDT 24
Peak memory 198368 kb
Host smart-78e0b23b-f4ac-485c-863c-ec76bb21405c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849231972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.849231972
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1229923418
Short name T880
Test name
Test status
Simulation time 60282143122 ps
CPU time 81.33 seconds
Started Aug 06 04:28:46 PM PDT 24
Finished Aug 06 04:30:07 PM PDT 24
Peak memory 198300 kb
Host smart-658011ac-9b51-4e05-a957-2123843afa8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229923418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1229923418
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1373943981
Short name T743
Test name
Test status
Simulation time 14480780528 ps
CPU time 161.94 seconds
Started Aug 06 04:28:44 PM PDT 24
Finished Aug 06 04:31:26 PM PDT 24
Peak memory 199764 kb
Host smart-6cb993c2-3d47-477d-b236-727afe185ae3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1373943981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1373943981
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3177717314
Short name T570
Test name
Test status
Simulation time 2517651285 ps
CPU time 14.94 seconds
Started Aug 06 04:28:57 PM PDT 24
Finished Aug 06 04:29:11 PM PDT 24
Peak memory 198008 kb
Host smart-775b3672-8d7d-4110-8cb8-692b98b61648
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3177717314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3177717314
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.479890619
Short name T384
Test name
Test status
Simulation time 46321548750 ps
CPU time 14.17 seconds
Started Aug 06 04:28:53 PM PDT 24
Finished Aug 06 04:29:07 PM PDT 24
Peak memory 195692 kb
Host smart-935c9b5c-0073-4fef-9c05-dc53a7f7aa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479890619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.479890619
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3456676144
Short name T494
Test name
Test status
Simulation time 509505565 ps
CPU time 1.61 seconds
Started Aug 06 04:28:57 PM PDT 24
Finished Aug 06 04:28:59 PM PDT 24
Peak memory 198032 kb
Host smart-66a8a71b-2133-483e-9bd8-26eb5a606a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456676144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3456676144
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3864427085
Short name T571
Test name
Test status
Simulation time 206615575015 ps
CPU time 486.81 seconds
Started Aug 06 04:28:56 PM PDT 24
Finished Aug 06 04:37:03 PM PDT 24
Peak memory 215864 kb
Host smart-b038b093-087d-42b0-9e44-5aa3eefc71c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864427085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3864427085
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3210515318
Short name T54
Test name
Test status
Simulation time 215677924563 ps
CPU time 308.56 seconds
Started Aug 06 04:28:49 PM PDT 24
Finished Aug 06 04:33:58 PM PDT 24
Peak memory 216244 kb
Host smart-7c7ef1f2-d504-4790-8ad4-95e44e73b719
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210515318 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3210515318
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.213276886
Short name T260
Test name
Test status
Simulation time 1358226470 ps
CPU time 1.49 seconds
Started Aug 06 04:28:55 PM PDT 24
Finished Aug 06 04:28:56 PM PDT 24
Peak memory 197944 kb
Host smart-814010d9-322a-40dc-bdd9-98ac7e576f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213276886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.213276886
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.1216924782
Short name T442
Test name
Test status
Simulation time 76791450135 ps
CPU time 108.04 seconds
Started Aug 06 04:28:54 PM PDT 24
Finished Aug 06 04:30:42 PM PDT 24
Peak memory 199768 kb
Host smart-6b5cd8eb-1259-4b35-a14a-aa5ffc61b77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216924782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1216924782
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.56674773
Short name T1085
Test name
Test status
Simulation time 59257524893 ps
CPU time 30.3 seconds
Started Aug 06 04:30:41 PM PDT 24
Finished Aug 06 04:31:12 PM PDT 24
Peak memory 199720 kb
Host smart-29210fdb-e893-486d-908b-7eb550818b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56674773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.56674773
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2976182909
Short name T200
Test name
Test status
Simulation time 165729815320 ps
CPU time 64.78 seconds
Started Aug 06 04:30:47 PM PDT 24
Finished Aug 06 04:31:52 PM PDT 24
Peak memory 199836 kb
Host smart-643a6c8d-1772-40bf-b70e-e19fc75aa48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976182909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2976182909
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3105995362
Short name T148
Test name
Test status
Simulation time 24053580294 ps
CPU time 38.65 seconds
Started Aug 06 04:30:39 PM PDT 24
Finished Aug 06 04:31:18 PM PDT 24
Peak memory 199696 kb
Host smart-44ae467c-56c1-411c-84f7-83f9e657b549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105995362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3105995362
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.266300571
Short name T172
Test name
Test status
Simulation time 151635123540 ps
CPU time 245.05 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:34:45 PM PDT 24
Peak memory 199760 kb
Host smart-68456d41-e012-4eaf-9504-8d3885ca52c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266300571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.266300571
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.819325486
Short name T552
Test name
Test status
Simulation time 120056148389 ps
CPU time 48.27 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:31:28 PM PDT 24
Peak memory 198940 kb
Host smart-b545bfc9-86ca-42f5-8cd6-1ff1ca46455a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819325486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.819325486
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2458780006
Short name T1099
Test name
Test status
Simulation time 87697283065 ps
CPU time 67.21 seconds
Started Aug 06 04:30:47 PM PDT 24
Finished Aug 06 04:31:54 PM PDT 24
Peak memory 199728 kb
Host smart-7869540c-229a-4ba1-bd0b-de7d30873d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458780006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2458780006
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.69507000
Short name T1149
Test name
Test status
Simulation time 90718962242 ps
CPU time 256.72 seconds
Started Aug 06 04:30:46 PM PDT 24
Finished Aug 06 04:35:02 PM PDT 24
Peak memory 199772 kb
Host smart-1eecf7f3-db25-4b50-825f-3f48aaef6d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69507000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.69507000
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3888539486
Short name T746
Test name
Test status
Simulation time 83729045824 ps
CPU time 130.29 seconds
Started Aug 06 04:30:46 PM PDT 24
Finished Aug 06 04:32:56 PM PDT 24
Peak memory 199764 kb
Host smart-4cee0e49-bf2d-463a-91ce-8bb7d705ee85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888539486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3888539486
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3401513927
Short name T362
Test name
Test status
Simulation time 42691094 ps
CPU time 0.55 seconds
Started Aug 06 04:28:48 PM PDT 24
Finished Aug 06 04:28:48 PM PDT 24
Peak memory 195100 kb
Host smart-d38ace8c-9c1a-4763-9275-ccbca3b1ba4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401513927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3401513927
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2478183223
Short name T1161
Test name
Test status
Simulation time 82829087280 ps
CPU time 55.53 seconds
Started Aug 06 04:28:57 PM PDT 24
Finished Aug 06 04:29:52 PM PDT 24
Peak memory 199712 kb
Host smart-58d5ad7c-ac9a-490e-8b08-7a442ec08796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478183223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2478183223
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1494503894
Short name T578
Test name
Test status
Simulation time 53676831015 ps
CPU time 28.67 seconds
Started Aug 06 04:28:54 PM PDT 24
Finished Aug 06 04:29:22 PM PDT 24
Peak memory 199720 kb
Host smart-9f609f7e-cb85-4b3b-955f-a4faa84396df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494503894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1494503894
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2446027566
Short name T1044
Test name
Test status
Simulation time 138233581945 ps
CPU time 141.53 seconds
Started Aug 06 04:28:53 PM PDT 24
Finished Aug 06 04:31:15 PM PDT 24
Peak memory 199560 kb
Host smart-a42e0c2b-8779-44d4-b6a5-0a630be53190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446027566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2446027566
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3479403114
Short name T473
Test name
Test status
Simulation time 322565322322 ps
CPU time 207.7 seconds
Started Aug 06 04:28:54 PM PDT 24
Finished Aug 06 04:32:22 PM PDT 24
Peak memory 199684 kb
Host smart-3aeb7a90-27c8-4b66-a1b9-fa6cdd69ff55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3479403114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3479403114
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3249469933
Short name T577
Test name
Test status
Simulation time 6489188528 ps
CPU time 3.26 seconds
Started Aug 06 04:29:01 PM PDT 24
Finished Aug 06 04:29:05 PM PDT 24
Peak memory 199660 kb
Host smart-7a6298a9-a21b-4295-bf01-c8a8fead8617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249469933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3249469933
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.3316433649
Short name T342
Test name
Test status
Simulation time 39054046767 ps
CPU time 14.29 seconds
Started Aug 06 04:28:55 PM PDT 24
Finished Aug 06 04:29:09 PM PDT 24
Peak memory 199616 kb
Host smart-fbebe0a2-0224-421e-8ff9-20321a928d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316433649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3316433649
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.514467085
Short name T313
Test name
Test status
Simulation time 26115069123 ps
CPU time 1511.6 seconds
Started Aug 06 04:28:51 PM PDT 24
Finished Aug 06 04:54:03 PM PDT 24
Peak memory 199776 kb
Host smart-6c824544-d79a-4675-abc6-ee934a79f723
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=514467085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.514467085
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.201456565
Short name T1068
Test name
Test status
Simulation time 5405213155 ps
CPU time 10.75 seconds
Started Aug 06 04:28:51 PM PDT 24
Finished Aug 06 04:29:02 PM PDT 24
Peak memory 197632 kb
Host smart-65dc0006-8293-4acf-92e5-7efe8516669b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201456565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.201456565
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.451632248
Short name T126
Test name
Test status
Simulation time 15908495691 ps
CPU time 25.8 seconds
Started Aug 06 04:28:53 PM PDT 24
Finished Aug 06 04:29:19 PM PDT 24
Peak memory 199652 kb
Host smart-644a462c-0d25-4929-bfcd-2fe2aac31b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451632248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.451632248
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.638831736
Short name T517
Test name
Test status
Simulation time 5727034921 ps
CPU time 9.81 seconds
Started Aug 06 04:28:50 PM PDT 24
Finished Aug 06 04:29:00 PM PDT 24
Peak memory 196296 kb
Host smart-d9e745bd-0378-4072-af59-b98384c0ae90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638831736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.638831736
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.307346629
Short name T865
Test name
Test status
Simulation time 270555267 ps
CPU time 1.16 seconds
Started Aug 06 04:28:48 PM PDT 24
Finished Aug 06 04:28:49 PM PDT 24
Peak memory 198152 kb
Host smart-e206f3fa-1e8c-41b2-bfa0-88bab1844052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307346629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.307346629
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.3350517518
Short name T1030
Test name
Test status
Simulation time 148463094719 ps
CPU time 110.17 seconds
Started Aug 06 04:28:51 PM PDT 24
Finished Aug 06 04:30:42 PM PDT 24
Peak memory 199648 kb
Host smart-785c9ab4-646f-455d-9e64-7c20c08098ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350517518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3350517518
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.241746968
Short name T1094
Test name
Test status
Simulation time 189664526729 ps
CPU time 523.22 seconds
Started Aug 06 04:28:47 PM PDT 24
Finished Aug 06 04:37:30 PM PDT 24
Peak memory 225008 kb
Host smart-ad9cc108-2ed0-4530-a6ac-186e22707e57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241746968 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.241746968
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.183232402
Short name T1034
Test name
Test status
Simulation time 2303648362 ps
CPU time 3.41 seconds
Started Aug 06 04:28:46 PM PDT 24
Finished Aug 06 04:28:50 PM PDT 24
Peak memory 199000 kb
Host smart-28c38640-7be4-451b-b48c-2258a422d909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183232402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.183232402
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3995578039
Short name T867
Test name
Test status
Simulation time 75273628194 ps
CPU time 134.9 seconds
Started Aug 06 04:28:53 PM PDT 24
Finished Aug 06 04:31:08 PM PDT 24
Peak memory 199704 kb
Host smart-a7ce9486-60c0-4779-95bc-6d9bfe1946ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995578039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3995578039
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2846900148
Short name T1017
Test name
Test status
Simulation time 13081481362 ps
CPU time 20.17 seconds
Started Aug 06 04:30:39 PM PDT 24
Finished Aug 06 04:31:00 PM PDT 24
Peak memory 199632 kb
Host smart-1e2024e7-868d-46d0-a6cf-6181e0168566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846900148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2846900148
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1984828476
Short name T624
Test name
Test status
Simulation time 110468626934 ps
CPU time 27.98 seconds
Started Aug 06 04:30:46 PM PDT 24
Finished Aug 06 04:31:14 PM PDT 24
Peak memory 199740 kb
Host smart-b5f0c5da-af6b-4253-9545-5db41aec265a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984828476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1984828476
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.735315773
Short name T944
Test name
Test status
Simulation time 61163543316 ps
CPU time 48.89 seconds
Started Aug 06 04:30:46 PM PDT 24
Finished Aug 06 04:31:35 PM PDT 24
Peak memory 199772 kb
Host smart-a728f00b-5ddc-495b-bd4e-2ebc8238602e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735315773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.735315773
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.299837649
Short name T971
Test name
Test status
Simulation time 62414058459 ps
CPU time 101.24 seconds
Started Aug 06 04:30:55 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 199728 kb
Host smart-ae523609-4930-479e-9ab2-853ee4872885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299837649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.299837649
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1579930890
Short name T983
Test name
Test status
Simulation time 9538157768 ps
CPU time 24.3 seconds
Started Aug 06 04:30:56 PM PDT 24
Finished Aug 06 04:31:20 PM PDT 24
Peak memory 199752 kb
Host smart-519b63f9-b43f-4d6f-8aa5-6bf9eae857d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579930890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1579930890
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.4185872444
Short name T224
Test name
Test status
Simulation time 55678725316 ps
CPU time 25.5 seconds
Started Aug 06 04:30:57 PM PDT 24
Finished Aug 06 04:31:22 PM PDT 24
Peak memory 199736 kb
Host smart-fa0310e6-2791-4343-ab25-ade6b8b9da36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185872444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.4185872444
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.705060304
Short name T447
Test name
Test status
Simulation time 51423813 ps
CPU time 0.6 seconds
Started Aug 06 04:28:46 PM PDT 24
Finished Aug 06 04:28:47 PM PDT 24
Peak memory 195028 kb
Host smart-67f6a363-1c0b-41fa-9a0e-db8ea5fa42e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705060304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.705060304
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2259018456
Short name T846
Test name
Test status
Simulation time 22378118319 ps
CPU time 34.86 seconds
Started Aug 06 04:28:50 PM PDT 24
Finished Aug 06 04:29:25 PM PDT 24
Peak memory 199588 kb
Host smart-ae100660-76d4-4602-aebe-b827152c791e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259018456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2259018456
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3354464530
Short name T583
Test name
Test status
Simulation time 35723778218 ps
CPU time 15.02 seconds
Started Aug 06 04:28:58 PM PDT 24
Finished Aug 06 04:29:13 PM PDT 24
Peak memory 199660 kb
Host smart-9c73c001-c93d-42d4-ac37-ca32430eab97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354464530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3354464530
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.4268985857
Short name T50
Test name
Test status
Simulation time 149883309736 ps
CPU time 355.92 seconds
Started Aug 06 04:29:04 PM PDT 24
Finished Aug 06 04:35:00 PM PDT 24
Peak memory 199716 kb
Host smart-ba9dc8a9-ef47-47e0-b2a9-f3dc1779ecee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268985857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.4268985857
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.663282715
Short name T506
Test name
Test status
Simulation time 270849283847 ps
CPU time 514.84 seconds
Started Aug 06 04:28:43 PM PDT 24
Finished Aug 06 04:37:18 PM PDT 24
Peak memory 199396 kb
Host smart-e9ed9682-4cc5-4f1f-812f-f1d0012c928d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663282715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.663282715
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3013290254
Short name T681
Test name
Test status
Simulation time 137215544011 ps
CPU time 631.77 seconds
Started Aug 06 04:28:54 PM PDT 24
Finished Aug 06 04:39:26 PM PDT 24
Peak memory 199784 kb
Host smart-f9e5b55d-9ef9-4f3f-a6fe-b2e94f02edad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3013290254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3013290254
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.3931507148
Short name T1171
Test name
Test status
Simulation time 10530503285 ps
CPU time 6.04 seconds
Started Aug 06 04:28:51 PM PDT 24
Finished Aug 06 04:28:57 PM PDT 24
Peak memory 199688 kb
Host smart-543d6a10-1805-4343-b29f-3061413174fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931507148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3931507148
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3014615161
Short name T540
Test name
Test status
Simulation time 20094951944 ps
CPU time 28.37 seconds
Started Aug 06 04:28:50 PM PDT 24
Finished Aug 06 04:29:19 PM PDT 24
Peak memory 199656 kb
Host smart-43db044b-0f59-4568-bb6a-d441f0d1fc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014615161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3014615161
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.899633515
Short name T446
Test name
Test status
Simulation time 2712202800 ps
CPU time 9.42 seconds
Started Aug 06 04:28:44 PM PDT 24
Finished Aug 06 04:28:53 PM PDT 24
Peak memory 199680 kb
Host smart-c60ed032-b4b7-4f52-bfc5-7c4edbf67d69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=899633515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.899633515
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.4016172193
Short name T903
Test name
Test status
Simulation time 6998351002 ps
CPU time 19.35 seconds
Started Aug 06 04:28:52 PM PDT 24
Finished Aug 06 04:29:12 PM PDT 24
Peak memory 198940 kb
Host smart-ec691691-fde2-4e1e-945d-e931faabd7a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4016172193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.4016172193
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1940072569
Short name T312
Test name
Test status
Simulation time 83764498124 ps
CPU time 94.81 seconds
Started Aug 06 04:29:00 PM PDT 24
Finished Aug 06 04:30:35 PM PDT 24
Peak memory 199740 kb
Host smart-940dc948-a2af-4bda-b47b-f6af1ab823d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940072569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1940072569
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3726673301
Short name T557
Test name
Test status
Simulation time 4295214687 ps
CPU time 7.57 seconds
Started Aug 06 04:28:53 PM PDT 24
Finished Aug 06 04:29:01 PM PDT 24
Peak memory 196280 kb
Host smart-908b53b2-df5d-421e-b51f-e489029729e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726673301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3726673301
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3254569808
Short name T996
Test name
Test status
Simulation time 509793697 ps
CPU time 1.22 seconds
Started Aug 06 04:28:51 PM PDT 24
Finished Aug 06 04:28:52 PM PDT 24
Peak memory 198184 kb
Host smart-cd3ceeed-0345-4763-a2d2-e8bb4359d953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254569808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3254569808
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.4256958773
Short name T682
Test name
Test status
Simulation time 144923010450 ps
CPU time 315.81 seconds
Started Aug 06 04:28:39 PM PDT 24
Finished Aug 06 04:33:55 PM PDT 24
Peak memory 199868 kb
Host smart-fa1845f1-d038-407e-bb56-5b183036f665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256958773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.4256958773
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1887049794
Short name T135
Test name
Test status
Simulation time 64750147481 ps
CPU time 298.84 seconds
Started Aug 06 04:28:53 PM PDT 24
Finished Aug 06 04:33:52 PM PDT 24
Peak memory 216204 kb
Host smart-058302f8-67c4-4f3a-8d6a-e91cc6fbcc31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887049794 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1887049794
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1890503310
Short name T647
Test name
Test status
Simulation time 1078753191 ps
CPU time 1.95 seconds
Started Aug 06 04:28:48 PM PDT 24
Finished Aug 06 04:28:50 PM PDT 24
Peak memory 198248 kb
Host smart-2f297c08-8184-4ffc-8782-117528ad2313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890503310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1890503310
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.491340528
Short name T976
Test name
Test status
Simulation time 53529892538 ps
CPU time 22.9 seconds
Started Aug 06 04:28:48 PM PDT 24
Finished Aug 06 04:29:11 PM PDT 24
Peak memory 199752 kb
Host smart-7b357f00-078e-4f46-a823-23f0622cdd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491340528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.491340528
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2518661480
Short name T197
Test name
Test status
Simulation time 140118193616 ps
CPU time 59.32 seconds
Started Aug 06 04:30:57 PM PDT 24
Finished Aug 06 04:31:56 PM PDT 24
Peak memory 199704 kb
Host smart-737ff553-312a-4470-a32d-6be02c2695e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518661480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2518661480
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.654866034
Short name T278
Test name
Test status
Simulation time 69321769411 ps
CPU time 134.18 seconds
Started Aug 06 04:30:58 PM PDT 24
Finished Aug 06 04:33:12 PM PDT 24
Peak memory 199640 kb
Host smart-6ba24f46-8436-4317-ba91-242c2af132e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654866034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.654866034
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3057090056
Short name T749
Test name
Test status
Simulation time 32167691016 ps
CPU time 85.12 seconds
Started Aug 06 04:31:02 PM PDT 24
Finished Aug 06 04:32:27 PM PDT 24
Peak memory 199644 kb
Host smart-4dd97e41-5734-4ae9-b699-26bbf84ec740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057090056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3057090056
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1615457699
Short name T203
Test name
Test status
Simulation time 254084796594 ps
CPU time 107.21 seconds
Started Aug 06 04:30:58 PM PDT 24
Finished Aug 06 04:32:45 PM PDT 24
Peak memory 199692 kb
Host smart-15af5ced-401b-420c-8ffb-f1d7155aac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615457699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1615457699
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2725514715
Short name T309
Test name
Test status
Simulation time 142663703148 ps
CPU time 672.59 seconds
Started Aug 06 04:30:59 PM PDT 24
Finished Aug 06 04:42:11 PM PDT 24
Peak memory 199712 kb
Host smart-43716170-3c65-42be-9eac-ea76277a37f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725514715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2725514715
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3547807020
Short name T1101
Test name
Test status
Simulation time 33003562128 ps
CPU time 18.19 seconds
Started Aug 06 04:30:57 PM PDT 24
Finished Aug 06 04:31:15 PM PDT 24
Peak memory 199780 kb
Host smart-ba060961-8888-4b7a-ba0c-50c3591e36d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547807020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3547807020
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.5249218
Short name T1174
Test name
Test status
Simulation time 255329587192 ps
CPU time 131.03 seconds
Started Aug 06 04:31:50 PM PDT 24
Finished Aug 06 04:34:01 PM PDT 24
Peak memory 199524 kb
Host smart-bb97a81f-1be5-48c3-aaca-483fe7557d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5249218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.5249218
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3121845436
Short name T1096
Test name
Test status
Simulation time 137611552104 ps
CPU time 48.48 seconds
Started Aug 06 04:30:56 PM PDT 24
Finished Aug 06 04:31:45 PM PDT 24
Peak memory 199536 kb
Host smart-422fbaf5-ed62-4a43-99f1-040b175f70de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121845436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3121845436
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.4275218697
Short name T201
Test name
Test status
Simulation time 115094336903 ps
CPU time 164.94 seconds
Started Aug 06 04:30:58 PM PDT 24
Finished Aug 06 04:33:43 PM PDT 24
Peak memory 199776 kb
Host smart-5d7363c3-1b55-49bf-8193-01af13563fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275218697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.4275218697
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.814548269
Short name T1088
Test name
Test status
Simulation time 182713690 ps
CPU time 0.57 seconds
Started Aug 06 04:28:52 PM PDT 24
Finished Aug 06 04:28:52 PM PDT 24
Peak memory 195072 kb
Host smart-6095e7d0-787d-40b1-bd3e-f6ea78560523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814548269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.814548269
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2548932713
Short name T969
Test name
Test status
Simulation time 287653511208 ps
CPU time 359.86 seconds
Started Aug 06 04:28:54 PM PDT 24
Finished Aug 06 04:34:54 PM PDT 24
Peak memory 199552 kb
Host smart-e6436d79-09bf-4087-b947-1a5817dd59dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548932713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2548932713
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.404427000
Short name T116
Test name
Test status
Simulation time 32392605849 ps
CPU time 18.87 seconds
Started Aug 06 04:28:52 PM PDT 24
Finished Aug 06 04:29:11 PM PDT 24
Peak memory 199804 kb
Host smart-3a85c008-a2bb-4a61-bce7-dd3334fea4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404427000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.404427000
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1113114825
Short name T892
Test name
Test status
Simulation time 121431196244 ps
CPU time 33.38 seconds
Started Aug 06 04:28:54 PM PDT 24
Finished Aug 06 04:29:27 PM PDT 24
Peak memory 199668 kb
Host smart-3e80ca0d-358c-4a2f-a5b0-2cbe39d5a9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113114825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1113114825
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.406597802
Short name T409
Test name
Test status
Simulation time 19190742309 ps
CPU time 7.69 seconds
Started Aug 06 04:28:51 PM PDT 24
Finished Aug 06 04:28:59 PM PDT 24
Peak memory 198196 kb
Host smart-1410d399-534f-4810-a732-93b9e8432ab5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406597802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.406597802
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2335529929
Short name T88
Test name
Test status
Simulation time 89625401919 ps
CPU time 239.11 seconds
Started Aug 06 04:28:54 PM PDT 24
Finished Aug 06 04:32:53 PM PDT 24
Peak memory 199660 kb
Host smart-1605ec63-1582-4ccd-8eb8-d4ad6942e612
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2335529929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2335529929
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2510312329
Short name T338
Test name
Test status
Simulation time 2420154571 ps
CPU time 2.66 seconds
Started Aug 06 04:29:01 PM PDT 24
Finished Aug 06 04:29:04 PM PDT 24
Peak memory 195504 kb
Host smart-d0b61a1d-34d0-419c-8973-bf410779972c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510312329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2510312329
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.197974780
Short name T482
Test name
Test status
Simulation time 5583699248 ps
CPU time 8.83 seconds
Started Aug 06 04:28:51 PM PDT 24
Finished Aug 06 04:29:00 PM PDT 24
Peak memory 195844 kb
Host smart-c6a53fcd-b8bd-4ed3-96bc-fc82dbb7e0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197974780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.197974780
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2750270847
Short name T37
Test name
Test status
Simulation time 18471014022 ps
CPU time 97.07 seconds
Started Aug 06 04:28:48 PM PDT 24
Finished Aug 06 04:30:25 PM PDT 24
Peak memory 199660 kb
Host smart-03d02b25-e52a-4f60-9084-6af7cbb3ec32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2750270847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2750270847
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2733977868
Short name T802
Test name
Test status
Simulation time 5646635835 ps
CPU time 48.92 seconds
Started Aug 06 04:28:54 PM PDT 24
Finished Aug 06 04:29:44 PM PDT 24
Peak memory 197876 kb
Host smart-7aec7257-65cc-4a12-81e4-b27d610c27ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2733977868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2733977868
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.3820684332
Short name T1001
Test name
Test status
Simulation time 45101934265 ps
CPU time 19.41 seconds
Started Aug 06 04:28:51 PM PDT 24
Finished Aug 06 04:29:11 PM PDT 24
Peak memory 199468 kb
Host smart-8166a053-39ab-4a15-bf12-4a0b1a3c35ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820684332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3820684332
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.876606256
Short name T796
Test name
Test status
Simulation time 1256495619 ps
CPU time 1.25 seconds
Started Aug 06 04:28:56 PM PDT 24
Finished Aug 06 04:28:57 PM PDT 24
Peak memory 195396 kb
Host smart-dd3064e8-f22b-4ce1-a98d-57ff001e3508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876606256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.876606256
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1682374991
Short name T546
Test name
Test status
Simulation time 127965483 ps
CPU time 0.73 seconds
Started Aug 06 04:29:02 PM PDT 24
Finished Aug 06 04:29:03 PM PDT 24
Peak memory 196916 kb
Host smart-17fd0682-2fe3-4e60-ab25-ca30df34388c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682374991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1682374991
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3855484134
Short name T555
Test name
Test status
Simulation time 73926260567 ps
CPU time 110.52 seconds
Started Aug 06 04:28:50 PM PDT 24
Finished Aug 06 04:30:40 PM PDT 24
Peak memory 199728 kb
Host smart-120db134-4aaf-4202-a780-50a87de8b4e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855484134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3855484134
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.873914387
Short name T31
Test name
Test status
Simulation time 69447489305 ps
CPU time 132.64 seconds
Started Aug 06 04:28:52 PM PDT 24
Finished Aug 06 04:31:05 PM PDT 24
Peak memory 208032 kb
Host smart-02ccf16c-80ba-4a16-bc2f-7b0bfb8d4a26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873914387 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.873914387
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.996402198
Short name T980
Test name
Test status
Simulation time 601845521 ps
CPU time 2.39 seconds
Started Aug 06 04:28:49 PM PDT 24
Finished Aug 06 04:28:51 PM PDT 24
Peak memory 198448 kb
Host smart-d683f10d-ff63-4a53-a176-eb2453ac7ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996402198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.996402198
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2532302031
Short name T314
Test name
Test status
Simulation time 17094832755 ps
CPU time 8.22 seconds
Started Aug 06 04:28:50 PM PDT 24
Finished Aug 06 04:28:58 PM PDT 24
Peak memory 199736 kb
Host smart-bebe2ce9-6e14-408e-afd8-21a549f8babc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532302031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2532302031
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1011393207
Short name T242
Test name
Test status
Simulation time 22620857802 ps
CPU time 35.76 seconds
Started Aug 06 04:31:49 PM PDT 24
Finished Aug 06 04:32:25 PM PDT 24
Peak memory 199528 kb
Host smart-aa0c87ef-e579-4fe9-8255-1aca0227274b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011393207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1011393207
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.150785008
Short name T972
Test name
Test status
Simulation time 167156039601 ps
CPU time 252.4 seconds
Started Aug 06 04:30:57 PM PDT 24
Finished Aug 06 04:35:10 PM PDT 24
Peak memory 199748 kb
Host smart-c62dc1cc-fad7-435d-bf8b-cb2a78cefffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150785008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.150785008
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.303677304
Short name T464
Test name
Test status
Simulation time 23592785564 ps
CPU time 52.51 seconds
Started Aug 06 04:30:56 PM PDT 24
Finished Aug 06 04:31:49 PM PDT 24
Peak memory 199712 kb
Host smart-78fd8e47-d3ed-4b3a-bd2a-4119ed59c941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303677304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.303677304
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1084470533
Short name T124
Test name
Test status
Simulation time 25311870939 ps
CPU time 9.18 seconds
Started Aug 06 04:32:11 PM PDT 24
Finished Aug 06 04:32:20 PM PDT 24
Peak memory 198996 kb
Host smart-380d0940-a3be-46f3-937d-83f6840d0ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084470533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1084470533
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3405030096
Short name T184
Test name
Test status
Simulation time 27027671249 ps
CPU time 40.37 seconds
Started Aug 06 04:31:01 PM PDT 24
Finished Aug 06 04:31:41 PM PDT 24
Peak memory 199716 kb
Host smart-de2a0a57-2814-4e57-9581-f6ed70ba434a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405030096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3405030096
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1460782785
Short name T1165
Test name
Test status
Simulation time 79888373853 ps
CPU time 29.18 seconds
Started Aug 06 04:32:26 PM PDT 24
Finished Aug 06 04:32:55 PM PDT 24
Peak memory 199692 kb
Host smart-98edafe6-2562-4108-8c9c-ce301379e8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460782785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1460782785
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3723040899
Short name T851
Test name
Test status
Simulation time 95265867506 ps
CPU time 43.39 seconds
Started Aug 06 04:32:11 PM PDT 24
Finished Aug 06 04:32:55 PM PDT 24
Peak memory 197768 kb
Host smart-f866545a-d170-4e29-abb2-2f3722cc1106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723040899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3723040899
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1565394430
Short name T1162
Test name
Test status
Simulation time 436287547143 ps
CPU time 39.83 seconds
Started Aug 06 04:30:57 PM PDT 24
Finished Aug 06 04:31:37 PM PDT 24
Peak memory 199720 kb
Host smart-1f7385ee-8ba4-4188-b210-863d5528401d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565394430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1565394430
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1793678453
Short name T183
Test name
Test status
Simulation time 286539609268 ps
CPU time 41.42 seconds
Started Aug 06 04:30:58 PM PDT 24
Finished Aug 06 04:31:39 PM PDT 24
Peak memory 199772 kb
Host smart-645d440d-bde8-4360-872c-37af0ea2f335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793678453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1793678453
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2610950098
Short name T428
Test name
Test status
Simulation time 100320281051 ps
CPU time 170.21 seconds
Started Aug 06 04:30:57 PM PDT 24
Finished Aug 06 04:33:47 PM PDT 24
Peak memory 199532 kb
Host smart-ea10efd3-6b3a-46f2-b3d9-b31f07a74713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610950098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2610950098
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.3892691637
Short name T1013
Test name
Test status
Simulation time 26781497 ps
CPU time 0.54 seconds
Started Aug 06 04:29:05 PM PDT 24
Finished Aug 06 04:29:05 PM PDT 24
Peak memory 195072 kb
Host smart-2eda2985-830e-452a-8630-ca75d6df189d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892691637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3892691637
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.39734896
Short name T1121
Test name
Test status
Simulation time 35396940658 ps
CPU time 13.7 seconds
Started Aug 06 04:28:43 PM PDT 24
Finished Aug 06 04:28:57 PM PDT 24
Peak memory 199716 kb
Host smart-d445bb3b-6d06-40ac-9f6d-e37cd09104bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39734896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.39734896
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3110604374
Short name T340
Test name
Test status
Simulation time 17011255281 ps
CPU time 31.93 seconds
Started Aug 06 04:29:04 PM PDT 24
Finished Aug 06 04:29:36 PM PDT 24
Peak memory 199740 kb
Host smart-502a00c8-d972-4573-b148-85c14913f514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110604374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3110604374
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3793149343
Short name T828
Test name
Test status
Simulation time 201638089674 ps
CPU time 269.42 seconds
Started Aug 06 04:28:54 PM PDT 24
Finished Aug 06 04:33:24 PM PDT 24
Peak memory 199640 kb
Host smart-ec0cf54c-674e-41b5-96aa-b664a9a84235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793149343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3793149343
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.4289467082
Short name T562
Test name
Test status
Simulation time 208549841232 ps
CPU time 156.84 seconds
Started Aug 06 04:28:50 PM PDT 24
Finished Aug 06 04:31:27 PM PDT 24
Peak memory 197752 kb
Host smart-27718d0a-4c70-4d28-a77b-2a1651985c2b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289467082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.4289467082
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2444023748
Short name T285
Test name
Test status
Simulation time 82755137680 ps
CPU time 397.86 seconds
Started Aug 06 04:28:58 PM PDT 24
Finished Aug 06 04:35:36 PM PDT 24
Peak memory 199744 kb
Host smart-b33c5ffe-138f-4ead-adf5-440e15b62271
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2444023748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2444023748
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3126792131
Short name T908
Test name
Test status
Simulation time 6624660417 ps
CPU time 7.09 seconds
Started Aug 06 04:28:53 PM PDT 24
Finished Aug 06 04:29:00 PM PDT 24
Peak memory 199736 kb
Host smart-7965939e-0fba-4571-89fc-1c9be6dc5d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126792131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3126792131
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2644803330
Short name T657
Test name
Test status
Simulation time 6286372951 ps
CPU time 12.82 seconds
Started Aug 06 04:28:54 PM PDT 24
Finished Aug 06 04:29:06 PM PDT 24
Peak memory 199852 kb
Host smart-a6daf21a-5fbf-4014-b624-ee347db82911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644803330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2644803330
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1198805452
Short name T299
Test name
Test status
Simulation time 13217182002 ps
CPU time 315.81 seconds
Started Aug 06 04:28:52 PM PDT 24
Finished Aug 06 04:34:08 PM PDT 24
Peak memory 199704 kb
Host smart-94e9c17d-50e7-4ab0-bcd2-d127d7ffe0ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1198805452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1198805452
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3596831495
Short name T544
Test name
Test status
Simulation time 1587232174 ps
CPU time 5.64 seconds
Started Aug 06 04:28:43 PM PDT 24
Finished Aug 06 04:28:49 PM PDT 24
Peak memory 198236 kb
Host smart-429def82-2466-434b-be6c-4bfc157bde69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3596831495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3596831495
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.900495683
Short name T936
Test name
Test status
Simulation time 42548063934 ps
CPU time 20 seconds
Started Aug 06 04:28:48 PM PDT 24
Finished Aug 06 04:29:08 PM PDT 24
Peak memory 199804 kb
Host smart-18d0b45d-6d99-441a-aa7f-dc6e0046caa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900495683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.900495683
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3278318111
Short name T844
Test name
Test status
Simulation time 3737563432 ps
CPU time 6.7 seconds
Started Aug 06 04:28:56 PM PDT 24
Finished Aug 06 04:29:03 PM PDT 24
Peak memory 196748 kb
Host smart-bbc01450-acfd-44bd-9fca-39322c132506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278318111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3278318111
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3124500855
Short name T463
Test name
Test status
Simulation time 6174198452 ps
CPU time 9.49 seconds
Started Aug 06 04:28:44 PM PDT 24
Finished Aug 06 04:28:54 PM PDT 24
Peak memory 199628 kb
Host smart-e24df2f2-88e7-4108-a66b-ddd25f27fbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124500855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3124500855
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.782004707
Short name T1105
Test name
Test status
Simulation time 181796572516 ps
CPU time 1069.03 seconds
Started Aug 06 04:28:51 PM PDT 24
Finished Aug 06 04:46:40 PM PDT 24
Peak memory 208088 kb
Host smart-d6c27cd0-703b-41a1-92e5-14145e49fd21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782004707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.782004707
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.3427379306
Short name T910
Test name
Test status
Simulation time 202848159434 ps
CPU time 1008.04 seconds
Started Aug 06 04:28:51 PM PDT 24
Finished Aug 06 04:45:40 PM PDT 24
Peak memory 224564 kb
Host smart-b1b478af-a81b-4df6-b503-c241bb3379c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427379306 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3427379306
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1483023645
Short name T717
Test name
Test status
Simulation time 6654649934 ps
CPU time 24.04 seconds
Started Aug 06 04:28:52 PM PDT 24
Finished Aug 06 04:29:16 PM PDT 24
Peak memory 199096 kb
Host smart-f88ec180-29f5-4fba-ae42-2d17f8781405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483023645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1483023645
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2308096143
Short name T724
Test name
Test status
Simulation time 87896988184 ps
CPU time 16.72 seconds
Started Aug 06 04:28:53 PM PDT 24
Finished Aug 06 04:29:10 PM PDT 24
Peak memory 199668 kb
Host smart-bea90323-022c-4ef9-b763-eeac6b38320e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308096143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2308096143
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1748139255
Short name T12
Test name
Test status
Simulation time 81035329753 ps
CPU time 34.09 seconds
Started Aug 06 04:30:58 PM PDT 24
Finished Aug 06 04:31:32 PM PDT 24
Peak memory 199676 kb
Host smart-a2796bc4-744d-41fe-9e37-06af8846f0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748139255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1748139255
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1318610313
Short name T284
Test name
Test status
Simulation time 22632873224 ps
CPU time 23.2 seconds
Started Aug 06 04:32:27 PM PDT 24
Finished Aug 06 04:32:50 PM PDT 24
Peak memory 199692 kb
Host smart-be369c57-d067-49fd-a6cc-9c880387f1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318610313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1318610313
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1895096883
Short name T631
Test name
Test status
Simulation time 71414996352 ps
CPU time 29.33 seconds
Started Aug 06 04:31:00 PM PDT 24
Finished Aug 06 04:31:30 PM PDT 24
Peak memory 199720 kb
Host smart-4483a958-69fc-4c9a-a28d-28ea189e879c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895096883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1895096883
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.348863419
Short name T91
Test name
Test status
Simulation time 29184058590 ps
CPU time 22.27 seconds
Started Aug 06 04:30:59 PM PDT 24
Finished Aug 06 04:31:21 PM PDT 24
Peak memory 199700 kb
Host smart-04538b0a-a87f-48a3-b18a-b6b1fec41cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348863419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.348863419
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3265009911
Short name T10
Test name
Test status
Simulation time 39754890163 ps
CPU time 30.78 seconds
Started Aug 06 04:31:01 PM PDT 24
Finished Aug 06 04:31:32 PM PDT 24
Peak memory 199792 kb
Host smart-dbba7364-21e8-4e9b-a1b7-0013e20b2011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265009911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3265009911
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.4136947791
Short name T214
Test name
Test status
Simulation time 23168419168 ps
CPU time 34.19 seconds
Started Aug 06 04:31:00 PM PDT 24
Finished Aug 06 04:31:34 PM PDT 24
Peak memory 199724 kb
Host smart-2a3fe12b-7079-4c11-b547-4e5aef3e3c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136947791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.4136947791
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.2183010920
Short name T1011
Test name
Test status
Simulation time 37680779237 ps
CPU time 20.55 seconds
Started Aug 06 04:31:02 PM PDT 24
Finished Aug 06 04:31:23 PM PDT 24
Peak memory 199688 kb
Host smart-ce5645c3-7667-45de-8c79-84707644a235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183010920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2183010920
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.450121968
Short name T441
Test name
Test status
Simulation time 37593086425 ps
CPU time 19.78 seconds
Started Aug 06 04:30:54 PM PDT 24
Finished Aug 06 04:31:14 PM PDT 24
Peak memory 199676 kb
Host smart-d42f696e-456d-4f89-93d9-82c55af83dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450121968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.450121968
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2570380272
Short name T1
Test name
Test status
Simulation time 19218301 ps
CPU time 0.57 seconds
Started Aug 06 04:28:05 PM PDT 24
Finished Aug 06 04:28:05 PM PDT 24
Peak memory 195104 kb
Host smart-0b8894ce-17d4-489a-87af-d9119624d35b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570380272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2570380272
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.995999370
Short name T420
Test name
Test status
Simulation time 124151262637 ps
CPU time 197.88 seconds
Started Aug 06 04:28:04 PM PDT 24
Finished Aug 06 04:31:22 PM PDT 24
Peak memory 199668 kb
Host smart-aa59bb27-738b-4c46-b5a4-c25728092648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995999370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.995999370
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3614016675
Short name T758
Test name
Test status
Simulation time 35689532368 ps
CPU time 52.69 seconds
Started Aug 06 04:28:11 PM PDT 24
Finished Aug 06 04:29:03 PM PDT 24
Peak memory 199684 kb
Host smart-ed2f1dc1-f423-44ef-b40c-1dee13aee0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614016675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3614016675
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2357851344
Short name T940
Test name
Test status
Simulation time 102121917563 ps
CPU time 40.11 seconds
Started Aug 06 04:28:04 PM PDT 24
Finished Aug 06 04:28:44 PM PDT 24
Peak memory 199516 kb
Host smart-4d03bcdf-7277-48fc-9cdf-fe35bd21747e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357851344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2357851344
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.95848364
Short name T592
Test name
Test status
Simulation time 5490887033 ps
CPU time 4.68 seconds
Started Aug 06 04:28:12 PM PDT 24
Finished Aug 06 04:28:17 PM PDT 24
Peak memory 196240 kb
Host smart-249ca9f0-1c0a-4db6-af0c-42b4c2701358
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95848364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.95848364
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3241307327
Short name T274
Test name
Test status
Simulation time 113866259073 ps
CPU time 1037.09 seconds
Started Aug 06 04:28:04 PM PDT 24
Finished Aug 06 04:45:21 PM PDT 24
Peak memory 199732 kb
Host smart-069155a1-ea05-4b08-8044-0620a23e43f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3241307327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3241307327
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2479823286
Short name T394
Test name
Test status
Simulation time 5008261619 ps
CPU time 6.34 seconds
Started Aug 06 04:28:05 PM PDT 24
Finished Aug 06 04:28:11 PM PDT 24
Peak memory 199736 kb
Host smart-33dd1111-c8de-4248-8fde-5ae4d257e360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479823286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2479823286
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.881840786
Short name T423
Test name
Test status
Simulation time 19899935545 ps
CPU time 16.02 seconds
Started Aug 06 04:28:12 PM PDT 24
Finished Aug 06 04:28:33 PM PDT 24
Peak memory 199744 kb
Host smart-ed0fd7de-a56b-4f8d-bae5-4119192be152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881840786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.881840786
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3498645114
Short name T587
Test name
Test status
Simulation time 16459459345 ps
CPU time 233.98 seconds
Started Aug 06 04:28:12 PM PDT 24
Finished Aug 06 04:32:06 PM PDT 24
Peak memory 199612 kb
Host smart-809a2a01-b19d-4010-9b3a-ee1d13600527
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3498645114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3498645114
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1512783038
Short name T1127
Test name
Test status
Simulation time 2925564252 ps
CPU time 11.64 seconds
Started Aug 06 04:28:08 PM PDT 24
Finished Aug 06 04:28:20 PM PDT 24
Peak memory 198236 kb
Host smart-22855307-9fc8-41e7-aca0-2799e61b86ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1512783038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1512783038
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.2674000519
Short name T712
Test name
Test status
Simulation time 29774321661 ps
CPU time 17.88 seconds
Started Aug 06 04:28:04 PM PDT 24
Finished Aug 06 04:28:22 PM PDT 24
Peak memory 199496 kb
Host smart-4dde02ca-0362-4747-b256-e55e642fa11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674000519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2674000519
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2379014906
Short name T391
Test name
Test status
Simulation time 1565417741 ps
CPU time 2.92 seconds
Started Aug 06 04:28:07 PM PDT 24
Finished Aug 06 04:28:10 PM PDT 24
Peak memory 195212 kb
Host smart-5163e802-79d5-4fc6-a28d-b54088cc8088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379014906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2379014906
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2990941223
Short name T87
Test name
Test status
Simulation time 243470129 ps
CPU time 0.79 seconds
Started Aug 06 04:28:10 PM PDT 24
Finished Aug 06 04:28:11 PM PDT 24
Peak memory 218036 kb
Host smart-1f128497-6d0d-414d-8d1b-9ca8678b126e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990941223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2990941223
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1642171133
Short name T701
Test name
Test status
Simulation time 109527746 ps
CPU time 0.82 seconds
Started Aug 06 04:28:00 PM PDT 24
Finished Aug 06 04:28:01 PM PDT 24
Peak memory 196796 kb
Host smart-d1989627-1ebc-4dbd-9d7c-045eaad0b384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642171133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1642171133
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2966596496
Short name T1065
Test name
Test status
Simulation time 6846099796 ps
CPU time 2.08 seconds
Started Aug 06 04:28:11 PM PDT 24
Finished Aug 06 04:28:13 PM PDT 24
Peak memory 199636 kb
Host smart-cbbd8001-e7af-44b8-970c-392dddc66419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966596496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2966596496
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1117146422
Short name T497
Test name
Test status
Simulation time 42329539053 ps
CPU time 21.91 seconds
Started Aug 06 04:28:08 PM PDT 24
Finished Aug 06 04:28:30 PM PDT 24
Peak memory 199740 kb
Host smart-7c6f50ab-8191-490d-ae13-86f684304282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117146422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1117146422
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1035246632
Short name T665
Test name
Test status
Simulation time 14986595 ps
CPU time 0.57 seconds
Started Aug 06 04:28:55 PM PDT 24
Finished Aug 06 04:28:56 PM PDT 24
Peak memory 195080 kb
Host smart-e3500874-d694-4f45-9dc0-a630d8abce34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035246632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1035246632
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.989694163
Short name T468
Test name
Test status
Simulation time 72204843933 ps
CPU time 128.3 seconds
Started Aug 06 04:28:54 PM PDT 24
Finished Aug 06 04:31:02 PM PDT 24
Peak memory 199700 kb
Host smart-b3cd6e4a-2347-4a91-85fe-70f795232bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989694163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.989694163
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2480362198
Short name T1104
Test name
Test status
Simulation time 75763830109 ps
CPU time 81.49 seconds
Started Aug 06 04:28:56 PM PDT 24
Finished Aug 06 04:30:18 PM PDT 24
Peak memory 199768 kb
Host smart-38acf978-2b11-4376-b42c-c65e08d3fcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480362198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2480362198
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.515408370
Short name T576
Test name
Test status
Simulation time 112135684300 ps
CPU time 24.24 seconds
Started Aug 06 04:28:55 PM PDT 24
Finished Aug 06 04:29:20 PM PDT 24
Peak memory 199748 kb
Host smart-fbdb4f16-b913-4d72-b183-1c33310b0916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515408370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.515408370
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.2166857956
Short name T700
Test name
Test status
Simulation time 26019811793 ps
CPU time 40.31 seconds
Started Aug 06 04:28:42 PM PDT 24
Finished Aug 06 04:29:23 PM PDT 24
Peak memory 199724 kb
Host smart-45cccfb3-0f9c-49d2-b956-f80d201d02c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166857956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2166857956
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1600890199
Short name T852
Test name
Test status
Simulation time 155292638155 ps
CPU time 1174.15 seconds
Started Aug 06 04:28:51 PM PDT 24
Finished Aug 06 04:48:25 PM PDT 24
Peak memory 199588 kb
Host smart-c4275488-2869-438a-84cc-4bbd2a20369a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1600890199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1600890199
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3591446372
Short name T366
Test name
Test status
Simulation time 5364080091 ps
CPU time 3.34 seconds
Started Aug 06 04:28:52 PM PDT 24
Finished Aug 06 04:28:56 PM PDT 24
Peak memory 198368 kb
Host smart-730da223-7ece-41ca-9a0d-917b71edd293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591446372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3591446372
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.1976804905
Short name T365
Test name
Test status
Simulation time 52663263260 ps
CPU time 14.47 seconds
Started Aug 06 04:28:56 PM PDT 24
Finished Aug 06 04:29:10 PM PDT 24
Peak memory 195656 kb
Host smart-445d1480-539f-4dce-a3ea-29a0467aaf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976804905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1976804905
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.2983619936
Short name T529
Test name
Test status
Simulation time 13453178602 ps
CPU time 713.74 seconds
Started Aug 06 04:28:52 PM PDT 24
Finished Aug 06 04:40:46 PM PDT 24
Peak memory 199648 kb
Host smart-3d1015a9-cff3-4553-b793-9a51de976997
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2983619936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2983619936
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2651341441
Short name T841
Test name
Test status
Simulation time 3961350049 ps
CPU time 27.92 seconds
Started Aug 06 04:28:52 PM PDT 24
Finished Aug 06 04:29:21 PM PDT 24
Peak memory 198320 kb
Host smart-3e6ca4bc-2796-456a-b0a6-9308a8ca8091
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2651341441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2651341441
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2848118198
Short name T774
Test name
Test status
Simulation time 77035812927 ps
CPU time 82.89 seconds
Started Aug 06 04:28:51 PM PDT 24
Finished Aug 06 04:30:14 PM PDT 24
Peak memory 199588 kb
Host smart-7af0f6f9-8794-4252-ba4c-144d0c11465a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848118198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2848118198
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3543180357
Short name T688
Test name
Test status
Simulation time 3284860364 ps
CPU time 3.31 seconds
Started Aug 06 04:28:51 PM PDT 24
Finished Aug 06 04:28:54 PM PDT 24
Peak memory 196136 kb
Host smart-07d29586-9f32-4a65-9f1f-74eeb5057891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543180357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3543180357
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2525214328
Short name T452
Test name
Test status
Simulation time 427895180 ps
CPU time 2.13 seconds
Started Aug 06 04:28:54 PM PDT 24
Finished Aug 06 04:28:56 PM PDT 24
Peak memory 199420 kb
Host smart-e02c2e96-4975-4d14-973f-83230e4ac1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525214328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2525214328
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2729160952
Short name T676
Test name
Test status
Simulation time 1875657775 ps
CPU time 1.74 seconds
Started Aug 06 04:28:47 PM PDT 24
Finished Aug 06 04:28:49 PM PDT 24
Peak memory 198156 kb
Host smart-b57c984e-4123-4e7a-b206-c8b054420dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729160952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2729160952
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1982529510
Short name T662
Test name
Test status
Simulation time 178733033074 ps
CPU time 95.22 seconds
Started Aug 06 04:28:54 PM PDT 24
Finished Aug 06 04:30:30 PM PDT 24
Peak memory 199784 kb
Host smart-7661b653-e3ad-4388-bb2e-754c0e5aef6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982529510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1982529510
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.4189772829
Short name T1112
Test name
Test status
Simulation time 109163597105 ps
CPU time 36.39 seconds
Started Aug 06 04:30:59 PM PDT 24
Finished Aug 06 04:31:36 PM PDT 24
Peak memory 199708 kb
Host smart-24984437-f328-4dc6-ac3c-3ae24c1a20f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189772829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.4189772829
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1514851050
Short name T186
Test name
Test status
Simulation time 30717128504 ps
CPU time 44.33 seconds
Started Aug 06 04:30:57 PM PDT 24
Finished Aug 06 04:31:41 PM PDT 24
Peak memory 199692 kb
Host smart-8b603e8a-5f5b-4a7e-94e4-3d143bd8c3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514851050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1514851050
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3511561476
Short name T659
Test name
Test status
Simulation time 18309431305 ps
CPU time 13.56 seconds
Started Aug 06 04:32:26 PM PDT 24
Finished Aug 06 04:32:40 PM PDT 24
Peak memory 199632 kb
Host smart-e40acf65-c933-4998-a07d-40192467cedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511561476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3511561476
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1285937210
Short name T1006
Test name
Test status
Simulation time 52690471835 ps
CPU time 21.45 seconds
Started Aug 06 04:31:00 PM PDT 24
Finished Aug 06 04:31:21 PM PDT 24
Peak memory 199724 kb
Host smart-e5bb18dd-f826-4634-ab3f-fe7c1509f57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285937210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1285937210
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3565344185
Short name T400
Test name
Test status
Simulation time 57629857660 ps
CPU time 19.03 seconds
Started Aug 06 04:30:58 PM PDT 24
Finished Aug 06 04:31:17 PM PDT 24
Peak memory 198896 kb
Host smart-fca7a96f-f776-409c-be94-8596b67ca15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565344185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3565344185
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.2272248819
Short name T392
Test name
Test status
Simulation time 180479486463 ps
CPU time 20.92 seconds
Started Aug 06 04:30:58 PM PDT 24
Finished Aug 06 04:31:19 PM PDT 24
Peak memory 199668 kb
Host smart-ec55a6ca-1962-4a3f-9ab7-330f6f74194f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272248819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2272248819
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2851353153
Short name T222
Test name
Test status
Simulation time 50287302366 ps
CPU time 20.51 seconds
Started Aug 06 04:31:11 PM PDT 24
Finished Aug 06 04:31:32 PM PDT 24
Peak memory 199704 kb
Host smart-76c0f56c-ae4e-4674-a7f2-8ec85d3c8a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851353153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2851353153
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.4082797799
Short name T152
Test name
Test status
Simulation time 26273979064 ps
CPU time 41.96 seconds
Started Aug 06 04:30:59 PM PDT 24
Finished Aug 06 04:31:41 PM PDT 24
Peak memory 199724 kb
Host smart-b4c7fab7-9d9a-4cd8-a368-7d53f35c4625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082797799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.4082797799
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3778390566
Short name T872
Test name
Test status
Simulation time 25724045685 ps
CPU time 6.53 seconds
Started Aug 06 04:30:58 PM PDT 24
Finished Aug 06 04:31:04 PM PDT 24
Peak memory 199660 kb
Host smart-f09a4721-8175-4074-80f2-3da1020e83c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778390566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3778390566
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.151638575
Short name T354
Test name
Test status
Simulation time 28168758 ps
CPU time 0.54 seconds
Started Aug 06 04:29:11 PM PDT 24
Finished Aug 06 04:29:12 PM PDT 24
Peak memory 195036 kb
Host smart-1c228b02-3305-45b1-9ece-d5863ff5531e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151638575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.151638575
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.445159574
Short name T819
Test name
Test status
Simulation time 25903765623 ps
CPU time 8.81 seconds
Started Aug 06 04:28:51 PM PDT 24
Finished Aug 06 04:29:00 PM PDT 24
Peak memory 199060 kb
Host smart-f2f52e83-9e4f-4951-b314-ee3927515afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445159574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.445159574
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.517843302
Short name T860
Test name
Test status
Simulation time 15969934109 ps
CPU time 23.05 seconds
Started Aug 06 04:29:07 PM PDT 24
Finished Aug 06 04:29:30 PM PDT 24
Peak memory 199692 kb
Host smart-2ebae54a-b4cb-49c4-9651-9b3c34d4915f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517843302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.517843302
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2696727414
Short name T589
Test name
Test status
Simulation time 15434641285 ps
CPU time 36.81 seconds
Started Aug 06 04:29:05 PM PDT 24
Finished Aug 06 04:29:42 PM PDT 24
Peak memory 199712 kb
Host smart-2455bc64-e8eb-4235-9f3a-72e7218ad9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696727414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2696727414
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3872349066
Short name T550
Test name
Test status
Simulation time 36745044679 ps
CPU time 10.49 seconds
Started Aug 06 04:29:04 PM PDT 24
Finished Aug 06 04:29:14 PM PDT 24
Peak memory 199704 kb
Host smart-94ae454d-6134-47a8-9523-07d32d989944
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872349066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3872349066
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.443633841
Short name T684
Test name
Test status
Simulation time 192972568514 ps
CPU time 1066.59 seconds
Started Aug 06 04:29:07 PM PDT 24
Finished Aug 06 04:46:54 PM PDT 24
Peak memory 199708 kb
Host smart-530452d7-80e9-49ac-bb66-773a428543bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=443633841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.443633841
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.961312730
Short name T1095
Test name
Test status
Simulation time 468214746 ps
CPU time 1.2 seconds
Started Aug 06 04:29:02 PM PDT 24
Finished Aug 06 04:29:03 PM PDT 24
Peak memory 195212 kb
Host smart-156cbc41-232e-40f8-8355-b92aa5bfea3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961312730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.961312730
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.619511124
Short name T1091
Test name
Test status
Simulation time 39545080474 ps
CPU time 34.39 seconds
Started Aug 06 04:29:05 PM PDT 24
Finished Aug 06 04:29:40 PM PDT 24
Peak memory 199844 kb
Host smart-0e763da0-39d0-4b29-ab67-3ef8cac34076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619511124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.619511124
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1513096964
Short name T4
Test name
Test status
Simulation time 16058393807 ps
CPU time 855.22 seconds
Started Aug 06 04:29:07 PM PDT 24
Finished Aug 06 04:43:22 PM PDT 24
Peak memory 199632 kb
Host smart-2ff98220-7d08-4d47-9b1b-66c8668406a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1513096964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1513096964
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1514507492
Short name T503
Test name
Test status
Simulation time 6092770124 ps
CPU time 9.29 seconds
Started Aug 06 04:29:05 PM PDT 24
Finished Aug 06 04:29:15 PM PDT 24
Peak memory 198952 kb
Host smart-3bf1e356-6dec-468f-9e71-dbd6a589b52e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1514507492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1514507492
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1952168435
Short name T896
Test name
Test status
Simulation time 49125652670 ps
CPU time 18.29 seconds
Started Aug 06 04:29:07 PM PDT 24
Finished Aug 06 04:29:26 PM PDT 24
Peak memory 199680 kb
Host smart-1dac4167-bfd5-4295-b1f7-b397f0383e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952168435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1952168435
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2160409580
Short name T901
Test name
Test status
Simulation time 6777168117 ps
CPU time 11.77 seconds
Started Aug 06 04:29:07 PM PDT 24
Finished Aug 06 04:29:19 PM PDT 24
Peak memory 195840 kb
Host smart-fc4546a5-69f7-4ce1-ab3a-bda5c4419e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160409580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2160409580
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3194501898
Short name T897
Test name
Test status
Simulation time 505399426 ps
CPU time 2.54 seconds
Started Aug 06 04:28:58 PM PDT 24
Finished Aug 06 04:29:00 PM PDT 24
Peak memory 198432 kb
Host smart-6c2181bf-bd0b-4a3c-a390-e7075a80d641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194501898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3194501898
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2098038750
Short name T20
Test name
Test status
Simulation time 192993613785 ps
CPU time 79.84 seconds
Started Aug 06 04:29:04 PM PDT 24
Finished Aug 06 04:30:24 PM PDT 24
Peak memory 208044 kb
Host smart-a07d5840-e4ba-4734-ba80-1f79af6b2414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098038750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2098038750
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2347474751
Short name T55
Test name
Test status
Simulation time 114148980028 ps
CPU time 1380.18 seconds
Started Aug 06 04:29:03 PM PDT 24
Finished Aug 06 04:52:03 PM PDT 24
Peak memory 216272 kb
Host smart-3ebc82ad-d2ec-4742-92e7-f2012da99236
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347474751 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2347474751
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3666350753
Short name T15
Test name
Test status
Simulation time 510794271 ps
CPU time 1.99 seconds
Started Aug 06 04:29:02 PM PDT 24
Finished Aug 06 04:29:04 PM PDT 24
Peak memory 199636 kb
Host smart-419cca6b-cfec-4dbb-875d-d33982289129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666350753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3666350753
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2733421874
Short name T1083
Test name
Test status
Simulation time 18276992055 ps
CPU time 9.1 seconds
Started Aug 06 04:28:54 PM PDT 24
Finished Aug 06 04:29:03 PM PDT 24
Peak memory 197492 kb
Host smart-4213e3d4-d594-4be0-acfb-678c2b506a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733421874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2733421874
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.289031491
Short name T598
Test name
Test status
Simulation time 90592480802 ps
CPU time 178.84 seconds
Started Aug 06 04:32:11 PM PDT 24
Finished Aug 06 04:35:10 PM PDT 24
Peak memory 199384 kb
Host smart-761338b5-4058-4a9a-851d-6cb4161ef6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289031491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.289031491
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2265959069
Short name T215
Test name
Test status
Simulation time 127133845853 ps
CPU time 168.56 seconds
Started Aug 06 04:30:55 PM PDT 24
Finished Aug 06 04:33:44 PM PDT 24
Peak memory 199688 kb
Host smart-31137711-a5a8-4880-ba0e-16b76dba64fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265959069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2265959069
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.363147773
Short name T992
Test name
Test status
Simulation time 95728254964 ps
CPU time 122.77 seconds
Started Aug 06 04:30:57 PM PDT 24
Finished Aug 06 04:33:00 PM PDT 24
Peak memory 199744 kb
Host smart-2e58b2ff-a6ce-4f49-878f-0c9f8d5674b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363147773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.363147773
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.600828259
Short name T716
Test name
Test status
Simulation time 4774984397 ps
CPU time 5.12 seconds
Started Aug 06 04:30:58 PM PDT 24
Finished Aug 06 04:31:03 PM PDT 24
Peak memory 199556 kb
Host smart-3b2cb841-a2f0-46bb-ae13-6a60efd1dc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600828259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.600828259
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2789826790
Short name T1003
Test name
Test status
Simulation time 36222527860 ps
CPU time 35.04 seconds
Started Aug 06 04:30:57 PM PDT 24
Finished Aug 06 04:31:32 PM PDT 24
Peak memory 199576 kb
Host smart-3120f718-daa0-44ca-b70a-80d74b1915fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789826790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2789826790
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3871115207
Short name T1136
Test name
Test status
Simulation time 32307266607 ps
CPU time 14.44 seconds
Started Aug 06 04:30:56 PM PDT 24
Finished Aug 06 04:31:10 PM PDT 24
Peak memory 199704 kb
Host smart-537458a1-7cf7-4c46-83b3-13986c79fb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871115207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3871115207
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.302437494
Short name T229
Test name
Test status
Simulation time 50904709428 ps
CPU time 72.61 seconds
Started Aug 06 04:30:59 PM PDT 24
Finished Aug 06 04:32:11 PM PDT 24
Peak memory 199772 kb
Host smart-d709e7f0-cb75-4f8a-b878-b55cb28c74ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302437494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.302437494
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.4186163269
Short name T1015
Test name
Test status
Simulation time 48921124 ps
CPU time 0.62 seconds
Started Aug 06 04:29:03 PM PDT 24
Finished Aug 06 04:29:04 PM PDT 24
Peak memory 195560 kb
Host smart-f0ebdee6-7ae4-43f0-9127-33d457e7ecd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186163269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.4186163269
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.375007489
Short name T1053
Test name
Test status
Simulation time 138224319069 ps
CPU time 198.57 seconds
Started Aug 06 04:28:57 PM PDT 24
Finished Aug 06 04:32:16 PM PDT 24
Peak memory 199556 kb
Host smart-b5195e62-4e6b-4f3a-a3ac-dfa8b3802406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375007489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.375007489
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2740613828
Short name T1076
Test name
Test status
Simulation time 20837950052 ps
CPU time 28.36 seconds
Started Aug 06 04:29:01 PM PDT 24
Finished Aug 06 04:29:30 PM PDT 24
Peak memory 199676 kb
Host smart-95bda425-0e86-41f2-b8cd-a498b785e94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740613828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2740613828
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1435454323
Short name T218
Test name
Test status
Simulation time 172975456290 ps
CPU time 300.26 seconds
Started Aug 06 04:29:04 PM PDT 24
Finished Aug 06 04:34:04 PM PDT 24
Peak memory 199704 kb
Host smart-8b8df6e9-2ef8-42f1-a25f-146d243cb7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435454323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1435454323
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3467589777
Short name T575
Test name
Test status
Simulation time 12061054473 ps
CPU time 20.15 seconds
Started Aug 06 04:29:05 PM PDT 24
Finished Aug 06 04:29:26 PM PDT 24
Peak memory 199772 kb
Host smart-32d7a8f5-4be8-41cb-b8f9-71f750aaa5e0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467589777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3467589777
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1044200564
Short name T608
Test name
Test status
Simulation time 167411774975 ps
CPU time 381.28 seconds
Started Aug 06 04:29:05 PM PDT 24
Finished Aug 06 04:35:26 PM PDT 24
Peak memory 199628 kb
Host smart-7e18ea27-553e-474c-8018-fdb936330673
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1044200564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1044200564
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1486054411
Short name T989
Test name
Test status
Simulation time 10521351940 ps
CPU time 10.67 seconds
Started Aug 06 04:29:06 PM PDT 24
Finished Aug 06 04:29:17 PM PDT 24
Peak memory 198872 kb
Host smart-70839aac-eec9-48e7-9a8c-9f6080f502c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486054411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1486054411
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.791552307
Short name T270
Test name
Test status
Simulation time 51750376466 ps
CPU time 97.25 seconds
Started Aug 06 04:29:06 PM PDT 24
Finished Aug 06 04:30:43 PM PDT 24
Peak memory 198440 kb
Host smart-d8d5e924-30c7-4e95-9dbd-9c9bbe1273c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791552307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.791552307
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.988858717
Short name T298
Test name
Test status
Simulation time 15825398543 ps
CPU time 796.47 seconds
Started Aug 06 04:29:04 PM PDT 24
Finished Aug 06 04:42:21 PM PDT 24
Peak memory 199672 kb
Host smart-27b1f3e6-2bb2-4793-8052-62073690ae94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988858717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.988858717
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3860594375
Short name T386
Test name
Test status
Simulation time 4301200072 ps
CPU time 35.46 seconds
Started Aug 06 04:29:04 PM PDT 24
Finished Aug 06 04:29:39 PM PDT 24
Peak memory 198520 kb
Host smart-95baf415-c8f0-4552-a3d5-9a56cb8af2a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3860594375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3860594375
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.366356625
Short name T927
Test name
Test status
Simulation time 22842051194 ps
CPU time 9.81 seconds
Started Aug 06 04:29:04 PM PDT 24
Finished Aug 06 04:29:14 PM PDT 24
Peak memory 199028 kb
Host smart-b113cc00-8a7d-40f1-89d4-9821b7bbfb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366356625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.366356625
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2691261160
Short name T687
Test name
Test status
Simulation time 5303530671 ps
CPU time 7.9 seconds
Started Aug 06 04:28:56 PM PDT 24
Finished Aug 06 04:29:04 PM PDT 24
Peak memory 196552 kb
Host smart-a971d72f-84ce-4ba6-8e85-6d4f1eda7f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691261160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2691261160
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1094382618
Short name T563
Test name
Test status
Simulation time 712846531 ps
CPU time 1.87 seconds
Started Aug 06 04:29:01 PM PDT 24
Finished Aug 06 04:29:03 PM PDT 24
Peak memory 197924 kb
Host smart-71909753-3807-4bc3-b0c7-0425c6b616c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094382618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1094382618
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.1929374732
Short name T1035
Test name
Test status
Simulation time 186175720187 ps
CPU time 112.96 seconds
Started Aug 06 04:29:05 PM PDT 24
Finished Aug 06 04:30:58 PM PDT 24
Peak memory 208052 kb
Host smart-3ccf921f-f851-4d06-9ac6-10a4ca77e97c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929374732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1929374732
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3271933836
Short name T836
Test name
Test status
Simulation time 81249655669 ps
CPU time 818.29 seconds
Started Aug 06 04:28:55 PM PDT 24
Finished Aug 06 04:42:34 PM PDT 24
Peak memory 225880 kb
Host smart-c6e2b35e-009c-431b-8c7a-b777de103e00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271933836 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3271933836
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1966739010
Short name T454
Test name
Test status
Simulation time 1185520900 ps
CPU time 1.15 seconds
Started Aug 06 04:29:01 PM PDT 24
Finished Aug 06 04:29:03 PM PDT 24
Peak memory 196960 kb
Host smart-eea9ecfa-058f-4bc2-ab6b-f028e2acbe5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966739010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1966739010
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3090530103
Short name T1007
Test name
Test status
Simulation time 63942868830 ps
CPU time 47.65 seconds
Started Aug 06 04:29:04 PM PDT 24
Finished Aug 06 04:29:52 PM PDT 24
Peak memory 199700 kb
Host smart-94668c82-977c-4410-81dd-89842f58e429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090530103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3090530103
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.4207135791
Short name T130
Test name
Test status
Simulation time 39279996581 ps
CPU time 39.25 seconds
Started Aug 06 04:31:01 PM PDT 24
Finished Aug 06 04:31:40 PM PDT 24
Peak memory 199716 kb
Host smart-f420a69b-48ec-4927-ab53-bb7e66217a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207135791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.4207135791
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2025661341
Short name T798
Test name
Test status
Simulation time 16793755608 ps
CPU time 24.99 seconds
Started Aug 06 04:30:58 PM PDT 24
Finished Aug 06 04:31:23 PM PDT 24
Peak memory 199736 kb
Host smart-96e70dbc-44dc-47c5-93c3-5a6c56cbc30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025661341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2025661341
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1805820572
Short name T159
Test name
Test status
Simulation time 63213596186 ps
CPU time 97.55 seconds
Started Aug 06 04:30:59 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 199688 kb
Host smart-1d228fa2-ce34-477c-a8f5-2d5d74fcab70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805820572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1805820572
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2804373677
Short name T196
Test name
Test status
Simulation time 9961714440 ps
CPU time 16.35 seconds
Started Aug 06 04:31:02 PM PDT 24
Finished Aug 06 04:31:18 PM PDT 24
Peak memory 199576 kb
Host smart-635b606d-4293-487d-a1ba-5f5bd51b0c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804373677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2804373677
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3743184328
Short name T810
Test name
Test status
Simulation time 219915048470 ps
CPU time 181.78 seconds
Started Aug 06 04:30:59 PM PDT 24
Finished Aug 06 04:34:01 PM PDT 24
Peak memory 199812 kb
Host smart-6473beac-5c8e-4ef2-906f-8dc2240c7b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743184328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3743184328
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.4268280824
Short name T495
Test name
Test status
Simulation time 46903051750 ps
CPU time 65.14 seconds
Started Aug 06 04:30:58 PM PDT 24
Finished Aug 06 04:32:03 PM PDT 24
Peak memory 199588 kb
Host smart-86ef4911-a8b1-4df1-913e-96c8585f633d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268280824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.4268280824
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1923063856
Short name T1108
Test name
Test status
Simulation time 40077316931 ps
CPU time 31.72 seconds
Started Aug 06 04:31:01 PM PDT 24
Finished Aug 06 04:31:33 PM PDT 24
Peak memory 199768 kb
Host smart-2db693ef-bb39-4f5b-abf3-c52a6923ff0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923063856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1923063856
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1312671889
Short name T241
Test name
Test status
Simulation time 259356158743 ps
CPU time 98.08 seconds
Started Aug 06 04:30:59 PM PDT 24
Finished Aug 06 04:32:37 PM PDT 24
Peak memory 199748 kb
Host smart-3e9afb3d-92b7-4a76-9d25-bf965ebcce33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312671889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1312671889
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1193491608
Short name T243
Test name
Test status
Simulation time 10056774072 ps
CPU time 15.39 seconds
Started Aug 06 04:30:57 PM PDT 24
Finished Aug 06 04:31:13 PM PDT 24
Peak memory 199508 kb
Host smart-053d43cd-0845-4ff1-a090-b78c39956b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193491608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1193491608
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3834349496
Short name T353
Test name
Test status
Simulation time 22316168 ps
CPU time 0.57 seconds
Started Aug 06 04:29:05 PM PDT 24
Finished Aug 06 04:29:06 PM PDT 24
Peak memory 195096 kb
Host smart-0e68c1e9-0b7e-452a-83c5-f5ea52bc56ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834349496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3834349496
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.443483733
Short name T639
Test name
Test status
Simulation time 33224046993 ps
CPU time 54.26 seconds
Started Aug 06 04:29:03 PM PDT 24
Finished Aug 06 04:29:57 PM PDT 24
Peak memory 199748 kb
Host smart-5a6dddb3-a3f2-437a-a6c0-639fa3c0f7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443483733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.443483733
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.2819368059
Short name T568
Test name
Test status
Simulation time 82593991566 ps
CPU time 62.77 seconds
Started Aug 06 04:29:06 PM PDT 24
Finished Aug 06 04:30:09 PM PDT 24
Peak memory 199628 kb
Host smart-1428e0d8-f33c-4f6e-8af1-2d8cf4eadd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819368059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2819368059
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.4209577032
Short name T906
Test name
Test status
Simulation time 20093694189 ps
CPU time 30.52 seconds
Started Aug 06 04:29:06 PM PDT 24
Finished Aug 06 04:29:37 PM PDT 24
Peak memory 199740 kb
Host smart-57580da2-e000-412e-8968-2472e1d0b8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209577032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.4209577032
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.3474558589
Short name T17
Test name
Test status
Simulation time 28686764784 ps
CPU time 11.03 seconds
Started Aug 06 04:29:03 PM PDT 24
Finished Aug 06 04:29:14 PM PDT 24
Peak memory 199560 kb
Host smart-41d598b1-218b-4425-9cf7-8891a3fb4eb4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474558589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3474558589
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2249597691
Short name T718
Test name
Test status
Simulation time 69173515044 ps
CPU time 124.03 seconds
Started Aug 06 04:29:05 PM PDT 24
Finished Aug 06 04:31:09 PM PDT 24
Peak memory 199660 kb
Host smart-364bfdd4-38d6-456a-8a17-6bb55c518c89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2249597691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2249597691
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1026958539
Short name T1107
Test name
Test status
Simulation time 367462687 ps
CPU time 0.72 seconds
Started Aug 06 04:29:02 PM PDT 24
Finished Aug 06 04:29:03 PM PDT 24
Peak memory 195856 kb
Host smart-98ee3f83-d56a-49a6-85c3-af499b0b224a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026958539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1026958539
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.498256585
Short name T287
Test name
Test status
Simulation time 260720514084 ps
CPU time 85.31 seconds
Started Aug 06 04:29:07 PM PDT 24
Finished Aug 06 04:30:32 PM PDT 24
Peak memory 199764 kb
Host smart-d368f694-9ad3-44c3-82f8-8d97026de21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498256585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.498256585
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.769660555
Short name T502
Test name
Test status
Simulation time 9584071756 ps
CPU time 120.48 seconds
Started Aug 06 04:29:06 PM PDT 24
Finished Aug 06 04:31:06 PM PDT 24
Peak memory 199624 kb
Host smart-a6892de1-f642-469c-9380-2f67d6472068
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=769660555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.769660555
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3981165056
Short name T1132
Test name
Test status
Simulation time 5178466945 ps
CPU time 4.67 seconds
Started Aug 06 04:29:02 PM PDT 24
Finished Aug 06 04:29:07 PM PDT 24
Peak memory 197780 kb
Host smart-db3c4a43-515b-4fcb-84d2-3f57c8d967f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3981165056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3981165056
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1076003241
Short name T832
Test name
Test status
Simulation time 97448441623 ps
CPU time 201.81 seconds
Started Aug 06 04:29:10 PM PDT 24
Finished Aug 06 04:32:32 PM PDT 24
Peak memory 199664 kb
Host smart-e8eedc5c-160f-4ded-8e3f-a457d83505c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076003241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1076003241
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.3624394115
Short name T941
Test name
Test status
Simulation time 27653401097 ps
CPU time 44.19 seconds
Started Aug 06 04:29:05 PM PDT 24
Finished Aug 06 04:29:50 PM PDT 24
Peak memory 196292 kb
Host smart-bed5b6a7-f9d4-4047-8c42-1c06688f169d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624394115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3624394115
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.2960084259
Short name T521
Test name
Test status
Simulation time 443000393 ps
CPU time 1.81 seconds
Started Aug 06 04:29:05 PM PDT 24
Finished Aug 06 04:29:07 PM PDT 24
Peak memory 198380 kb
Host smart-a57c3997-efc6-4fc4-b86c-d7698aa9a415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960084259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2960084259
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.374287437
Short name T679
Test name
Test status
Simulation time 470563388355 ps
CPU time 193.02 seconds
Started Aug 06 04:29:04 PM PDT 24
Finished Aug 06 04:32:17 PM PDT 24
Peak memory 216188 kb
Host smart-90a57a02-083f-4d04-b134-c8cba0ae3e3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374287437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.374287437
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.1768969261
Short name T101
Test name
Test status
Simulation time 45413275644 ps
CPU time 452.02 seconds
Started Aug 06 04:29:01 PM PDT 24
Finished Aug 06 04:36:33 PM PDT 24
Peak memory 216348 kb
Host smart-d02fb7a1-64f3-4d2c-bf58-2ce1ec6f03a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768969261 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1768969261
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3293678673
Short name T953
Test name
Test status
Simulation time 2136981072 ps
CPU time 2.2 seconds
Started Aug 06 04:29:08 PM PDT 24
Finished Aug 06 04:29:10 PM PDT 24
Peak memory 199404 kb
Host smart-36f84f84-9201-45f1-971d-e62c3ecf03bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293678673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3293678673
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1138147745
Short name T1039
Test name
Test status
Simulation time 29081226827 ps
CPU time 12.21 seconds
Started Aug 06 04:29:03 PM PDT 24
Finished Aug 06 04:29:15 PM PDT 24
Peak memory 199724 kb
Host smart-669f0bfc-70c8-4416-9e27-4c52f86f62ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138147745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1138147745
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2958055180
Short name T531
Test name
Test status
Simulation time 78091456182 ps
CPU time 31.28 seconds
Started Aug 06 04:32:11 PM PDT 24
Finished Aug 06 04:32:43 PM PDT 24
Peak memory 197660 kb
Host smart-c9c42b1f-a3ad-42cc-b6fd-49c3cea32bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958055180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2958055180
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3193512652
Short name T1175
Test name
Test status
Simulation time 12942894065 ps
CPU time 5.73 seconds
Started Aug 06 04:32:11 PM PDT 24
Finished Aug 06 04:32:17 PM PDT 24
Peak memory 197924 kb
Host smart-2cdcb650-5188-4ecd-b0a2-affb29e396ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193512652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3193512652
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2060658044
Short name T206
Test name
Test status
Simulation time 66333812564 ps
CPU time 25.08 seconds
Started Aug 06 04:32:11 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 197512 kb
Host smart-baef2107-6669-489b-858b-3cdbe2983e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060658044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2060658044
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2369561871
Short name T1176
Test name
Test status
Simulation time 101045877269 ps
CPU time 56.39 seconds
Started Aug 06 04:32:26 PM PDT 24
Finished Aug 06 04:33:23 PM PDT 24
Peak memory 199688 kb
Host smart-5cdee8f3-e7af-469f-9c85-fa19cc4592ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369561871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2369561871
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.1255806107
Short name T1172
Test name
Test status
Simulation time 66951741478 ps
CPU time 29.77 seconds
Started Aug 06 04:32:26 PM PDT 24
Finished Aug 06 04:32:56 PM PDT 24
Peak memory 199692 kb
Host smart-d8468c8d-b1a5-48aa-a5f2-bd363f543998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255806107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1255806107
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3162978174
Short name T96
Test name
Test status
Simulation time 256284397042 ps
CPU time 95.38 seconds
Started Aug 06 04:31:00 PM PDT 24
Finished Aug 06 04:32:35 PM PDT 24
Peak memory 199732 kb
Host smart-3bcef07f-f76d-421e-b783-3711d76d7f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162978174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3162978174
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.765099289
Short name T1125
Test name
Test status
Simulation time 38471037455 ps
CPU time 37.7 seconds
Started Aug 06 04:31:17 PM PDT 24
Finished Aug 06 04:31:55 PM PDT 24
Peak memory 199676 kb
Host smart-7d66e876-8341-4661-afc8-6f893f47532d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765099289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.765099289
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3977986722
Short name T458
Test name
Test status
Simulation time 235313055614 ps
CPU time 90.48 seconds
Started Aug 06 04:31:17 PM PDT 24
Finished Aug 06 04:32:47 PM PDT 24
Peak memory 199664 kb
Host smart-b3a52115-cd07-4553-92c0-9ce84ac607e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977986722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3977986722
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1833743012
Short name T620
Test name
Test status
Simulation time 6495362950 ps
CPU time 5.17 seconds
Started Aug 06 04:31:12 PM PDT 24
Finished Aug 06 04:31:17 PM PDT 24
Peak memory 197924 kb
Host smart-8197c9f8-8c5f-49c0-b202-e0164b5bf7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833743012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1833743012
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2152302955
Short name T761
Test name
Test status
Simulation time 100930901071 ps
CPU time 37.76 seconds
Started Aug 06 04:31:13 PM PDT 24
Finished Aug 06 04:31:51 PM PDT 24
Peak memory 199272 kb
Host smart-c5d47990-93ad-4e8d-a8b0-8d734d3cfbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152302955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2152302955
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3706449460
Short name T1148
Test name
Test status
Simulation time 14596886 ps
CPU time 0.55 seconds
Started Aug 06 04:29:08 PM PDT 24
Finished Aug 06 04:29:09 PM PDT 24
Peak memory 195380 kb
Host smart-4c0cf32e-cd58-4e03-9c0b-19cbcd0135c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706449460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3706449460
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.951447078
Short name T118
Test name
Test status
Simulation time 43282691530 ps
CPU time 12.46 seconds
Started Aug 06 04:29:03 PM PDT 24
Finished Aug 06 04:29:15 PM PDT 24
Peak memory 199500 kb
Host smart-4fb47ea8-af27-47f7-a09e-9385d6a42a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951447078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.951447078
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.863063613
Short name T154
Test name
Test status
Simulation time 30217289209 ps
CPU time 13.03 seconds
Started Aug 06 04:29:07 PM PDT 24
Finished Aug 06 04:29:20 PM PDT 24
Peak memory 199684 kb
Host smart-6295a0d5-ce65-4283-9454-6bb84793f72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863063613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.863063613
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3917785804
Short name T734
Test name
Test status
Simulation time 9832148898 ps
CPU time 14.83 seconds
Started Aug 06 04:29:03 PM PDT 24
Finished Aug 06 04:29:18 PM PDT 24
Peak memory 199728 kb
Host smart-a89e67aa-38ef-4a05-b875-b2327197f794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917785804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3917785804
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.427644746
Short name T703
Test name
Test status
Simulation time 6636623170 ps
CPU time 5.26 seconds
Started Aug 06 04:28:58 PM PDT 24
Finished Aug 06 04:29:03 PM PDT 24
Peak memory 196544 kb
Host smart-f46955e4-b7fe-424f-84cf-5de5919174c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427644746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.427644746
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1408489203
Short name T1066
Test name
Test status
Simulation time 75502280867 ps
CPU time 392.33 seconds
Started Aug 06 04:29:07 PM PDT 24
Finished Aug 06 04:35:40 PM PDT 24
Peak memory 199744 kb
Host smart-4e3ea868-c59f-4441-a901-8905f666f9f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1408489203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1408489203
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2964306650
Short name T355
Test name
Test status
Simulation time 4351827988 ps
CPU time 5.31 seconds
Started Aug 06 04:29:08 PM PDT 24
Finished Aug 06 04:29:13 PM PDT 24
Peak memory 198232 kb
Host smart-106c53a4-c458-4535-a9f3-a25b8b025f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964306650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2964306650
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.1381353732
Short name T610
Test name
Test status
Simulation time 56927254823 ps
CPU time 43.85 seconds
Started Aug 06 04:29:04 PM PDT 24
Finished Aug 06 04:29:48 PM PDT 24
Peak memory 199860 kb
Host smart-b840aa81-d106-4d87-8b65-03dab88b0df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381353732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1381353732
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.1829091415
Short name T470
Test name
Test status
Simulation time 17890705302 ps
CPU time 591.11 seconds
Started Aug 06 04:29:05 PM PDT 24
Finished Aug 06 04:39:02 PM PDT 24
Peak memory 199672 kb
Host smart-d87b0099-a1ad-47a9-9716-9d1d68e1be94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1829091415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1829091415
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.174247328
Short name T1122
Test name
Test status
Simulation time 4893194391 ps
CPU time 11 seconds
Started Aug 06 04:29:03 PM PDT 24
Finished Aug 06 04:29:14 PM PDT 24
Peak memory 197876 kb
Host smart-42fbfb66-d7cf-49c0-98df-7a4c5d38ae3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=174247328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.174247328
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.676692171
Short name T856
Test name
Test status
Simulation time 130814257457 ps
CPU time 102.14 seconds
Started Aug 06 04:29:06 PM PDT 24
Finished Aug 06 04:30:49 PM PDT 24
Peak memory 199692 kb
Host smart-7a94a554-d752-4aac-9730-ccbe73aa16f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676692171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.676692171
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1228063854
Short name T1077
Test name
Test status
Simulation time 38758590202 ps
CPU time 28.9 seconds
Started Aug 06 04:29:02 PM PDT 24
Finished Aug 06 04:29:31 PM PDT 24
Peak memory 196060 kb
Host smart-a0bfac87-c91e-4d9a-b5d0-3e8f05aa0f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228063854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1228063854
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3133154878
Short name T300
Test name
Test status
Simulation time 290733398 ps
CPU time 1.5 seconds
Started Aug 06 04:28:58 PM PDT 24
Finished Aug 06 04:28:59 PM PDT 24
Peak memory 198140 kb
Host smart-92847c98-9871-4d50-bc9e-372c4a42ee1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133154878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3133154878
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3477656914
Short name T97
Test name
Test status
Simulation time 72709514190 ps
CPU time 715.04 seconds
Started Aug 06 04:29:07 PM PDT 24
Finished Aug 06 04:41:02 PM PDT 24
Peak memory 224600 kb
Host smart-12c6e428-43af-4559-9ba0-27e753fad4b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477656914 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3477656914
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3344829435
Short name T427
Test name
Test status
Simulation time 2450210054 ps
CPU time 2.3 seconds
Started Aug 06 04:29:08 PM PDT 24
Finished Aug 06 04:29:11 PM PDT 24
Peak memory 199508 kb
Host smart-d30b6c1f-3a12-463e-8170-ffd64df55ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344829435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3344829435
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2382929325
Short name T606
Test name
Test status
Simulation time 74820539093 ps
CPU time 113.18 seconds
Started Aug 06 04:29:05 PM PDT 24
Finished Aug 06 04:30:59 PM PDT 24
Peak memory 199620 kb
Host smart-f0f26b01-2b1a-4f3c-b99d-cfcc14125d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382929325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2382929325
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1554026433
Short name T1129
Test name
Test status
Simulation time 119224583924 ps
CPU time 44.85 seconds
Started Aug 06 04:31:13 PM PDT 24
Finished Aug 06 04:31:58 PM PDT 24
Peak memory 199712 kb
Host smart-21ab440e-9c6f-44c9-b7fc-0ea02deffd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554026433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1554026433
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2791197453
Short name T1150
Test name
Test status
Simulation time 70088931338 ps
CPU time 54.12 seconds
Started Aug 06 04:31:17 PM PDT 24
Finished Aug 06 04:32:11 PM PDT 24
Peak memory 199728 kb
Host smart-d2cf420e-1c43-4492-8e4a-5a04c5951af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791197453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2791197453
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.630050810
Short name T1123
Test name
Test status
Simulation time 102090001692 ps
CPU time 397.09 seconds
Started Aug 06 04:31:13 PM PDT 24
Finished Aug 06 04:37:50 PM PDT 24
Peak memory 199676 kb
Host smart-8c332de6-ec6c-4c2d-b7b1-35f1d0f8c486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630050810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.630050810
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2662938008
Short name T202
Test name
Test status
Simulation time 27661733578 ps
CPU time 23.13 seconds
Started Aug 06 04:31:18 PM PDT 24
Finished Aug 06 04:31:41 PM PDT 24
Peak memory 199768 kb
Host smart-e4382058-0857-4265-a861-5e3c142d9083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662938008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2662938008
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.262146489
Short name T689
Test name
Test status
Simulation time 19994313902 ps
CPU time 23.28 seconds
Started Aug 06 04:31:14 PM PDT 24
Finished Aug 06 04:31:37 PM PDT 24
Peak memory 199760 kb
Host smart-c5324ad4-1a8d-4d3c-ac59-2e2f98f208b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262146489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.262146489
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3945712368
Short name T141
Test name
Test status
Simulation time 37478132328 ps
CPU time 65.05 seconds
Started Aug 06 04:31:13 PM PDT 24
Finished Aug 06 04:32:18 PM PDT 24
Peak memory 199688 kb
Host smart-e2fc8d21-50cd-4487-bdc4-b02d902d220e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945712368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3945712368
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2608978430
Short name T533
Test name
Test status
Simulation time 169613485537 ps
CPU time 18.23 seconds
Started Aug 06 04:31:15 PM PDT 24
Finished Aug 06 04:31:33 PM PDT 24
Peak memory 199496 kb
Host smart-a0e6bfb8-0edc-440c-80ad-c4a1e673b51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608978430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2608978430
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1167396971
Short name T1014
Test name
Test status
Simulation time 74979823 ps
CPU time 0.53 seconds
Started Aug 06 04:29:10 PM PDT 24
Finished Aug 06 04:29:10 PM PDT 24
Peak memory 195076 kb
Host smart-7be98a69-ffcc-40c3-a224-0d9f7039ff90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167396971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1167396971
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3995305224
Short name T493
Test name
Test status
Simulation time 51006234334 ps
CPU time 21.17 seconds
Started Aug 06 04:29:03 PM PDT 24
Finished Aug 06 04:29:29 PM PDT 24
Peak memory 199660 kb
Host smart-f14ccf3c-90c7-4f4e-abf6-51b3f3b8aca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995305224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3995305224
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1899101958
Short name T617
Test name
Test status
Simulation time 8387234119 ps
CPU time 12.93 seconds
Started Aug 06 04:29:04 PM PDT 24
Finished Aug 06 04:29:17 PM PDT 24
Peak memory 199640 kb
Host smart-e0354deb-bf42-4906-b5cc-f1f11062be2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899101958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1899101958
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2537438528
Short name T161
Test name
Test status
Simulation time 24873143978 ps
CPU time 20.16 seconds
Started Aug 06 04:29:04 PM PDT 24
Finished Aug 06 04:29:24 PM PDT 24
Peak memory 199748 kb
Host smart-7d1efc03-4e8e-4088-8ccd-e84a7e556065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537438528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2537438528
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2830202461
Short name T964
Test name
Test status
Simulation time 19001710158 ps
CPU time 15.33 seconds
Started Aug 06 04:29:04 PM PDT 24
Finished Aug 06 04:29:20 PM PDT 24
Peak memory 199668 kb
Host smart-4f375d1d-b8de-4873-b1ac-24cb3cb50ec0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830202461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2830202461
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.3176284275
Short name T1059
Test name
Test status
Simulation time 87887340622 ps
CPU time 318.52 seconds
Started Aug 06 04:29:05 PM PDT 24
Finished Aug 06 04:34:23 PM PDT 24
Peak memory 199588 kb
Host smart-692185db-1529-4e73-a35b-bffd40f9c0de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3176284275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3176284275
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1963184001
Short name T748
Test name
Test status
Simulation time 914689361 ps
CPU time 1.05 seconds
Started Aug 06 04:29:02 PM PDT 24
Finished Aug 06 04:29:03 PM PDT 24
Peak memory 198204 kb
Host smart-a725f5c0-3b21-436d-b5cc-53f2a3b9f6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963184001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1963184001
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2070539116
Short name T1045
Test name
Test status
Simulation time 128847162906 ps
CPU time 57.69 seconds
Started Aug 06 04:28:57 PM PDT 24
Finished Aug 06 04:29:55 PM PDT 24
Peak memory 208036 kb
Host smart-bbfcb09f-77b3-411e-8776-5d42e1454aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070539116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2070539116
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3582026279
Short name T636
Test name
Test status
Simulation time 15973138808 ps
CPU time 399.84 seconds
Started Aug 06 04:29:02 PM PDT 24
Finished Aug 06 04:35:42 PM PDT 24
Peak memory 199784 kb
Host smart-e6c46e1f-17f4-4348-a73a-4a26c4430b06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3582026279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3582026279
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1610614091
Short name T453
Test name
Test status
Simulation time 3288126155 ps
CPU time 22.23 seconds
Started Aug 06 04:29:03 PM PDT 24
Finished Aug 06 04:29:25 PM PDT 24
Peak memory 198792 kb
Host smart-f9346eac-c119-4cfa-be4e-62859518d96b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1610614091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1610614091
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1102362512
Short name T713
Test name
Test status
Simulation time 208501744583 ps
CPU time 75.68 seconds
Started Aug 06 04:29:03 PM PDT 24
Finished Aug 06 04:30:19 PM PDT 24
Peak memory 199676 kb
Host smart-06ac7141-57c9-4493-9456-ff6bbcd858d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102362512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1102362512
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3176810144
Short name T772
Test name
Test status
Simulation time 2571803264 ps
CPU time 1.59 seconds
Started Aug 06 04:29:05 PM PDT 24
Finished Aug 06 04:29:06 PM PDT 24
Peak memory 195648 kb
Host smart-26d9935e-ac3e-4183-82a3-54222212d0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176810144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3176810144
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1128229363
Short name T1130
Test name
Test status
Simulation time 5489469267 ps
CPU time 18.06 seconds
Started Aug 06 04:29:08 PM PDT 24
Finished Aug 06 04:29:26 PM PDT 24
Peak memory 199292 kb
Host smart-652841da-8656-477f-bcb0-8ca2613df6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128229363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1128229363
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1862711235
Short name T56
Test name
Test status
Simulation time 378448649483 ps
CPU time 890.21 seconds
Started Aug 06 04:29:00 PM PDT 24
Finished Aug 06 04:43:50 PM PDT 24
Peak memory 224596 kb
Host smart-dad9531a-bb14-4037-9463-2a2afe5937e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862711235 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1862711235
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3421720011
Short name T691
Test name
Test status
Simulation time 12300871427 ps
CPU time 5.06 seconds
Started Aug 06 04:29:02 PM PDT 24
Finished Aug 06 04:29:08 PM PDT 24
Peak memory 199388 kb
Host smart-fe96607d-0f3a-4baf-9d84-720c27fcb7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421720011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3421720011
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.12682992
Short name T933
Test name
Test status
Simulation time 239820740556 ps
CPU time 226.1 seconds
Started Aug 06 04:29:05 PM PDT 24
Finished Aug 06 04:32:51 PM PDT 24
Peak memory 199588 kb
Host smart-bb327eb2-3543-4a8a-b43e-3f7b572bde90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12682992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.12682992
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.4021810827
Short name T187
Test name
Test status
Simulation time 11530294986 ps
CPU time 20.19 seconds
Started Aug 06 04:31:15 PM PDT 24
Finished Aug 06 04:31:35 PM PDT 24
Peak memory 199732 kb
Host smart-b4376e3f-4758-4dcc-8dfb-3854d5ec608a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021810827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.4021810827
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1867255775
Short name T1103
Test name
Test status
Simulation time 42336573863 ps
CPU time 13.68 seconds
Started Aug 06 04:31:17 PM PDT 24
Finished Aug 06 04:31:30 PM PDT 24
Peak memory 199696 kb
Host smart-d5cb4952-3e3d-477f-83d0-9e7fd5e40b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867255775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1867255775
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2738840518
Short name T671
Test name
Test status
Simulation time 31412734676 ps
CPU time 19.82 seconds
Started Aug 06 04:31:12 PM PDT 24
Finished Aug 06 04:31:32 PM PDT 24
Peak memory 199760 kb
Host smart-34643d7b-14e8-4b1f-830a-fa7a36bb75b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738840518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2738840518
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.796139094
Short name T45
Test name
Test status
Simulation time 75798326332 ps
CPU time 400.04 seconds
Started Aug 06 04:31:14 PM PDT 24
Finished Aug 06 04:37:54 PM PDT 24
Peak memory 199736 kb
Host smart-721d047b-a972-4c7f-ac13-cea3139deabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796139094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.796139094
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2403773148
Short name T395
Test name
Test status
Simulation time 105387305954 ps
CPU time 34.52 seconds
Started Aug 06 04:31:13 PM PDT 24
Finished Aug 06 04:31:48 PM PDT 24
Peak memory 199708 kb
Host smart-6cdfdf7b-9aa2-47c0-80e8-490c6d7c5f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403773148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2403773148
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2030552325
Short name T993
Test name
Test status
Simulation time 82245019653 ps
CPU time 28.51 seconds
Started Aug 06 04:31:12 PM PDT 24
Finished Aug 06 04:31:41 PM PDT 24
Peak memory 199736 kb
Host smart-ac28e20f-bd5b-4388-ba3d-b6e7aab98a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030552325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2030552325
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2853278278
Short name T590
Test name
Test status
Simulation time 15258827223 ps
CPU time 11.93 seconds
Started Aug 06 04:31:11 PM PDT 24
Finished Aug 06 04:31:24 PM PDT 24
Peak memory 199692 kb
Host smart-c0223d31-8953-45ea-bdb8-69f5ab4aa42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853278278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2853278278
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.102675551
Short name T226
Test name
Test status
Simulation time 83988046719 ps
CPU time 29.87 seconds
Started Aug 06 04:31:17 PM PDT 24
Finished Aug 06 04:31:47 PM PDT 24
Peak memory 199664 kb
Host smart-5ebcac3b-bedb-44a9-bbbb-2e151d26f048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102675551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.102675551
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.3268867453
Short name T640
Test name
Test status
Simulation time 93767031918 ps
CPU time 24.44 seconds
Started Aug 06 04:31:14 PM PDT 24
Finished Aug 06 04:31:39 PM PDT 24
Peak memory 199668 kb
Host smart-52d5bc27-c220-4490-9f64-8a43582b192c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268867453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3268867453
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.716466962
Short name T663
Test name
Test status
Simulation time 13980751 ps
CPU time 0.54 seconds
Started Aug 06 04:29:12 PM PDT 24
Finished Aug 06 04:29:12 PM PDT 24
Peak memory 195112 kb
Host smart-b683f7ca-be80-4fd4-9070-9015217601ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716466962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.716466962
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.944240205
Short name T899
Test name
Test status
Simulation time 228203587058 ps
CPU time 684.71 seconds
Started Aug 06 04:29:07 PM PDT 24
Finished Aug 06 04:40:32 PM PDT 24
Peak memory 199696 kb
Host smart-a0bcfbf7-333b-4612-8d23-54180e60a918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944240205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.944240205
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.4016689255
Short name T878
Test name
Test status
Simulation time 56279337511 ps
CPU time 12.67 seconds
Started Aug 06 04:29:03 PM PDT 24
Finished Aug 06 04:29:16 PM PDT 24
Peak memory 197708 kb
Host smart-2ae59af6-5309-4a8b-9fa5-ce6dd926026e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016689255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.4016689255
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1520268152
Short name T334
Test name
Test status
Simulation time 414482579106 ps
CPU time 39.29 seconds
Started Aug 06 04:29:09 PM PDT 24
Finished Aug 06 04:29:49 PM PDT 24
Peak memory 199648 kb
Host smart-e9d0d757-1c08-4f2a-aa15-ff5e7e896880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520268152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1520268152
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1461068003
Short name T393
Test name
Test status
Simulation time 15683146593 ps
CPU time 13.51 seconds
Started Aug 06 04:29:01 PM PDT 24
Finished Aug 06 04:29:14 PM PDT 24
Peak memory 199768 kb
Host smart-02c6cda2-ff0e-4473-9ceb-3e51706f6d70
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461068003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1461068003
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.4209694045
Short name T1102
Test name
Test status
Simulation time 29278277675 ps
CPU time 218.68 seconds
Started Aug 06 04:29:08 PM PDT 24
Finished Aug 06 04:32:49 PM PDT 24
Peak memory 199536 kb
Host smart-ba11c2f5-db0a-4ff0-9ab9-410d82c62482
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209694045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.4209694045
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2597194566
Short name T389
Test name
Test status
Simulation time 7193461293 ps
CPU time 12.94 seconds
Started Aug 06 04:29:08 PM PDT 24
Finished Aug 06 04:29:22 PM PDT 24
Peak memory 198576 kb
Host smart-c49c47c8-e1ad-434e-9e1a-5dc8891769ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597194566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2597194566
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1173853390
Short name T1060
Test name
Test status
Simulation time 19752483106 ps
CPU time 27.49 seconds
Started Aug 06 04:29:02 PM PDT 24
Finished Aug 06 04:29:30 PM PDT 24
Peak memory 196876 kb
Host smart-9b573ec0-31e6-43d6-9066-3ebe795f23f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173853390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1173853390
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3592337056
Short name T444
Test name
Test status
Simulation time 13303590485 ps
CPU time 377.26 seconds
Started Aug 06 04:29:09 PM PDT 24
Finished Aug 06 04:35:27 PM PDT 24
Peak memory 199660 kb
Host smart-abf60cb3-7558-40d9-8489-4a111127f40e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3592337056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3592337056
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3560075086
Short name T396
Test name
Test status
Simulation time 5030807626 ps
CPU time 37.49 seconds
Started Aug 06 04:29:09 PM PDT 24
Finished Aug 06 04:29:47 PM PDT 24
Peak memory 198996 kb
Host smart-0b85426d-e1fb-4902-b2c3-f32c85a196b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3560075086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3560075086
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1866716426
Short name T1146
Test name
Test status
Simulation time 66418738773 ps
CPU time 29.56 seconds
Started Aug 06 04:29:10 PM PDT 24
Finished Aug 06 04:29:40 PM PDT 24
Peak memory 199656 kb
Host smart-4bf4b160-9e8f-4483-8a0d-bc5f8b9c059d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866716426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1866716426
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.126470588
Short name T1063
Test name
Test status
Simulation time 5021890347 ps
CPU time 7.89 seconds
Started Aug 06 04:29:05 PM PDT 24
Finished Aug 06 04:29:13 PM PDT 24
Peak memory 196196 kb
Host smart-0c4278f0-b5f0-4fc4-b1e8-d3a5e508b88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126470588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.126470588
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3933019474
Short name T310
Test name
Test status
Simulation time 783362580 ps
CPU time 1.62 seconds
Started Aug 06 04:29:05 PM PDT 24
Finished Aug 06 04:29:07 PM PDT 24
Peak memory 198640 kb
Host smart-a7048a38-a332-47de-a6ec-907dd2d59b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933019474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3933019474
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.837807920
Short name T812
Test name
Test status
Simulation time 334990433158 ps
CPU time 106.04 seconds
Started Aug 06 04:29:14 PM PDT 24
Finished Aug 06 04:31:00 PM PDT 24
Peak memory 208068 kb
Host smart-9f6ac852-2aee-4215-b965-b9d81c57a640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837807920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.837807920
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1785196685
Short name T176
Test name
Test status
Simulation time 23930962819 ps
CPU time 223.9 seconds
Started Aug 06 04:29:08 PM PDT 24
Finished Aug 06 04:32:52 PM PDT 24
Peak memory 216256 kb
Host smart-bc757a58-56f4-48b2-a3a3-ac94e1075e8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785196685 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1785196685
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1147653399
Short name T754
Test name
Test status
Simulation time 5161570442 ps
CPU time 1.48 seconds
Started Aug 06 04:29:10 PM PDT 24
Finished Aug 06 04:29:11 PM PDT 24
Peak memory 199360 kb
Host smart-74c9b2d8-67af-4489-8ec1-d35c99d959c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147653399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1147653399
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2293582503
Short name T929
Test name
Test status
Simulation time 73517427854 ps
CPU time 115.25 seconds
Started Aug 06 04:29:10 PM PDT 24
Finished Aug 06 04:31:05 PM PDT 24
Peak memory 199668 kb
Host smart-61144f3b-cf79-4291-ac86-156f43f4fd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293582503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2293582503
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2916118820
Short name T625
Test name
Test status
Simulation time 268961747802 ps
CPU time 47.64 seconds
Started Aug 06 04:31:15 PM PDT 24
Finished Aug 06 04:32:03 PM PDT 24
Peak memory 199648 kb
Host smart-1ae5daf5-abf5-4774-90f7-34530540dd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916118820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2916118820
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.511980516
Short name T547
Test name
Test status
Simulation time 9656279134 ps
CPU time 15.86 seconds
Started Aug 06 04:31:14 PM PDT 24
Finished Aug 06 04:31:30 PM PDT 24
Peak memory 199772 kb
Host smart-ecf85fd3-bd17-42e8-b935-90814fd10469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511980516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.511980516
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.617575506
Short name T777
Test name
Test status
Simulation time 111414828928 ps
CPU time 164.51 seconds
Started Aug 06 04:31:13 PM PDT 24
Finished Aug 06 04:33:58 PM PDT 24
Peak memory 199752 kb
Host smart-163d5aaa-1e27-41de-869c-45afc71be86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617575506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.617575506
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3020578616
Short name T127
Test name
Test status
Simulation time 47551551303 ps
CPU time 315.92 seconds
Started Aug 06 04:31:14 PM PDT 24
Finished Aug 06 04:36:30 PM PDT 24
Peak memory 199732 kb
Host smart-71fa7d44-5464-49df-9c62-ae218a6f74a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020578616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3020578616
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3272063513
Short name T612
Test name
Test status
Simulation time 106548650349 ps
CPU time 42.11 seconds
Started Aug 06 04:31:14 PM PDT 24
Finished Aug 06 04:31:57 PM PDT 24
Peak memory 199592 kb
Host smart-b43216d2-1d4c-4857-a11d-c79a331a6e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272063513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3272063513
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.234873481
Short name T213
Test name
Test status
Simulation time 92603756028 ps
CPU time 37.8 seconds
Started Aug 06 04:31:15 PM PDT 24
Finished Aug 06 04:31:53 PM PDT 24
Peak memory 199580 kb
Host smart-cb7928c9-0b0b-41cd-934a-eb6b5634fa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234873481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.234873481
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.949099387
Short name T893
Test name
Test status
Simulation time 50689060307 ps
CPU time 67.2 seconds
Started Aug 06 04:31:16 PM PDT 24
Finished Aug 06 04:32:23 PM PDT 24
Peak memory 199748 kb
Host smart-5eb07650-c377-4947-a322-58670e0a3780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949099387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.949099387
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.350936623
Short name T554
Test name
Test status
Simulation time 14516957 ps
CPU time 0.54 seconds
Started Aug 06 04:29:14 PM PDT 24
Finished Aug 06 04:29:15 PM PDT 24
Peak memory 194484 kb
Host smart-6e26f8cc-f038-49c3-b070-1346a779b0b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350936623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.350936623
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.2999410600
Short name T253
Test name
Test status
Simulation time 32463042778 ps
CPU time 47.82 seconds
Started Aug 06 04:29:19 PM PDT 24
Finished Aug 06 04:30:07 PM PDT 24
Peak memory 199740 kb
Host smart-3394cd87-f527-4ae1-a0d0-1b2a27d8905c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999410600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2999410600
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2068458413
Short name T785
Test name
Test status
Simulation time 70066298021 ps
CPU time 111.54 seconds
Started Aug 06 04:29:09 PM PDT 24
Finished Aug 06 04:31:01 PM PDT 24
Peak memory 199712 kb
Host smart-1363dfaa-6961-4ece-a511-c400eadc681f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068458413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2068458413
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.19657243
Short name T723
Test name
Test status
Simulation time 18087646452 ps
CPU time 14.11 seconds
Started Aug 06 04:29:07 PM PDT 24
Finished Aug 06 04:29:22 PM PDT 24
Peak memory 199648 kb
Host smart-a4bd5481-ca6b-43d5-9714-0b9644b3f9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19657243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.19657243
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.774775810
Short name T582
Test name
Test status
Simulation time 47862923955 ps
CPU time 64.54 seconds
Started Aug 06 04:29:07 PM PDT 24
Finished Aug 06 04:30:12 PM PDT 24
Peak memory 199744 kb
Host smart-bbde8bf0-9877-4584-8d75-5dbf8a11cc06
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774775810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.774775810
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3917328755
Short name T526
Test name
Test status
Simulation time 102280443772 ps
CPU time 328.29 seconds
Started Aug 06 04:29:13 PM PDT 24
Finished Aug 06 04:34:41 PM PDT 24
Peak memory 199752 kb
Host smart-124c6513-2b82-4f17-b4d8-2b78e68cac3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3917328755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3917328755
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1943711005
Short name T351
Test name
Test status
Simulation time 12316978467 ps
CPU time 46.22 seconds
Started Aug 06 04:29:07 PM PDT 24
Finished Aug 06 04:29:53 PM PDT 24
Peak memory 199752 kb
Host smart-3ddd5290-26f9-4cdd-bd6a-89b4c7381988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943711005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1943711005
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.1585803227
Short name T250
Test name
Test status
Simulation time 131779075541 ps
CPU time 155.77 seconds
Started Aug 06 04:29:09 PM PDT 24
Finished Aug 06 04:31:46 PM PDT 24
Peak memory 199916 kb
Host smart-2f8afdb6-47f1-4517-8dc3-92f98c4a0e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585803227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1585803227
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.4185093077
Short name T979
Test name
Test status
Simulation time 9083286333 ps
CPU time 505.71 seconds
Started Aug 06 04:29:08 PM PDT 24
Finished Aug 06 04:37:33 PM PDT 24
Peak memory 199732 kb
Host smart-db4e150a-e5f5-4be1-9aca-9e1e7135ec5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4185093077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.4185093077
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.744213454
Short name T644
Test name
Test status
Simulation time 4707370720 ps
CPU time 35.45 seconds
Started Aug 06 04:29:17 PM PDT 24
Finished Aug 06 04:29:53 PM PDT 24
Peak memory 198888 kb
Host smart-03157f4b-72ff-471e-b6a3-a249bf291423
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=744213454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.744213454
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1513708700
Short name T483
Test name
Test status
Simulation time 57402326972 ps
CPU time 25.53 seconds
Started Aug 06 04:29:06 PM PDT 24
Finished Aug 06 04:29:32 PM PDT 24
Peak memory 199616 kb
Host smart-0d42165b-03b7-4cc0-872b-e5a4b3a96495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513708700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1513708700
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.593995377
Short name T619
Test name
Test status
Simulation time 3143691042 ps
CPU time 1.84 seconds
Started Aug 06 04:29:11 PM PDT 24
Finished Aug 06 04:29:13 PM PDT 24
Peak memory 196344 kb
Host smart-0f47ef5e-81aa-41e0-81d8-91468dff5b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593995377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.593995377
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.893749391
Short name T407
Test name
Test status
Simulation time 539051963 ps
CPU time 1.14 seconds
Started Aug 06 04:29:09 PM PDT 24
Finished Aug 06 04:29:11 PM PDT 24
Peak memory 198380 kb
Host smart-4048b960-954b-4654-a019-79344c0c3d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893749391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.893749391
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3590804719
Short name T686
Test name
Test status
Simulation time 136645021916 ps
CPU time 214.72 seconds
Started Aug 06 04:29:14 PM PDT 24
Finished Aug 06 04:32:49 PM PDT 24
Peak memory 208132 kb
Host smart-68ce2433-1264-4930-ad58-24a671768cfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590804719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3590804719
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.416004085
Short name T335
Test name
Test status
Simulation time 35125752066 ps
CPU time 350.51 seconds
Started Aug 06 04:29:14 PM PDT 24
Finished Aug 06 04:35:05 PM PDT 24
Peak memory 216208 kb
Host smart-76471881-6ebc-4a23-a842-2e27a683ac45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416004085 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.416004085
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.593465348
Short name T599
Test name
Test status
Simulation time 426331736 ps
CPU time 1.89 seconds
Started Aug 06 04:29:09 PM PDT 24
Finished Aug 06 04:29:12 PM PDT 24
Peak memory 198140 kb
Host smart-7e1f550b-9f38-47d8-9ea7-23f5d2cf46cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593465348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.593465348
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.768594012
Short name T251
Test name
Test status
Simulation time 42148299755 ps
CPU time 91.33 seconds
Started Aug 06 04:29:13 PM PDT 24
Finished Aug 06 04:30:50 PM PDT 24
Peak memory 199712 kb
Host smart-0e836631-fc23-4d27-af20-3f6a0083d6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768594012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.768594012
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.4205519950
Short name T308
Test name
Test status
Simulation time 63803798653 ps
CPU time 48.13 seconds
Started Aug 06 04:31:15 PM PDT 24
Finished Aug 06 04:32:03 PM PDT 24
Peak memory 199700 kb
Host smart-22b8b4f2-9449-4967-88ce-d3390174dc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205519950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.4205519950
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2893031045
Short name T1054
Test name
Test status
Simulation time 181704102246 ps
CPU time 280.13 seconds
Started Aug 06 04:31:14 PM PDT 24
Finished Aug 06 04:35:54 PM PDT 24
Peak memory 199692 kb
Host smart-1574a779-fe09-47f5-9bad-e0c395b0a873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893031045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2893031045
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1901201144
Short name T990
Test name
Test status
Simulation time 121284574633 ps
CPU time 190.75 seconds
Started Aug 06 04:31:15 PM PDT 24
Finished Aug 06 04:34:26 PM PDT 24
Peak memory 199664 kb
Host smart-5da76c53-43c6-4ad4-a727-065bdb80e0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901201144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1901201144
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1932799466
Short name T248
Test name
Test status
Simulation time 85777009967 ps
CPU time 97.48 seconds
Started Aug 06 04:31:20 PM PDT 24
Finished Aug 06 04:32:57 PM PDT 24
Peak memory 199504 kb
Host smart-5613312f-3ffa-435c-8fa3-09656e6f8d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932799466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1932799466
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3867393192
Short name T123
Test name
Test status
Simulation time 35258799453 ps
CPU time 15.88 seconds
Started Aug 06 04:31:18 PM PDT 24
Finished Aug 06 04:31:34 PM PDT 24
Peak memory 199648 kb
Host smart-67fd00c1-180e-4a8e-a7e4-88026b9c3d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867393192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3867393192
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1019591755
Short name T956
Test name
Test status
Simulation time 164724680486 ps
CPU time 282.01 seconds
Started Aug 06 04:31:19 PM PDT 24
Finished Aug 06 04:36:02 PM PDT 24
Peak memory 199648 kb
Host smart-dae56722-66a9-4256-a102-efaee45aa385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019591755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1019591755
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.510631818
Short name T1051
Test name
Test status
Simulation time 116142722449 ps
CPU time 58.82 seconds
Started Aug 06 04:31:17 PM PDT 24
Finished Aug 06 04:32:16 PM PDT 24
Peak memory 199748 kb
Host smart-8cba2a07-660f-4ba3-966b-505e9f8d6ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510631818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.510631818
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2933453869
Short name T827
Test name
Test status
Simulation time 52530551008 ps
CPU time 144.22 seconds
Started Aug 06 04:31:24 PM PDT 24
Finished Aug 06 04:33:48 PM PDT 24
Peak memory 199780 kb
Host smart-2946213a-6d2c-4425-b85e-08156269bf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933453869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2933453869
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.4067512682
Short name T345
Test name
Test status
Simulation time 19717255458 ps
CPU time 15.24 seconds
Started Aug 06 04:31:20 PM PDT 24
Finished Aug 06 04:31:35 PM PDT 24
Peak memory 199560 kb
Host smart-f34e13e5-da48-4529-84ba-c874fb317bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067512682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.4067512682
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.2418857221
Short name T986
Test name
Test status
Simulation time 13053930958 ps
CPU time 22.21 seconds
Started Aug 06 04:31:31 PM PDT 24
Finished Aug 06 04:31:53 PM PDT 24
Peak memory 199748 kb
Host smart-589c1119-b37d-4179-b6b2-28b9ad2f4a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418857221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2418857221
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.2772257048
Short name T418
Test name
Test status
Simulation time 17869245 ps
CPU time 0.51 seconds
Started Aug 06 04:29:12 PM PDT 24
Finished Aug 06 04:29:12 PM PDT 24
Peak memory 195412 kb
Host smart-b169d0b5-7283-4333-9e02-14aef5aa7f7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772257048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2772257048
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3789548431
Short name T410
Test name
Test status
Simulation time 14822351344 ps
CPU time 39.32 seconds
Started Aug 06 04:29:08 PM PDT 24
Finished Aug 06 04:29:47 PM PDT 24
Peak memory 199688 kb
Host smart-cf65ef96-01d8-4398-bdff-86f37295d6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789548431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3789548431
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2887767784
Short name T249
Test name
Test status
Simulation time 24044901183 ps
CPU time 47.25 seconds
Started Aug 06 04:29:07 PM PDT 24
Finished Aug 06 04:29:55 PM PDT 24
Peak memory 199672 kb
Host smart-ea87667c-5981-46ba-b483-f25b71cec18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887767784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2887767784
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.4261623434
Short name T220
Test name
Test status
Simulation time 16930656133 ps
CPU time 31.26 seconds
Started Aug 06 04:29:12 PM PDT 24
Finished Aug 06 04:29:43 PM PDT 24
Peak memory 199720 kb
Host smart-50e11094-46da-4880-8a7e-9509d77f6644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261623434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.4261623434
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1436343032
Short name T744
Test name
Test status
Simulation time 46517752403 ps
CPU time 46.69 seconds
Started Aug 06 04:29:10 PM PDT 24
Finished Aug 06 04:29:57 PM PDT 24
Peak memory 199600 kb
Host smart-dac5fe0c-69e4-4ff3-92a6-ce51d6d3cef7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436343032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1436343032
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.4237786336
Short name T457
Test name
Test status
Simulation time 73509294342 ps
CPU time 312.78 seconds
Started Aug 06 04:29:10 PM PDT 24
Finished Aug 06 04:34:23 PM PDT 24
Peak memory 199720 kb
Host smart-50ac606d-5db6-4c8f-aaab-9ab1d85c3069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4237786336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.4237786336
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3440604302
Short name T350
Test name
Test status
Simulation time 1502050842 ps
CPU time 2.89 seconds
Started Aug 06 04:29:30 PM PDT 24
Finished Aug 06 04:29:33 PM PDT 24
Peak memory 197084 kb
Host smart-feae2340-6d43-47ff-b73f-b4aef04e4746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440604302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3440604302
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.4292945621
Short name T408
Test name
Test status
Simulation time 32782430267 ps
CPU time 55.17 seconds
Started Aug 06 04:29:14 PM PDT 24
Finished Aug 06 04:30:09 PM PDT 24
Peak memory 199816 kb
Host smart-178f785b-e1b9-4704-86b5-9aa7c378a590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292945621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.4292945621
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1611531612
Short name T1155
Test name
Test status
Simulation time 18588357763 ps
CPU time 196.02 seconds
Started Aug 06 04:29:12 PM PDT 24
Finished Aug 06 04:32:33 PM PDT 24
Peak memory 199512 kb
Host smart-4bde70f0-de73-49b3-8547-17852de79f3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611531612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1611531612
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1910065424
Short name T862
Test name
Test status
Simulation time 1983977844 ps
CPU time 1.37 seconds
Started Aug 06 04:29:12 PM PDT 24
Finished Aug 06 04:29:13 PM PDT 24
Peak memory 198452 kb
Host smart-26e6c288-a59e-45c4-9819-218ba154a27b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1910065424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1910065424
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2650495891
Short name T560
Test name
Test status
Simulation time 15320089908 ps
CPU time 23.71 seconds
Started Aug 06 04:29:12 PM PDT 24
Finished Aug 06 04:29:35 PM PDT 24
Peak memory 199656 kb
Host smart-6f3c4671-d6f6-4009-9f21-4734f3355298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650495891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2650495891
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3234421045
Short name T92
Test name
Test status
Simulation time 41478491427 ps
CPU time 56.31 seconds
Started Aug 06 04:29:13 PM PDT 24
Finished Aug 06 04:30:09 PM PDT 24
Peak memory 195748 kb
Host smart-b2c449e8-604e-4cef-a3f1-b650d538f29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234421045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3234421045
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2954790691
Short name T635
Test name
Test status
Simulation time 5376834670 ps
CPU time 31.33 seconds
Started Aug 06 04:29:14 PM PDT 24
Finished Aug 06 04:29:45 PM PDT 24
Peak memory 199472 kb
Host smart-e3623222-58f3-4255-b18d-8f50e19a5031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954790691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2954790691
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.58803005
Short name T736
Test name
Test status
Simulation time 165551027236 ps
CPU time 250.23 seconds
Started Aug 06 04:29:09 PM PDT 24
Finished Aug 06 04:33:20 PM PDT 24
Peak memory 208116 kb
Host smart-2f57bb9b-03da-44e0-ab52-475ba50461f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58803005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.58803005
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2011930283
Short name T455
Test name
Test status
Simulation time 1726038750 ps
CPU time 2 seconds
Started Aug 06 04:29:08 PM PDT 24
Finished Aug 06 04:29:10 PM PDT 24
Peak memory 198224 kb
Host smart-81686ca1-d2b1-4bf2-b2bf-87bfa81a7f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011930283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2011930283
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3782381420
Short name T741
Test name
Test status
Simulation time 121954917491 ps
CPU time 20.08 seconds
Started Aug 06 04:29:14 PM PDT 24
Finished Aug 06 04:29:34 PM PDT 24
Peak memory 199676 kb
Host smart-d31fe482-47ae-4767-bca9-be4dbfcb8627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782381420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3782381420
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2872608262
Short name T806
Test name
Test status
Simulation time 35398007450 ps
CPU time 18.88 seconds
Started Aug 06 04:31:34 PM PDT 24
Finished Aug 06 04:31:53 PM PDT 24
Peak memory 199760 kb
Host smart-2eb9ffe5-ac18-4610-8a49-f105985f278a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872608262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2872608262
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.4077650074
Short name T349
Test name
Test status
Simulation time 114732026780 ps
CPU time 85.97 seconds
Started Aug 06 04:31:34 PM PDT 24
Finished Aug 06 04:33:00 PM PDT 24
Peak memory 199760 kb
Host smart-5e83e922-3587-4c3d-ac15-97c6109023f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077650074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.4077650074
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3407567610
Short name T1152
Test name
Test status
Simulation time 14661891408 ps
CPU time 26.81 seconds
Started Aug 06 04:31:30 PM PDT 24
Finished Aug 06 04:31:57 PM PDT 24
Peak memory 199668 kb
Host smart-382dbbfa-f517-4e70-8c07-ed42b076d397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407567610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3407567610
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1872018275
Short name T471
Test name
Test status
Simulation time 16305976328 ps
CPU time 6.73 seconds
Started Aug 06 04:31:32 PM PDT 24
Finished Aug 06 04:31:39 PM PDT 24
Peak memory 199676 kb
Host smart-82289ade-3acd-4f91-8f90-71c10f854a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872018275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1872018275
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3578682687
Short name T321
Test name
Test status
Simulation time 60508043243 ps
CPU time 117.04 seconds
Started Aug 06 04:31:32 PM PDT 24
Finished Aug 06 04:33:29 PM PDT 24
Peak memory 199728 kb
Host smart-b4e317de-366f-4833-8698-aac845036f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578682687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3578682687
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2978028683
Short name T190
Test name
Test status
Simulation time 42840426186 ps
CPU time 35.58 seconds
Started Aug 06 04:31:33 PM PDT 24
Finished Aug 06 04:32:08 PM PDT 24
Peak memory 200100 kb
Host smart-13228334-b061-48e6-bd8a-a0ab0ec4f8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978028683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2978028683
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1846337903
Short name T858
Test name
Test status
Simulation time 127119137801 ps
CPU time 267.89 seconds
Started Aug 06 04:31:31 PM PDT 24
Finished Aug 06 04:35:59 PM PDT 24
Peak memory 199752 kb
Host smart-467ac49f-09bd-4064-94f3-bff6a5b00073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846337903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1846337903
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1159768889
Short name T974
Test name
Test status
Simulation time 25757482796 ps
CPU time 11.89 seconds
Started Aug 06 04:31:34 PM PDT 24
Finished Aug 06 04:31:46 PM PDT 24
Peak memory 199536 kb
Host smart-f8aff89c-8740-4a06-ad08-fdb66d51ff1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159768889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1159768889
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2422837271
Short name T913
Test name
Test status
Simulation time 22300118 ps
CPU time 0.55 seconds
Started Aug 06 04:29:09 PM PDT 24
Finished Aug 06 04:29:09 PM PDT 24
Peak memory 194072 kb
Host smart-956d4d76-3aeb-49a3-b69a-0465e953b697
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422837271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2422837271
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2671867253
Short name T273
Test name
Test status
Simulation time 46117128339 ps
CPU time 60.59 seconds
Started Aug 06 04:29:10 PM PDT 24
Finished Aug 06 04:30:10 PM PDT 24
Peak memory 199712 kb
Host smart-187ae07b-2709-4161-84e7-c1686701eb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671867253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2671867253
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3756302372
Short name T481
Test name
Test status
Simulation time 34427725887 ps
CPU time 29.42 seconds
Started Aug 06 04:29:14 PM PDT 24
Finished Aug 06 04:29:44 PM PDT 24
Peak memory 199696 kb
Host smart-9250b20b-8024-4c90-95f0-f7e65cc44d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756302372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3756302372
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3280391869
Short name T1092
Test name
Test status
Simulation time 47566791315 ps
CPU time 79.03 seconds
Started Aug 06 04:29:14 PM PDT 24
Finished Aug 06 04:30:33 PM PDT 24
Peak memory 199728 kb
Host smart-b560d9fa-94e6-485d-885e-710a355b1000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280391869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3280391869
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2732901740
Short name T613
Test name
Test status
Simulation time 13936323413 ps
CPU time 26.18 seconds
Started Aug 06 04:29:14 PM PDT 24
Finished Aug 06 04:29:40 PM PDT 24
Peak memory 199604 kb
Host smart-08a9deaf-0e33-4cd3-8815-985ecb250cde
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732901740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2732901740
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2152900165
Short name T807
Test name
Test status
Simulation time 268470401847 ps
CPU time 195.35 seconds
Started Aug 06 04:29:13 PM PDT 24
Finished Aug 06 04:32:28 PM PDT 24
Peak memory 199608 kb
Host smart-675cbe48-bdf0-4929-a606-fdd46bf8a343
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2152900165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2152900165
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.797273964
Short name T403
Test name
Test status
Simulation time 7218069953 ps
CPU time 8.5 seconds
Started Aug 06 04:29:07 PM PDT 24
Finished Aug 06 04:29:16 PM PDT 24
Peak memory 199756 kb
Host smart-26b91caa-a944-44bb-a1fc-1eaf8b2270f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797273964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.797273964
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.992908720
Short name T1056
Test name
Test status
Simulation time 68303202989 ps
CPU time 68.54 seconds
Started Aug 06 04:29:09 PM PDT 24
Finished Aug 06 04:30:17 PM PDT 24
Peak memory 199916 kb
Host smart-9c682c45-fffb-427c-9016-9cf7ba6be303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992908720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.992908720
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2355919625
Short name T496
Test name
Test status
Simulation time 7412420721 ps
CPU time 24.09 seconds
Started Aug 06 04:29:12 PM PDT 24
Finished Aug 06 04:29:36 PM PDT 24
Peak memory 199612 kb
Host smart-270f5dda-4f28-493a-860d-81a372a97d41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2355919625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2355919625
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2521642793
Short name T1081
Test name
Test status
Simulation time 6411953696 ps
CPU time 15.38 seconds
Started Aug 06 04:29:10 PM PDT 24
Finished Aug 06 04:29:26 PM PDT 24
Peak memory 197840 kb
Host smart-6db27fb9-9995-4e76-988c-f02f96d23d14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521642793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2521642793
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.4175040977
Short name T117
Test name
Test status
Simulation time 85849713518 ps
CPU time 45.67 seconds
Started Aug 06 04:29:18 PM PDT 24
Finished Aug 06 04:30:04 PM PDT 24
Peak memory 199388 kb
Host smart-76803169-ebe6-4b43-839e-4e8d912e6ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175040977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.4175040977
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.4109326300
Short name T414
Test name
Test status
Simulation time 4416083555 ps
CPU time 3.96 seconds
Started Aug 06 04:29:10 PM PDT 24
Finished Aug 06 04:29:14 PM PDT 24
Peak memory 196284 kb
Host smart-a4fed685-fa54-448a-ab9c-8230748cadc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109326300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.4109326300
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2855796772
Short name T1139
Test name
Test status
Simulation time 646234996 ps
CPU time 3.65 seconds
Started Aug 06 04:29:08 PM PDT 24
Finished Aug 06 04:29:12 PM PDT 24
Peak memory 199484 kb
Host smart-99f8d684-93bb-43e5-bd7c-9f3af88af7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855796772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2855796772
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3624679237
Short name T107
Test name
Test status
Simulation time 401315606563 ps
CPU time 207.91 seconds
Started Aug 06 04:29:13 PM PDT 24
Finished Aug 06 04:32:41 PM PDT 24
Peak memory 199764 kb
Host smart-6a22b557-aa86-4f74-a960-57872da6ca51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624679237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3624679237
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.129130349
Short name T735
Test name
Test status
Simulation time 339584394098 ps
CPU time 884.36 seconds
Started Aug 06 04:29:14 PM PDT 24
Finished Aug 06 04:43:58 PM PDT 24
Peak memory 230736 kb
Host smart-fca83546-a636-4519-866f-62c6a21b6ec1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129130349 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.129130349
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1720781618
Short name T371
Test name
Test status
Simulation time 803469140 ps
CPU time 1.47 seconds
Started Aug 06 04:29:08 PM PDT 24
Finished Aug 06 04:29:09 PM PDT 24
Peak memory 197780 kb
Host smart-e0e76861-f11a-4b84-aefc-886647ba25c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720781618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1720781618
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1340954887
Short name T318
Test name
Test status
Simulation time 56776872756 ps
CPU time 49.51 seconds
Started Aug 06 04:29:09 PM PDT 24
Finished Aug 06 04:29:59 PM PDT 24
Peak memory 199796 kb
Host smart-f753faba-db2e-492d-b854-a87fe36b15ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340954887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1340954887
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.3739432398
Short name T421
Test name
Test status
Simulation time 144137618138 ps
CPU time 15.55 seconds
Started Aug 06 04:31:32 PM PDT 24
Finished Aug 06 04:31:47 PM PDT 24
Peak memory 198664 kb
Host smart-66fa91a8-20b3-4abe-b089-c3209e693d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739432398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3739432398
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.268383051
Short name T1025
Test name
Test status
Simulation time 27099537092 ps
CPU time 49.06 seconds
Started Aug 06 04:31:31 PM PDT 24
Finished Aug 06 04:32:20 PM PDT 24
Peak memory 199760 kb
Host smart-17f9b93f-81b3-4d7d-aed1-bd901e702455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268383051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.268383051
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3685613661
Short name T181
Test name
Test status
Simulation time 48807578878 ps
CPU time 18.1 seconds
Started Aug 06 04:31:32 PM PDT 24
Finished Aug 06 04:31:51 PM PDT 24
Peak memory 199652 kb
Host smart-823d88de-cfbf-4041-b812-33e2c604839a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685613661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3685613661
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1025516300
Short name T328
Test name
Test status
Simulation time 191493114773 ps
CPU time 83.38 seconds
Started Aug 06 04:31:30 PM PDT 24
Finished Aug 06 04:32:54 PM PDT 24
Peak memory 199720 kb
Host smart-fd2b2131-4361-46e1-bb14-da0e896037fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025516300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1025516300
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2931046606
Short name T216
Test name
Test status
Simulation time 67686845363 ps
CPU time 24.22 seconds
Started Aug 06 04:31:33 PM PDT 24
Finished Aug 06 04:31:57 PM PDT 24
Peak memory 199744 kb
Host smart-80b4b412-8818-47ca-a13b-82c4f7a62bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931046606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2931046606
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1510116152
Short name T120
Test name
Test status
Simulation time 88788527279 ps
CPU time 38.44 seconds
Started Aug 06 04:31:30 PM PDT 24
Finished Aug 06 04:32:09 PM PDT 24
Peak memory 199748 kb
Host smart-e1c55e10-3c4c-4f00-9cb9-3450e1ffed20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510116152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1510116152
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2489010616
Short name T581
Test name
Test status
Simulation time 137701615828 ps
CPU time 82.73 seconds
Started Aug 06 04:31:34 PM PDT 24
Finished Aug 06 04:32:57 PM PDT 24
Peak memory 199760 kb
Host smart-5b3b99a8-c3a9-4177-a38a-357f3f378705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489010616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2489010616
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.612491027
Short name T234
Test name
Test status
Simulation time 31811297953 ps
CPU time 22.14 seconds
Started Aug 06 04:31:30 PM PDT 24
Finished Aug 06 04:31:53 PM PDT 24
Peak memory 198884 kb
Host smart-52fbe019-9130-46ab-aabd-cc5fc61b8ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612491027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.612491027
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3107112118
Short name T960
Test name
Test status
Simulation time 14104854 ps
CPU time 0.57 seconds
Started Aug 06 04:28:14 PM PDT 24
Finished Aug 06 04:28:15 PM PDT 24
Peak memory 195104 kb
Host smart-84273c5a-0f41-40f8-a602-b012d1d5c340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107112118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3107112118
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3682393689
Short name T1032
Test name
Test status
Simulation time 107826840356 ps
CPU time 42.77 seconds
Started Aug 06 04:28:03 PM PDT 24
Finished Aug 06 04:28:46 PM PDT 24
Peak memory 199700 kb
Host smart-1b9e9196-dcd6-43cd-bf5d-5e7d12915789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682393689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3682393689
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.3563791293
Short name T189
Test name
Test status
Simulation time 298184113864 ps
CPU time 111.6 seconds
Started Aug 06 04:28:04 PM PDT 24
Finished Aug 06 04:29:56 PM PDT 24
Peak memory 199712 kb
Host smart-6818ea33-4052-406b-8498-780a1fd75d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563791293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3563791293
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.3079634793
Short name T788
Test name
Test status
Simulation time 314670602976 ps
CPU time 589.25 seconds
Started Aug 06 04:28:11 PM PDT 24
Finished Aug 06 04:38:00 PM PDT 24
Peak memory 199660 kb
Host smart-9158e8fe-25c6-4b9a-89d5-7a60ecaf23e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079634793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3079634793
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1131335882
Short name T1084
Test name
Test status
Simulation time 129672350985 ps
CPU time 687.63 seconds
Started Aug 06 04:28:08 PM PDT 24
Finished Aug 06 04:39:36 PM PDT 24
Peak memory 199724 kb
Host smart-2f6235d1-5bad-443e-9f8f-660877700a06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1131335882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1131335882
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.731777207
Short name T387
Test name
Test status
Simulation time 11680509506 ps
CPU time 7.61 seconds
Started Aug 06 04:28:15 PM PDT 24
Finished Aug 06 04:28:23 PM PDT 24
Peak memory 199336 kb
Host smart-811497f1-7aa3-42f4-aa94-6bb2b2524cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731777207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.731777207
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.2192000905
Short name T1170
Test name
Test status
Simulation time 73960657043 ps
CPU time 30.34 seconds
Started Aug 06 04:28:58 PM PDT 24
Finished Aug 06 04:29:29 PM PDT 24
Peak memory 196528 kb
Host smart-233d8364-d023-4791-aeda-e16acc7d233d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192000905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2192000905
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3856742634
Short name T1117
Test name
Test status
Simulation time 23135569156 ps
CPU time 106.38 seconds
Started Aug 06 04:28:13 PM PDT 24
Finished Aug 06 04:29:59 PM PDT 24
Peak memory 199616 kb
Host smart-2df4bab6-5dc5-4a09-b2b6-8c2a95c20ae6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856742634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3856742634
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2081854842
Short name T358
Test name
Test status
Simulation time 2992552283 ps
CPU time 3.21 seconds
Started Aug 06 04:28:03 PM PDT 24
Finished Aug 06 04:28:06 PM PDT 24
Peak memory 198228 kb
Host smart-7d7c0e70-00cd-45a2-a933-459adc3506c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2081854842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2081854842
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3716029733
Short name T822
Test name
Test status
Simulation time 4825267947 ps
CPU time 1.68 seconds
Started Aug 06 04:28:11 PM PDT 24
Finished Aug 06 04:28:13 PM PDT 24
Peak memory 196060 kb
Host smart-d05e9286-f79f-4847-8810-cc8633d2ad6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716029733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3716029733
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3429179824
Short name T86
Test name
Test status
Simulation time 230993024 ps
CPU time 0.84 seconds
Started Aug 06 04:28:23 PM PDT 24
Finished Aug 06 04:28:24 PM PDT 24
Peak memory 218060 kb
Host smart-d3385098-cbe5-4506-94ed-39cddcdc78cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429179824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3429179824
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3440191486
Short name T319
Test name
Test status
Simulation time 503855903 ps
CPU time 2 seconds
Started Aug 06 04:28:01 PM PDT 24
Finished Aug 06 04:28:04 PM PDT 24
Peak memory 197968 kb
Host smart-5c07d3ee-b231-4fef-b311-13dbe22d8d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440191486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3440191486
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.3313909920
Short name T783
Test name
Test status
Simulation time 454449663850 ps
CPU time 694.54 seconds
Started Aug 06 04:28:09 PM PDT 24
Finished Aug 06 04:39:43 PM PDT 24
Peak memory 200140 kb
Host smart-1b3a9f20-e4b1-477e-bc60-670e6af14569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313909920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3313909920
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2618638938
Short name T859
Test name
Test status
Simulation time 37476247270 ps
CPU time 310.23 seconds
Started Aug 06 04:28:25 PM PDT 24
Finished Aug 06 04:33:35 PM PDT 24
Peak memory 215608 kb
Host smart-fa830e7e-3242-4061-83fb-bf28fa3fc860
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618638938 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2618638938
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2623180824
Short name T787
Test name
Test status
Simulation time 6773452825 ps
CPU time 19.07 seconds
Started Aug 06 04:28:03 PM PDT 24
Finished Aug 06 04:28:22 PM PDT 24
Peak memory 199456 kb
Host smart-3edb9495-3e20-49a6-99e6-3d9d0e3bf111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623180824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2623180824
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2241306902
Short name T280
Test name
Test status
Simulation time 118490314513 ps
CPU time 117.1 seconds
Started Aug 06 04:28:09 PM PDT 24
Finished Aug 06 04:30:06 PM PDT 24
Peak memory 199688 kb
Host smart-8e9109ce-1c09-4a22-a264-172504d87e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241306902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2241306902
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2502721529
Short name T966
Test name
Test status
Simulation time 19519696 ps
CPU time 0.6 seconds
Started Aug 06 04:29:18 PM PDT 24
Finished Aug 06 04:29:19 PM PDT 24
Peak memory 194596 kb
Host smart-32f09d92-3c8b-4e7e-b2f1-5fbd93dc2437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502721529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2502721529
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.4162141399
Short name T871
Test name
Test status
Simulation time 217368453478 ps
CPU time 105.35 seconds
Started Aug 06 04:29:12 PM PDT 24
Finished Aug 06 04:30:57 PM PDT 24
Peak memory 199656 kb
Host smart-3257f13d-fc66-462e-9c10-0c240fc8d6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162141399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.4162141399
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.612694347
Short name T500
Test name
Test status
Simulation time 99853963024 ps
CPU time 35.22 seconds
Started Aug 06 04:29:12 PM PDT 24
Finished Aug 06 04:29:53 PM PDT 24
Peak memory 199688 kb
Host smart-934283d2-ce29-4692-8177-8d6957b558c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612694347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.612694347
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.4121257439
Short name T478
Test name
Test status
Simulation time 197973410541 ps
CPU time 43.94 seconds
Started Aug 06 04:29:07 PM PDT 24
Finished Aug 06 04:29:51 PM PDT 24
Peak memory 199692 kb
Host smart-d0e33752-7397-47c5-bd09-1ad0fee61c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121257439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.4121257439
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.493167208
Short name T626
Test name
Test status
Simulation time 15478895241 ps
CPU time 29.15 seconds
Started Aug 06 04:29:08 PM PDT 24
Finished Aug 06 04:29:37 PM PDT 24
Peak memory 199624 kb
Host smart-8a3ff530-d0b6-481f-8561-1053d8972061
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493167208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.493167208
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3574144209
Short name T558
Test name
Test status
Simulation time 66387621333 ps
CPU time 220.78 seconds
Started Aug 06 04:29:14 PM PDT 24
Finished Aug 06 04:32:55 PM PDT 24
Peak memory 199728 kb
Host smart-243b1931-5391-4d83-8508-0c0a6d9636af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3574144209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3574144209
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3262657830
Short name T352
Test name
Test status
Simulation time 5337955178 ps
CPU time 9.66 seconds
Started Aug 06 04:29:12 PM PDT 24
Finished Aug 06 04:29:22 PM PDT 24
Peak memory 198164 kb
Host smart-7a7c55a3-be73-4cf0-adb4-0f5c680c9259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262657830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3262657830
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3634379470
Short name T267
Test name
Test status
Simulation time 267371239665 ps
CPU time 41.42 seconds
Started Aug 06 04:29:14 PM PDT 24
Finished Aug 06 04:29:56 PM PDT 24
Peak memory 208040 kb
Host smart-d28e5622-2fe8-4aad-af22-72d4f8434238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634379470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3634379470
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.3115574940
Short name T256
Test name
Test status
Simulation time 26008380216 ps
CPU time 318.08 seconds
Started Aug 06 04:29:18 PM PDT 24
Finished Aug 06 04:34:36 PM PDT 24
Peak memory 199528 kb
Host smart-23d0cd1b-90b9-4b21-acaa-47bc90bc1597
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3115574940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3115574940
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3890985301
Short name T360
Test name
Test status
Simulation time 6307281255 ps
CPU time 5.63 seconds
Started Aug 06 04:29:13 PM PDT 24
Finished Aug 06 04:29:19 PM PDT 24
Peak memory 197724 kb
Host smart-2bae9a6a-8454-4910-8ebb-b4c81d51887f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3890985301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3890985301
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2341090073
Short name T959
Test name
Test status
Simulation time 36578368282 ps
CPU time 52.46 seconds
Started Aug 06 04:29:10 PM PDT 24
Finished Aug 06 04:30:03 PM PDT 24
Peak memory 199712 kb
Host smart-c9020f63-e7a1-4975-83e1-c8c8aca1988c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341090073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2341090073
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2613065849
Short name T430
Test name
Test status
Simulation time 49175640597 ps
CPU time 65.96 seconds
Started Aug 06 04:29:19 PM PDT 24
Finished Aug 06 04:30:25 PM PDT 24
Peak memory 195564 kb
Host smart-25c99f4f-8aca-4172-ac02-b6a178d04eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613065849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2613065849
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.979582259
Short name T1055
Test name
Test status
Simulation time 5916589377 ps
CPU time 18.94 seconds
Started Aug 06 04:29:12 PM PDT 24
Finished Aug 06 04:29:31 PM PDT 24
Peak memory 199748 kb
Host smart-be03bb59-34ae-4ebe-8b38-62a93c01f25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979582259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.979582259
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3992805637
Short name T1050
Test name
Test status
Simulation time 165836578454 ps
CPU time 74.57 seconds
Started Aug 06 04:29:18 PM PDT 24
Finished Aug 06 04:30:33 PM PDT 24
Peak memory 199192 kb
Host smart-d1933255-8c3e-4fb0-94a4-76e8b501d629
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992805637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3992805637
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.636095722
Short name T915
Test name
Test status
Simulation time 15080281201 ps
CPU time 100.18 seconds
Started Aug 06 04:29:12 PM PDT 24
Finished Aug 06 04:30:52 PM PDT 24
Peak memory 216412 kb
Host smart-d830bb26-09a3-4798-b8cd-d9c39c7cb99b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636095722 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.636095722
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2282418774
Short name T934
Test name
Test status
Simulation time 12728767421 ps
CPU time 23.21 seconds
Started Aug 06 04:29:18 PM PDT 24
Finished Aug 06 04:29:42 PM PDT 24
Peak memory 199684 kb
Host smart-1e390ceb-677b-4e5b-ab56-cc4f14897b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282418774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2282418774
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.193925882
Short name T511
Test name
Test status
Simulation time 36745124571 ps
CPU time 31.26 seconds
Started Aug 06 04:29:09 PM PDT 24
Finished Aug 06 04:29:41 PM PDT 24
Peak memory 199736 kb
Host smart-63781f02-e8de-4993-a380-7b59b77f4d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193925882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.193925882
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3400471648
Short name T963
Test name
Test status
Simulation time 20989730 ps
CPU time 0.59 seconds
Started Aug 06 04:29:34 PM PDT 24
Finished Aug 06 04:29:35 PM PDT 24
Peak memory 194808 kb
Host smart-d22b5b88-aace-4169-add3-ee00837983bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400471648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3400471648
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1194358985
Short name T928
Test name
Test status
Simulation time 268996082804 ps
CPU time 87.79 seconds
Started Aug 06 04:29:14 PM PDT 24
Finished Aug 06 04:30:42 PM PDT 24
Peak memory 199608 kb
Host smart-dae83186-c873-4578-baa5-fe2e03126bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194358985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1194358985
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3631963891
Short name T304
Test name
Test status
Simulation time 4777132945 ps
CPU time 8.52 seconds
Started Aug 06 04:29:08 PM PDT 24
Finished Aug 06 04:29:19 PM PDT 24
Peak memory 199580 kb
Host smart-464bfd22-e0d1-442d-bc89-c179adf89a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631963891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3631963891
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2058848414
Short name T1086
Test name
Test status
Simulation time 40843399948 ps
CPU time 16.68 seconds
Started Aug 06 04:29:16 PM PDT 24
Finished Aug 06 04:29:33 PM PDT 24
Peak memory 199564 kb
Host smart-0c42c139-2669-4039-b9b2-ce189775b613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058848414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2058848414
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3508031544
Short name T999
Test name
Test status
Simulation time 94307029780 ps
CPU time 81.08 seconds
Started Aug 06 04:29:12 PM PDT 24
Finished Aug 06 04:30:33 PM PDT 24
Peak memory 199768 kb
Host smart-29710d9f-0a89-4e32-87cd-7379cde871ed
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508031544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3508031544
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2306916359
Short name T450
Test name
Test status
Simulation time 97654843405 ps
CPU time 345.41 seconds
Started Aug 06 04:29:11 PM PDT 24
Finished Aug 06 04:34:57 PM PDT 24
Peak memory 199724 kb
Host smart-295ae80e-2342-4a32-b1af-397ed4cffa90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2306916359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2306916359
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3362777251
Short name T775
Test name
Test status
Simulation time 1361484598 ps
CPU time 2.83 seconds
Started Aug 06 04:29:16 PM PDT 24
Finished Aug 06 04:29:19 PM PDT 24
Peak memory 195048 kb
Host smart-3b676246-6f76-40dc-b399-dd9ea2782bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362777251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3362777251
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.4244308280
Short name T261
Test name
Test status
Simulation time 188407902740 ps
CPU time 74.05 seconds
Started Aug 06 04:29:16 PM PDT 24
Finished Aug 06 04:30:30 PM PDT 24
Peak memory 199340 kb
Host smart-c9c26c19-4949-4970-8c0f-979c344e072d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244308280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.4244308280
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1076033676
Short name T784
Test name
Test status
Simulation time 22800702966 ps
CPU time 967.94 seconds
Started Aug 06 04:29:16 PM PDT 24
Finished Aug 06 04:45:24 PM PDT 24
Peak memory 199696 kb
Host smart-3d21954b-ee64-48ac-8435-9bf01a310e3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1076033676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1076033676
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1027828266
Short name T359
Test name
Test status
Simulation time 3923254139 ps
CPU time 4.34 seconds
Started Aug 06 04:29:22 PM PDT 24
Finished Aug 06 04:29:26 PM PDT 24
Peak memory 198664 kb
Host smart-4048f502-ab4c-4610-882e-73c5950354df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1027828266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1027828266
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1103805276
Short name T1047
Test name
Test status
Simulation time 119060752990 ps
CPU time 54.33 seconds
Started Aug 06 04:29:17 PM PDT 24
Finished Aug 06 04:30:11 PM PDT 24
Peak memory 199608 kb
Host smart-43150723-cd1d-4846-8a50-3b29ac338a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103805276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1103805276
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2130349170
Short name T538
Test name
Test status
Simulation time 35646366705 ps
CPU time 14.1 seconds
Started Aug 06 04:29:16 PM PDT 24
Finished Aug 06 04:29:30 PM PDT 24
Peak memory 195428 kb
Host smart-12b04e46-53df-491d-afaa-1d245261a95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130349170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2130349170
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.4085024540
Short name T799
Test name
Test status
Simulation time 692853412 ps
CPU time 1.8 seconds
Started Aug 06 04:29:11 PM PDT 24
Finished Aug 06 04:29:13 PM PDT 24
Peak memory 198440 kb
Host smart-5183b602-3eb3-4e79-b246-afe31c67776a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085024540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.4085024540
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3819191665
Short name T714
Test name
Test status
Simulation time 407496846252 ps
CPU time 332.22 seconds
Started Aug 06 04:29:40 PM PDT 24
Finished Aug 06 04:35:12 PM PDT 24
Peak memory 208124 kb
Host smart-458b1efe-086f-444e-b8ea-3617efa3e305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819191665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3819191665
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.412981776
Short name T949
Test name
Test status
Simulation time 411181018129 ps
CPU time 386.72 seconds
Started Aug 06 04:29:38 PM PDT 24
Finished Aug 06 04:36:05 PM PDT 24
Peak memory 216232 kb
Host smart-854d49d5-a3d2-4dbd-b7b5-19dfe983c0b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412981776 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.412981776
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2172054647
Short name T1109
Test name
Test status
Simulation time 419532362 ps
CPU time 1.45 seconds
Started Aug 06 04:29:27 PM PDT 24
Finished Aug 06 04:29:28 PM PDT 24
Peak memory 198380 kb
Host smart-16984d33-52c1-4188-a4a3-26739fc9bdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172054647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2172054647
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2662520250
Short name T621
Test name
Test status
Simulation time 121448179075 ps
CPU time 216.38 seconds
Started Aug 06 04:29:20 PM PDT 24
Finished Aug 06 04:32:56 PM PDT 24
Peak memory 199712 kb
Host smart-ac87dab2-47d3-4c2b-898b-7a1a0fa147a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662520250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2662520250
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2533844753
Short name T388
Test name
Test status
Simulation time 12953641 ps
CPU time 0.55 seconds
Started Aug 06 04:29:40 PM PDT 24
Finished Aug 06 04:29:40 PM PDT 24
Peak memory 195408 kb
Host smart-4426e5ee-8553-4bf2-82c7-b226aa93dfcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533844753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2533844753
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1860370865
Short name T479
Test name
Test status
Simulation time 29117960772 ps
CPU time 49.31 seconds
Started Aug 06 04:29:18 PM PDT 24
Finished Aug 06 04:30:13 PM PDT 24
Peak memory 199508 kb
Host smart-c95c4ea8-4ab1-45a5-a34f-8260c2a1cfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860370865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1860370865
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2772581798
Short name T477
Test name
Test status
Simulation time 86433459951 ps
CPU time 19.63 seconds
Started Aug 06 04:29:23 PM PDT 24
Finished Aug 06 04:29:42 PM PDT 24
Peak memory 199760 kb
Host smart-12bf1e7f-4c7b-4cd8-a7a5-7f074383e3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772581798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2772581798
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1103501469
Short name T875
Test name
Test status
Simulation time 6713323186 ps
CPU time 11.51 seconds
Started Aug 06 04:29:20 PM PDT 24
Finished Aug 06 04:29:32 PM PDT 24
Peak memory 198848 kb
Host smart-7ac98ef1-c5a7-47d2-b577-be36802cab44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103501469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1103501469
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2362531469
Short name T519
Test name
Test status
Simulation time 26200863952 ps
CPU time 23.76 seconds
Started Aug 06 04:29:33 PM PDT 24
Finished Aug 06 04:29:57 PM PDT 24
Peak memory 198124 kb
Host smart-675cabe0-8a9f-4671-a8eb-5c786dd7a028
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362531469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2362531469
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.501623196
Short name T1097
Test name
Test status
Simulation time 58514742425 ps
CPU time 315.51 seconds
Started Aug 06 04:29:34 PM PDT 24
Finished Aug 06 04:34:49 PM PDT 24
Peak memory 199708 kb
Host smart-abe106c0-b3f5-4de2-ac29-c2e94fa849c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=501623196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.501623196
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1650345367
Short name T876
Test name
Test status
Simulation time 5448437082 ps
CPU time 8.64 seconds
Started Aug 06 04:29:30 PM PDT 24
Finished Aug 06 04:29:38 PM PDT 24
Peak memory 199172 kb
Host smart-f9b44d99-760c-4ff9-ab87-8025143a8910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650345367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1650345367
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.122889190
Short name T268
Test name
Test status
Simulation time 63807643520 ps
CPU time 112.08 seconds
Started Aug 06 04:29:31 PM PDT 24
Finished Aug 06 04:31:23 PM PDT 24
Peak memory 199896 kb
Host smart-1b0cf52e-c1c3-4d71-911d-dc336bd9151c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122889190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.122889190
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2314494063
Short name T793
Test name
Test status
Simulation time 11141106857 ps
CPU time 111.53 seconds
Started Aug 06 04:29:20 PM PDT 24
Finished Aug 06 04:31:12 PM PDT 24
Peak memory 199632 kb
Host smart-200204a7-3efe-46e1-ba3b-597dc1c683bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2314494063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2314494063
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1347847508
Short name T504
Test name
Test status
Simulation time 5735714673 ps
CPU time 24.02 seconds
Started Aug 06 04:29:21 PM PDT 24
Finished Aug 06 04:29:45 PM PDT 24
Peak memory 198460 kb
Host smart-cfa44c4f-037e-4c16-946c-6b9ee95eff92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1347847508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1347847508
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3744607605
Short name T895
Test name
Test status
Simulation time 34835957272 ps
CPU time 76 seconds
Started Aug 06 04:29:28 PM PDT 24
Finished Aug 06 04:30:44 PM PDT 24
Peak memory 199776 kb
Host smart-8f597f77-a83b-4e0b-9017-41ccd73c82d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744607605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3744607605
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1617796313
Short name T1073
Test name
Test status
Simulation time 19799765874 ps
CPU time 8.56 seconds
Started Aug 06 04:29:35 PM PDT 24
Finished Aug 06 04:29:43 PM PDT 24
Peak memory 195888 kb
Host smart-9961d876-2407-4c45-8579-ae5780dd85d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617796313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1617796313
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3059948556
Short name T693
Test name
Test status
Simulation time 5369549316 ps
CPU time 14.62 seconds
Started Aug 06 04:29:33 PM PDT 24
Finished Aug 06 04:29:48 PM PDT 24
Peak memory 199576 kb
Host smart-14cd86ce-4b7a-4a22-b969-a1f49192bae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059948556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3059948556
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.2370334044
Short name T146
Test name
Test status
Simulation time 193698133550 ps
CPU time 82.38 seconds
Started Aug 06 04:29:39 PM PDT 24
Finished Aug 06 04:31:02 PM PDT 24
Peak memory 199696 kb
Host smart-0bdce37c-c38e-4892-8daa-cf510765c3b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370334044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2370334044
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3861701920
Short name T1100
Test name
Test status
Simulation time 45831031452 ps
CPU time 711.07 seconds
Started Aug 06 04:29:38 PM PDT 24
Finished Aug 06 04:41:30 PM PDT 24
Peak memory 216220 kb
Host smart-e0fc8e29-b448-4b20-8d58-2e27ce24af5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861701920 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3861701920
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.921904619
Short name T604
Test name
Test status
Simulation time 690112497 ps
CPU time 1.19 seconds
Started Aug 06 04:29:22 PM PDT 24
Finished Aug 06 04:29:23 PM PDT 24
Peak memory 198192 kb
Host smart-b2db7d38-2861-4a68-a0f8-ff4e5aee8154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921904619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.921904619
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3235871433
Short name T824
Test name
Test status
Simulation time 16458463148 ps
CPU time 6.08 seconds
Started Aug 06 04:29:29 PM PDT 24
Finished Aug 06 04:29:36 PM PDT 24
Peak memory 198932 kb
Host smart-5af667ac-1230-4163-8a4a-3cd77407462d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235871433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3235871433
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2004916487
Short name T467
Test name
Test status
Simulation time 12735162 ps
CPU time 0.54 seconds
Started Aug 06 04:29:35 PM PDT 24
Finished Aug 06 04:29:36 PM PDT 24
Peak memory 194684 kb
Host smart-c0f14b0f-08e1-4df5-81df-6491c0945f92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004916487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2004916487
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2313431400
Short name T561
Test name
Test status
Simulation time 72984193381 ps
CPU time 31.24 seconds
Started Aug 06 04:29:36 PM PDT 24
Finished Aug 06 04:30:08 PM PDT 24
Peak memory 199612 kb
Host smart-ac1d4428-3bfa-4f94-80bc-90824d5d4874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313431400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2313431400
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.20774219
Short name T653
Test name
Test status
Simulation time 131042667847 ps
CPU time 282.15 seconds
Started Aug 06 04:29:38 PM PDT 24
Finished Aug 06 04:34:20 PM PDT 24
Peak memory 199660 kb
Host smart-cf4978a1-ed80-4977-a9c9-e6d8fcc4bb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20774219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.20774219
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.830359574
Short name T905
Test name
Test status
Simulation time 28079051005 ps
CPU time 8.74 seconds
Started Aug 06 04:29:31 PM PDT 24
Finished Aug 06 04:29:40 PM PDT 24
Peak memory 199688 kb
Host smart-6705eab5-45e8-41fd-932c-795eaaedb286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830359574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.830359574
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2628544277
Short name T690
Test name
Test status
Simulation time 36054218937 ps
CPU time 52.87 seconds
Started Aug 06 04:29:43 PM PDT 24
Finished Aug 06 04:30:36 PM PDT 24
Peak memory 199720 kb
Host smart-1e97ac5a-4cbb-47eb-b1e9-7da35d47bb17
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628544277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2628544277
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2563510028
Short name T584
Test name
Test status
Simulation time 102932087368 ps
CPU time 238.89 seconds
Started Aug 06 04:29:34 PM PDT 24
Finished Aug 06 04:33:33 PM PDT 24
Peak memory 199776 kb
Host smart-a0a53d4b-15ee-4c09-9b31-3f9bd2a1bbec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2563510028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2563510028
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3147001519
Short name T1005
Test name
Test status
Simulation time 816983664 ps
CPU time 0.98 seconds
Started Aug 06 04:29:53 PM PDT 24
Finished Aug 06 04:29:54 PM PDT 24
Peak memory 196880 kb
Host smart-6e5b3cb2-0e4e-45c8-ae26-a145b445ae63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147001519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3147001519
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.754190211
Short name T330
Test name
Test status
Simulation time 74525137223 ps
CPU time 63.62 seconds
Started Aug 06 04:29:38 PM PDT 24
Finished Aug 06 04:30:42 PM PDT 24
Peak memory 199748 kb
Host smart-2f5b3c91-ab23-4f3d-b55e-c1dee87cea27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754190211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.754190211
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2267607294
Short name T984
Test name
Test status
Simulation time 21126384370 ps
CPU time 963.38 seconds
Started Aug 06 04:29:41 PM PDT 24
Finished Aug 06 04:45:45 PM PDT 24
Peak memory 199780 kb
Host smart-47ca11be-679f-4a38-bbb7-d86e01462e8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2267607294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2267607294
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3777701195
Short name T845
Test name
Test status
Simulation time 3402428059 ps
CPU time 25.82 seconds
Started Aug 06 04:29:35 PM PDT 24
Finished Aug 06 04:30:01 PM PDT 24
Peak memory 197848 kb
Host smart-ce655b5c-605a-407b-935f-500f51de7e80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3777701195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3777701195
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.263389867
Short name T153
Test name
Test status
Simulation time 116811841223 ps
CPU time 58.8 seconds
Started Aug 06 04:29:29 PM PDT 24
Finished Aug 06 04:30:28 PM PDT 24
Peak memory 199728 kb
Host smart-1e805e9c-4151-4e1e-a9e4-8b8fbe133c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263389867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.263389867
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1560507816
Short name T904
Test name
Test status
Simulation time 609204409 ps
CPU time 0.87 seconds
Started Aug 06 04:29:39 PM PDT 24
Finished Aug 06 04:29:40 PM PDT 24
Peak memory 195232 kb
Host smart-33ecc5ed-37e7-4e97-85fa-4957837c7647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560507816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1560507816
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1725355261
Short name T902
Test name
Test status
Simulation time 155238841 ps
CPU time 0.74 seconds
Started Aug 06 04:29:28 PM PDT 24
Finished Aug 06 04:29:29 PM PDT 24
Peak memory 196868 kb
Host smart-018c6164-c773-420b-b931-7652cad905e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725355261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1725355261
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.1412063227
Short name T778
Test name
Test status
Simulation time 270260849373 ps
CPU time 1001.52 seconds
Started Aug 06 04:29:33 PM PDT 24
Finished Aug 06 04:46:14 PM PDT 24
Peak memory 199780 kb
Host smart-8280f31c-6dab-4fd1-baa0-ecef1979cbcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412063227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1412063227
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1119660931
Short name T643
Test name
Test status
Simulation time 781046055 ps
CPU time 1.48 seconds
Started Aug 06 04:29:33 PM PDT 24
Finished Aug 06 04:29:34 PM PDT 24
Peak memory 198860 kb
Host smart-dfd7d88d-1856-48d6-9543-b8be415c2725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119660931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1119660931
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2637523546
Short name T48
Test name
Test status
Simulation time 34044130538 ps
CPU time 15.16 seconds
Started Aug 06 04:29:20 PM PDT 24
Finished Aug 06 04:29:35 PM PDT 24
Peak memory 197572 kb
Host smart-0e523398-c080-484f-9539-3b482516167b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637523546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2637523546
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1150276282
Short name T374
Test name
Test status
Simulation time 28926870 ps
CPU time 0.55 seconds
Started Aug 06 04:29:23 PM PDT 24
Finished Aug 06 04:29:23 PM PDT 24
Peak memory 195412 kb
Host smart-692480a2-9d82-4e24-bb76-31289c910cda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150276282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1150276282
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.2598821372
Short name T1120
Test name
Test status
Simulation time 25424888566 ps
CPU time 23.72 seconds
Started Aug 06 04:29:36 PM PDT 24
Finished Aug 06 04:30:00 PM PDT 24
Peak memory 199728 kb
Host smart-08f13be3-e341-40b9-ac6d-3a1bfaf3bba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598821372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2598821372
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.323501159
Short name T1144
Test name
Test status
Simulation time 70177717946 ps
CPU time 29.04 seconds
Started Aug 06 04:29:41 PM PDT 24
Finished Aug 06 04:30:10 PM PDT 24
Peak memory 198584 kb
Host smart-90b3bc99-50c5-474c-8299-4d88f3a3b583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323501159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.323501159
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3835909437
Short name T132
Test name
Test status
Simulation time 64564251380 ps
CPU time 16.86 seconds
Started Aug 06 04:29:46 PM PDT 24
Finished Aug 06 04:30:03 PM PDT 24
Peak memory 199780 kb
Host smart-32f99015-ece7-4b2f-b9e4-043660a9032c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835909437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3835909437
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3760972271
Short name T439
Test name
Test status
Simulation time 29573079954 ps
CPU time 50.76 seconds
Started Aug 06 04:29:41 PM PDT 24
Finished Aug 06 04:30:32 PM PDT 24
Peak memory 199680 kb
Host smart-6ac5a4c4-1e97-42d9-bdb2-74f4ab69128b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760972271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3760972271
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.389388583
Short name T780
Test name
Test status
Simulation time 83636161883 ps
CPU time 358.69 seconds
Started Aug 06 04:29:42 PM PDT 24
Finished Aug 06 04:35:40 PM PDT 24
Peak memory 199720 kb
Host smart-4efd99a8-1a24-4114-8e96-ca9d36747d33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=389388583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.389388583
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2577062081
Short name T680
Test name
Test status
Simulation time 7542608654 ps
CPU time 6.33 seconds
Started Aug 06 04:29:34 PM PDT 24
Finished Aug 06 04:29:40 PM PDT 24
Peak memory 198800 kb
Host smart-f5fdd97c-9feb-4cd6-9402-2a8faa64f721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577062081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2577062081
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3459885634
Short name T753
Test name
Test status
Simulation time 26300640067 ps
CPU time 48.16 seconds
Started Aug 06 04:29:21 PM PDT 24
Finished Aug 06 04:30:10 PM PDT 24
Peak memory 198096 kb
Host smart-e346b5fa-fbff-4c14-bcc3-6e4f6d179d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459885634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3459885634
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.4135082947
Short name T1159
Test name
Test status
Simulation time 14796886627 ps
CPU time 133.78 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:32:54 PM PDT 24
Peak memory 199452 kb
Host smart-79ed7ef5-d50c-46a6-99a8-a22918bda455
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4135082947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.4135082947
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3039380852
Short name T917
Test name
Test status
Simulation time 5746316264 ps
CPU time 13.7 seconds
Started Aug 06 04:29:39 PM PDT 24
Finished Aug 06 04:29:53 PM PDT 24
Peak memory 198976 kb
Host smart-16ac503e-df53-45b2-93d8-c18dca799766
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3039380852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3039380852
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.3007153519
Short name T5
Test name
Test status
Simulation time 219068429236 ps
CPU time 88.56 seconds
Started Aug 06 04:30:25 PM PDT 24
Finished Aug 06 04:31:55 PM PDT 24
Peak memory 198916 kb
Host smart-0d377730-60c2-40bb-8aa4-c4419f48ef7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007153519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3007153519
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.427174882
Short name T406
Test name
Test status
Simulation time 3049064612 ps
CPU time 1.79 seconds
Started Aug 06 04:29:30 PM PDT 24
Finished Aug 06 04:29:32 PM PDT 24
Peak memory 196108 kb
Host smart-2d0aa55d-ef7b-4498-bbec-f8f62ec6d18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427174882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.427174882
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.858817904
Short name T762
Test name
Test status
Simulation time 715234003 ps
CPU time 3.19 seconds
Started Aug 06 04:29:28 PM PDT 24
Finished Aug 06 04:29:31 PM PDT 24
Peak memory 198704 kb
Host smart-c7c0d154-4261-4a2d-aef9-784242b2bca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858817904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.858817904
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3456974832
Short name T1179
Test name
Test status
Simulation time 33033184829 ps
CPU time 411.92 seconds
Started Aug 06 04:29:40 PM PDT 24
Finished Aug 06 04:36:32 PM PDT 24
Peak memory 224552 kb
Host smart-d25cb437-6265-4692-a1bb-180b6ca79332
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456974832 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3456974832
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1817732877
Short name T429
Test name
Test status
Simulation time 4630902940 ps
CPU time 1.63 seconds
Started Aug 06 04:29:33 PM PDT 24
Finished Aug 06 04:29:35 PM PDT 24
Peak memory 199396 kb
Host smart-5437c0be-d274-4a77-b444-b779f44bb8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817732877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1817732877
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2354226142
Short name T884
Test name
Test status
Simulation time 61986962420 ps
CPU time 86.93 seconds
Started Aug 06 04:29:32 PM PDT 24
Finished Aug 06 04:30:59 PM PDT 24
Peak memory 199760 kb
Host smart-2271e4cd-3f0d-4299-9db2-d0304e853a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354226142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2354226142
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2865563731
Short name T672
Test name
Test status
Simulation time 22131035 ps
CPU time 0.51 seconds
Started Aug 06 04:29:29 PM PDT 24
Finished Aug 06 04:29:30 PM PDT 24
Peak memory 195416 kb
Host smart-6311d266-28ce-4dc8-bdc6-a153b0e1c8a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865563731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2865563731
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2522708209
Short name T920
Test name
Test status
Simulation time 86017436211 ps
CPU time 27.34 seconds
Started Aug 06 04:29:38 PM PDT 24
Finished Aug 06 04:30:05 PM PDT 24
Peak memory 199552 kb
Host smart-df5b2933-b934-4c35-955c-63a7a36ea869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522708209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2522708209
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.771509807
Short name T1169
Test name
Test status
Simulation time 96359224857 ps
CPU time 17.77 seconds
Started Aug 06 04:29:33 PM PDT 24
Finished Aug 06 04:29:51 PM PDT 24
Peak memory 199788 kb
Host smart-4ce5fd14-e409-45c7-965a-ca22c0f1459f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771509807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.771509807
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1343803232
Short name T755
Test name
Test status
Simulation time 120334102392 ps
CPU time 13.39 seconds
Started Aug 06 04:29:33 PM PDT 24
Finished Aug 06 04:29:46 PM PDT 24
Peak memory 199732 kb
Host smart-2cd05244-39a9-4120-b89a-1b27f9e141e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343803232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1343803232
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1137041277
Short name T1069
Test name
Test status
Simulation time 32676616418 ps
CPU time 45.63 seconds
Started Aug 06 04:29:40 PM PDT 24
Finished Aug 06 04:30:26 PM PDT 24
Peak memory 200124 kb
Host smart-f3db7cf0-be5d-43bb-a5f6-a4e9a696ba27
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137041277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1137041277
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.312621628
Short name T719
Test name
Test status
Simulation time 189403913075 ps
CPU time 503.38 seconds
Started Aug 06 04:29:43 PM PDT 24
Finished Aug 06 04:38:07 PM PDT 24
Peak memory 199728 kb
Host smart-49408962-d7ef-4aff-976e-0dc672505a13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=312621628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.312621628
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.504023263
Short name T520
Test name
Test status
Simulation time 6251324035 ps
CPU time 6.16 seconds
Started Aug 06 04:29:21 PM PDT 24
Finished Aug 06 04:29:27 PM PDT 24
Peak memory 199068 kb
Host smart-6cc91b13-7667-499e-805b-e7e327309fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504023263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.504023263
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.4078226598
Short name T266
Test name
Test status
Simulation time 152899671638 ps
CPU time 57.24 seconds
Started Aug 06 04:29:21 PM PDT 24
Finished Aug 06 04:30:18 PM PDT 24
Peak memory 199840 kb
Host smart-d308bbda-fff5-402b-9a0c-dda0d247dfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078226598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.4078226598
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3066774024
Short name T981
Test name
Test status
Simulation time 26400804957 ps
CPU time 1308.18 seconds
Started Aug 06 04:29:29 PM PDT 24
Finished Aug 06 04:51:17 PM PDT 24
Peak memory 199756 kb
Host smart-d79fa82b-bd24-4003-89b4-45eca77a07ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3066774024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3066774024
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1347934174
Short name T863
Test name
Test status
Simulation time 7811187591 ps
CPU time 69.19 seconds
Started Aug 06 04:29:28 PM PDT 24
Finished Aug 06 04:30:37 PM PDT 24
Peak memory 197908 kb
Host smart-226cfc91-4887-4cf2-9c7a-b6b0fddc62dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1347934174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1347934174
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.298860253
Short name T970
Test name
Test status
Simulation time 64297087992 ps
CPU time 119.19 seconds
Started Aug 06 04:29:39 PM PDT 24
Finished Aug 06 04:31:38 PM PDT 24
Peak memory 199644 kb
Host smart-dd5f07a9-fa27-4b8f-8b69-7f431fe660bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298860253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.298860253
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1286853612
Short name T633
Test name
Test status
Simulation time 36012517425 ps
CPU time 47.8 seconds
Started Aug 06 04:29:35 PM PDT 24
Finished Aug 06 04:30:23 PM PDT 24
Peak memory 196036 kb
Host smart-39dcf9e9-bcf0-4b71-a558-899a77dd984d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286853612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1286853612
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1805018059
Short name T707
Test name
Test status
Simulation time 316576319 ps
CPU time 1.52 seconds
Started Aug 06 04:29:42 PM PDT 24
Finished Aug 06 04:29:43 PM PDT 24
Peak memory 199180 kb
Host smart-b7d16f69-6929-43e5-9523-fa9e8bb3bef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805018059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1805018059
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3593295117
Short name T912
Test name
Test status
Simulation time 83064840944 ps
CPU time 248.39 seconds
Started Aug 06 04:29:39 PM PDT 24
Finished Aug 06 04:33:48 PM PDT 24
Peak memory 216424 kb
Host smart-c4ef3e94-bac4-445f-9b9a-4fdb3c63b568
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593295117 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3593295117
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.1507544838
Short name T1137
Test name
Test status
Simulation time 1229784209 ps
CPU time 1.37 seconds
Started Aug 06 04:29:37 PM PDT 24
Finished Aug 06 04:29:39 PM PDT 24
Peak memory 198368 kb
Host smart-3c5051cc-52f4-4dcd-ad40-4bde329ee034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507544838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1507544838
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2344083360
Short name T685
Test name
Test status
Simulation time 47526550206 ps
CPU time 18.61 seconds
Started Aug 06 04:29:38 PM PDT 24
Finished Aug 06 04:29:56 PM PDT 24
Peak memory 198568 kb
Host smart-48716682-3b77-4e58-bb16-ca89184236a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344083360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2344083360
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.258304979
Short name T750
Test name
Test status
Simulation time 21156336 ps
CPU time 0.58 seconds
Started Aug 06 04:29:53 PM PDT 24
Finished Aug 06 04:29:53 PM PDT 24
Peak memory 195404 kb
Host smart-b96dab37-5179-40e9-9955-8f8a7e133081
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258304979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.258304979
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.230529280
Short name T373
Test name
Test status
Simulation time 10066301354 ps
CPU time 15.72 seconds
Started Aug 06 04:29:37 PM PDT 24
Finished Aug 06 04:29:53 PM PDT 24
Peak memory 199068 kb
Host smart-dc78d092-defc-4d16-b6a4-55e5767d43db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230529280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.230529280
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3428062518
Short name T1010
Test name
Test status
Simulation time 216307752955 ps
CPU time 319.22 seconds
Started Aug 06 04:29:32 PM PDT 24
Finished Aug 06 04:34:51 PM PDT 24
Peak memory 199600 kb
Host smart-14dabe10-4a45-443e-91ab-95871303f1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428062518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3428062518
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2472758648
Short name T507
Test name
Test status
Simulation time 41635148575 ps
CPU time 57.92 seconds
Started Aug 06 04:29:32 PM PDT 24
Finished Aug 06 04:30:30 PM PDT 24
Peak memory 199764 kb
Host smart-c008bff8-61fa-4e0d-8f4f-61b4e60bf606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472758648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2472758648
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3230136920
Short name T1115
Test name
Test status
Simulation time 34121248269 ps
CPU time 15.72 seconds
Started Aug 06 04:29:52 PM PDT 24
Finished Aug 06 04:30:08 PM PDT 24
Peak memory 199736 kb
Host smart-71bed8a4-a4bb-48e0-abb7-c3a02f48e7cf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230136920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3230136920
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.777760196
Short name T257
Test name
Test status
Simulation time 124741048143 ps
CPU time 653.89 seconds
Started Aug 06 04:29:46 PM PDT 24
Finished Aug 06 04:40:40 PM PDT 24
Peak memory 199688 kb
Host smart-24231a5c-556f-45e6-a4d5-2ab682c37008
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=777760196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.777760196
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3773199896
Short name T569
Test name
Test status
Simulation time 7934830823 ps
CPU time 6.55 seconds
Started Aug 06 04:29:39 PM PDT 24
Finished Aug 06 04:29:46 PM PDT 24
Peak memory 198880 kb
Host smart-a554720d-52fe-4f81-a2ec-943ea93c6add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773199896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3773199896
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.4109760352
Short name T914
Test name
Test status
Simulation time 108756969971 ps
CPU time 194.35 seconds
Started Aug 06 04:29:36 PM PDT 24
Finished Aug 06 04:32:51 PM PDT 24
Peak memory 199644 kb
Host smart-312d6069-c959-4ae9-9701-da204c6718db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109760352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.4109760352
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1520995170
Short name T510
Test name
Test status
Simulation time 20702213616 ps
CPU time 1069.62 seconds
Started Aug 06 04:29:55 PM PDT 24
Finished Aug 06 04:47:45 PM PDT 24
Peak memory 199720 kb
Host smart-e91fe833-f521-443b-8804-843feae67a2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1520995170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1520995170
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.639748669
Short name T1114
Test name
Test status
Simulation time 4123929810 ps
CPU time 33.34 seconds
Started Aug 06 04:29:43 PM PDT 24
Finished Aug 06 04:30:17 PM PDT 24
Peak memory 197852 kb
Host smart-df3f7348-ef33-462a-a5b2-3401d6dbf113
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=639748669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.639748669
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3312231548
Short name T303
Test name
Test status
Simulation time 45216652762 ps
CPU time 73.15 seconds
Started Aug 06 04:29:45 PM PDT 24
Finished Aug 06 04:30:59 PM PDT 24
Peak memory 199676 kb
Host smart-87006e6c-311a-407b-974b-9394c2c9e652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312231548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3312231548
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2712860487
Short name T422
Test name
Test status
Simulation time 1601790458 ps
CPU time 3.02 seconds
Started Aug 06 04:29:49 PM PDT 24
Finished Aug 06 04:29:52 PM PDT 24
Peak memory 195176 kb
Host smart-3b5ee542-733e-4a66-8356-55970156e86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712860487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2712860487
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2493979046
Short name T574
Test name
Test status
Simulation time 764147608 ps
CPU time 1.2 seconds
Started Aug 06 04:29:44 PM PDT 24
Finished Aug 06 04:29:45 PM PDT 24
Peak memory 199488 kb
Host smart-a256f4cf-882b-4231-8b0d-a45934414420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493979046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2493979046
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.157232462
Short name T1093
Test name
Test status
Simulation time 41617048033 ps
CPU time 1123.85 seconds
Started Aug 06 04:29:36 PM PDT 24
Finished Aug 06 04:48:20 PM PDT 24
Peak memory 199752 kb
Host smart-b0e9131c-0f5c-478f-bf55-e32cdb6b6115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157232462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.157232462
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3189443755
Short name T438
Test name
Test status
Simulation time 3277461818 ps
CPU time 69.36 seconds
Started Aug 06 04:29:47 PM PDT 24
Finished Aug 06 04:30:57 PM PDT 24
Peak memory 215436 kb
Host smart-30cb6dcd-88fd-4150-be4f-4f4458564edb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189443755 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3189443755
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2502360792
Short name T292
Test name
Test status
Simulation time 1634206553 ps
CPU time 2.64 seconds
Started Aug 06 04:29:35 PM PDT 24
Finished Aug 06 04:29:38 PM PDT 24
Peak memory 199460 kb
Host smart-cd0d45d9-26dc-4498-b617-759a191a14d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502360792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2502360792
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.42602968
Short name T655
Test name
Test status
Simulation time 19994470278 ps
CPU time 36.43 seconds
Started Aug 06 04:29:39 PM PDT 24
Finished Aug 06 04:30:16 PM PDT 24
Peak memory 199620 kb
Host smart-246eb023-2866-4129-bbdf-b135ea3b7b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42602968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.42602968
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.2054038502
Short name T829
Test name
Test status
Simulation time 12837797 ps
CPU time 0.54 seconds
Started Aug 06 04:29:46 PM PDT 24
Finished Aug 06 04:29:47 PM PDT 24
Peak memory 194100 kb
Host smart-78ca26c0-d675-4486-b9be-75408f61c804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054038502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2054038502
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2753977923
Short name T1074
Test name
Test status
Simulation time 28086005114 ps
CPU time 21.29 seconds
Started Aug 06 04:29:41 PM PDT 24
Finished Aug 06 04:30:03 PM PDT 24
Peak memory 199764 kb
Host smart-3b25a294-8651-4a38-ba1d-0b7eaedabbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753977923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2753977923
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1033001091
Short name T484
Test name
Test status
Simulation time 35011763562 ps
CPU time 55.13 seconds
Started Aug 06 04:29:52 PM PDT 24
Finished Aug 06 04:30:47 PM PDT 24
Peak memory 199740 kb
Host smart-d9a72b87-b58f-468e-96a8-d99e98a92779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033001091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1033001091
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2129310797
Short name T498
Test name
Test status
Simulation time 72382903312 ps
CPU time 119.75 seconds
Started Aug 06 04:29:46 PM PDT 24
Finished Aug 06 04:31:46 PM PDT 24
Peak memory 199684 kb
Host smart-ef57d679-8839-443b-a009-4d925f544515
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129310797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2129310797
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.937802126
Short name T536
Test name
Test status
Simulation time 260388810550 ps
CPU time 140.43 seconds
Started Aug 06 04:29:47 PM PDT 24
Finished Aug 06 04:32:07 PM PDT 24
Peak memory 199624 kb
Host smart-c7460a18-ff76-4452-8008-bc705f7ac674
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=937802126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.937802126
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1938543369
Short name T541
Test name
Test status
Simulation time 4072485248 ps
CPU time 3.92 seconds
Started Aug 06 04:29:37 PM PDT 24
Finished Aug 06 04:29:41 PM PDT 24
Peak memory 197784 kb
Host smart-683a1b66-454b-4a33-901b-8166934e6514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938543369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1938543369
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1160646691
Short name T466
Test name
Test status
Simulation time 72580221486 ps
CPU time 30.37 seconds
Started Aug 06 04:29:49 PM PDT 24
Finished Aug 06 04:30:20 PM PDT 24
Peak memory 198720 kb
Host smart-31e8d4e5-0071-4add-b5b7-272b8b8375c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160646691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1160646691
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1954855414
Short name T424
Test name
Test status
Simulation time 19415462250 ps
CPU time 144.59 seconds
Started Aug 06 04:29:44 PM PDT 24
Finished Aug 06 04:32:08 PM PDT 24
Peak memory 199528 kb
Host smart-54e873f4-dbf0-44bd-8309-89f967d08c37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954855414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1954855414
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2249018713
Short name T628
Test name
Test status
Simulation time 6355782378 ps
CPU time 54.22 seconds
Started Aug 06 04:30:00 PM PDT 24
Finished Aug 06 04:30:55 PM PDT 24
Peak memory 197932 kb
Host smart-4478fdab-3368-493a-8483-95c99964e019
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2249018713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2249018713
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.671327928
Short name T821
Test name
Test status
Simulation time 23293948158 ps
CPU time 49.64 seconds
Started Aug 06 04:29:39 PM PDT 24
Finished Aug 06 04:30:29 PM PDT 24
Peak memory 199792 kb
Host smart-e93ff09f-24a5-4e88-9e34-717267548e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671327928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.671327928
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3448115165
Short name T489
Test name
Test status
Simulation time 5086471167 ps
CPU time 7.51 seconds
Started Aug 06 04:29:41 PM PDT 24
Finished Aug 06 04:29:49 PM PDT 24
Peak memory 196516 kb
Host smart-2ff6c911-9951-455c-b1c8-8981803fb929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448115165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3448115165
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3731752531
Short name T381
Test name
Test status
Simulation time 306943525 ps
CPU time 1.22 seconds
Started Aug 06 04:29:38 PM PDT 24
Finished Aug 06 04:29:39 PM PDT 24
Peak memory 198436 kb
Host smart-d86155a7-45aa-40ff-831d-3c0c2fc44e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731752531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3731752531
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1264475076
Short name T1134
Test name
Test status
Simulation time 339948901350 ps
CPU time 272.32 seconds
Started Aug 06 04:29:36 PM PDT 24
Finished Aug 06 04:34:08 PM PDT 24
Peak memory 208340 kb
Host smart-142ffd2d-cbaa-46d7-b2f5-0fc654c292a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264475076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1264475076
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.577985942
Short name T325
Test name
Test status
Simulation time 172268268782 ps
CPU time 593.03 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:40:34 PM PDT 24
Peak memory 223848 kb
Host smart-d4a0a525-96b6-4455-96d9-0bef4b82caca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577985942 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.577985942
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1568206981
Short name T786
Test name
Test status
Simulation time 6690870270 ps
CPU time 9.88 seconds
Started Aug 06 04:29:45 PM PDT 24
Finished Aug 06 04:29:55 PM PDT 24
Peak memory 199736 kb
Host smart-2cf9fb80-f1b9-4d82-bc47-94970d451fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568206981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1568206981
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1421306226
Short name T721
Test name
Test status
Simulation time 62684723458 ps
CPU time 100.32 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:32:21 PM PDT 24
Peak memory 198776 kb
Host smart-d32e1f11-a3eb-4594-9fb2-3e610665c651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421306226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1421306226
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3656501364
Short name T1046
Test name
Test status
Simulation time 13203368 ps
CPU time 0.53 seconds
Started Aug 06 04:29:38 PM PDT 24
Finished Aug 06 04:29:39 PM PDT 24
Peak memory 195392 kb
Host smart-a86d9333-4f66-44e7-80a2-d8cfe7fcf8bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656501364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3656501364
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3793247843
Short name T879
Test name
Test status
Simulation time 155871954009 ps
CPU time 327.24 seconds
Started Aug 06 04:29:35 PM PDT 24
Finished Aug 06 04:35:03 PM PDT 24
Peak memory 199556 kb
Host smart-bcffe8f1-6c1f-4173-9c49-403daf0df9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793247843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3793247843
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1225240944
Short name T1173
Test name
Test status
Simulation time 164657209427 ps
CPU time 22.84 seconds
Started Aug 06 04:29:39 PM PDT 24
Finished Aug 06 04:30:02 PM PDT 24
Peak memory 199772 kb
Host smart-35838328-adfb-4dfb-a88f-51c4f5e583c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225240944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1225240944
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3088214145
Short name T809
Test name
Test status
Simulation time 298299659265 ps
CPU time 98.52 seconds
Started Aug 06 04:29:44 PM PDT 24
Finished Aug 06 04:31:23 PM PDT 24
Peak memory 199720 kb
Host smart-ba8646bb-7131-4cd3-8a1d-53505b060e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088214145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3088214145
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3219987459
Short name T843
Test name
Test status
Simulation time 91271856741 ps
CPU time 11.64 seconds
Started Aug 06 04:29:36 PM PDT 24
Finished Aug 06 04:29:48 PM PDT 24
Peak memory 199632 kb
Host smart-018c555c-3cfa-4062-9ca5-ca98caea3aef
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219987459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3219987459
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1044805344
Short name T411
Test name
Test status
Simulation time 46034741075 ps
CPU time 261.63 seconds
Started Aug 06 04:29:37 PM PDT 24
Finished Aug 06 04:33:59 PM PDT 24
Peak memory 199692 kb
Host smart-ca687a60-45ee-4e47-8e5a-f9e569f285d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1044805344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1044805344
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2383579217
Short name T508
Test name
Test status
Simulation time 3763401336 ps
CPU time 12.06 seconds
Started Aug 06 04:29:46 PM PDT 24
Finished Aug 06 04:29:58 PM PDT 24
Peak memory 199516 kb
Host smart-b5a256b8-27cc-4dd8-a487-4bd8a531df86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383579217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2383579217
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.855961891
Short name T281
Test name
Test status
Simulation time 17953554609 ps
CPU time 23.2 seconds
Started Aug 06 04:29:40 PM PDT 24
Finished Aug 06 04:30:03 PM PDT 24
Peak memory 199844 kb
Host smart-c99b8d53-3dd5-43a9-a96f-93f7c1843f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855961891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.855961891
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1004030449
Short name T1037
Test name
Test status
Simulation time 32088286816 ps
CPU time 401.11 seconds
Started Aug 06 04:29:48 PM PDT 24
Finished Aug 06 04:36:29 PM PDT 24
Peak memory 199800 kb
Host smart-8059938e-4b90-4de3-a1cc-c2dfb3bd18bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004030449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1004030449
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.938703405
Short name T564
Test name
Test status
Simulation time 1806033160 ps
CPU time 3.12 seconds
Started Aug 06 04:29:52 PM PDT 24
Finished Aug 06 04:29:55 PM PDT 24
Peak memory 197848 kb
Host smart-5ff1f4ff-d787-43c7-a38c-f27c090e7491
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=938703405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.938703405
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.3751337998
Short name T1067
Test name
Test status
Simulation time 161262196845 ps
CPU time 64.1 seconds
Started Aug 06 04:29:52 PM PDT 24
Finished Aug 06 04:30:57 PM PDT 24
Peak memory 199672 kb
Host smart-330d5298-8741-43f2-bfaa-1bd02418cb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751337998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3751337998
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2313643761
Short name T945
Test name
Test status
Simulation time 2501705176 ps
CPU time 4.32 seconds
Started Aug 06 04:29:38 PM PDT 24
Finished Aug 06 04:29:42 PM PDT 24
Peak memory 195552 kb
Host smart-46d6628c-5802-484b-b459-1658a87bf7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313643761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2313643761
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.4035324402
Short name T955
Test name
Test status
Simulation time 661269581 ps
CPU time 1.43 seconds
Started Aug 06 04:29:38 PM PDT 24
Finished Aug 06 04:29:40 PM PDT 24
Peak memory 199760 kb
Host smart-2accae3a-92df-4f34-9d5a-8c4910c789dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035324402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4035324402
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.700544521
Short name T985
Test name
Test status
Simulation time 229638760464 ps
CPU time 395.74 seconds
Started Aug 06 04:29:40 PM PDT 24
Finished Aug 06 04:36:16 PM PDT 24
Peak memory 208016 kb
Host smart-d0540dd1-4814-4a9d-a363-56bfb40fb7d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700544521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.700544521
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.4239405039
Short name T60
Test name
Test status
Simulation time 59099634535 ps
CPU time 762.5 seconds
Started Aug 06 04:29:47 PM PDT 24
Finished Aug 06 04:42:30 PM PDT 24
Peak memory 224612 kb
Host smart-74386c77-e1b4-4be9-96db-644b062cad2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239405039 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.4239405039
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.368824259
Short name T370
Test name
Test status
Simulation time 1142789328 ps
CPU time 3.26 seconds
Started Aug 06 04:29:43 PM PDT 24
Finished Aug 06 04:29:46 PM PDT 24
Peak memory 198144 kb
Host smart-d84ebd84-385a-40a5-bafe-15434cdf1ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368824259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.368824259
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3737402586
Short name T726
Test name
Test status
Simulation time 69138084175 ps
CPU time 37.1 seconds
Started Aug 06 04:29:39 PM PDT 24
Finished Aug 06 04:30:16 PM PDT 24
Peak memory 199768 kb
Host smart-9dbaa28a-f53c-4217-8570-927cfa463a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737402586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3737402586
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1935264328
Short name T1143
Test name
Test status
Simulation time 17034059 ps
CPU time 0.53 seconds
Started Aug 06 04:29:40 PM PDT 24
Finished Aug 06 04:29:41 PM PDT 24
Peak memory 195124 kb
Host smart-0c3acc44-9329-4e3c-8e2a-edf04320347f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935264328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1935264328
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2747532592
Short name T645
Test name
Test status
Simulation time 74785787166 ps
CPU time 31.49 seconds
Started Aug 06 04:29:40 PM PDT 24
Finished Aug 06 04:30:12 PM PDT 24
Peak memory 199736 kb
Host smart-f45be7ff-0d50-4cac-ba83-44e23c206bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747532592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2747532592
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2075831865
Short name T1026
Test name
Test status
Simulation time 14423224637 ps
CPU time 25.95 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:31:06 PM PDT 24
Peak memory 199500 kb
Host smart-51c70cc0-a1e1-4097-99b2-c1e68e03e366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075831865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2075831865
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_intr.3477527013
Short name T106
Test name
Test status
Simulation time 67900502609 ps
CPU time 37.69 seconds
Started Aug 06 04:29:47 PM PDT 24
Finished Aug 06 04:30:24 PM PDT 24
Peak memory 199712 kb
Host smart-80727562-402d-4081-a2d7-90942f923882
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477527013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3477527013
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.794428663
Short name T654
Test name
Test status
Simulation time 148839870991 ps
CPU time 421.66 seconds
Started Aug 06 04:29:39 PM PDT 24
Finished Aug 06 04:36:41 PM PDT 24
Peak memory 199680 kb
Host smart-9bc49445-355b-4cf6-9f06-e45f9d715c8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=794428663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.794428663
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1245660720
Short name T937
Test name
Test status
Simulation time 276489891 ps
CPU time 1.04 seconds
Started Aug 06 04:29:55 PM PDT 24
Finished Aug 06 04:29:56 PM PDT 24
Peak memory 195160 kb
Host smart-c2baeb29-60db-4c34-af94-7ab48b936549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245660720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1245660720
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3781881045
Short name T616
Test name
Test status
Simulation time 102680842743 ps
CPU time 224.25 seconds
Started Aug 06 04:29:46 PM PDT 24
Finished Aug 06 04:33:30 PM PDT 24
Peak memory 199964 kb
Host smart-154e57d5-e5bd-4c70-afa2-a923fb6c36a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781881045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3781881045
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.353574671
Short name T1145
Test name
Test status
Simulation time 14197531326 ps
CPU time 215.14 seconds
Started Aug 06 04:29:47 PM PDT 24
Finished Aug 06 04:33:22 PM PDT 24
Peak memory 199748 kb
Host smart-67e0dd9f-c453-4259-a389-74dc8e849df5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=353574671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.353574671
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.827996276
Short name T594
Test name
Test status
Simulation time 7482235354 ps
CPU time 15.97 seconds
Started Aug 06 04:29:44 PM PDT 24
Finished Aug 06 04:30:00 PM PDT 24
Peak memory 197900 kb
Host smart-19f815ef-75a1-4a84-9433-16ad79c0b611
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=827996276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.827996276
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2662042675
Short name T572
Test name
Test status
Simulation time 56582360561 ps
CPU time 41 seconds
Started Aug 06 04:29:52 PM PDT 24
Finished Aug 06 04:30:33 PM PDT 24
Peak memory 199748 kb
Host smart-3e0e834a-80e3-42cb-b30c-aca2bf7b4147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662042675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2662042675
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2621597787
Short name T1142
Test name
Test status
Simulation time 73115179326 ps
CPU time 11.54 seconds
Started Aug 06 04:29:56 PM PDT 24
Finished Aug 06 04:30:08 PM PDT 24
Peak memory 195856 kb
Host smart-d020f46b-b52f-436b-978b-4b853a6598d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621597787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2621597787
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2384521248
Short name T1052
Test name
Test status
Simulation time 860521771 ps
CPU time 1.91 seconds
Started Aug 06 04:29:52 PM PDT 24
Finished Aug 06 04:29:54 PM PDT 24
Peak memory 198516 kb
Host smart-92c4a3f5-3fcc-4046-9380-d9a4fbabc181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384521248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2384521248
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2755637674
Short name T343
Test name
Test status
Simulation time 123330421201 ps
CPU time 143.82 seconds
Started Aug 06 04:29:43 PM PDT 24
Finished Aug 06 04:32:07 PM PDT 24
Peak memory 209604 kb
Host smart-20b71abf-76af-4244-ac10-8b9ec7d04d8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755637674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2755637674
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1431871847
Short name T813
Test name
Test status
Simulation time 12726143085 ps
CPU time 123.66 seconds
Started Aug 06 04:30:01 PM PDT 24
Finished Aug 06 04:32:04 PM PDT 24
Peak memory 216396 kb
Host smart-8fd68ee6-9217-440b-b972-5ee248296822
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431871847 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1431871847
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3138453160
Short name T696
Test name
Test status
Simulation time 111589310 ps
CPU time 1.07 seconds
Started Aug 06 04:29:38 PM PDT 24
Finished Aug 06 04:29:39 PM PDT 24
Peak memory 198592 kb
Host smart-6ff87936-00db-45bc-a361-501e2a673625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138453160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3138453160
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1691786930
Short name T1016
Test name
Test status
Simulation time 81418650492 ps
CPU time 33.87 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:31:14 PM PDT 24
Peak memory 199508 kb
Host smart-ea6e6488-4787-435a-a613-f9193de0b389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691786930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1691786930
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.4293387576
Short name T488
Test name
Test status
Simulation time 13881448 ps
CPU time 0.61 seconds
Started Aug 06 04:28:11 PM PDT 24
Finished Aug 06 04:28:11 PM PDT 24
Peak memory 195388 kb
Host smart-7b497955-3613-4179-872a-e36612af3403
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293387576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.4293387576
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1330513424
Short name T169
Test name
Test status
Simulation time 64236322556 ps
CPU time 37.11 seconds
Started Aug 06 04:28:27 PM PDT 24
Finished Aug 06 04:29:04 PM PDT 24
Peak memory 199668 kb
Host smart-dabd97a8-dd7e-4b72-87ad-22f11964b723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330513424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1330513424
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.280513957
Short name T316
Test name
Test status
Simulation time 91694967523 ps
CPU time 35.44 seconds
Started Aug 06 04:28:24 PM PDT 24
Finished Aug 06 04:29:00 PM PDT 24
Peak memory 199660 kb
Host smart-546dc44b-f515-46bb-b8e2-3a4637009e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280513957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.280513957
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3943665822
Short name T791
Test name
Test status
Simulation time 23739446766 ps
CPU time 36.42 seconds
Started Aug 06 04:28:10 PM PDT 24
Finished Aug 06 04:28:46 PM PDT 24
Peak memory 199688 kb
Host smart-6849cf29-02f0-43fd-b5e9-e7caad630417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943665822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3943665822
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1470636894
Short name T291
Test name
Test status
Simulation time 20918721345 ps
CPU time 10.26 seconds
Started Aug 06 04:28:18 PM PDT 24
Finished Aug 06 04:28:28 PM PDT 24
Peak memory 199740 kb
Host smart-3982b7bb-8b62-4fd2-b445-dca7cc5bce4b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470636894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1470636894
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3800419846
Short name T781
Test name
Test status
Simulation time 126096057666 ps
CPU time 980.76 seconds
Started Aug 06 04:28:15 PM PDT 24
Finished Aug 06 04:44:36 PM PDT 24
Peak memory 199588 kb
Host smart-9fd48fff-cfdf-46aa-b42c-9672e8713799
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800419846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3800419846
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1423599939
Short name T448
Test name
Test status
Simulation time 8389185920 ps
CPU time 5.09 seconds
Started Aug 06 04:28:29 PM PDT 24
Finished Aug 06 04:28:34 PM PDT 24
Peak memory 199700 kb
Host smart-d6b8832a-eaad-474c-8abd-3b790b3d04df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423599939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1423599939
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.2384571854
Short name T1113
Test name
Test status
Simulation time 15123866550 ps
CPU time 741.54 seconds
Started Aug 06 04:28:18 PM PDT 24
Finished Aug 06 04:40:39 PM PDT 24
Peak memory 199724 kb
Host smart-31bd08a3-80d8-482a-ba76-e6fa05ca6ee1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2384571854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2384571854
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1824299761
Short name T377
Test name
Test status
Simulation time 6563930450 ps
CPU time 56.29 seconds
Started Aug 06 04:28:17 PM PDT 24
Finished Aug 06 04:29:14 PM PDT 24
Peak memory 197752 kb
Host smart-b395aaa4-47ea-4d83-bcef-8d6dba15e246
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1824299761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1824299761
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1907296736
Short name T279
Test name
Test status
Simulation time 48375157205 ps
CPU time 35.18 seconds
Started Aug 06 04:28:23 PM PDT 24
Finished Aug 06 04:28:58 PM PDT 24
Peak memory 199736 kb
Host smart-abe1051a-a113-4f3d-a0f9-f22e6afad08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907296736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1907296736
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2158251350
Short name T307
Test name
Test status
Simulation time 4965210759 ps
CPU time 8.21 seconds
Started Aug 06 04:28:15 PM PDT 24
Finished Aug 06 04:28:23 PM PDT 24
Peak memory 196220 kb
Host smart-7ce5361e-e71a-4f72-b54f-2ab6850fe646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158251350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2158251350
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2680470898
Short name T26
Test name
Test status
Simulation time 75634613 ps
CPU time 0.82 seconds
Started Aug 06 04:28:37 PM PDT 24
Finished Aug 06 04:28:38 PM PDT 24
Peak memory 218016 kb
Host smart-f95580d2-08db-49de-8d08-53983c3f736b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680470898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2680470898
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.4099844099
Short name T677
Test name
Test status
Simulation time 11068515135 ps
CPU time 19.61 seconds
Started Aug 06 04:28:16 PM PDT 24
Finished Aug 06 04:28:36 PM PDT 24
Peak memory 199528 kb
Host smart-8bd40131-30eb-4cb6-a6a4-91b039d8c5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099844099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.4099844099
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.3488607715
Short name T950
Test name
Test status
Simulation time 158868747334 ps
CPU time 68.79 seconds
Started Aug 06 04:28:11 PM PDT 24
Finished Aug 06 04:29:19 PM PDT 24
Peak memory 208132 kb
Host smart-5442f5b0-14e6-4c59-a8fb-36fbeb1cc980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488607715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3488607715
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3685071778
Short name T98
Test name
Test status
Simulation time 34328121536 ps
CPU time 149.6 seconds
Started Aug 06 04:28:16 PM PDT 24
Finished Aug 06 04:30:46 PM PDT 24
Peak memory 215924 kb
Host smart-e6298ba4-614a-4e74-9455-0125a9237dc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685071778 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3685071778
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1077277444
Short name T14
Test name
Test status
Simulation time 843575454 ps
CPU time 1.71 seconds
Started Aug 06 04:28:18 PM PDT 24
Finished Aug 06 04:28:20 PM PDT 24
Peak memory 198264 kb
Host smart-b03d9fcd-b4f3-4d7f-9c23-254aeafbc9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077277444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1077277444
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2394531885
Short name T968
Test name
Test status
Simulation time 32591965461 ps
CPU time 10.36 seconds
Started Aug 06 04:28:29 PM PDT 24
Finished Aug 06 04:28:40 PM PDT 24
Peak memory 199652 kb
Host smart-45c37c2e-412c-4d9c-b00b-0b7d7e59a781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394531885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2394531885
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.862865387
Short name T642
Test name
Test status
Simulation time 90547809 ps
CPU time 0.58 seconds
Started Aug 06 04:29:50 PM PDT 24
Finished Aug 06 04:29:51 PM PDT 24
Peak memory 194652 kb
Host smart-bd3b0dc4-3ff5-44e2-a8fe-27137f499980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862865387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.862865387
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.388840970
Short name T119
Test name
Test status
Simulation time 13534705506 ps
CPU time 23.42 seconds
Started Aug 06 04:29:39 PM PDT 24
Finished Aug 06 04:30:02 PM PDT 24
Peak memory 199656 kb
Host smart-9c910b36-66fd-482d-96cf-f028c7caf289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388840970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.388840970
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2492708264
Short name T740
Test name
Test status
Simulation time 10575383936 ps
CPU time 15.5 seconds
Started Aug 06 04:29:43 PM PDT 24
Finished Aug 06 04:29:58 PM PDT 24
Peak memory 199556 kb
Host smart-85ade1eb-1398-44cf-b94d-be9d0cad571e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492708264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2492708264
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2745722762
Short name T89
Test name
Test status
Simulation time 152049688877 ps
CPU time 221.87 seconds
Started Aug 06 04:29:42 PM PDT 24
Finished Aug 06 04:33:24 PM PDT 24
Peak memory 199636 kb
Host smart-45abfc68-5975-4cec-879f-05486460de19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745722762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2745722762
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3982941748
Short name T1138
Test name
Test status
Simulation time 53383542465 ps
CPU time 47.32 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:31:28 PM PDT 24
Peak memory 199032 kb
Host smart-f75a621c-04c2-482a-b7a8-0bdf9728b21d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982941748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3982941748
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2156284421
Short name T732
Test name
Test status
Simulation time 69189379536 ps
CPU time 393.49 seconds
Started Aug 06 04:29:47 PM PDT 24
Finished Aug 06 04:36:20 PM PDT 24
Peak memory 199696 kb
Host smart-011d6543-864d-4d9e-8ba8-e51deeae9b15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2156284421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2156284421
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.1040215325
Short name T1040
Test name
Test status
Simulation time 6815897757 ps
CPU time 8.31 seconds
Started Aug 06 04:29:37 PM PDT 24
Finished Aug 06 04:29:46 PM PDT 24
Peak memory 199056 kb
Host smart-8d054fea-49f4-42bb-aea5-6f3ce0963da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040215325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1040215325
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.963499329
Short name T854
Test name
Test status
Simulation time 167433134844 ps
CPU time 52.49 seconds
Started Aug 06 04:29:39 PM PDT 24
Finished Aug 06 04:30:31 PM PDT 24
Peak memory 199864 kb
Host smart-fe758b91-a638-48bd-8fa1-85c0afe31424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963499329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.963499329
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.2098628819
Short name T524
Test name
Test status
Simulation time 7446781576 ps
CPU time 95.12 seconds
Started Aug 06 04:29:54 PM PDT 24
Finished Aug 06 04:31:29 PM PDT 24
Peak memory 199712 kb
Host smart-a4f1e8ba-f552-4575-8df5-07cdf6d55d39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2098628819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2098628819
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.152140218
Short name T385
Test name
Test status
Simulation time 2534414049 ps
CPU time 1.27 seconds
Started Aug 06 04:29:39 PM PDT 24
Finished Aug 06 04:29:41 PM PDT 24
Peak memory 198112 kb
Host smart-78b26c78-6d22-475c-a6e6-92396e387edc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=152140218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.152140218
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1293974698
Short name T336
Test name
Test status
Simulation time 44166001687 ps
CPU time 18.04 seconds
Started Aug 06 04:29:51 PM PDT 24
Finished Aug 06 04:30:09 PM PDT 24
Peak memory 199740 kb
Host smart-ca78356f-8df2-4c88-b867-f4bc80eda8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293974698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1293974698
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.855295913
Short name T891
Test name
Test status
Simulation time 5734144275 ps
CPU time 1.59 seconds
Started Aug 06 04:29:39 PM PDT 24
Finished Aug 06 04:29:41 PM PDT 24
Peak memory 195828 kb
Host smart-9bf8eaa9-7bee-4df1-8ab2-c753877f5727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855295913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.855295913
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.716570263
Short name T527
Test name
Test status
Simulation time 554340239 ps
CPU time 1.91 seconds
Started Aug 06 04:29:51 PM PDT 24
Finished Aug 06 04:29:53 PM PDT 24
Peak memory 198036 kb
Host smart-d6cba911-2ec6-4f21-9adb-d7052fa929d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716570263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.716570263
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.116144812
Short name T163
Test name
Test status
Simulation time 530100234914 ps
CPU time 537.29 seconds
Started Aug 06 04:29:48 PM PDT 24
Finished Aug 06 04:38:45 PM PDT 24
Peak memory 199760 kb
Host smart-394789a1-5ba6-40f4-99c9-b200b76bcfc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116144812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.116144812
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3492859609
Short name T998
Test name
Test status
Simulation time 59551914773 ps
CPU time 754.02 seconds
Started Aug 06 04:29:59 PM PDT 24
Finished Aug 06 04:42:33 PM PDT 24
Peak memory 216136 kb
Host smart-798c373d-e85e-47cf-a145-3cfce217f5a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492859609 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3492859609
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.4139645904
Short name T445
Test name
Test status
Simulation time 1504957101 ps
CPU time 2.26 seconds
Started Aug 06 04:29:49 PM PDT 24
Finished Aug 06 04:29:52 PM PDT 24
Peak memory 198728 kb
Host smart-79f004f5-020f-4a20-ac0f-10c42ed3e903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139645904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.4139645904
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3734713976
Short name T315
Test name
Test status
Simulation time 70679472801 ps
CPU time 15.68 seconds
Started Aug 06 04:29:57 PM PDT 24
Finished Aug 06 04:30:13 PM PDT 24
Peak memory 199592 kb
Host smart-d42987da-beee-430a-aa42-d8aa1c708fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734713976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3734713976
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2639519076
Short name T961
Test name
Test status
Simulation time 11955347 ps
CPU time 0.57 seconds
Started Aug 06 04:29:55 PM PDT 24
Finished Aug 06 04:29:56 PM PDT 24
Peak memory 195372 kb
Host smart-610fcf71-89f3-48ac-9cd2-dbfb5d23b0f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639519076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2639519076
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3738010797
Short name T794
Test name
Test status
Simulation time 18544549525 ps
CPU time 25.73 seconds
Started Aug 06 04:29:57 PM PDT 24
Finished Aug 06 04:30:22 PM PDT 24
Peak memory 199532 kb
Host smart-341cedfb-2a12-4e13-99ab-c5b398322077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738010797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3738010797
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.4260745206
Short name T830
Test name
Test status
Simulation time 68374687552 ps
CPU time 32.8 seconds
Started Aug 06 04:29:52 PM PDT 24
Finished Aug 06 04:30:25 PM PDT 24
Peak memory 199732 kb
Host smart-468853ea-07d8-471e-ba3c-2985705adf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260745206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.4260745206
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.525600433
Short name T888
Test name
Test status
Simulation time 203087173881 ps
CPU time 179.28 seconds
Started Aug 06 04:29:57 PM PDT 24
Finished Aug 06 04:32:56 PM PDT 24
Peak memory 199636 kb
Host smart-e366f3a1-ae34-4895-82aa-929c4da93fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525600433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.525600433
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1380150493
Short name T11
Test name
Test status
Simulation time 180254349819 ps
CPU time 264.08 seconds
Started Aug 06 04:29:47 PM PDT 24
Finished Aug 06 04:34:12 PM PDT 24
Peak memory 199564 kb
Host smart-0d5a2de5-0e6b-4d4b-b82b-18b3298918b4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380150493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1380150493
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.1273791839
Short name T666
Test name
Test status
Simulation time 103657781720 ps
CPU time 796.35 seconds
Started Aug 06 04:29:55 PM PDT 24
Finished Aug 06 04:43:11 PM PDT 24
Peak memory 199692 kb
Host smart-5a5740ee-378c-4c2a-8785-409f614661e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1273791839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1273791839
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.4087847284
Short name T402
Test name
Test status
Simulation time 6957176461 ps
CPU time 4.38 seconds
Started Aug 06 04:29:56 PM PDT 24
Finished Aug 06 04:30:01 PM PDT 24
Peak memory 199052 kb
Host smart-53be9510-0e0a-4d7f-af11-d510cdc78ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087847284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.4087847284
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_perf.3929740260
Short name T728
Test name
Test status
Simulation time 16057809151 ps
CPU time 383 seconds
Started Aug 06 04:29:54 PM PDT 24
Finished Aug 06 04:36:17 PM PDT 24
Peak memory 199648 kb
Host smart-56105d7a-96fb-49bb-9c8c-5aae2b462071
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3929740260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3929740260
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1131591949
Short name T1048
Test name
Test status
Simulation time 7128821794 ps
CPU time 36.48 seconds
Started Aug 06 04:29:51 PM PDT 24
Finished Aug 06 04:30:28 PM PDT 24
Peak memory 198892 kb
Host smart-ba7d8bdf-c573-4d14-b738-2fa221f0e72d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1131591949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1131591949
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2063219755
Short name T652
Test name
Test status
Simulation time 63168913680 ps
CPU time 51.98 seconds
Started Aug 06 04:29:52 PM PDT 24
Finished Aug 06 04:30:45 PM PDT 24
Peak memory 199188 kb
Host smart-fd0606be-5602-4163-93d5-e952d6736a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063219755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2063219755
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1451756732
Short name T615
Test name
Test status
Simulation time 586126503 ps
CPU time 1.07 seconds
Started Aug 06 04:29:51 PM PDT 24
Finished Aug 06 04:29:52 PM PDT 24
Peak memory 195208 kb
Host smart-3998cb25-f897-4332-b774-3af50fb973f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451756732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1451756732
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3338605397
Short name T675
Test name
Test status
Simulation time 314336240 ps
CPU time 1.01 seconds
Started Aug 06 04:29:54 PM PDT 24
Finished Aug 06 04:29:55 PM PDT 24
Peak memory 199044 kb
Host smart-6303a483-6bce-49fc-9ac3-0716ac9af069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338605397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3338605397
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1723836594
Short name T864
Test name
Test status
Simulation time 282069431772 ps
CPU time 1623.15 seconds
Started Aug 06 04:29:54 PM PDT 24
Finished Aug 06 04:56:57 PM PDT 24
Peak memory 199796 kb
Host smart-4f95b3de-07b2-4207-90a9-a1b0fa85e0c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723836594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1723836594
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.653772444
Short name T997
Test name
Test status
Simulation time 7638237981 ps
CPU time 14.26 seconds
Started Aug 06 04:29:51 PM PDT 24
Finished Aug 06 04:30:06 PM PDT 24
Peak memory 199800 kb
Host smart-e3eb9a6f-21b6-490b-b351-66448c56f864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653772444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.653772444
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3481231719
Short name T262
Test name
Test status
Simulation time 28531702369 ps
CPU time 13.28 seconds
Started Aug 06 04:29:47 PM PDT 24
Finished Aug 06 04:30:00 PM PDT 24
Peak memory 199704 kb
Host smart-9f815b84-2d9f-4b10-a652-59a9ef745301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481231719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3481231719
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3220569175
Short name T24
Test name
Test status
Simulation time 19163881 ps
CPU time 0.52 seconds
Started Aug 06 04:29:47 PM PDT 24
Finished Aug 06 04:29:47 PM PDT 24
Peak memory 195132 kb
Host smart-2095bd96-289f-437e-bca3-7a5bf398dedd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220569175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3220569175
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.4170568413
Short name T597
Test name
Test status
Simulation time 58730656820 ps
CPU time 90.87 seconds
Started Aug 06 04:29:53 PM PDT 24
Finished Aug 06 04:31:24 PM PDT 24
Peak memory 199748 kb
Host smart-4fc1c8ab-6092-478e-a135-b7b8457f8a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170568413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.4170568413
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3294901808
Short name T767
Test name
Test status
Simulation time 118456661700 ps
CPU time 148.92 seconds
Started Aug 06 04:29:45 PM PDT 24
Finished Aug 06 04:32:14 PM PDT 24
Peak memory 199700 kb
Host smart-36695cbe-5772-48e6-b887-24ebdb8ca993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294901808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3294901808
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1016568128
Short name T1071
Test name
Test status
Simulation time 32287859678 ps
CPU time 13.71 seconds
Started Aug 06 04:29:54 PM PDT 24
Finished Aug 06 04:30:08 PM PDT 24
Peak memory 199708 kb
Host smart-dc004364-f435-4dfd-a82e-ef7e6241cca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016568128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1016568128
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.3430789146
Short name T838
Test name
Test status
Simulation time 27337879443 ps
CPU time 40.62 seconds
Started Aug 06 04:29:52 PM PDT 24
Finished Aug 06 04:30:32 PM PDT 24
Peak memory 199684 kb
Host smart-9242517b-b631-4d2d-8bae-5a7e87fa710c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430789146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3430789146
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1818672204
Short name T462
Test name
Test status
Simulation time 93662294217 ps
CPU time 919.57 seconds
Started Aug 06 04:29:55 PM PDT 24
Finished Aug 06 04:45:15 PM PDT 24
Peak memory 199744 kb
Host smart-980a22cc-20c9-4cb3-a762-38c6732343d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1818672204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1818672204
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.156666027
Short name T22
Test name
Test status
Simulation time 1218879488 ps
CPU time 3.84 seconds
Started Aug 06 04:29:53 PM PDT 24
Finished Aug 06 04:29:57 PM PDT 24
Peak memory 198420 kb
Host smart-1fff9dd7-b28c-42c5-b765-ddab4d5aa092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156666027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.156666027
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1522062777
Short name T456
Test name
Test status
Simulation time 18839243682 ps
CPU time 32.5 seconds
Started Aug 06 04:29:52 PM PDT 24
Finished Aug 06 04:30:25 PM PDT 24
Peak memory 197716 kb
Host smart-19836593-b9ba-4175-8df4-9e82fe14dbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522062777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1522062777
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.2184822016
Short name T551
Test name
Test status
Simulation time 17293317659 ps
CPU time 230.62 seconds
Started Aug 06 04:29:52 PM PDT 24
Finished Aug 06 04:33:43 PM PDT 24
Peak memory 199788 kb
Host smart-45ddc64e-5efb-420f-a517-2d2f7676ab44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184822016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2184822016
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3955351497
Short name T356
Test name
Test status
Simulation time 3513240516 ps
CPU time 13.95 seconds
Started Aug 06 04:29:56 PM PDT 24
Finished Aug 06 04:30:10 PM PDT 24
Peak memory 198028 kb
Host smart-785a6de7-a701-4ce9-9fb2-eacda20de07e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3955351497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3955351497
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.842348014
Short name T1049
Test name
Test status
Simulation time 50973249190 ps
CPU time 82.23 seconds
Started Aug 06 04:29:56 PM PDT 24
Finished Aug 06 04:31:19 PM PDT 24
Peak memory 199708 kb
Host smart-4d0cbe8c-7cc1-4393-8104-6b7bb9e615f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842348014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.842348014
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.889816099
Short name T602
Test name
Test status
Simulation time 628599120 ps
CPU time 1.17 seconds
Started Aug 06 04:29:44 PM PDT 24
Finished Aug 06 04:29:45 PM PDT 24
Peak memory 195416 kb
Host smart-58bdfc00-2fa3-48d3-a2e2-1abffaaa8fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889816099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.889816099
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3885164278
Short name T925
Test name
Test status
Simulation time 5975529398 ps
CPU time 10.89 seconds
Started Aug 06 04:30:56 PM PDT 24
Finished Aug 06 04:31:07 PM PDT 24
Peak memory 199260 kb
Host smart-7f832cc7-5a00-43c5-a7b6-57d52765666a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885164278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3885164278
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.3937796975
Short name T664
Test name
Test status
Simulation time 280212412302 ps
CPU time 717.65 seconds
Started Aug 06 04:29:52 PM PDT 24
Finished Aug 06 04:41:50 PM PDT 24
Peak memory 215480 kb
Host smart-9663f471-c121-413d-8c8f-175a8cd1323c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937796975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3937796975
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2989315800
Short name T883
Test name
Test status
Simulation time 53341318241 ps
CPU time 422.41 seconds
Started Aug 06 04:29:53 PM PDT 24
Finished Aug 06 04:36:56 PM PDT 24
Peak memory 215832 kb
Host smart-616d595b-d518-48b9-ad0c-16e123d2084e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989315800 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2989315800
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2384119015
Short name T311
Test name
Test status
Simulation time 6775670819 ps
CPU time 14.19 seconds
Started Aug 06 04:29:53 PM PDT 24
Finished Aug 06 04:30:07 PM PDT 24
Peak memory 199664 kb
Host smart-4867d099-d20c-4de6-ab68-3599ba593f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384119015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2384119015
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1699380328
Short name T975
Test name
Test status
Simulation time 132852176125 ps
CPU time 403.06 seconds
Started Aug 06 04:29:58 PM PDT 24
Finished Aug 06 04:36:41 PM PDT 24
Peak memory 199740 kb
Host smart-adfafd9f-a1ae-458b-a86a-50d111df2457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699380328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1699380328
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2676544801
Short name T1012
Test name
Test status
Simulation time 33639128 ps
CPU time 0.53 seconds
Started Aug 06 04:29:56 PM PDT 24
Finished Aug 06 04:29:56 PM PDT 24
Peak memory 194084 kb
Host smart-e320f0e5-64b3-4bb8-a935-fc089f986f80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676544801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2676544801
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3896398403
Short name T348
Test name
Test status
Simulation time 34483355806 ps
CPU time 28.75 seconds
Started Aug 06 04:29:54 PM PDT 24
Finished Aug 06 04:30:23 PM PDT 24
Peak memory 199896 kb
Host smart-7b6a5183-3a8e-4b0c-855b-c5aeb733afa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896398403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3896398403
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1934377255
Short name T459
Test name
Test status
Simulation time 126449364289 ps
CPU time 11.48 seconds
Started Aug 06 04:29:47 PM PDT 24
Finished Aug 06 04:29:59 PM PDT 24
Peak memory 199504 kb
Host smart-3889ef62-661c-4946-99ae-002dc7275168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934377255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1934377255
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1177398632
Short name T194
Test name
Test status
Simulation time 71694617956 ps
CPU time 37.25 seconds
Started Aug 06 04:30:57 PM PDT 24
Finished Aug 06 04:31:34 PM PDT 24
Peak memory 199500 kb
Host smart-93fa3ae5-c79e-4f75-936f-20fb0d4f2293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177398632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1177398632
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3697312817
Short name T588
Test name
Test status
Simulation time 41759149677 ps
CPU time 75.97 seconds
Started Aug 06 04:29:54 PM PDT 24
Finished Aug 06 04:31:11 PM PDT 24
Peak memory 199732 kb
Host smart-84679f13-4c75-466a-9ebc-8cfa3ee6cf4b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697312817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3697312817
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.471439100
Short name T954
Test name
Test status
Simulation time 88648992661 ps
CPU time 136.79 seconds
Started Aug 06 04:29:57 PM PDT 24
Finished Aug 06 04:32:14 PM PDT 24
Peak memory 199684 kb
Host smart-e1dbc41b-f076-4bc9-8ef1-4e39407eac62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=471439100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.471439100
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3511018293
Short name T522
Test name
Test status
Simulation time 2515340110 ps
CPU time 5.22 seconds
Started Aug 06 04:29:54 PM PDT 24
Finished Aug 06 04:30:00 PM PDT 24
Peak memory 198008 kb
Host smart-45423295-70b4-4a24-9898-52b1d8fa9654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511018293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3511018293
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.336231704
Short name T907
Test name
Test status
Simulation time 152088817205 ps
CPU time 73.51 seconds
Started Aug 06 04:29:59 PM PDT 24
Finished Aug 06 04:31:13 PM PDT 24
Peak memory 199352 kb
Host smart-259cfb61-e8de-4229-b275-90a840c7de72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336231704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.336231704
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.715894781
Short name T739
Test name
Test status
Simulation time 15821700838 ps
CPU time 498.66 seconds
Started Aug 06 04:29:48 PM PDT 24
Finished Aug 06 04:38:07 PM PDT 24
Peak memory 199708 kb
Host smart-21acfd5c-bb47-4447-82f4-c5fc9259bc07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=715894781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.715894781
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.3839727361
Short name T840
Test name
Test status
Simulation time 5136484311 ps
CPU time 10.2 seconds
Started Aug 06 04:29:59 PM PDT 24
Finished Aug 06 04:30:10 PM PDT 24
Peak memory 198448 kb
Host smart-aa783ccd-4453-45e9-b080-a6f7707dabec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3839727361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3839727361
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.4240936481
Short name T683
Test name
Test status
Simulation time 79521897563 ps
CPU time 116.25 seconds
Started Aug 06 04:29:47 PM PDT 24
Finished Aug 06 04:31:44 PM PDT 24
Peak memory 199640 kb
Host smart-fb32c77e-e14d-4a11-ba33-bfa696148b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240936481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.4240936481
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.4046756971
Short name T711
Test name
Test status
Simulation time 1883339496 ps
CPU time 1.38 seconds
Started Aug 06 04:29:55 PM PDT 24
Finished Aug 06 04:29:56 PM PDT 24
Peak memory 195196 kb
Host smart-c5072bdb-b7f4-4a16-a2bb-406b35c4655b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046756971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.4046756971
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1242972128
Short name T327
Test name
Test status
Simulation time 5563340027 ps
CPU time 8.72 seconds
Started Aug 06 04:29:55 PM PDT 24
Finished Aug 06 04:30:04 PM PDT 24
Peak memory 199512 kb
Host smart-71dd48d7-2a93-464a-a70d-c5a1925d1910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242972128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1242972128
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.585082129
Short name T164
Test name
Test status
Simulation time 208098582727 ps
CPU time 155.62 seconds
Started Aug 06 04:29:50 PM PDT 24
Finished Aug 06 04:32:26 PM PDT 24
Peak memory 199548 kb
Host smart-64b9316a-bca9-48e6-b05c-31407fe260e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585082129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.585082129
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.316470456
Short name T16
Test name
Test status
Simulation time 6509006027 ps
CPU time 20.39 seconds
Started Aug 06 04:29:56 PM PDT 24
Finished Aug 06 04:30:16 PM PDT 24
Peak memory 199372 kb
Host smart-80d1194a-80c2-4997-b98b-046254b55dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316470456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.316470456
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3745751781
Short name T692
Test name
Test status
Simulation time 31328020831 ps
CPU time 59.59 seconds
Started Aug 06 04:29:55 PM PDT 24
Finished Aug 06 04:30:55 PM PDT 24
Peak memory 199740 kb
Host smart-47714fc2-9d57-47fe-8ceb-4f6d72508f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745751781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3745751781
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1854786683
Short name T733
Test name
Test status
Simulation time 17650459 ps
CPU time 0.57 seconds
Started Aug 06 04:29:57 PM PDT 24
Finished Aug 06 04:29:58 PM PDT 24
Peak memory 195096 kb
Host smart-b722745d-0e87-447b-9655-3ce1b639384d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854786683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1854786683
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.735035804
Short name T331
Test name
Test status
Simulation time 144920038044 ps
CPU time 142.8 seconds
Started Aug 06 04:29:57 PM PDT 24
Finished Aug 06 04:32:20 PM PDT 24
Peak memory 199632 kb
Host smart-08e31776-0990-4720-8feb-a23dccaef06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735035804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.735035804
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2657314327
Short name T1009
Test name
Test status
Simulation time 23103884219 ps
CPU time 45.65 seconds
Started Aug 06 04:30:02 PM PDT 24
Finished Aug 06 04:30:48 PM PDT 24
Peak memory 199772 kb
Host smart-907c9b61-1c5c-4fbf-8ba2-abe8870f3ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657314327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2657314327
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.42789972
Short name T694
Test name
Test status
Simulation time 209135034669 ps
CPU time 290.02 seconds
Started Aug 06 04:29:55 PM PDT 24
Finished Aug 06 04:34:46 PM PDT 24
Peak memory 197948 kb
Host smart-4aed50fa-b41f-4955-841b-2e7f2e5df0fd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42789972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.42789972
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.628862395
Short name T605
Test name
Test status
Simulation time 74399851449 ps
CPU time 560.77 seconds
Started Aug 06 04:30:03 PM PDT 24
Finished Aug 06 04:39:24 PM PDT 24
Peak memory 199120 kb
Host smart-7d62ee27-86b2-44c7-9c23-e222564db794
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=628862395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.628862395
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1923799854
Short name T449
Test name
Test status
Simulation time 2469189769 ps
CPU time 4.41 seconds
Started Aug 06 04:30:02 PM PDT 24
Finished Aug 06 04:30:06 PM PDT 24
Peak memory 196952 kb
Host smart-be76ec1a-c4d1-4c04-a4f3-e2ca06936ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923799854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1923799854
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3311864975
Short name T834
Test name
Test status
Simulation time 3940786927 ps
CPU time 6.48 seconds
Started Aug 06 04:31:21 PM PDT 24
Finished Aug 06 04:31:28 PM PDT 24
Peak memory 194332 kb
Host smart-d88f740d-d126-4fdf-8ea0-01d82ca223d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311864975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3311864975
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2305145740
Short name T632
Test name
Test status
Simulation time 10046291497 ps
CPU time 130.97 seconds
Started Aug 06 04:30:05 PM PDT 24
Finished Aug 06 04:32:17 PM PDT 24
Peak memory 199756 kb
Host smart-8800d6f4-3e61-4fc6-8121-981f06fb8b79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2305145740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2305145740
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3733181220
Short name T1177
Test name
Test status
Simulation time 1404200263 ps
CPU time 1.07 seconds
Started Aug 06 04:29:59 PM PDT 24
Finished Aug 06 04:30:01 PM PDT 24
Peak memory 195300 kb
Host smart-bb0438c9-cc65-4d21-b356-57781aa225ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3733181220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3733181220
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1870387430
Short name T137
Test name
Test status
Simulation time 65452418243 ps
CPU time 29.27 seconds
Started Aug 06 04:30:01 PM PDT 24
Finished Aug 06 04:30:30 PM PDT 24
Peak memory 199708 kb
Host smart-69c7ebba-d990-4548-ae3e-d2a4a2cf7006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870387430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1870387430
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.122015886
Short name T881
Test name
Test status
Simulation time 26895164095 ps
CPU time 22.94 seconds
Started Aug 06 04:29:57 PM PDT 24
Finished Aug 06 04:30:20 PM PDT 24
Peak memory 195828 kb
Host smart-8461d255-e400-4fc4-8e82-031570cd9874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122015886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.122015886
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3578468803
Short name T372
Test name
Test status
Simulation time 690863362 ps
CPU time 4.6 seconds
Started Aug 06 04:30:00 PM PDT 24
Finished Aug 06 04:30:05 PM PDT 24
Peak memory 198676 kb
Host smart-6e3ba9a9-f68f-45ee-85ea-05f1e56e52b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578468803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3578468803
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2856171813
Short name T1019
Test name
Test status
Simulation time 872569370462 ps
CPU time 273.41 seconds
Started Aug 06 04:30:02 PM PDT 24
Finished Aug 06 04:34:35 PM PDT 24
Peak memory 199600 kb
Host smart-80f47a78-1836-48af-884d-4025906c5edf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856171813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2856171813
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.890936843
Short name T296
Test name
Test status
Simulation time 53371806573 ps
CPU time 282.97 seconds
Started Aug 06 04:29:58 PM PDT 24
Finished Aug 06 04:34:41 PM PDT 24
Peak memory 216268 kb
Host smart-c288c84a-0690-489c-913d-cb1151929b41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890936843 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.890936843
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.3240369475
Short name T1147
Test name
Test status
Simulation time 7106762891 ps
CPU time 11.85 seconds
Started Aug 06 04:30:02 PM PDT 24
Finished Aug 06 04:30:14 PM PDT 24
Peak memory 199676 kb
Host smart-5815c558-0350-4193-9bd1-71c6b279b60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240369475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3240369475
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.46020353
Short name T660
Test name
Test status
Simulation time 24752367437 ps
CPU time 38.12 seconds
Started Aug 06 04:30:01 PM PDT 24
Finished Aug 06 04:30:39 PM PDT 24
Peak memory 199764 kb
Host smart-13c5c2f6-369c-46a8-a6db-224d4a0feb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46020353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.46020353
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3782935008
Short name T390
Test name
Test status
Simulation time 14851908 ps
CPU time 0.54 seconds
Started Aug 06 04:30:06 PM PDT 24
Finished Aug 06 04:30:06 PM PDT 24
Peak memory 195076 kb
Host smart-c386dc35-8891-4da5-bb8a-dced7931ad2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782935008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3782935008
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.199754866
Short name T943
Test name
Test status
Simulation time 173867425045 ps
CPU time 407.32 seconds
Started Aug 06 04:29:56 PM PDT 24
Finished Aug 06 04:36:43 PM PDT 24
Peak memory 199768 kb
Host smart-ff483e06-f11e-4baa-ad46-306e4e814db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199754866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.199754866
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.842226378
Short name T890
Test name
Test status
Simulation time 29533572982 ps
CPU time 48.22 seconds
Started Aug 06 04:30:01 PM PDT 24
Finished Aug 06 04:30:49 PM PDT 24
Peak memory 199732 kb
Host smart-de57ea62-7c2f-4e7b-bf1e-579b1cfb9099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842226378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.842226378
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.545272034
Short name T833
Test name
Test status
Simulation time 17754303403 ps
CPU time 34.46 seconds
Started Aug 06 04:29:59 PM PDT 24
Finished Aug 06 04:30:33 PM PDT 24
Peak memory 199476 kb
Host smart-06cf8b29-bca4-4a68-b686-ba6149e158a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545272034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.545272034
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2441806582
Short name T586
Test name
Test status
Simulation time 45268032895 ps
CPU time 74.94 seconds
Started Aug 06 04:30:02 PM PDT 24
Finished Aug 06 04:31:17 PM PDT 24
Peak memory 199736 kb
Host smart-4c62c444-187f-47d9-aeec-5d7fa946f00f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441806582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2441806582
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3817059868
Short name T1166
Test name
Test status
Simulation time 181041504906 ps
CPU time 1098.78 seconds
Started Aug 06 04:29:58 PM PDT 24
Finished Aug 06 04:48:17 PM PDT 24
Peak memory 199712 kb
Host smart-49c7a634-77d9-42f1-9b7f-256500d4d789
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3817059868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3817059868
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.4174163807
Short name T380
Test name
Test status
Simulation time 9092870710 ps
CPU time 11.65 seconds
Started Aug 06 04:30:01 PM PDT 24
Finished Aug 06 04:30:13 PM PDT 24
Peak memory 199656 kb
Host smart-c4434af0-913d-4694-bbc8-e0a44a3d17f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174163807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.4174163807
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1312033463
Short name T290
Test name
Test status
Simulation time 11033835190 ps
CPU time 8.62 seconds
Started Aug 06 04:30:01 PM PDT 24
Finished Aug 06 04:30:10 PM PDT 24
Peak memory 199696 kb
Host smart-cc8c6739-d01f-4825-80bc-31f5a1f75697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312033463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1312033463
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3613176986
Short name T747
Test name
Test status
Simulation time 7618342382 ps
CPU time 464.3 seconds
Started Aug 06 04:29:54 PM PDT 24
Finished Aug 06 04:37:39 PM PDT 24
Peak memory 199756 kb
Host smart-c23f33b5-ef0a-4e4e-98eb-ebf72c682361
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3613176986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3613176986
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1788757391
Short name T416
Test name
Test status
Simulation time 5073475438 ps
CPU time 11.94 seconds
Started Aug 06 04:30:06 PM PDT 24
Finished Aug 06 04:30:18 PM PDT 24
Peak memory 199660 kb
Host smart-222fe10b-c436-4ffd-936b-1a726e5e62fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1788757391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1788757391
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3518288000
Short name T947
Test name
Test status
Simulation time 43622159291 ps
CPU time 32.28 seconds
Started Aug 06 04:29:58 PM PDT 24
Finished Aug 06 04:30:30 PM PDT 24
Peak memory 199300 kb
Host smart-de810d8f-eefd-4443-a7de-2d17c793cf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518288000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3518288000
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.855452726
Short name T368
Test name
Test status
Simulation time 3674304560 ps
CPU time 2.2 seconds
Started Aug 06 04:29:58 PM PDT 24
Finished Aug 06 04:30:00 PM PDT 24
Peak memory 196088 kb
Host smart-e063c9ed-e372-4d3c-a95e-ee7b691aee02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855452726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.855452726
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1877273554
Short name T847
Test name
Test status
Simulation time 523935445 ps
CPU time 1.56 seconds
Started Aug 06 04:30:01 PM PDT 24
Finished Aug 06 04:30:03 PM PDT 24
Peak memory 199384 kb
Host smart-af20597b-2c4b-4442-a75f-ebaca7e46019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877273554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1877273554
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.3576099770
Short name T105
Test name
Test status
Simulation time 194146316293 ps
CPU time 455.68 seconds
Started Aug 06 04:29:57 PM PDT 24
Finished Aug 06 04:37:33 PM PDT 24
Peak memory 226560 kb
Host smart-2507c3fa-ae5d-45e8-b877-239f3c19aad9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576099770 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.3576099770
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2687319087
Short name T674
Test name
Test status
Simulation time 1463661735 ps
CPU time 2.11 seconds
Started Aug 06 04:30:07 PM PDT 24
Finished Aug 06 04:30:09 PM PDT 24
Peak memory 198252 kb
Host smart-902418c9-292b-4578-b926-92f6da88a276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687319087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2687319087
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2822366731
Short name T535
Test name
Test status
Simulation time 41300622976 ps
CPU time 10.54 seconds
Started Aug 06 04:29:56 PM PDT 24
Finished Aug 06 04:30:07 PM PDT 24
Peak memory 199600 kb
Host smart-f9b97ad2-17d5-4feb-bb60-8fb4191d7cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822366731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2822366731
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.877112131
Short name T440
Test name
Test status
Simulation time 34359602 ps
CPU time 0.58 seconds
Started Aug 06 04:30:00 PM PDT 24
Finished Aug 06 04:30:01 PM PDT 24
Peak memory 195184 kb
Host smart-80da02c1-59d4-4b12-a497-2986fbc8f458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877112131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.877112131
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3221179903
Short name T898
Test name
Test status
Simulation time 31721576513 ps
CPU time 41.78 seconds
Started Aug 06 04:29:58 PM PDT 24
Finished Aug 06 04:30:39 PM PDT 24
Peak memory 199824 kb
Host smart-bbbdf60b-3602-4b86-a743-895f9c94f2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221179903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3221179903
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2754196818
Short name T835
Test name
Test status
Simulation time 55356318348 ps
CPU time 22.44 seconds
Started Aug 06 04:30:02 PM PDT 24
Finished Aug 06 04:30:25 PM PDT 24
Peak memory 199664 kb
Host smart-98666a9a-1002-4b6a-b1ee-9b37eac5fb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754196818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2754196818
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_intr.3933919645
Short name T705
Test name
Test status
Simulation time 7072628397 ps
CPU time 7.26 seconds
Started Aug 06 04:29:57 PM PDT 24
Finished Aug 06 04:30:04 PM PDT 24
Peak memory 199716 kb
Host smart-1d133848-4ca1-4c8e-8958-f0bd41521ba0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933919645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3933919645
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2647402652
Short name T585
Test name
Test status
Simulation time 36245484769 ps
CPU time 102.89 seconds
Started Aug 06 04:29:57 PM PDT 24
Finished Aug 06 04:31:40 PM PDT 24
Peak memory 199700 kb
Host smart-630e2f44-a9b8-4a2b-8f04-73f5e68f8711
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2647402652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2647402652
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.1795103670
Short name T861
Test name
Test status
Simulation time 8610804476 ps
CPU time 3.55 seconds
Started Aug 06 04:29:57 PM PDT 24
Finished Aug 06 04:30:01 PM PDT 24
Peak memory 198404 kb
Host smart-585d0f49-f1a4-46f5-b37b-f08b719d687f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795103670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1795103670
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3141298959
Short name T344
Test name
Test status
Simulation time 2090074086 ps
CPU time 3.51 seconds
Started Aug 06 04:31:20 PM PDT 24
Finished Aug 06 04:31:24 PM PDT 24
Peak memory 199528 kb
Host smart-b8fe6158-cc26-44c1-aece-c9300091c140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141298959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3141298959
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2594935052
Short name T297
Test name
Test status
Simulation time 18268602025 ps
CPU time 80.88 seconds
Started Aug 06 04:29:57 PM PDT 24
Finished Aug 06 04:31:19 PM PDT 24
Peak memory 199712 kb
Host smart-a3b55f71-338d-4094-a300-734c07f059c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2594935052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2594935052
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2742516219
Short name T771
Test name
Test status
Simulation time 1698462539 ps
CPU time 9.03 seconds
Started Aug 06 04:29:58 PM PDT 24
Finished Aug 06 04:30:07 PM PDT 24
Peak memory 197816 kb
Host smart-4459f9a7-3551-4440-9913-951596da108a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2742516219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2742516219
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.4180718368
Short name T6
Test name
Test status
Simulation time 102340427812 ps
CPU time 43.54 seconds
Started Aug 06 04:30:01 PM PDT 24
Finished Aug 06 04:30:45 PM PDT 24
Peak memory 199656 kb
Host smart-919c4ae5-1a64-4b9b-9777-4da8f9f139af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180718368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.4180718368
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.193035175
Short name T415
Test name
Test status
Simulation time 2739778514 ps
CPU time 4.37 seconds
Started Aug 06 04:30:01 PM PDT 24
Finished Aug 06 04:30:05 PM PDT 24
Peak memory 196300 kb
Host smart-5dcb20a1-0956-4b59-a05b-21a94f0fa007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193035175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.193035175
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1358033941
Short name T305
Test name
Test status
Simulation time 264597373 ps
CPU time 1.51 seconds
Started Aug 06 04:29:54 PM PDT 24
Finished Aug 06 04:29:56 PM PDT 24
Peak memory 198152 kb
Host smart-6c61f141-062d-480b-b4eb-c7c6d1c03460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358033941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1358033941
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.2093065117
Short name T887
Test name
Test status
Simulation time 464141874689 ps
CPU time 821.63 seconds
Started Aug 06 04:30:03 PM PDT 24
Finished Aug 06 04:43:45 PM PDT 24
Peak memory 199172 kb
Host smart-e9a58665-0a4d-4ccd-8c68-3e31c047d4c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093065117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2093065117
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1037100499
Short name T1079
Test name
Test status
Simulation time 45494931977 ps
CPU time 560.74 seconds
Started Aug 06 04:30:00 PM PDT 24
Finished Aug 06 04:39:21 PM PDT 24
Peak memory 216252 kb
Host smart-5ebb1a7f-1dbc-4c86-84c6-cea7add6e602
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037100499 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1037100499
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.751431350
Short name T1116
Test name
Test status
Simulation time 2767649167 ps
CPU time 1.81 seconds
Started Aug 06 04:29:59 PM PDT 24
Finished Aug 06 04:30:01 PM PDT 24
Peak memory 198388 kb
Host smart-755d9bd4-1765-4e8b-b14d-c8ed22f34ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751431350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.751431350
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.948184044
Short name T1000
Test name
Test status
Simulation time 22629549820 ps
CPU time 9.88 seconds
Started Aug 06 04:30:00 PM PDT 24
Finished Aug 06 04:30:10 PM PDT 24
Peak memory 198896 kb
Host smart-d92b1925-c2e7-48a6-9549-30b675d5409e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948184044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.948184044
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2191642043
Short name T579
Test name
Test status
Simulation time 45357857 ps
CPU time 0.53 seconds
Started Aug 06 04:31:21 PM PDT 24
Finished Aug 06 04:31:22 PM PDT 24
Peak memory 194908 kb
Host smart-37417f61-a834-440e-a030-a963be5203d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191642043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2191642043
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1772716321
Short name T168
Test name
Test status
Simulation time 247753453391 ps
CPU time 260.12 seconds
Started Aug 06 04:30:06 PM PDT 24
Finished Aug 06 04:34:26 PM PDT 24
Peak memory 199752 kb
Host smart-3a4de85e-7fe7-43d5-aa4d-139f241c95f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772716321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1772716321
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.49681693
Short name T725
Test name
Test status
Simulation time 87818204219 ps
CPU time 32.27 seconds
Started Aug 06 04:29:56 PM PDT 24
Finished Aug 06 04:30:29 PM PDT 24
Peak memory 199324 kb
Host smart-e77ae8b3-4594-42c3-8870-3be57f3fa143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49681693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.49681693
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2506119455
Short name T341
Test name
Test status
Simulation time 25555371076 ps
CPU time 22.73 seconds
Started Aug 06 04:30:00 PM PDT 24
Finished Aug 06 04:30:23 PM PDT 24
Peak memory 199772 kb
Host smart-0001a6e5-1c0c-4375-b539-9d6dcac35268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506119455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2506119455
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1694293114
Short name T931
Test name
Test status
Simulation time 79384924310 ps
CPU time 32.77 seconds
Started Aug 06 04:30:03 PM PDT 24
Finished Aug 06 04:30:35 PM PDT 24
Peak memory 199620 kb
Host smart-b310aae1-bdd8-49a9-aa19-4d57af7005e6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694293114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1694293114
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.685120525
Short name T505
Test name
Test status
Simulation time 112816385546 ps
CPU time 222.81 seconds
Started Aug 06 04:31:20 PM PDT 24
Finished Aug 06 04:35:03 PM PDT 24
Peak memory 199668 kb
Host smart-b47b8a57-e531-43b7-ba4f-8fd8124d67a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=685120525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.685120525
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.1577813463
Short name T363
Test name
Test status
Simulation time 5006743919 ps
CPU time 3 seconds
Started Aug 06 04:30:02 PM PDT 24
Finished Aug 06 04:30:05 PM PDT 24
Peak memory 197848 kb
Host smart-89fcb7a8-557f-488e-bf3b-e26cd64aedbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577813463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1577813463
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3789170034
Short name T1029
Test name
Test status
Simulation time 15750201412 ps
CPU time 26.92 seconds
Started Aug 06 04:29:59 PM PDT 24
Finished Aug 06 04:30:26 PM PDT 24
Peak memory 198240 kb
Host smart-f855513a-f069-42ad-8976-4f6414567e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789170034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3789170034
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.734621854
Short name T678
Test name
Test status
Simulation time 7948937428 ps
CPU time 87.86 seconds
Started Aug 06 04:31:21 PM PDT 24
Finished Aug 06 04:32:49 PM PDT 24
Peak memory 199700 kb
Host smart-5117c3a7-5b26-4cae-b36d-1e677dbb79c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=734621854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.734621854
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.3333239971
Short name T518
Test name
Test status
Simulation time 6332352564 ps
CPU time 48.67 seconds
Started Aug 06 04:30:00 PM PDT 24
Finished Aug 06 04:30:49 PM PDT 24
Peak memory 198496 kb
Host smart-736b7807-0641-464b-9071-1702ccb7b771
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3333239971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3333239971
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1214767133
Short name T634
Test name
Test status
Simulation time 109465188363 ps
CPU time 88.27 seconds
Started Aug 06 04:30:03 PM PDT 24
Finished Aug 06 04:31:32 PM PDT 24
Peak memory 199732 kb
Host smart-afd98f4e-6c61-4c6e-9b16-d75ba65e2558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214767133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1214767133
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1446578525
Short name T1024
Test name
Test status
Simulation time 3634555641 ps
CPU time 5.54 seconds
Started Aug 06 04:30:01 PM PDT 24
Finished Aug 06 04:30:07 PM PDT 24
Peak memory 196084 kb
Host smart-b273337f-37cd-4c64-ba1e-c1818ab048e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446578525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1446578525
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.349054648
Short name T383
Test name
Test status
Simulation time 449512999 ps
CPU time 1.68 seconds
Started Aug 06 04:29:58 PM PDT 24
Finished Aug 06 04:29:59 PM PDT 24
Peak memory 199024 kb
Host smart-6eb06290-9ac7-4330-a4ba-47a8e01b51b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349054648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.349054648
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3748798473
Short name T637
Test name
Test status
Simulation time 176566168798 ps
CPU time 1358.13 seconds
Started Aug 06 04:30:00 PM PDT 24
Finished Aug 06 04:52:38 PM PDT 24
Peak memory 226620 kb
Host smart-e6b21f5c-c818-464b-859b-8ed730a9b26f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748798473 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3748798473
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.596959175
Short name T627
Test name
Test status
Simulation time 3662140003 ps
CPU time 1.85 seconds
Started Aug 06 04:29:59 PM PDT 24
Finished Aug 06 04:30:01 PM PDT 24
Peak memory 198876 kb
Host smart-b47bd6fa-e5b0-424c-92c2-5cc250ef6327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596959175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.596959175
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1186023114
Short name T814
Test name
Test status
Simulation time 12886832414 ps
CPU time 8.8 seconds
Started Aug 06 04:30:01 PM PDT 24
Finished Aug 06 04:30:10 PM PDT 24
Peak memory 199764 kb
Host smart-b0e9e65a-2e7a-45e3-9f27-6dcd76e3f917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186023114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1186023114
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3167131279
Short name T25
Test name
Test status
Simulation time 28333260 ps
CPU time 0.57 seconds
Started Aug 06 04:29:59 PM PDT 24
Finished Aug 06 04:30:00 PM PDT 24
Peak memory 195328 kb
Host smart-378cb674-4d2a-4d50-a75b-91ffe2366b1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167131279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3167131279
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.900962742
Short name T918
Test name
Test status
Simulation time 77718359951 ps
CPU time 139.03 seconds
Started Aug 06 04:30:13 PM PDT 24
Finished Aug 06 04:32:32 PM PDT 24
Peak memory 199720 kb
Host smart-076f4635-c8fe-4d94-95ca-6553f26742fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900962742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.900962742
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.656982324
Short name T720
Test name
Test status
Simulation time 95337246767 ps
CPU time 23.78 seconds
Started Aug 06 04:30:00 PM PDT 24
Finished Aug 06 04:30:24 PM PDT 24
Peak memory 199616 kb
Host smart-7ab6b333-82ec-4fa8-9825-390364b67311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656982324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.656982324
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.3883870144
Short name T263
Test name
Test status
Simulation time 102736504418 ps
CPU time 19.41 seconds
Started Aug 06 04:29:56 PM PDT 24
Finished Aug 06 04:30:16 PM PDT 24
Peak memory 199664 kb
Host smart-fbd71e7b-4126-49b6-86cd-5bd8cc827edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883870144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3883870144
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.2043922088
Short name T1167
Test name
Test status
Simulation time 37144951347 ps
CPU time 61.46 seconds
Started Aug 06 04:29:58 PM PDT 24
Finished Aug 06 04:31:00 PM PDT 24
Peak memory 199712 kb
Host smart-974233b3-c6ec-4f5a-b3d3-ebf12e8c782f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043922088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2043922088
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.126827521
Short name T919
Test name
Test status
Simulation time 100582499476 ps
CPU time 456.24 seconds
Started Aug 06 04:30:01 PM PDT 24
Finished Aug 06 04:37:37 PM PDT 24
Peak memory 199708 kb
Host smart-7ddc2787-f3be-4837-bbdb-6d6592391879
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126827521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.126827521
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1078866603
Short name T882
Test name
Test status
Simulation time 1558432443 ps
CPU time 3.04 seconds
Started Aug 06 04:29:57 PM PDT 24
Finished Aug 06 04:30:00 PM PDT 24
Peak memory 198112 kb
Host smart-dd3079d8-a0ea-433e-bb84-b1474e0daab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078866603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1078866603
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2288959636
Short name T476
Test name
Test status
Simulation time 77730523880 ps
CPU time 55.61 seconds
Started Aug 06 04:30:00 PM PDT 24
Finished Aug 06 04:30:56 PM PDT 24
Peak memory 200016 kb
Host smart-e4f7cb2e-83d9-46cd-b918-ec3d78c5963b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288959636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2288959636
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2158355146
Short name T894
Test name
Test status
Simulation time 15397892174 ps
CPU time 815.19 seconds
Started Aug 06 04:31:06 PM PDT 24
Finished Aug 06 04:44:42 PM PDT 24
Peak memory 198752 kb
Host smart-826235ab-ffdf-4edf-a0f2-6125bf3c909e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2158355146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2158355146
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3585011978
Short name T1031
Test name
Test status
Simulation time 1797146041 ps
CPU time 3.13 seconds
Started Aug 06 04:29:59 PM PDT 24
Finished Aug 06 04:30:03 PM PDT 24
Peak memory 197744 kb
Host smart-5f9e509b-992d-4ab2-ab88-97a6da816bf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3585011978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3585011978
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3627597504
Short name T600
Test name
Test status
Simulation time 53211110032 ps
CPU time 69.68 seconds
Started Aug 06 04:30:01 PM PDT 24
Finished Aug 06 04:31:10 PM PDT 24
Peak memory 199792 kb
Host smart-0dde3b1e-ef5d-4807-8adf-1b70218640f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627597504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3627597504
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3295908037
Short name T825
Test name
Test status
Simulation time 679771823 ps
CPU time 1.72 seconds
Started Aug 06 04:30:02 PM PDT 24
Finished Aug 06 04:30:03 PM PDT 24
Peak memory 195468 kb
Host smart-7d62d3e1-3ea9-4bc3-95ee-e7e3e799538e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295908037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3295908037
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2554518957
Short name T991
Test name
Test status
Simulation time 343664326 ps
CPU time 0.95 seconds
Started Aug 06 04:31:21 PM PDT 24
Finished Aug 06 04:31:22 PM PDT 24
Peak memory 198420 kb
Host smart-bbe5a994-2989-4d5b-b5a9-529363d26eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554518957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2554518957
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2452122242
Short name T512
Test name
Test status
Simulation time 272732551904 ps
CPU time 232.38 seconds
Started Aug 06 04:30:02 PM PDT 24
Finished Aug 06 04:33:54 PM PDT 24
Peak memory 199752 kb
Host smart-90c309d1-ee3a-4fbb-97c8-0e08f63798ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452122242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2452122242
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1219127207
Short name T295
Test name
Test status
Simulation time 10324419310 ps
CPU time 115.97 seconds
Started Aug 06 04:30:02 PM PDT 24
Finished Aug 06 04:31:58 PM PDT 24
Peak memory 215792 kb
Host smart-b5c032d0-6f69-48ad-bef9-f804b90e3410
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219127207 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1219127207
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3830730331
Short name T95
Test name
Test status
Simulation time 635729504 ps
CPU time 0.94 seconds
Started Aug 06 04:29:57 PM PDT 24
Finished Aug 06 04:29:58 PM PDT 24
Peak memory 197772 kb
Host smart-9db1b84c-f0f5-4306-9b7b-46a234043659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830730331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3830730331
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3311320783
Short name T849
Test name
Test status
Simulation time 7704499491 ps
CPU time 8.42 seconds
Started Aug 06 04:30:57 PM PDT 24
Finished Aug 06 04:31:05 PM PDT 24
Peak memory 196196 kb
Host smart-f4b677c7-974c-40cf-a09d-9c81705734a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311320783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3311320783
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1662178074
Short name T708
Test name
Test status
Simulation time 66737329 ps
CPU time 0.56 seconds
Started Aug 06 04:30:11 PM PDT 24
Finished Aug 06 04:30:12 PM PDT 24
Peak memory 195108 kb
Host smart-05984e16-0f53-4295-aad8-3fc8d664669f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662178074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1662178074
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.429239305
Short name T545
Test name
Test status
Simulation time 136512543640 ps
CPU time 68.56 seconds
Started Aug 06 04:31:20 PM PDT 24
Finished Aug 06 04:32:29 PM PDT 24
Peak memory 199684 kb
Host smart-89eeb6a8-b52f-4160-a743-b75172f8d374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429239305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.429239305
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3142660412
Short name T134
Test name
Test status
Simulation time 24057423078 ps
CPU time 48.28 seconds
Started Aug 06 04:29:59 PM PDT 24
Finished Aug 06 04:30:48 PM PDT 24
Peak memory 199536 kb
Host smart-0ae0ccfd-3e27-4d32-9c68-00fe05797863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142660412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3142660412
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.4079922833
Short name T465
Test name
Test status
Simulation time 73799310040 ps
CPU time 116.14 seconds
Started Aug 06 04:30:01 PM PDT 24
Finished Aug 06 04:31:57 PM PDT 24
Peak memory 199680 kb
Host smart-23073bfe-c57c-40f7-a726-7b5ec4e801fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079922833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.4079922833
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3151928757
Short name T926
Test name
Test status
Simulation time 8792166798 ps
CPU time 4.7 seconds
Started Aug 06 04:29:58 PM PDT 24
Finished Aug 06 04:30:03 PM PDT 24
Peak memory 199784 kb
Host smart-7f6e8462-a126-43b4-8fff-55e51b89b663
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151928757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3151928757
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3013922819
Short name T532
Test name
Test status
Simulation time 71176892105 ps
CPU time 748 seconds
Started Aug 06 04:30:10 PM PDT 24
Finished Aug 06 04:42:38 PM PDT 24
Peak memory 199676 kb
Host smart-309daf63-b1d1-49ba-bba5-b2012550dd18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3013922819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3013922819
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.297101371
Short name T1157
Test name
Test status
Simulation time 5739504108 ps
CPU time 3.64 seconds
Started Aug 06 04:30:08 PM PDT 24
Finished Aug 06 04:30:12 PM PDT 24
Peak memory 199304 kb
Host smart-b307aa10-6f0c-40b4-b8bf-236d0caac28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297101371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.297101371
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3823894605
Short name T413
Test name
Test status
Simulation time 117918376257 ps
CPU time 63.93 seconds
Started Aug 06 04:31:20 PM PDT 24
Finished Aug 06 04:32:24 PM PDT 24
Peak memory 199816 kb
Host smart-cde5a401-5c8c-480a-985c-6d12d54be9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823894605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3823894605
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.4185095589
Short name T1062
Test name
Test status
Simulation time 19017427963 ps
CPU time 194.58 seconds
Started Aug 06 04:30:10 PM PDT 24
Finished Aug 06 04:33:25 PM PDT 24
Peak memory 199672 kb
Host smart-cc25fb5a-ab96-48f2-970f-6345707fedba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4185095589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.4185095589
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.4246992739
Short name T1018
Test name
Test status
Simulation time 6827049851 ps
CPU time 16.56 seconds
Started Aug 06 04:29:57 PM PDT 24
Finished Aug 06 04:30:14 PM PDT 24
Peak memory 197952 kb
Host smart-0cacebfc-7599-4dcb-a18a-9ee99f8fb7ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4246992739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.4246992739
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1312905309
Short name T737
Test name
Test status
Simulation time 20424214724 ps
CPU time 19.11 seconds
Started Aug 06 04:30:12 PM PDT 24
Finished Aug 06 04:30:32 PM PDT 24
Peak memory 199644 kb
Host smart-83f73568-af6b-4beb-88f6-69367d2525a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312905309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1312905309
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.4014184670
Short name T595
Test name
Test status
Simulation time 5565700391 ps
CPU time 2.59 seconds
Started Aug 06 04:30:10 PM PDT 24
Finished Aug 06 04:30:12 PM PDT 24
Peak memory 196248 kb
Host smart-c7466f40-fa6b-45a8-9d65-709ae4510f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014184670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.4014184670
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3957812047
Short name T769
Test name
Test status
Simulation time 484882742 ps
CPU time 3.19 seconds
Started Aug 06 04:31:06 PM PDT 24
Finished Aug 06 04:31:10 PM PDT 24
Peak memory 197780 kb
Host smart-7725f4fa-279f-4ec6-b3a0-794b6a386661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957812047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3957812047
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2883905037
Short name T656
Test name
Test status
Simulation time 141954495868 ps
CPU time 178.64 seconds
Started Aug 06 04:30:07 PM PDT 24
Finished Aug 06 04:33:06 PM PDT 24
Peak memory 208092 kb
Host smart-e60e035d-b450-49fd-9be7-c20e93f34659
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883905037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2883905037
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2884006804
Short name T53
Test name
Test status
Simulation time 261495177200 ps
CPU time 1203.82 seconds
Started Aug 06 04:30:13 PM PDT 24
Finished Aug 06 04:50:17 PM PDT 24
Peak memory 228008 kb
Host smart-ed6dc86a-3948-4cff-951f-b210319657b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884006804 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2884006804
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2157822828
Short name T911
Test name
Test status
Simulation time 861241253 ps
CPU time 1.35 seconds
Started Aug 06 04:30:08 PM PDT 24
Finished Aug 06 04:30:10 PM PDT 24
Peak memory 198656 kb
Host smart-c295325b-fe30-4012-96e0-3d44d42d12b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157822828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2157822828
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3854326514
Short name T646
Test name
Test status
Simulation time 79665031487 ps
CPU time 136.61 seconds
Started Aug 06 04:30:01 PM PDT 24
Finished Aug 06 04:32:18 PM PDT 24
Peak memory 199668 kb
Host smart-d8517986-5f77-4779-84e9-1c679bbda9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854326514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3854326514
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.1449702314
Short name T376
Test name
Test status
Simulation time 19182784 ps
CPU time 0.54 seconds
Started Aug 06 04:28:31 PM PDT 24
Finished Aug 06 04:28:31 PM PDT 24
Peak memory 195084 kb
Host smart-0f9fd3d6-37a2-438a-a506-e9f59e49ee9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449702314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1449702314
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.3138521307
Short name T982
Test name
Test status
Simulation time 56158709600 ps
CPU time 47.2 seconds
Started Aug 06 04:28:15 PM PDT 24
Finished Aug 06 04:29:02 PM PDT 24
Peak memory 199696 kb
Host smart-61eebbba-1c48-45e8-b52d-5b2a331a339e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138521307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3138521307
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2700948047
Short name T145
Test name
Test status
Simulation time 91130294406 ps
CPU time 28.57 seconds
Started Aug 06 04:28:17 PM PDT 24
Finished Aug 06 04:28:45 PM PDT 24
Peak memory 199640 kb
Host smart-3efc907b-581d-494d-b59f-018ba5ea4455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700948047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2700948047
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.446995526
Short name T235
Test name
Test status
Simulation time 39871113472 ps
CPU time 20.81 seconds
Started Aug 06 04:28:13 PM PDT 24
Finished Aug 06 04:28:34 PM PDT 24
Peak memory 199720 kb
Host smart-e4750010-09fd-4a3a-9fb1-289ab75a5f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446995526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.446995526
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3142571251
Short name T930
Test name
Test status
Simulation time 44698033591 ps
CPU time 18.12 seconds
Started Aug 06 04:28:28 PM PDT 24
Finished Aug 06 04:28:46 PM PDT 24
Peak memory 198560 kb
Host smart-f19735aa-202e-4369-9641-d9b13f0536c1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142571251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3142571251
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1272966221
Short name T837
Test name
Test status
Simulation time 221510930424 ps
CPU time 329.35 seconds
Started Aug 06 04:28:11 PM PDT 24
Finished Aug 06 04:33:41 PM PDT 24
Peak memory 199640 kb
Host smart-20f018ae-1788-45d4-81c2-5435f8688470
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1272966221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1272966221
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.999866431
Short name T364
Test name
Test status
Simulation time 7544614569 ps
CPU time 5.14 seconds
Started Aug 06 04:28:20 PM PDT 24
Finished Aug 06 04:28:26 PM PDT 24
Peak memory 198304 kb
Host smart-8df90f1a-2d20-4d9b-9ff7-36651a780579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999866431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.999866431
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.65649494
Short name T35
Test name
Test status
Simulation time 68013796985 ps
CPU time 32.86 seconds
Started Aug 06 04:28:15 PM PDT 24
Finished Aug 06 04:28:48 PM PDT 24
Peak memory 198844 kb
Host smart-cfca9a70-ad83-4e42-8329-ba3c90b89980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65649494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.65649494
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.614606157
Short name T874
Test name
Test status
Simulation time 20609625470 ps
CPU time 211.52 seconds
Started Aug 06 04:28:16 PM PDT 24
Finished Aug 06 04:31:47 PM PDT 24
Peak memory 199664 kb
Host smart-bb359543-5b15-4cb6-aad2-daca04d50b4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=614606157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.614606157
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2452699702
Short name T818
Test name
Test status
Simulation time 1585362691 ps
CPU time 6.04 seconds
Started Aug 06 04:28:21 PM PDT 24
Finished Aug 06 04:28:28 PM PDT 24
Peak memory 197752 kb
Host smart-c06d898c-1332-4e60-9fab-7b0e28d8843a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2452699702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2452699702
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.2550343613
Short name T877
Test name
Test status
Simulation time 18546567158 ps
CPU time 20.39 seconds
Started Aug 06 04:28:19 PM PDT 24
Finished Aug 06 04:28:39 PM PDT 24
Peak memory 199760 kb
Host smart-fe2de13b-f023-42a2-bc83-0aad12526606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550343613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2550343613
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2192834343
Short name T776
Test name
Test status
Simulation time 80092303565 ps
CPU time 118.83 seconds
Started Aug 06 04:28:15 PM PDT 24
Finished Aug 06 04:30:14 PM PDT 24
Peak memory 196160 kb
Host smart-888d9e1b-6e90-41df-b887-d23c03af7c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192834343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2192834343
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2385617459
Short name T499
Test name
Test status
Simulation time 5535849024 ps
CPU time 9 seconds
Started Aug 06 04:28:14 PM PDT 24
Finished Aug 06 04:28:23 PM PDT 24
Peak memory 199588 kb
Host smart-f31c5a22-38aa-4dd7-bf20-88d7a48b386e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385617459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2385617459
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3203853119
Short name T935
Test name
Test status
Simulation time 97214017730 ps
CPU time 1028.87 seconds
Started Aug 06 04:28:18 PM PDT 24
Finished Aug 06 04:45:27 PM PDT 24
Peak memory 199712 kb
Host smart-3f0237a8-4e4f-4e76-a078-9f4df2d86062
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203853119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3203853119
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2938685479
Short name T317
Test name
Test status
Simulation time 954857432 ps
CPU time 2.84 seconds
Started Aug 06 04:28:20 PM PDT 24
Finished Aug 06 04:28:23 PM PDT 24
Peak memory 198516 kb
Host smart-b6ea6622-2c6b-45b6-89f8-9bb5e7eb8cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938685479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2938685479
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.97034075
Short name T275
Test name
Test status
Simulation time 31732295476 ps
CPU time 50.13 seconds
Started Aug 06 04:28:22 PM PDT 24
Finished Aug 06 04:29:12 PM PDT 24
Peak memory 199604 kb
Host smart-db1d33bc-c6f3-4c4c-8c5f-3660f141a198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97034075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.97034075
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3038844149
Short name T283
Test name
Test status
Simulation time 23778758079 ps
CPU time 37.34 seconds
Started Aug 06 04:31:35 PM PDT 24
Finished Aug 06 04:32:12 PM PDT 24
Peak memory 199484 kb
Host smart-0edab503-aff1-4088-9999-c0c39b0c964e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038844149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3038844149
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1819810114
Short name T651
Test name
Test status
Simulation time 347645392021 ps
CPU time 790.4 seconds
Started Aug 06 04:31:35 PM PDT 24
Finished Aug 06 04:44:45 PM PDT 24
Peak memory 224380 kb
Host smart-befaeec8-806e-423a-92b1-1250c79879d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819810114 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1819810114
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.518791668
Short name T629
Test name
Test status
Simulation time 132060347740 ps
CPU time 621.91 seconds
Started Aug 06 04:30:09 PM PDT 24
Finished Aug 06 04:40:32 PM PDT 24
Peak memory 199696 kb
Host smart-5017372a-6cf6-4518-a187-aad7b7b8c710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518791668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.518791668
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.4209395988
Short name T195
Test name
Test status
Simulation time 46476786501 ps
CPU time 37.45 seconds
Started Aug 06 04:31:20 PM PDT 24
Finished Aug 06 04:31:58 PM PDT 24
Peak memory 199664 kb
Host smart-4937cacc-c71f-4f66-a258-68a0791e5177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209395988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.4209395988
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1210507261
Short name T23
Test name
Test status
Simulation time 5447282513 ps
CPU time 57.27 seconds
Started Aug 06 04:30:09 PM PDT 24
Finished Aug 06 04:31:07 PM PDT 24
Peak memory 208052 kb
Host smart-eae2151e-09f2-497f-a089-ab349fe29c39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210507261 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1210507261
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.913723026
Short name T1135
Test name
Test status
Simulation time 220176972382 ps
CPU time 45.25 seconds
Started Aug 06 04:30:10 PM PDT 24
Finished Aug 06 04:30:55 PM PDT 24
Peak memory 199696 kb
Host smart-1d376d5b-c85e-4e6a-bcf1-ff4adc62bf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913723026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.913723026
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.4017174801
Short name T1022
Test name
Test status
Simulation time 142289342623 ps
CPU time 359.35 seconds
Started Aug 06 04:30:09 PM PDT 24
Finished Aug 06 04:36:09 PM PDT 24
Peak memory 216192 kb
Host smart-e8f4be6b-a7bc-4fb8-9751-95fc61ac9ca7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017174801 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.4017174801
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.4009311227
Short name T668
Test name
Test status
Simulation time 77989022970 ps
CPU time 33.45 seconds
Started Aug 06 04:30:10 PM PDT 24
Finished Aug 06 04:30:44 PM PDT 24
Peak memory 199728 kb
Host smart-99cb6e20-4832-4165-9369-ed59df45a8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009311227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.4009311227
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1175032021
Short name T210
Test name
Test status
Simulation time 302042316959 ps
CPU time 875.7 seconds
Started Aug 06 04:30:09 PM PDT 24
Finished Aug 06 04:44:45 PM PDT 24
Peak memory 225288 kb
Host smart-64aa8d7c-338b-45e7-8b79-21a8e1b1a6ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175032021 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1175032021
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.679293984
Short name T501
Test name
Test status
Simulation time 47790749956 ps
CPU time 73.97 seconds
Started Aug 06 04:30:09 PM PDT 24
Finished Aug 06 04:31:23 PM PDT 24
Peak memory 199212 kb
Host smart-6fadcc0a-7d14-495b-b3f0-bf1b306d9d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679293984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.679293984
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.930516267
Short name T198
Test name
Test status
Simulation time 86663572017 ps
CPU time 11.7 seconds
Started Aug 06 04:30:12 PM PDT 24
Finished Aug 06 04:30:24 PM PDT 24
Peak memory 199580 kb
Host smart-c17ea585-1121-4874-9cb1-2c1c5f9cc86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930516267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.930516267
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.968952496
Short name T614
Test name
Test status
Simulation time 32843875006 ps
CPU time 78.94 seconds
Started Aug 06 04:30:11 PM PDT 24
Finished Aug 06 04:31:30 PM PDT 24
Peak memory 208188 kb
Host smart-913df0d4-5057-4920-bf96-01bb87895903
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968952496 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.968952496
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3442065993
Short name T611
Test name
Test status
Simulation time 116941332915 ps
CPU time 51.95 seconds
Started Aug 06 04:30:09 PM PDT 24
Finished Aug 06 04:31:02 PM PDT 24
Peak memory 199668 kb
Host smart-6feb9e8d-1f9c-4064-8999-f0e49dfd2b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442065993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3442065993
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.354330866
Short name T958
Test name
Test status
Simulation time 494793691740 ps
CPU time 823.86 seconds
Started Aug 06 04:30:13 PM PDT 24
Finished Aug 06 04:43:57 PM PDT 24
Peak memory 216292 kb
Host smart-79c62ace-0007-4d1a-8d6f-9f9099f74e8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354330866 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.354330866
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3460007657
Short name T221
Test name
Test status
Simulation time 252211052069 ps
CPU time 60.01 seconds
Started Aug 06 04:30:09 PM PDT 24
Finished Aug 06 04:31:09 PM PDT 24
Peak memory 199700 kb
Host smart-fef363ff-9ddf-44e1-b092-4ac2455a2b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460007657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3460007657
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.4086017953
Short name T1178
Test name
Test status
Simulation time 44122046016 ps
CPU time 1239.11 seconds
Started Aug 06 04:31:21 PM PDT 24
Finished Aug 06 04:52:01 PM PDT 24
Peak memory 224816 kb
Host smart-fd3a7596-1d97-43ac-a4c9-603432145a52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086017953 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.4086017953
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.98841451
Short name T515
Test name
Test status
Simulation time 185634972983 ps
CPU time 75.54 seconds
Started Aug 06 04:31:35 PM PDT 24
Finished Aug 06 04:32:50 PM PDT 24
Peak memory 199188 kb
Host smart-b4f0221b-e182-4fa1-b907-21820120580d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98841451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.98841451
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.128325991
Short name T339
Test name
Test status
Simulation time 135123513426 ps
CPU time 1475.25 seconds
Started Aug 06 04:30:08 PM PDT 24
Finished Aug 06 04:54:44 PM PDT 24
Peak memory 224864 kb
Host smart-7637e53e-14b6-4292-97da-46cde81accc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128325991 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.128325991
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1749491213
Short name T831
Test name
Test status
Simulation time 29426687 ps
CPU time 0.55 seconds
Started Aug 06 04:28:24 PM PDT 24
Finished Aug 06 04:28:25 PM PDT 24
Peak memory 194540 kb
Host smart-00ace469-fefb-4b74-a920-cccbc2099e8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749491213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1749491213
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1906493082
Short name T1004
Test name
Test status
Simulation time 50029279151 ps
CPU time 54.96 seconds
Started Aug 06 04:28:15 PM PDT 24
Finished Aug 06 04:29:10 PM PDT 24
Peak memory 199644 kb
Host smart-127c96da-ffbf-4e59-acea-e28b9f0467f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906493082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1906493082
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.584379304
Short name T282
Test name
Test status
Simulation time 20082738910 ps
CPU time 30.14 seconds
Started Aug 06 04:28:15 PM PDT 24
Finished Aug 06 04:28:45 PM PDT 24
Peak memory 199712 kb
Host smart-9244e078-7b13-4dda-9f12-c45482258bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584379304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.584379304
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.4073321555
Short name T276
Test name
Test status
Simulation time 111455487980 ps
CPU time 41.59 seconds
Started Aug 06 04:28:24 PM PDT 24
Finished Aug 06 04:29:05 PM PDT 24
Peak memory 199616 kb
Host smart-e7e43feb-040c-4903-a0e3-f355bd0a5868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073321555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.4073321555
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2619814637
Short name T401
Test name
Test status
Simulation time 70466482110 ps
CPU time 43.4 seconds
Started Aug 06 04:29:06 PM PDT 24
Finished Aug 06 04:29:50 PM PDT 24
Peak memory 199380 kb
Host smart-cbd4fa16-5762-4394-bd70-081670d5f9a3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619814637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2619814637
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3374428037
Short name T623
Test name
Test status
Simulation time 144782564662 ps
CPU time 378.09 seconds
Started Aug 06 04:28:14 PM PDT 24
Finished Aug 06 04:34:32 PM PDT 24
Peak memory 199712 kb
Host smart-dea48ac1-ae6a-42c9-a9c1-fa773d65c9f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3374428037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3374428037
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2698132218
Short name T378
Test name
Test status
Simulation time 5673614401 ps
CPU time 3.58 seconds
Started Aug 06 04:28:17 PM PDT 24
Finished Aug 06 04:28:21 PM PDT 24
Peak memory 199312 kb
Host smart-36fe7fa6-878f-4e91-ace9-5b0dee721b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698132218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2698132218
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.4069524929
Short name T433
Test name
Test status
Simulation time 12557417322 ps
CPU time 10.45 seconds
Started Aug 06 04:28:25 PM PDT 24
Finished Aug 06 04:28:35 PM PDT 24
Peak memory 199664 kb
Host smart-1fb1ec84-0b1d-4860-a12e-88a2aaaeee45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069524929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.4069524929
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.1797231272
Short name T490
Test name
Test status
Simulation time 12612436241 ps
CPU time 683.96 seconds
Started Aug 06 04:28:31 PM PDT 24
Finished Aug 06 04:39:55 PM PDT 24
Peak memory 199708 kb
Host smart-edb29001-285e-4c73-b836-9324001d15a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1797231272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1797231272
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2657644899
Short name T792
Test name
Test status
Simulation time 4560484380 ps
CPU time 19.15 seconds
Started Aug 06 04:28:22 PM PDT 24
Finished Aug 06 04:28:41 PM PDT 24
Peak memory 199032 kb
Host smart-e92d4865-5da8-4249-894c-a9c22721faa8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2657644899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2657644899
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2499292792
Short name T528
Test name
Test status
Simulation time 102624740597 ps
CPU time 29.75 seconds
Started Aug 06 04:28:29 PM PDT 24
Finished Aug 06 04:28:58 PM PDT 24
Peak memory 198708 kb
Host smart-aee526d6-34b9-45d6-9cbe-9c1620d5128e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499292792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2499292792
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.90996073
Short name T435
Test name
Test status
Simulation time 2489997349 ps
CPU time 1.65 seconds
Started Aug 06 04:28:14 PM PDT 24
Finished Aug 06 04:28:16 PM PDT 24
Peak memory 195776 kb
Host smart-09ef5ca6-daed-4625-9624-93bb37a12669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90996073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.90996073
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.4189219394
Short name T405
Test name
Test status
Simulation time 886289683 ps
CPU time 3.57 seconds
Started Aug 06 04:28:35 PM PDT 24
Finished Aug 06 04:28:39 PM PDT 24
Peak memory 198552 kb
Host smart-99398aa2-0fff-4778-827f-33d4d9707fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189219394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.4189219394
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2337896186
Short name T764
Test name
Test status
Simulation time 227714126900 ps
CPU time 349.02 seconds
Started Aug 06 04:28:24 PM PDT 24
Finished Aug 06 04:34:13 PM PDT 24
Peak memory 199824 kb
Host smart-e39b8188-cf54-494e-89a0-f7c5f1fb68d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337896186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2337896186
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.370432814
Short name T491
Test name
Test status
Simulation time 90627726475 ps
CPU time 415.57 seconds
Started Aug 06 04:28:15 PM PDT 24
Finished Aug 06 04:35:20 PM PDT 24
Peak memory 216384 kb
Host smart-10b19e8f-8139-47f0-ad90-3f3f95edc783
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370432814 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.370432814
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2371098334
Short name T773
Test name
Test status
Simulation time 11700870698 ps
CPU time 5.07 seconds
Started Aug 06 04:28:21 PM PDT 24
Finished Aug 06 04:28:26 PM PDT 24
Peak memory 199580 kb
Host smart-18101657-c691-431b-9f02-5d197ac26ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371098334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2371098334
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2863396831
Short name T1028
Test name
Test status
Simulation time 46628948437 ps
CPU time 35.1 seconds
Started Aug 06 04:28:23 PM PDT 24
Finished Aug 06 04:28:58 PM PDT 24
Peak memory 199724 kb
Host smart-c00b78af-2ba6-43d5-9334-5a524338e4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863396831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2863396831
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1281190613
Short name T1023
Test name
Test status
Simulation time 15652704210 ps
CPU time 26.52 seconds
Started Aug 06 04:30:11 PM PDT 24
Finished Aug 06 04:30:38 PM PDT 24
Peak memory 199704 kb
Host smart-095493ba-e2d4-4482-8127-1047fe563a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281190613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1281190613
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2161016215
Short name T1128
Test name
Test status
Simulation time 131797240685 ps
CPU time 386.62 seconds
Started Aug 06 04:30:11 PM PDT 24
Finished Aug 06 04:36:38 PM PDT 24
Peak memory 216128 kb
Host smart-2acdd1c3-3f81-4e45-b3a5-139f4dad93c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161016215 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2161016215
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1202657082
Short name T978
Test name
Test status
Simulation time 44372942363 ps
CPU time 32.18 seconds
Started Aug 06 04:30:10 PM PDT 24
Finished Aug 06 04:30:42 PM PDT 24
Peak memory 199732 kb
Host smart-19ca71e5-1751-4ba9-9ea9-0f822906211d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202657082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1202657082
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.3892566731
Short name T709
Test name
Test status
Simulation time 97429543853 ps
CPU time 1511.8 seconds
Started Aug 06 04:30:13 PM PDT 24
Finished Aug 06 04:55:25 PM PDT 24
Peak memory 224648 kb
Host smart-f7e24505-b184-4ce9-a4be-43655953e6a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892566731 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3892566731
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.384782317
Short name T1082
Test name
Test status
Simulation time 36126539741 ps
CPU time 61.32 seconds
Started Aug 06 04:30:11 PM PDT 24
Finished Aug 06 04:31:12 PM PDT 24
Peak memory 199664 kb
Host smart-ccc9041f-fad1-4a05-82ac-27fc91a43c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384782317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.384782317
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2643922125
Short name T650
Test name
Test status
Simulation time 365177070771 ps
CPU time 1137.22 seconds
Started Aug 06 04:31:34 PM PDT 24
Finished Aug 06 04:50:32 PM PDT 24
Peak memory 226824 kb
Host smart-2872532f-4d1e-4be8-b5b0-b06e21ca933e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643922125 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2643922125
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3390214287
Short name T182
Test name
Test status
Simulation time 22116875873 ps
CPU time 217.81 seconds
Started Aug 06 04:31:35 PM PDT 24
Finished Aug 06 04:35:13 PM PDT 24
Peak memory 215512 kb
Host smart-15d47e3e-3d31-433a-b5ba-b2c9e3679129
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390214287 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3390214287
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.929768810
Short name T1181
Test name
Test status
Simulation time 65249597958 ps
CPU time 74.75 seconds
Started Aug 06 04:30:10 PM PDT 24
Finished Aug 06 04:31:24 PM PDT 24
Peak memory 199732 kb
Host smart-02f81a16-97ef-4cf4-bc70-ec62197d21b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929768810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.929768810
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1436495453
Short name T811
Test name
Test status
Simulation time 370205483115 ps
CPU time 919.76 seconds
Started Aug 06 04:30:13 PM PDT 24
Finished Aug 06 04:45:33 PM PDT 24
Peak memory 224492 kb
Host smart-a7aca59a-7b1e-43c0-8a3c-6faa814fcba8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436495453 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1436495453
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2397031363
Short name T208
Test name
Test status
Simulation time 176546847034 ps
CPU time 65.52 seconds
Started Aug 06 04:30:11 PM PDT 24
Finished Aug 06 04:31:17 PM PDT 24
Peak memory 199688 kb
Host smart-1d5c4720-adff-4617-8706-103b85439324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397031363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2397031363
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3934735867
Short name T770
Test name
Test status
Simulation time 193575370740 ps
CPU time 1235.6 seconds
Started Aug 06 04:31:35 PM PDT 24
Finished Aug 06 04:52:10 PM PDT 24
Peak memory 229976 kb
Host smart-9969b1be-9bdf-4ef7-abb2-53be64b1e403
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934735867 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3934735867
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.4268167269
Short name T320
Test name
Test status
Simulation time 162529673817 ps
CPU time 93.5 seconds
Started Aug 06 04:30:13 PM PDT 24
Finished Aug 06 04:31:47 PM PDT 24
Peak memory 199776 kb
Host smart-f67ad6de-24fd-4d6f-8e0d-3e61d2f35889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268167269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.4268167269
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.664186454
Short name T596
Test name
Test status
Simulation time 65053106718 ps
CPU time 171.31 seconds
Started Aug 06 04:30:12 PM PDT 24
Finished Aug 06 04:33:03 PM PDT 24
Peak memory 216304 kb
Host smart-9d669919-4194-4ea8-84d9-3427897026bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664186454 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.664186454
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.901098671
Short name T211
Test name
Test status
Simulation time 84799555236 ps
CPU time 19.34 seconds
Started Aug 06 04:30:11 PM PDT 24
Finished Aug 06 04:30:30 PM PDT 24
Peak memory 199724 kb
Host smart-d1b39098-9334-4e8d-acf7-25f461925c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901098671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.901098671
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1750824663
Short name T199
Test name
Test status
Simulation time 49852502633 ps
CPU time 564.47 seconds
Started Aug 06 04:31:35 PM PDT 24
Finished Aug 06 04:40:59 PM PDT 24
Peak memory 224384 kb
Host smart-100cb03a-4cba-449d-99e0-23c25a751c95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750824663 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1750824663
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.905704575
Short name T697
Test name
Test status
Simulation time 6946600494 ps
CPU time 12.68 seconds
Started Aug 06 04:30:13 PM PDT 24
Finished Aug 06 04:30:26 PM PDT 24
Peak memory 199736 kb
Host smart-f82d4011-0215-40b7-892c-36a3c71bc0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905704575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.905704575
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.1089576373
Short name T140
Test name
Test status
Simulation time 390437642275 ps
CPU time 918.73 seconds
Started Aug 06 04:30:26 PM PDT 24
Finished Aug 06 04:45:45 PM PDT 24
Peak memory 224624 kb
Host smart-f7493d8b-84a5-4fa0-ac3a-43405dd34b42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089576373 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1089576373
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.424061194
Short name T269
Test name
Test status
Simulation time 168328021902 ps
CPU time 72.88 seconds
Started Aug 06 04:30:25 PM PDT 24
Finished Aug 06 04:31:38 PM PDT 24
Peak memory 199592 kb
Host smart-7b04324b-5a31-44bf-96a3-b36c8a9a81b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424061194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.424061194
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3362239511
Short name T57
Test name
Test status
Simulation time 84297859578 ps
CPU time 696.74 seconds
Started Aug 06 04:30:28 PM PDT 24
Finished Aug 06 04:42:05 PM PDT 24
Peak memory 214192 kb
Host smart-034def4a-b96a-4170-bff4-947792566336
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362239511 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3362239511
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2745826939
Short name T367
Test name
Test status
Simulation time 24873096 ps
CPU time 0.56 seconds
Started Aug 06 04:28:15 PM PDT 24
Finished Aug 06 04:28:15 PM PDT 24
Peak memory 195100 kb
Host smart-0cb3435d-794c-4ecb-9d1d-80a28a0eaabc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745826939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2745826939
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3072042482
Short name T855
Test name
Test status
Simulation time 77426353119 ps
CPU time 200.55 seconds
Started Aug 06 04:28:19 PM PDT 24
Finished Aug 06 04:31:40 PM PDT 24
Peak memory 199648 kb
Host smart-c5d91aff-271b-4d7e-bf13-4646852223d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072042482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3072042482
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.222901271
Short name T171
Test name
Test status
Simulation time 31562025394 ps
CPU time 13.2 seconds
Started Aug 06 04:28:15 PM PDT 24
Finished Aug 06 04:28:28 PM PDT 24
Peak memory 199652 kb
Host smart-132a2a73-3188-4de3-81af-ee587299eba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222901271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.222901271
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1358772728
Short name T461
Test name
Test status
Simulation time 138681403701 ps
CPU time 49.41 seconds
Started Aug 06 04:28:28 PM PDT 24
Finished Aug 06 04:29:18 PM PDT 24
Peak memory 199244 kb
Host smart-ad726a62-e95a-47be-b929-2f296491b7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358772728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1358772728
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1508965390
Short name T417
Test name
Test status
Simulation time 26161494821 ps
CPU time 11.81 seconds
Started Aug 06 04:28:21 PM PDT 24
Finished Aug 06 04:28:33 PM PDT 24
Peak memory 199724 kb
Host smart-61a4b879-a7f2-40de-986a-89632826040c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508965390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1508965390
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3344207981
Short name T333
Test name
Test status
Simulation time 141172585681 ps
CPU time 652.66 seconds
Started Aug 06 04:28:26 PM PDT 24
Finished Aug 06 04:39:18 PM PDT 24
Peak memory 199680 kb
Host smart-c7ef27d2-e322-41c3-8408-d13511f95489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3344207981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3344207981
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.756390521
Short name T369
Test name
Test status
Simulation time 1025899391 ps
CPU time 1.68 seconds
Started Aug 06 04:28:17 PM PDT 24
Finished Aug 06 04:28:19 PM PDT 24
Peak memory 198376 kb
Host smart-581c5ca2-71d1-48d0-b5c9-272996743f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756390521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.756390521
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.4197924561
Short name T797
Test name
Test status
Simulation time 172677987138 ps
CPU time 178.67 seconds
Started Aug 06 04:28:17 PM PDT 24
Finished Aug 06 04:31:15 PM PDT 24
Peak memory 199956 kb
Host smart-6c74e5ff-9477-4e1a-89e4-b861ed3c5d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197924561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.4197924561
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.73893764
Short name T729
Test name
Test status
Simulation time 8797057841 ps
CPU time 226.52 seconds
Started Aug 06 04:28:19 PM PDT 24
Finished Aug 06 04:32:06 PM PDT 24
Peak memory 199660 kb
Host smart-e90e3e84-2d03-4302-9c53-0ea8e8d51b9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=73893764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.73893764
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.4164597929
Short name T39
Test name
Test status
Simulation time 2386717649 ps
CPU time 1.7 seconds
Started Aug 06 04:28:26 PM PDT 24
Finished Aug 06 04:28:28 PM PDT 24
Peak memory 197816 kb
Host smart-26f48dae-f6f0-418f-b78e-19e0d2094e41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164597929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.4164597929
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3975825933
Short name T460
Test name
Test status
Simulation time 127904758375 ps
CPU time 25.99 seconds
Started Aug 06 04:28:28 PM PDT 24
Finished Aug 06 04:28:54 PM PDT 24
Peak memory 199608 kb
Host smart-13e3685e-25cd-4469-bfa6-360c519e3d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975825933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3975825933
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3645529378
Short name T698
Test name
Test status
Simulation time 34580481999 ps
CPU time 8.89 seconds
Started Aug 06 04:29:06 PM PDT 24
Finished Aug 06 04:29:15 PM PDT 24
Peak memory 196240 kb
Host smart-57775578-3f14-4e4d-a3bf-c2b52790045e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645529378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3645529378
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1182251855
Short name T795
Test name
Test status
Simulation time 654633076 ps
CPU time 1.35 seconds
Started Aug 06 04:28:18 PM PDT 24
Finished Aug 06 04:28:19 PM PDT 24
Peak memory 198488 kb
Host smart-7217a01f-1b31-4127-b384-0b0d8aeaaa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182251855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1182251855
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.4018129676
Short name T302
Test name
Test status
Simulation time 50749983176 ps
CPU time 22.68 seconds
Started Aug 06 04:28:28 PM PDT 24
Finished Aug 06 04:28:51 PM PDT 24
Peak memory 199684 kb
Host smart-c1b477ab-7153-4b5a-bec6-018e61817a57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018129676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.4018129676
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.1291091733
Short name T1061
Test name
Test status
Simulation time 48309124319 ps
CPU time 798.09 seconds
Started Aug 06 04:28:18 PM PDT 24
Finished Aug 06 04:41:37 PM PDT 24
Peak memory 216372 kb
Host smart-4972ff05-4926-45c6-b186-89a8222e2883
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291091733 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1291091733
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.4178743555
Short name T1020
Test name
Test status
Simulation time 1551663173 ps
CPU time 1.61 seconds
Started Aug 06 04:28:28 PM PDT 24
Finished Aug 06 04:28:30 PM PDT 24
Peak memory 198120 kb
Host smart-bffd26c4-4c09-4c58-960b-cb1ba29900ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178743555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.4178743555
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1600806188
Short name T534
Test name
Test status
Simulation time 39251101302 ps
CPU time 9.15 seconds
Started Aug 06 04:29:06 PM PDT 24
Finished Aug 06 04:29:16 PM PDT 24
Peak memory 199432 kb
Host smart-07d73d8b-274b-40da-9c2c-c1cdc74531fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600806188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1600806188
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3526729639
Short name T567
Test name
Test status
Simulation time 193672768385 ps
CPU time 76.63 seconds
Started Aug 06 04:30:28 PM PDT 24
Finished Aug 06 04:31:44 PM PDT 24
Peak memory 199752 kb
Host smart-4bb64198-132d-463f-9725-bc4c9d6e3c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526729639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3526729639
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.176334497
Short name T103
Test name
Test status
Simulation time 13489522487 ps
CPU time 123.65 seconds
Started Aug 06 04:30:27 PM PDT 24
Finished Aug 06 04:32:31 PM PDT 24
Peak memory 216352 kb
Host smart-624a9e8a-bc68-4c8b-a696-c491bc5d468a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176334497 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.176334497
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1278413617
Short name T375
Test name
Test status
Simulation time 35741272489 ps
CPU time 16.71 seconds
Started Aug 06 04:30:26 PM PDT 24
Finished Aug 06 04:30:43 PM PDT 24
Peak memory 199764 kb
Host smart-2cc0f7e8-dcf5-414a-9504-7e6e3549eebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278413617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1278413617
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.761151249
Short name T779
Test name
Test status
Simulation time 61857608245 ps
CPU time 447.28 seconds
Started Aug 06 04:30:27 PM PDT 24
Finished Aug 06 04:37:54 PM PDT 24
Peak memory 216396 kb
Host smart-a2bf049b-8d80-4538-a164-dd43c35628eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761151249 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.761151249
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.4083468226
Short name T548
Test name
Test status
Simulation time 227881239041 ps
CPU time 776.76 seconds
Started Aug 06 04:30:25 PM PDT 24
Finished Aug 06 04:43:22 PM PDT 24
Peak memory 216368 kb
Host smart-153b065f-604e-47f8-b535-efce931c7734
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083468226 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.4083468226
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3115533123
Short name T332
Test name
Test status
Simulation time 34731043784 ps
CPU time 77.98 seconds
Started Aug 06 04:30:26 PM PDT 24
Finished Aug 06 04:31:44 PM PDT 24
Peak memory 199716 kb
Host smart-76ac2e5c-2723-4d61-b5f7-b490a14df8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115533123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3115533123
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1701833567
Short name T1140
Test name
Test status
Simulation time 57985768936 ps
CPU time 477.02 seconds
Started Aug 06 04:30:27 PM PDT 24
Finished Aug 06 04:38:24 PM PDT 24
Peak memory 208024 kb
Host smart-314c2686-7fca-45c1-babb-464b9f0abe70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701833567 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1701833567
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3426539816
Short name T398
Test name
Test status
Simulation time 46155527570 ps
CPU time 32.3 seconds
Started Aug 06 04:30:25 PM PDT 24
Finished Aug 06 04:30:58 PM PDT 24
Peak memory 199660 kb
Host smart-56253f2b-dd58-4960-9aa2-dbb356026610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426539816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3426539816
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.224415639
Short name T1027
Test name
Test status
Simulation time 50803759411 ps
CPU time 538.4 seconds
Started Aug 06 04:30:24 PM PDT 24
Finished Aug 06 04:39:23 PM PDT 24
Peak memory 216204 kb
Host smart-804ffbc4-9d55-4301-b4f5-790b5717b297
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224415639 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.224415639
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1422450945
Short name T179
Test name
Test status
Simulation time 19259873613 ps
CPU time 38.11 seconds
Started Aug 06 04:30:25 PM PDT 24
Finished Aug 06 04:31:04 PM PDT 24
Peak memory 199648 kb
Host smart-162fe63d-9af0-48cf-998e-d14c3337d5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422450945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1422450945
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.681450988
Short name T52
Test name
Test status
Simulation time 111585027253 ps
CPU time 812.44 seconds
Started Aug 06 04:30:24 PM PDT 24
Finished Aug 06 04:43:57 PM PDT 24
Peak memory 216332 kb
Host smart-155d6e49-9726-4ce3-93db-9511dd433f09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681450988 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.681450988
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1040133817
Short name T272
Test name
Test status
Simulation time 121248693984 ps
CPU time 47.74 seconds
Started Aug 06 04:30:26 PM PDT 24
Finished Aug 06 04:31:13 PM PDT 24
Peak memory 199620 kb
Host smart-58695f2d-adb9-49ed-8eca-2c73d3dc11a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040133817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1040133817
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3492609228
Short name T706
Test name
Test status
Simulation time 18740884363 ps
CPU time 268.79 seconds
Started Aug 06 04:30:24 PM PDT 24
Finished Aug 06 04:34:53 PM PDT 24
Peak memory 216400 kb
Host smart-7bb787fc-0058-4d19-a766-2c2431aa69f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492609228 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3492609228
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1821075469
Short name T239
Test name
Test status
Simulation time 476444624147 ps
CPU time 35.69 seconds
Started Aug 06 04:30:25 PM PDT 24
Finished Aug 06 04:31:01 PM PDT 24
Peak memory 199764 kb
Host smart-32b4ed6c-1d84-4d2a-83a4-d8051eea3f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821075469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1821075469
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.4227710370
Short name T217
Test name
Test status
Simulation time 20059330538 ps
CPU time 20.54 seconds
Started Aug 06 04:30:26 PM PDT 24
Finished Aug 06 04:30:47 PM PDT 24
Peak memory 199664 kb
Host smart-0677674c-5dbe-48fb-84dd-c50bdac47d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227710370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.4227710370
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3908246330
Short name T1078
Test name
Test status
Simulation time 403803217643 ps
CPU time 367.92 seconds
Started Aug 06 04:30:27 PM PDT 24
Finished Aug 06 04:36:35 PM PDT 24
Peak memory 216340 kb
Host smart-60935475-c487-4640-9577-fe2f3b802a8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908246330 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3908246330
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.411216089
Short name T34
Test name
Test status
Simulation time 109592728573 ps
CPU time 43.18 seconds
Started Aug 06 04:30:28 PM PDT 24
Finished Aug 06 04:31:11 PM PDT 24
Peak memory 199684 kb
Host smart-9ac701a4-8cd3-42b1-a6d9-82852b6eeac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411216089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.411216089
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1684070153
Short name T425
Test name
Test status
Simulation time 11946492 ps
CPU time 0.54 seconds
Started Aug 06 04:28:34 PM PDT 24
Finished Aug 06 04:28:34 PM PDT 24
Peak memory 195436 kb
Host smart-eb0e5f79-479d-41b5-9d3f-a85d1b0c2209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684070153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1684070153
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.595204288
Short name T839
Test name
Test status
Simulation time 134204180885 ps
CPU time 48.97 seconds
Started Aug 06 04:28:28 PM PDT 24
Finished Aug 06 04:29:17 PM PDT 24
Peak memory 199784 kb
Host smart-6f706fc5-dac2-4fd1-8847-23cdf2c77970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595204288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.595204288
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3278906981
Short name T487
Test name
Test status
Simulation time 15234939142 ps
CPU time 22.99 seconds
Started Aug 06 04:28:43 PM PDT 24
Finished Aug 06 04:29:06 PM PDT 24
Peak memory 199484 kb
Host smart-bd8ae3f2-7873-49ba-9018-f761d553ef8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278906981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3278906981
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2728883512
Short name T147
Test name
Test status
Simulation time 14177899240 ps
CPU time 5.3 seconds
Started Aug 06 04:28:23 PM PDT 24
Finished Aug 06 04:28:29 PM PDT 24
Peak memory 199232 kb
Host smart-68869d39-ec24-4765-b325-8c5f5e1c3569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728883512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2728883512
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.168703327
Short name T946
Test name
Test status
Simulation time 45587913026 ps
CPU time 33.55 seconds
Started Aug 06 04:28:26 PM PDT 24
Finished Aug 06 04:29:00 PM PDT 24
Peak memory 199536 kb
Host smart-c9524c02-dd1b-4e29-a3ca-8a0127d46ba6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168703327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.168703327
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.832968348
Short name T301
Test name
Test status
Simulation time 87987451179 ps
CPU time 587.71 seconds
Started Aug 06 04:28:38 PM PDT 24
Finished Aug 06 04:38:26 PM PDT 24
Peak memory 199724 kb
Host smart-62f2ab57-9fe9-4602-94dd-a25ac4764718
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=832968348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.832968348
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3627843721
Short name T451
Test name
Test status
Simulation time 5354544732 ps
CPU time 5.65 seconds
Started Aug 06 04:28:13 PM PDT 24
Finished Aug 06 04:28:19 PM PDT 24
Peak memory 198456 kb
Host smart-985e1e67-54e5-4689-9818-a6baffdf04c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627843721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3627843721
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3347424233
Short name T649
Test name
Test status
Simulation time 56475298495 ps
CPU time 26.97 seconds
Started Aug 06 04:28:26 PM PDT 24
Finished Aug 06 04:28:53 PM PDT 24
Peak memory 199856 kb
Host smart-725d87aa-b1cb-48e2-9373-4fdbcc88b189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347424233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3347424233
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.748977804
Short name T525
Test name
Test status
Simulation time 13850455233 ps
CPU time 636.15 seconds
Started Aug 06 04:28:23 PM PDT 24
Finished Aug 06 04:38:59 PM PDT 24
Peak memory 199756 kb
Host smart-5632bb68-45fe-44bc-b24b-33751ff75c5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=748977804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.748977804
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2528988684
Short name T1080
Test name
Test status
Simulation time 6268207252 ps
CPU time 55.88 seconds
Started Aug 06 04:28:25 PM PDT 24
Finished Aug 06 04:29:21 PM PDT 24
Peak memory 197864 kb
Host smart-470f5552-828d-4e73-924e-ebf703fc386d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528988684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2528988684
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3860550737
Short name T404
Test name
Test status
Simulation time 43876437240 ps
CPU time 14.15 seconds
Started Aug 06 04:28:41 PM PDT 24
Finished Aug 06 04:28:55 PM PDT 24
Peak memory 199684 kb
Host smart-d875a2a0-3468-4e42-8920-375cb2fdb7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860550737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3860550737
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2431012116
Short name T738
Test name
Test status
Simulation time 4023576077 ps
CPU time 6.73 seconds
Started Aug 06 04:28:20 PM PDT 24
Finished Aug 06 04:28:27 PM PDT 24
Peak memory 196324 kb
Host smart-0abd7d20-57b6-4f32-ba68-d5dd3362464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431012116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2431012116
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1884434731
Short name T472
Test name
Test status
Simulation time 5815644432 ps
CPU time 17.61 seconds
Started Aug 06 04:28:23 PM PDT 24
Finished Aug 06 04:28:41 PM PDT 24
Peak memory 199480 kb
Host smart-fa060da3-462d-41ea-abbd-352230ad150f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884434731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1884434731
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.3607484103
Short name T486
Test name
Test status
Simulation time 127838849405 ps
CPU time 92.16 seconds
Started Aug 06 04:28:34 PM PDT 24
Finished Aug 06 04:30:11 PM PDT 24
Peak memory 199504 kb
Host smart-29e0985c-6905-45df-af17-495d2e7ff792
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607484103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3607484103
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1485108835
Short name T509
Test name
Test status
Simulation time 62555451697 ps
CPU time 286.9 seconds
Started Aug 06 04:28:27 PM PDT 24
Finished Aug 06 04:33:14 PM PDT 24
Peak memory 216396 kb
Host smart-f7214e53-a070-4f41-923a-8852734371c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485108835 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1485108835
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3798765065
Short name T603
Test name
Test status
Simulation time 7342287082 ps
CPU time 8.19 seconds
Started Aug 06 04:28:34 PM PDT 24
Finished Aug 06 04:28:42 PM PDT 24
Peak memory 199568 kb
Host smart-36483922-a819-4144-add9-614ffdecba19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798765065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3798765065
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2185808642
Short name T951
Test name
Test status
Simulation time 24040698312 ps
CPU time 12.63 seconds
Started Aug 06 04:28:18 PM PDT 24
Finished Aug 06 04:28:31 PM PDT 24
Peak memory 199676 kb
Host smart-aacdb6ba-e152-4105-9c94-b8bb63f54d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185808642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2185808642
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1626718156
Short name T523
Test name
Test status
Simulation time 27385234114 ps
CPU time 47.33 seconds
Started Aug 06 04:30:25 PM PDT 24
Finished Aug 06 04:31:13 PM PDT 24
Peak memory 199732 kb
Host smart-c16f57e0-d297-44d9-abb4-a8840f761a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626718156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1626718156
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.878162044
Short name T150
Test name
Test status
Simulation time 94229378964 ps
CPU time 342.21 seconds
Started Aug 06 04:30:25 PM PDT 24
Finished Aug 06 04:36:07 PM PDT 24
Peak memory 216428 kb
Host smart-01a9b815-b767-4b25-af7f-6f348665dd0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878162044 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.878162044
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.2142840922
Short name T286
Test name
Test status
Simulation time 9857052777 ps
CPU time 15.5 seconds
Started Aug 06 04:30:26 PM PDT 24
Finished Aug 06 04:30:41 PM PDT 24
Peak memory 199744 kb
Host smart-0c767915-7b1d-408a-b9ae-a0a73c8e11aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142840922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2142840922
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3253985419
Short name T710
Test name
Test status
Simulation time 31433436691 ps
CPU time 692.07 seconds
Started Aug 06 04:30:24 PM PDT 24
Finished Aug 06 04:41:56 PM PDT 24
Peak memory 208184 kb
Host smart-b55ac2e3-7724-4edb-8013-4227b1e2456e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253985419 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3253985419
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.660629402
Short name T324
Test name
Test status
Simulation time 86965792101 ps
CPU time 34.17 seconds
Started Aug 06 04:30:28 PM PDT 24
Finished Aug 06 04:31:02 PM PDT 24
Peak memory 199580 kb
Host smart-a7f2f0a1-df41-4f70-bb5c-0049b144cdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660629402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.660629402
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.2684893947
Short name T1131
Test name
Test status
Simulation time 133031401048 ps
CPU time 866.84 seconds
Started Aug 06 04:30:27 PM PDT 24
Finished Aug 06 04:44:54 PM PDT 24
Peak memory 215504 kb
Host smart-4d610a5c-ec1f-44aa-be05-7203b55e9e79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684893947 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.2684893947
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.61599210
Short name T591
Test name
Test status
Simulation time 58817535485 ps
CPU time 31.15 seconds
Started Aug 06 04:30:28 PM PDT 24
Finished Aug 06 04:30:59 PM PDT 24
Peak memory 199776 kb
Host smart-91c43352-480e-446a-b9a4-572fc158297d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61599210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.61599210
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3062202512
Short name T100
Test name
Test status
Simulation time 104357250415 ps
CPU time 139.69 seconds
Started Aug 06 04:30:28 PM PDT 24
Finished Aug 06 04:32:47 PM PDT 24
Peak memory 216228 kb
Host smart-1f8f5960-bea9-452f-8843-370e6a9673cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062202512 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3062202512
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3210354510
Short name T1118
Test name
Test status
Simulation time 16828543032 ps
CPU time 25.89 seconds
Started Aug 06 04:30:25 PM PDT 24
Finished Aug 06 04:30:51 PM PDT 24
Peak memory 199772 kb
Host smart-fae8a65e-4e79-4bd0-b46a-7138e5722dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210354510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3210354510
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.404675469
Short name T752
Test name
Test status
Simulation time 292255942420 ps
CPU time 943.79 seconds
Started Aug 06 04:30:26 PM PDT 24
Finished Aug 06 04:46:10 PM PDT 24
Peak memory 224624 kb
Host smart-02f09c14-2827-460b-8b86-fc1506df06da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404675469 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.404675469
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2963263439
Short name T136
Test name
Test status
Simulation time 33130816297 ps
CPU time 16.79 seconds
Started Aug 06 04:30:24 PM PDT 24
Finished Aug 06 04:30:41 PM PDT 24
Peak memory 199656 kb
Host smart-774a6627-9294-429d-899a-a3954969352c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963263439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2963263439
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.539890072
Short name T973
Test name
Test status
Simulation time 158827456521 ps
CPU time 258.86 seconds
Started Aug 06 04:30:25 PM PDT 24
Finished Aug 06 04:34:44 PM PDT 24
Peak memory 214328 kb
Host smart-4ec3f083-10c2-4724-bd6b-fcea104c9e24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539890072 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.539890072
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.592927777
Short name T745
Test name
Test status
Simulation time 10950925217 ps
CPU time 15.77 seconds
Started Aug 06 04:30:28 PM PDT 24
Finished Aug 06 04:30:44 PM PDT 24
Peak memory 199460 kb
Host smart-5296078e-00d2-4e95-8050-8814356d08fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592927777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.592927777
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3086905654
Short name T695
Test name
Test status
Simulation time 452071141033 ps
CPU time 856.49 seconds
Started Aug 06 04:30:34 PM PDT 24
Finished Aug 06 04:44:50 PM PDT 24
Peak memory 224540 kb
Host smart-9a51209b-5d2e-4b99-8804-26cac3a92d4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086905654 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3086905654
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.4294178962
Short name T1042
Test name
Test status
Simulation time 21925201565 ps
CPU time 11.69 seconds
Started Aug 06 04:30:27 PM PDT 24
Finished Aug 06 04:30:39 PM PDT 24
Peak memory 200160 kb
Host smart-2710f788-3546-47c4-9794-aa0ea66b8946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294178962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.4294178962
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.695020052
Short name T923
Test name
Test status
Simulation time 642120715276 ps
CPU time 1002.99 seconds
Started Aug 06 04:30:28 PM PDT 24
Finished Aug 06 04:47:11 PM PDT 24
Peak memory 224616 kb
Host smart-d88650a2-0816-4cd5-8d1a-6162849d43e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695020052 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.695020052
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.3963030163
Short name T782
Test name
Test status
Simulation time 57829882001 ps
CPU time 28.81 seconds
Started Aug 06 04:30:27 PM PDT 24
Finished Aug 06 04:30:56 PM PDT 24
Peak memory 199768 kb
Host smart-28d4c4b2-25b3-43cc-98db-1dc64255b9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963030163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3963030163
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3511156043
Short name T99
Test name
Test status
Simulation time 55295576296 ps
CPU time 240.46 seconds
Started Aug 06 04:30:28 PM PDT 24
Finished Aug 06 04:34:28 PM PDT 24
Peak memory 216204 kb
Host smart-6f964ff9-6cc9-44c1-8abb-018c83af58fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511156043 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3511156043
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3538990465
Short name T1072
Test name
Test status
Simulation time 75508596153 ps
CPU time 169.28 seconds
Started Aug 06 04:30:26 PM PDT 24
Finished Aug 06 04:33:15 PM PDT 24
Peak memory 199704 kb
Host smart-562b2807-27d9-4eee-9eae-fea7c2c5ebab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538990465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3538990465
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2551557991
Short name T58
Test name
Test status
Simulation time 266535623769 ps
CPU time 818.08 seconds
Started Aug 06 04:30:28 PM PDT 24
Finished Aug 06 04:44:07 PM PDT 24
Peak memory 224500 kb
Host smart-b6aa4be9-58ae-4d0e-bd5f-d1edcd49bb55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551557991 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2551557991
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3386244782
Short name T434
Test name
Test status
Simulation time 13228681 ps
CPU time 0.55 seconds
Started Aug 06 04:28:23 PM PDT 24
Finished Aug 06 04:28:23 PM PDT 24
Peak memory 194064 kb
Host smart-aad31068-a67b-4536-97ba-ec99de148dfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386244782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3386244782
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3629602025
Short name T641
Test name
Test status
Simulation time 91297145797 ps
CPU time 324.91 seconds
Started Aug 06 04:28:30 PM PDT 24
Finished Aug 06 04:33:56 PM PDT 24
Peak memory 199676 kb
Host smart-d3bf010b-f7c7-4859-9bc5-3a25c4376e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629602025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3629602025
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1435624022
Short name T128
Test name
Test status
Simulation time 10705203098 ps
CPU time 18.98 seconds
Started Aug 06 04:28:20 PM PDT 24
Finished Aug 06 04:28:39 PM PDT 24
Peak memory 199664 kb
Host smart-4e969210-694a-4005-8455-9cbe17b6bf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435624022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1435624022
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1955314199
Short name T233
Test name
Test status
Simulation time 10315986558 ps
CPU time 6.5 seconds
Started Aug 06 04:28:34 PM PDT 24
Finished Aug 06 04:28:40 PM PDT 24
Peak memory 199432 kb
Host smart-b8cf515a-49c2-48fd-aebc-bfebc4fa9ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955314199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1955314199
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1234968973
Short name T916
Test name
Test status
Simulation time 104183867713 ps
CPU time 110.93 seconds
Started Aug 06 04:28:36 PM PDT 24
Finished Aug 06 04:30:27 PM PDT 24
Peak memory 196912 kb
Host smart-e9d9693f-131e-4af6-b20f-d448b961642a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234968973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1234968973
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.280414863
Short name T1002
Test name
Test status
Simulation time 104834717630 ps
CPU time 155.13 seconds
Started Aug 06 04:28:17 PM PDT 24
Finished Aug 06 04:30:57 PM PDT 24
Peak memory 200144 kb
Host smart-70134933-4bf6-497c-b0bc-418a6d95736a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=280414863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.280414863
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.4233670114
Short name T361
Test name
Test status
Simulation time 1558868215 ps
CPU time 1.98 seconds
Started Aug 06 04:28:18 PM PDT 24
Finished Aug 06 04:28:20 PM PDT 24
Peak memory 197276 kb
Host smart-e423d6aa-7e11-46cf-ba82-33a034cb39ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233670114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.4233670114
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3111784529
Short name T820
Test name
Test status
Simulation time 60623055075 ps
CPU time 105.71 seconds
Started Aug 06 04:28:41 PM PDT 24
Finished Aug 06 04:30:27 PM PDT 24
Peak memory 200064 kb
Host smart-19a580f8-4775-4489-85c9-ec0aa2775a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111784529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3111784529
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.4095738832
Short name T399
Test name
Test status
Simulation time 17547721696 ps
CPU time 85.81 seconds
Started Aug 06 04:28:26 PM PDT 24
Finished Aug 06 04:29:52 PM PDT 24
Peak memory 199712 kb
Host smart-aa81ad88-7252-498c-84d9-3d414a90e633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4095738832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.4095738832
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1598277424
Short name T337
Test name
Test status
Simulation time 7013089993 ps
CPU time 31 seconds
Started Aug 06 04:28:43 PM PDT 24
Finished Aug 06 04:29:15 PM PDT 24
Peak memory 198888 kb
Host smart-8934dee2-359a-4c49-8093-9c7317642240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1598277424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1598277424
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3102660953
Short name T125
Test name
Test status
Simulation time 45998511686 ps
CPU time 39.89 seconds
Started Aug 06 04:28:26 PM PDT 24
Finished Aug 06 04:29:06 PM PDT 24
Peak memory 199508 kb
Host smart-006e1597-f951-4815-b5bc-40c7f8f000ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102660953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3102660953
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1894534091
Short name T1110
Test name
Test status
Simulation time 3387956222 ps
CPU time 1.94 seconds
Started Aug 06 04:28:19 PM PDT 24
Finished Aug 06 04:28:21 PM PDT 24
Peak memory 196288 kb
Host smart-1bc3578c-e0cd-4854-b211-d84a3ed5710d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894534091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1894534091
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.422906479
Short name T277
Test name
Test status
Simulation time 246346059 ps
CPU time 1.19 seconds
Started Aug 06 04:28:25 PM PDT 24
Finished Aug 06 04:28:27 PM PDT 24
Peak memory 197992 kb
Host smart-4cd19884-4f63-47f0-a868-c31c614a6d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422906479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.422906479
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3046785184
Short name T204
Test name
Test status
Simulation time 312776101909 ps
CPU time 451.06 seconds
Started Aug 06 04:28:18 PM PDT 24
Finished Aug 06 04:35:49 PM PDT 24
Peak memory 199696 kb
Host smart-6b4c3a93-1741-4275-a5bd-406b29c28621
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046785184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3046785184
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3872919361
Short name T33
Test name
Test status
Simulation time 24465246763 ps
CPU time 737.86 seconds
Started Aug 06 04:28:27 PM PDT 24
Finished Aug 06 04:40:45 PM PDT 24
Peak memory 215636 kb
Host smart-436d57d2-8e2b-4a9b-a8bf-63b3c12c5163
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872919361 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3872919361
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3690225894
Short name T730
Test name
Test status
Simulation time 975898254 ps
CPU time 2.05 seconds
Started Aug 06 04:28:22 PM PDT 24
Finished Aug 06 04:28:24 PM PDT 24
Peak memory 199004 kb
Host smart-bc1c2c94-5799-457e-befb-ce5f70fad563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690225894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3690225894
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3923539253
Short name T994
Test name
Test status
Simulation time 23664808379 ps
CPU time 20.21 seconds
Started Aug 06 04:28:31 PM PDT 24
Finished Aug 06 04:28:51 PM PDT 24
Peak memory 199704 kb
Host smart-63ba3646-25c5-4599-b713-938332189a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923539253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3923539253
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1382534631
Short name T326
Test name
Test status
Simulation time 104037072315 ps
CPU time 153.18 seconds
Started Aug 06 04:30:24 PM PDT 24
Finished Aug 06 04:32:58 PM PDT 24
Peak memory 199692 kb
Host smart-7aa268b1-c112-4c3d-95c5-7c67b7ddb644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382534631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1382534631
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3332719590
Short name T191
Test name
Test status
Simulation time 176218164545 ps
CPU time 792.61 seconds
Started Aug 06 04:30:27 PM PDT 24
Finished Aug 06 04:43:40 PM PDT 24
Peak memory 224536 kb
Host smart-9d5261a0-4225-4ac5-8db5-56d87beedd53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332719590 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3332719590
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1705937864
Short name T967
Test name
Test status
Simulation time 39087687641 ps
CPU time 26.09 seconds
Started Aug 06 04:30:26 PM PDT 24
Finished Aug 06 04:30:52 PM PDT 24
Peak memory 199628 kb
Host smart-e01a614d-7578-4c72-8a6e-d874e7fdc169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705937864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1705937864
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.437511324
Short name T294
Test name
Test status
Simulation time 214889866253 ps
CPU time 517.45 seconds
Started Aug 06 04:30:28 PM PDT 24
Finished Aug 06 04:39:06 PM PDT 24
Peak memory 216244 kb
Host smart-c5236e21-b524-4a97-9eb7-c2e2a788df2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437511324 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.437511324
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.395467030
Short name T661
Test name
Test status
Simulation time 33721528564 ps
CPU time 18.78 seconds
Started Aug 06 04:30:28 PM PDT 24
Finished Aug 06 04:30:47 PM PDT 24
Peak memory 198884 kb
Host smart-c624d705-d6b1-4f15-be0e-0bb1eb0ab4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395467030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.395467030
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.331973788
Short name T1058
Test name
Test status
Simulation time 50118304112 ps
CPU time 594.55 seconds
Started Aug 06 04:30:26 PM PDT 24
Finished Aug 06 04:40:20 PM PDT 24
Peak memory 224684 kb
Host smart-f60e5cc7-b8f0-4e95-b2a6-0da43a004189
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331973788 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.331973788
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.54468472
Short name T630
Test name
Test status
Simulation time 105929829781 ps
CPU time 81 seconds
Started Aug 06 04:30:26 PM PDT 24
Finished Aug 06 04:31:47 PM PDT 24
Peak memory 199708 kb
Host smart-9f152f53-6672-4102-9c91-80c78f532191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54468472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.54468472
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.389379100
Short name T727
Test name
Test status
Simulation time 92337836776 ps
CPU time 498.84 seconds
Started Aug 06 04:30:27 PM PDT 24
Finished Aug 06 04:38:46 PM PDT 24
Peak memory 216200 kb
Host smart-28c2a82d-dc8e-46bd-bf2b-9f5fcf12de1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389379100 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.389379100
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.705899374
Short name T175
Test name
Test status
Simulation time 111063254824 ps
CPU time 79.46 seconds
Started Aug 06 04:30:25 PM PDT 24
Finished Aug 06 04:31:44 PM PDT 24
Peak memory 199836 kb
Host smart-85d5f650-a39d-44ae-a714-0db73940c886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705899374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.705899374
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.911590334
Short name T757
Test name
Test status
Simulation time 83353268530 ps
CPU time 328.78 seconds
Started Aug 06 04:30:26 PM PDT 24
Finished Aug 06 04:35:55 PM PDT 24
Peak memory 215632 kb
Host smart-372eac69-9509-4a65-a9b0-e38cd9d3b337
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911590334 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.911590334
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.954006334
Short name T742
Test name
Test status
Simulation time 152447423942 ps
CPU time 101.85 seconds
Started Aug 06 04:30:26 PM PDT 24
Finished Aug 06 04:32:07 PM PDT 24
Peak memory 199724 kb
Host smart-e22e8610-fdef-4ec5-a079-940f75ef36a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954006334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.954006334
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.418089556
Short name T1158
Test name
Test status
Simulation time 40801239377 ps
CPU time 190.34 seconds
Started Aug 06 04:30:28 PM PDT 24
Finished Aug 06 04:33:38 PM PDT 24
Peak memory 216324 kb
Host smart-0c49889a-9f62-42d5-9708-5ba9db16ddad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418089556 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.418089556
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.38350229
Short name T1180
Test name
Test status
Simulation time 14631059367 ps
CPU time 28.72 seconds
Started Aug 06 04:30:26 PM PDT 24
Finished Aug 06 04:30:55 PM PDT 24
Peak memory 199688 kb
Host smart-e680388c-2a97-4444-9f81-f06ae40386fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38350229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.38350229
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1925848998
Short name T13
Test name
Test status
Simulation time 14635184234 ps
CPU time 157.77 seconds
Started Aug 06 04:30:27 PM PDT 24
Finished Aug 06 04:33:05 PM PDT 24
Peak memory 215968 kb
Host smart-6ee1063b-e75e-4dd4-9728-17e8c7f91ca3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925848998 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1925848998
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.841704264
Short name T347
Test name
Test status
Simulation time 115198945011 ps
CPU time 31.63 seconds
Started Aug 06 04:30:28 PM PDT 24
Finished Aug 06 04:31:00 PM PDT 24
Peak memory 199572 kb
Host smart-5af8b529-78eb-4be1-a5e4-517440cba151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841704264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.841704264
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.926130916
Short name T756
Test name
Test status
Simulation time 19776492067 ps
CPU time 61.57 seconds
Started Aug 06 04:30:27 PM PDT 24
Finished Aug 06 04:31:29 PM PDT 24
Peak memory 209660 kb
Host smart-bb8f9b48-b75d-44ca-9199-d424ff649888
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926130916 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.926130916
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2936212304
Short name T44
Test name
Test status
Simulation time 77655562753 ps
CPU time 33.74 seconds
Started Aug 06 04:30:40 PM PDT 24
Finished Aug 06 04:31:14 PM PDT 24
Peak memory 199748 kb
Host smart-84e861b9-e143-4d86-bde3-691cc381abb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936212304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2936212304
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.64332642
Short name T238
Test name
Test status
Simulation time 26489878636 ps
CPU time 40.03 seconds
Started Aug 06 04:30:42 PM PDT 24
Finished Aug 06 04:31:22 PM PDT 24
Peak memory 199660 kb
Host smart-f1ac7afc-64a3-405b-8a34-c2c05bccb0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64332642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.64332642
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1176759209
Short name T59
Test name
Test status
Simulation time 102671926835 ps
CPU time 656.17 seconds
Started Aug 06 04:30:41 PM PDT 24
Finished Aug 06 04:41:37 PM PDT 24
Peak memory 224608 kb
Host smart-97ecf6f7-ad6d-4768-bffa-0c6d9626a1b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176759209 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1176759209
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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