Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	109147	1			T1	6		T2	39		T3	34
all_values[1]	109147	1			T1	6		T2	39		T3	34
all_values[2]	109147	1			T1	6		T2	39		T3	34
all_values[3]	109147	1			T1	6		T2	39		T3	34
all_values[4]	109147	1			T1	6		T2	39		T3	34
all_values[5]	109147	1			T1	6		T2	39		T3	34
all_values[6]	109147	1			T1	6		T2	39		T3	34
all_values[7]	109147	1			T1	6		T2	39		T3	34
all_values[8]	109147	1			T1	6		T2	39		T3	34

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

492349

1

T1

38

T2

225

T3

125

auto[1]

489974

1

T1

16

T2

126

T3

181

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

893291

1

T1

41

T2

304

T3

256

auto[1]

89032

1

T1

13

T2

47

T3

50

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	33405	1			T5	2		T7	756		T8	1
all_values[0]	auto[0]	auto[1]	23653	1			T1	6		T2	23		T4	2
all_values[0]	auto[1]	auto[0]	32262	1			T2	16		T3	9		T4	2
all_values[0]	auto[1]	auto[1]	19827	1			T3	25		T4	5		T5	4
all_values[1]	auto[0]	auto[0]	51962	1			T2	19		T3	33		T4	5
all_values[1]	auto[0]	auto[1]	1765	1			T2	10		T4	2		T7	1
all_values[1]	auto[1]	auto[0]	53822	1			T1	6		T2	10		T3	1
all_values[1]	auto[1]	auto[1]	1598	1			T7	33		T8	2		T12	6
all_values[2]	auto[0]	auto[0]	52867	1			T1	5		T2	33		T4	6
all_values[2]	auto[0]	auto[1]	2792	1			T1	1		T2	6		T4	1
all_values[2]	auto[1]	auto[0]	50995	1			T3	34		T4	1		T5	3
all_values[2]	auto[1]	auto[1]	2493	1			T4	1		T5	2		T7	10
all_values[3]	auto[0]	auto[0]	52913	1			T1	4		T2	5		T3	1
all_values[3]	auto[0]	auto[1]	284	1			T5	1		T12	3		T72	2
all_values[3]	auto[1]	auto[0]	55623	1			T1	2		T2	34		T3	33
all_values[3]	auto[1]	auto[1]	327	1			T11	1		T73	1		T14	3
all_values[4]	auto[0]	auto[0]	53498	1			T1	4		T2	13		T3	9
all_values[4]	auto[0]	auto[1]	521	1			T14	8		T20	4		T16	1
all_values[4]	auto[1]	auto[0]	54601	1			T1	2		T2	26		T3	25
all_values[4]	auto[1]	auto[1]	527	1			T14	5		T15	2		T16	2
all_values[5]	auto[0]	auto[0]	52903	1			T1	4		T2	20		T3	33
all_values[5]	auto[0]	auto[1]	176	1			T16	3		T71	2		T35	1
all_values[5]	auto[1]	auto[0]	55872	1			T1	2		T2	19		T3	1
all_values[5]	auto[1]	auto[1]	196	1			T16	1		T71	4		T98	5
all_values[6]	auto[0]	auto[0]	55898	1			T1	2		T2	26		T3	1
all_values[6]	auto[0]	auto[1]	202	1			T16	3		T71	2		T36	2
all_values[6]	auto[1]	auto[0]	52854	1			T1	4		T2	13		T3	33
all_values[6]	auto[1]	auto[1]	193	1			T16	1		T71	2		T33	3
all_values[7]	auto[0]	auto[0]	54478	1			T1	6		T2	31		T3	24
all_values[7]	auto[0]	auto[1]	366	1			T15	1		T71	4		T137	2
all_values[7]	auto[1]	auto[0]	53930	1			T2	8		T3	10		T4	4
all_values[7]	auto[1]	auto[1]	373	1			T14	9		T16	1		T244	1
all_values[8]	auto[0]	auto[0]	37688	1			T2	31		T7	119		T8	6
all_values[8]	auto[0]	auto[1]	16978	1			T1	6		T2	8		T3	24
all_values[8]	auto[1]	auto[0]	37720	1			T3	9		T4	2		T5	2
all_values[8]	auto[1]	auto[1]	16761	1			T3	1		T4	7		T6	1