Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2629

1

T1

1

T2

1

T3

1

auto[UartRx]

2629

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4638	1			T1	2		T2	2		T3	2
values[1]	42	1			T12	2		T35	1		T37	1
values[2]	50	1			T34	2		T35	1		T36	2
values[3]	61	1			T7	1		T35	2		T37	3
values[4]	61	1			T7	1		T12	1		T32	2
values[5]	58	1			T20	2		T33	1		T99	1
values[6]	57	1			T7	2		T33	1		T35	4
values[7]	57	1			T32	1		T33	1		T35	2
values[8]	63	1			T7	1		T33	1		T34	1
values[9]	68	1			T7	1		T20	1		T33	1
values[10]	79	1			T7	1		T20	1		T33	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2425	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	8	1			T12	1		T148	1		T305	1
auto[UartTx]	values[2]	22	1			T34	1		T36	1		T98	1
auto[UartTx]	values[3]	20	1			T35	1		T37	1		T98	1
auto[UartTx]	values[4]	16	1			T7	1		T32	1		T48	1
auto[UartTx]	values[5]	23	1			T33	1		T99	1		T111	1
auto[UartTx]	values[6]	20	1			T7	1		T33	1		T35	1
auto[UartTx]	values[7]	18	1			T35	1		T306	1		T307	1
auto[UartTx]	values[8]	24	1			T33	1		T111	1		T100	1
auto[UartTx]	values[9]	23	1			T7	1		T37	1		T99	1
auto[UartTx]	values[10]	25	1			T7	1		T98	4		T100	1
auto[UartRx]	values[0]	2213	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	34	1			T12	1		T35	1		T37	1
auto[UartRx]	values[2]	28	1			T34	1		T35	1		T36	1
auto[UartRx]	values[3]	41	1			T7	1		T35	1		T37	2
auto[UartRx]	values[4]	45	1			T12	1		T32	1		T35	1
auto[UartRx]	values[5]	35	1			T20	2		T101	1		T176	1
auto[UartRx]	values[6]	37	1			T7	1		T35	3		T38	1
auto[UartRx]	values[7]	39	1			T32	1		T33	1		T35	1
auto[UartRx]	values[8]	39	1			T7	1		T34	1		T37	1
auto[UartRx]	values[9]	45	1			T20	1		T33	1		T98	2
auto[UartRx]	values[10]	54	1			T20	1		T33	1		T34	2