Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2540	1			T2	5		T3	1		T7	2
auto[BaudRate115200]	2216	1			T1	2		T4	5		T5	3
auto[BaudRate230400]	2175	1			T1	1		T3	1		T4	3
auto[BaudRate128Kbps]	2136	1			T1	2		T2	1		T3	1
auto[BaudRate256Kbps]	2249	1			T2	1		T3	1		T4	1
auto[BaudRate1Mbps]	2010	1			T1	1		T5	1		T6	9
auto[BaudRate1p5Mbps]	1415	1			T1	1		T3	1		T7	7

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1680	1			T6	24		T8	5		T42	11
freqs[25]	1550	1			T11	20		T116	14		T72	10
freqs[48]	741	1			T196	6		T290	2		T136	6
freqs[50]	718	1			T44	8		T274	2		T273	2
freqs[100]	951	1			T3	5		T18	2		T250	7

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	313	1			T42	2		T308	18		T181	1
auto[BaudRate9600]	freqs[25]	279	1			T11	4		T116	1		T72	2
auto[BaudRate9600]	freqs[48]	90	1			T290	1		T309	1		T199	1
auto[BaudRate9600]	freqs[50]	123	1			T256	1		T108	3		T157	1
auto[BaudRate9600]	freqs[100]	164	1			T3	1		T276	1		T135	1
auto[BaudRate115200]	freqs[24]	238	1			T6	6		T8	1		T42	2
auto[BaudRate115200]	freqs[25]	219	1			T11	5		T116	2		T72	2
auto[BaudRate115200]	freqs[48]	116	1			T196	1		T136	2		T199	1
auto[BaudRate115200]	freqs[50]	97	1			T44	2		T274	1		T108	1
auto[BaudRate115200]	freqs[100]	149	1			T135	3		T310	1		T287	1
auto[BaudRate230400]	freqs[24]	229	1			T6	6		T8	1		T42	3
auto[BaudRate230400]	freqs[25]	230	1			T11	2		T116	4		T72	1
auto[BaudRate230400]	freqs[48]	125	1			T136	1		T199	1		T162	2
auto[BaudRate230400]	freqs[50]	94	1			T44	1		T273	1		T256	3
auto[BaudRate230400]	freqs[100]	110	1			T3	1		T276	2		T133	1
auto[BaudRate128Kbps]	freqs[24]	248	1			T6	3		T8	1		T181	1
auto[BaudRate128Kbps]	freqs[25]	217	1			T11	7		T116	4		T72	2
auto[BaudRate128Kbps]	freqs[48]	96	1			T196	1		T290	1		T162	1
auto[BaudRate128Kbps]	freqs[50]	99	1			T274	1		T262	1		T256	2
auto[BaudRate128Kbps]	freqs[100]	124	1			T3	1		T281	5		T287	3
auto[BaudRate256Kbps]	freqs[24]	242	1			T42	3		T181	1		T126	3
auto[BaudRate256Kbps]	freqs[25]	236	1			T11	1		T116	2		T72	1
auto[BaudRate256Kbps]	freqs[48]	76	1			T136	1		T309	1		T162	1
auto[BaudRate256Kbps]	freqs[50]	92	1			T44	1		T262	1		T108	1
auto[BaudRate256Kbps]	freqs[100]	129	1			T3	1		T18	1		T250	3
auto[BaudRate1Mbps]	freqs[24]	282	1			T6	9		T8	1		T42	1
auto[BaudRate1Mbps]	freqs[25]	243	1			T72	1		T145	1		T20	3
auto[BaudRate1Mbps]	freqs[48]	108	1			T196	2		T136	1		T199	1
auto[BaudRate1Mbps]	freqs[50]	117	1			T44	2		T256	2		T108	2
auto[BaudRate1Mbps]	freqs[100]	150	1			T250	3		T276	1		T135	1
auto[BaudRate1p5Mbps]	freqs[25]	126	1			T11	1		T116	1		T72	1
auto[BaudRate1p5Mbps]	freqs[48]	130	1			T196	2		T136	1		T199	1
auto[BaudRate1p5Mbps]	freqs[50]	96	1			T44	2		T273	1		T108	2
auto[BaudRate1p5Mbps]	freqs[100]	125	1			T3	1		T18	1		T250	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded