Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	11	119	91.54

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	11	119	91.54	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	29001445	1			T1	26		T2	28		T3	24
all_levels[1]	192878	1			T2	9		T4	2		T5	1
all_levels[2]	2650	1			T2	7		T7	2		T9	10
all_levels[3]	1081	1			T2	11		T7	1		T40	2
all_levels[4]	774	1			T2	6		T7	1		T42	1
all_levels[5]	553	1			T2	3		T7	1		T116	3
all_levels[6]	389	1			T2	1		T7	1		T40	1
all_levels[7]	320	1			T2	1		T7	3		T11	1
all_levels[8]	280	1			T2	3		T7	1		T41	1
all_levels[9]	246	1			T2	3		T7	1		T8	1
all_levels[10]	193	1			T2	2		T4	4		T107	1
all_levels[11]	173	1			T11	1		T45	1		T117	1
all_levels[12]	159	1			T41	1		T11	2		T45	2
all_levels[13]	139	1			T2	2		T7	1		T106	1
all_levels[14]	125	1			T3	1		T118	1		T20	1
all_levels[15]	114	1			T7	1		T8	1		T119	1
all_levels[16]	108	1			T2	1		T120	1		T121	1
all_levels[17]	95	1			T2	1		T107	1		T45	2
all_levels[18]	71	1			T8	2		T107	1		T120	1
all_levels[19]	90	1			T5	2		T41	1		T11	1
all_levels[20]	72	1			T108	1		T122	1		T123	1
all_levels[21]	74	1			T8	1		T11	1		T121	1
all_levels[22]	56	1			T121	2		T124	3		T33	1
all_levels[23]	68	1			T125	2		T126	1		T127	2
all_levels[24]	60	1			T128	1		T129	1		T71	1
all_levels[25]	48	1			T130	1		T131	1		T132	1
all_levels[26]	48	1			T117	1		T133	1		T134	1
all_levels[27]	38	1			T135	1		T33	1		T136	1
all_levels[28]	45	1			T73	1		T105	2		T137	1
all_levels[29]	36	1			T126	4		T33	1		T132	1
all_levels[30]	40	1			T71	2		T33	1		T131	1
all_levels[31]	26	1			T137	1		T33	1		T138	1
all_levels[32]	36	1			T107	1		T139	1		T124	1
all_levels[33]	16	1			T140	1		T141	1		T142	1
all_levels[34]	18	1			T124	1		T143	1		T144	1
all_levels[35]	28	1			T145	1		T146	1		T147	1
all_levels[36]	17	1			T35	1		T148	1		T146	1
all_levels[37]	29	1			T45	1		T71	1		T149	1
all_levels[38]	16	1			T4	1		T34	1		T35	1
all_levels[39]	12	1			T130	1		T34	1		T140	1
all_levels[40]	20	1			T73	2		T141	1		T150	1
all_levels[41]	25	1			T109	1		T140	1		T149	1
all_levels[42]	30	1			T45	1		T151	2		T152	1
all_levels[43]	20	1			T153	1		T142	1		T154	1
all_levels[44]	14	1			T142	3		T144	1		T155	1
all_levels[45]	30	1			T128	1		T139	3		T99	1
all_levels[46]	11	1			T141	1		T144	1		T156	1
all_levels[47]	14	1			T16	1		T143	1		T157	1
all_levels[48]	14	1			T108	1		T143	1		T112	1
all_levels[49]	15	1			T158	1		T159	1		T142	1
all_levels[50]	11	1			T123	1		T157	1		T132	1
all_levels[51]	4	1			T123	1		T160	1		T161	1
all_levels[52]	12	1			T112	2		T162	1		T102	1
all_levels[53]	7	1			T160	1		T163	1		T164	1
all_levels[54]	8	1			T129	1		T159	1		T165	1
all_levels[55]	7	1			T49	1		T166	1		T167	1
all_levels[56]	12	1			T106	1		T107	1		T118	1
all_levels[57]	8	1			T132	1		T112	1		T152	1
all_levels[58]	7	1			T168	1		T169	1		T170	1
all_levels[59]	6	1			T143	2		T157	1		T171	1
all_levels[60]	6	1			T172	1		T173	1		T174	1
all_levels[61]	4	1			T132	1		T175	1		T156	1
all_levels[62]	7	1			T132	1		T112	1		T162	2
all_levels[63]	9	1			T122	1		T176	1		T172	2
all_levels[64]	83	1			T5	1		T122	1		T127	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29198030

1

T1

21

T2

71

T3

22

auto[1]

5020

1

T1

5

T2

7

T3

3

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	11	119	91.54	11

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[38] , all_levels[39]]	[auto[1]]	--	--	2
[all_levels[43]]	[auto[1]]	0	1	1
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[50] , all_levels[51]]	[auto[1]]	--	--	2
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[57]]	[auto[1]]	0	1	1
[all_levels[59] , all_levels[60] , all_levels[61]]	[auto[1]]	--	--	3

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	28996898	1			T1	21		T2	23		T3	21
all_levels[0]	auto[1]	4547	1			T1	5		T2	5		T3	3
all_levels[1]	auto[0]	192784	1			T2	9		T4	2		T5	1
all_levels[1]	auto[1]	94	1			T11	17		T12	2		T125	1
all_levels[2]	auto[0]	2621	1			T2	7		T7	2		T9	10
all_levels[2]	auto[1]	29	1			T135	1		T177	1		T178	1
all_levels[3]	auto[0]	1064	1			T2	11		T7	1		T40	2
all_levels[3]	auto[1]	17	1			T128	1		T45	1		T179	1
all_levels[4]	auto[0]	759	1			T2	6		T7	1		T42	1
all_levels[4]	auto[1]	15	1			T108	2		T179	1		T180	3
all_levels[5]	auto[0]	532	1			T2	3		T7	1		T116	3
all_levels[5]	auto[1]	21	1			T128	2		T181	1		T182	1
all_levels[6]	auto[0]	370	1			T2	1		T7	1		T40	1
all_levels[6]	auto[1]	19	1			T45	1		T33	1		T183	1
all_levels[7]	auto[0]	304	1			T2	1		T7	3		T11	1
all_levels[7]	auto[1]	16	1			T73	2		T179	2		T184	4
all_levels[8]	auto[0]	260	1			T2	1		T7	1		T41	1
all_levels[8]	auto[1]	20	1			T2	2		T182	1		T157	1
all_levels[9]	auto[0]	227	1			T2	3		T7	1		T8	1
all_levels[9]	auto[1]	19	1			T183	1		T185	1		T186	1
all_levels[10]	auto[0]	181	1			T2	2		T4	1		T107	1
all_levels[10]	auto[1]	12	1			T4	3		T187	1		T171	3
all_levels[11]	auto[0]	161	1			T11	1		T45	1		T117	1
all_levels[11]	auto[1]	12	1			T188	1		T189	1		T190	1
all_levels[12]	auto[0]	149	1			T41	1		T11	2		T45	2
all_levels[12]	auto[1]	10	1			T176	1		T163	1		T191	1
all_levels[13]	auto[0]	127	1			T2	2		T7	1		T106	1
all_levels[13]	auto[1]	12	1			T192	2		T149	1		T193	1
all_levels[14]	auto[0]	122	1			T3	1		T118	1		T20	1
all_levels[14]	auto[1]	3	1			T194	1		T195	2		-	-
all_levels[15]	auto[0]	111	1			T7	1		T8	1		T119	1
all_levels[15]	auto[1]	3	1			T196	1		T197	1		T198	1
all_levels[16]	auto[0]	94	1			T2	1		T120	1		T121	1
all_levels[16]	auto[1]	14	1			T199	1		T200	1		T201	2
all_levels[17]	auto[0]	89	1			T2	1		T107	1		T45	1
all_levels[17]	auto[1]	6	1			T45	1		T16	3		T202	1
all_levels[18]	auto[0]	65	1			T8	1		T107	1		T120	1
all_levels[18]	auto[1]	6	1			T8	1		T141	1		T203	1
all_levels[19]	auto[0]	79	1			T5	2		T41	1		T11	1
all_levels[19]	auto[1]	11	1			T183	1		T204	1		T205	1
all_levels[20]	auto[0]	63	1			T108	1		T122	1		T123	1
all_levels[20]	auto[1]	9	1			T206	1		T189	3		T207	3
all_levels[21]	auto[0]	67	1			T8	1		T11	1		T121	1
all_levels[21]	auto[1]	7	1			T208	2		T209	2		T210	3
all_levels[22]	auto[0]	49	1			T121	1		T124	2		T33	1
all_levels[22]	auto[1]	7	1			T121	1		T124	1		T211	1
all_levels[23]	auto[0]	54	1			T125	1		T126	1		T127	1
all_levels[23]	auto[1]	14	1			T125	1		T127	1		T168	1
all_levels[24]	auto[0]	52	1			T128	1		T129	1		T71	1
all_levels[24]	auto[1]	8	1			T212	2		T213	1		T214	1
all_levels[25]	auto[0]	42	1			T130	1		T131	1		T132	1
all_levels[25]	auto[1]	6	1			T215	1		T216	2		T195	3
all_levels[26]	auto[0]	42	1			T117	1		T133	1		T134	1
all_levels[26]	auto[1]	6	1			T217	1		T162	1		T218	1
all_levels[27]	auto[0]	35	1			T135	1		T33	1		T136	1
all_levels[27]	auto[1]	3	1			T162	1		T163	1		T219	1
all_levels[28]	auto[0]	43	1			T73	1		T105	1		T137	1
all_levels[28]	auto[1]	2	1			T105	1		T33	1		-	-
all_levels[29]	auto[0]	33	1			T126	1		T33	1		T132	1
all_levels[29]	auto[1]	3	1			T126	3		-	-		-	-
all_levels[30]	auto[0]	38	1			T71	2		T33	1		T131	1
all_levels[30]	auto[1]	2	1			T134	2		-	-		-	-
all_levels[31]	auto[0]	22	1			T137	1		T33	1		T138	1
all_levels[31]	auto[1]	4	1			T220	2		T221	1		T222	1
all_levels[32]	auto[0]	34	1			T107	1		T139	1		T124	1
all_levels[32]	auto[1]	2	1			T123	1		T134	1		-	-
all_levels[33]	auto[0]	15	1			T140	1		T141	1		T142	1
all_levels[33]	auto[1]	1	1			T223	1		-	-		-	-
all_levels[34]	auto[0]	17	1			T124	1		T143	1		T144	1
all_levels[34]	auto[1]	1	1			T156	1		-	-		-	-
all_levels[35]	auto[0]	26	1			T145	1		T146	1		T147	1
all_levels[35]	auto[1]	2	1			T224	1		T225	1		-	-
all_levels[36]	auto[0]	14	1			T35	1		T148	1		T146	1
all_levels[36]	auto[1]	3	1			T170	1		T226	2		-	-
all_levels[37]	auto[0]	25	1			T45	1		T71	1		T149	1
all_levels[37]	auto[1]	4	1			T133	1		T227	2		T228	1
all_levels[38]	auto[0]	16	1			T4	1		T34	1		T35	1
all_levels[39]	auto[0]	12	1			T130	1		T34	1		T140	1
all_levels[40]	auto[0]	19	1			T73	1		T141	1		T150	1
all_levels[40]	auto[1]	1	1			T73	1		-	-		-	-
all_levels[41]	auto[0]	21	1			T109	1		T140	1		T149	1
all_levels[41]	auto[1]	4	1			T171	1		T229	1		T230	2
all_levels[42]	auto[0]	28	1			T45	1		T151	1		T152	1
all_levels[42]	auto[1]	2	1			T151	1		T231	1		-	-
all_levels[43]	auto[0]	20	1			T153	1		T142	1		T154	1
all_levels[44]	auto[0]	12	1			T142	1		T144	1		T155	1
all_levels[44]	auto[1]	2	1			T142	2		-	-		-	-
all_levels[45]	auto[0]	21	1			T128	1		T139	1		T99	1
all_levels[45]	auto[1]	9	1			T139	2		T93	2		T232	1
all_levels[46]	auto[0]	11	1			T141	1		T144	1		T156	1
all_levels[47]	auto[0]	11	1			T16	1		T143	1		T157	1
all_levels[47]	auto[1]	3	1			T233	2		T234	1		-	-
all_levels[48]	auto[0]	12	1			T108	1		T143	1		T112	1
all_levels[48]	auto[1]	2	1			T170	1		T235	1		-	-
all_levels[49]	auto[0]	14	1			T158	1		T159	1		T142	1
all_levels[49]	auto[1]	1	1			T236	1		-	-		-	-
all_levels[50]	auto[0]	11	1			T123	1		T157	1		T132	1
all_levels[51]	auto[0]	4	1			T123	1		T160	1		T161	1
all_levels[52]	auto[0]	9	1			T112	2		T162	1		T102	1
all_levels[52]	auto[1]	3	1			T237	2		T238	1		-	-
all_levels[53]	auto[0]	5	1			T160	1		T163	1		T164	1
all_levels[53]	auto[1]	2	1			T239	2		-	-		-	-
all_levels[54]	auto[0]	8	1			T129	1		T159	1		T165	1
all_levels[55]	auto[0]	6	1			T49	1		T166	1		T167	1
all_levels[55]	auto[1]	1	1			T240	1		-	-		-	-
all_levels[56]	auto[0]	11	1			T106	1		T107	1		T118	1
all_levels[56]	auto[1]	1	1			T210	1		-	-		-	-
all_levels[57]	auto[0]	8	1			T132	1		T112	1		T152	1
all_levels[58]	auto[0]	6	1			T168	1		T169	1		T170	1
all_levels[58]	auto[1]	1	1			T241	1		-	-		-	-
all_levels[59]	auto[0]	6	1			T143	2		T157	1		T171	1
all_levels[60]	auto[0]	6	1			T172	1		T173	1		T174	1
all_levels[61]	auto[0]	4	1			T132	1		T175	1		T156	1
all_levels[62]	auto[0]	6	1			T132	1		T112	1		T162	1
all_levels[62]	auto[1]	1	1			T162	1		-	-		-	-
all_levels[63]	auto[0]	7	1			T122	1		T176	1		T172	2
all_levels[63]	auto[1]	2	1			T242	2		-	-		-	-
all_levels[64]	auto[0]	68	1			T5	1		T122	1		T127	1
all_levels[64]	auto[1]	15	1			T168	1		T175	1		T243	2