Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	109147	1			T1	6		T2	39		T3	34
all_pins[1]	109147	1			T1	6		T2	39		T3	34
all_pins[2]	109147	1			T1	6		T2	39		T3	34
all_pins[3]	109147	1			T1	6		T2	39		T3	34
all_pins[4]	109147	1			T1	6		T2	39		T3	34
all_pins[5]	109147	1			T1	6		T2	39		T3	34
all_pins[6]	109147	1			T1	6		T2	39		T3	34
all_pins[7]	109147	1			T1	6		T2	39		T3	34
all_pins[8]	109147	1			T1	6		T2	39		T3	34

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	938948	1			T1	50		T2	351		T3	280
values[0x1]	43375	1			T1	4		T3	26		T4	14
transitions[0x0=>0x1]	34220	1			T1	4		T3	25		T4	9
transitions[0x1=>0x0]	34019	1			T1	4		T3	25		T4	10

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	89233	1			T1	6		T2	39		T3	9
all_pins[0]	values[0x1]	19914	1			T3	25		T4	5		T5	4
all_pins[0]	transitions[0x0=>0x1]	19319	1			T3	25		T4	5		T5	4
all_pins[0]	transitions[0x1=>0x0]	1002	1			T7	31		T8	2		T12	6
all_pins[1]	values[0x0]	107550	1			T1	6		T2	39		T3	34
all_pins[1]	values[0x1]	1597	1			T7	35		T8	2		T12	6
all_pins[1]	transitions[0x0=>0x1]	1500	1			T7	35		T8	2		T12	6
all_pins[1]	transitions[0x1=>0x0]	2456	1			T4	1		T5	2		T7	10
all_pins[2]	values[0x0]	106594	1			T1	6		T2	39		T3	34
all_pins[2]	values[0x1]	2553	1			T4	1		T5	2		T7	10
all_pins[2]	transitions[0x0=>0x1]	2498	1			T4	1		T5	2		T7	10
all_pins[2]	transitions[0x1=>0x0]	272	1			T11	1		T73	1		T14	3
all_pins[3]	values[0x0]	108820	1			T1	6		T2	39		T3	34
all_pins[3]	values[0x1]	327	1			T11	1		T73	1		T14	3
all_pins[3]	transitions[0x0=>0x1]	283	1			T11	1		T73	1		T14	3
all_pins[3]	transitions[0x1=>0x0]	483	1			T14	5		T15	2		T16	2
all_pins[4]	values[0x0]	108620	1			T1	6		T2	39		T3	34
all_pins[4]	values[0x1]	527	1			T14	5		T15	2		T16	2
all_pins[4]	transitions[0x0=>0x1]	439	1			T14	5		T15	2		T16	2
all_pins[4]	transitions[0x1=>0x0]	192	1			T14	2		T16	1		T17	3
all_pins[5]	values[0x0]	108867	1			T1	6		T2	39		T3	34
all_pins[5]	values[0x1]	280	1			T14	2		T16	1		T17	3
all_pins[5]	transitions[0x0=>0x1]	229	1			T14	2		T16	1		T17	3
all_pins[5]	transitions[0x1=>0x0]	909	1			T1	4		T4	1		T5	1
all_pins[6]	values[0x0]	108187	1			T1	2		T2	39		T3	34
all_pins[6]	values[0x1]	960	1			T1	4		T4	1		T5	1
all_pins[6]	transitions[0x0=>0x1]	913	1			T1	4		T4	1		T5	1
all_pins[6]	transitions[0x1=>0x0]	326	1			T14	9		T16	1		T244	1
all_pins[7]	values[0x0]	108774	1			T1	6		T2	39		T3	34
all_pins[7]	values[0x1]	373	1			T14	9		T16	1		T244	1
all_pins[7]	transitions[0x0=>0x1]	221	1			T14	6		T244	1		T71	3
all_pins[7]	transitions[0x1=>0x0]	16692	1			T3	1		T4	7		T6	1
all_pins[8]	values[0x0]	92303	1			T1	6		T2	39		T3	33
all_pins[8]	values[0x1]	16844	1			T3	1		T4	7		T6	1
all_pins[8]	transitions[0x0=>0x1]	8818	1			T4	2		T7	132		T9	2
all_pins[8]	transitions[0x1=>0x0]	11687	1			T3	24		T4	1		T5	4