Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6607077	1			T1	4		T2	38		T3	21
all_levels[1]	1332306	1			T1	2		T4	3		T5	1
all_levels[2]	528737	1			T2	17		T5	1		T7	772
all_levels[3]	339340	1			T5	1		T7	956		T9	32
all_levels[4]	277484	1			T7	805		T9	28		T10	2426
all_levels[5]	232425	1			T2	3		T5	1		T7	572
all_levels[6]	249354	1			T1	3		T7	459		T9	31
all_levels[7]	315226	1			T2	2		T7	929		T9	32
all_levels[8]	386029	1			T7	798		T9	35		T10	2437
all_levels[9]	472611	1			T1	1		T2	1		T5	2
all_levels[10]	225532	1			T1	1		T5	1		T7	327
all_levels[11]	244540	1			T1	2		T7	326		T9	37
all_levels[12]	194524	1			T1	1		T2	2		T7	203
all_levels[13]	241053	1			T1	6		T2	1		T7	329
all_levels[14]	423376	1			T2	1		T7	282		T9	34
all_levels[15]	196114	1			T1	1		T2	2		T7	278
all_levels[16]	396063	1			T1	1		T7	331		T9	33
all_levels[17]	238797	1			T7	262		T9	41		T10	3107
all_levels[18]	224799	1			T1	2		T7	263		T9	31
all_levels[19]	272365	1			T7	342		T9	32		T10	3125
all_levels[20]	179319	1			T2	3		T7	373		T9	36
all_levels[21]	196226	1			T7	283		T9	33		T10	3123
all_levels[22]	220681	1			T7	201		T9	29		T10	3106
all_levels[23]	180212	1			T7	262		T9	30		T10	3129
all_levels[24]	185940	1			T2	1		T5	2		T7	311
all_levels[25]	196591	1			T2	2		T5	1		T7	319
all_levels[26]	265894	1			T1	2		T2	1		T5	1
all_levels[27]	257275	1			T2	1		T7	327		T9	29
all_levels[28]	199062	1			T7	555		T9	37		T10	1719
all_levels[29]	179715	1			T1	2		T7	552		T9	40
all_levels[30]	157730	1			T7	401		T9	33		T10	1722
all_levels[31]	747277	1			T2	3		T5	3		T7	1470
all_levels[32]	12838860	1			T3	5		T4	4		T5	4

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29198030

1

T1

21

T2

71

T3

22

auto[1]

4504

1

T1

7

T2

7

T3

4

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6604601	1			T1	3		T2	33		T3	18
all_levels[0]	auto[1]	2476	1			T1	1		T2	5		T3	3
all_levels[1]	auto[0]	1331945	1			T1	2		T4	2		T5	1
all_levels[1]	auto[1]	361	1			T4	1		T8	3		T11	3
all_levels[2]	auto[0]	528708	1			T2	15		T5	1		T7	772
all_levels[2]	auto[1]	29	1			T2	2		T147	2		T154	1
all_levels[3]	auto[0]	339128	1			T5	1		T7	956		T9	32
all_levels[3]	auto[1]	212	1			T72	1		T121	1		T255	17
all_levels[4]	auto[0]	277460	1			T7	805		T9	28		T10	2426
all_levels[4]	auto[1]	24	1			T127	1		T168	1		T311	3
all_levels[5]	auto[0]	232393	1			T2	3		T5	1		T7	572
all_levels[5]	auto[1]	32	1			T11	16		T118	1		T20	1
all_levels[6]	auto[0]	249330	1			T1	1		T7	459		T9	31
all_levels[6]	auto[1]	24	1			T1	2		T45	1		T136	1
all_levels[7]	auto[0]	315075	1			T2	2		T7	929		T9	32
all_levels[7]	auto[1]	151	1			T11	1		T12	6		T118	2
all_levels[8]	auto[0]	386000	1			T7	798		T9	35		T10	2437
all_levels[8]	auto[1]	29	1			T71	3		T312	1		T313	1
all_levels[9]	auto[0]	472591	1			T1	1		T2	1		T5	2
all_levels[9]	auto[1]	20	1			T151	1		T96	1		T272	1
all_levels[10]	auto[0]	225487	1			T1	1		T5	1		T7	327
all_levels[10]	auto[1]	45	1			T16	5		T105	2		T96	1
all_levels[11]	auto[0]	244505	1			T1	2		T7	326		T9	37
all_levels[11]	auto[1]	35	1			T151	2		T105	1		T314	1
all_levels[12]	auto[0]	194491	1			T1	1		T2	2		T7	203
all_levels[12]	auto[1]	33	1			T107	1		T125	1		T45	1
all_levels[13]	auto[0]	241017	1			T1	2		T2	1		T7	329
all_levels[13]	auto[1]	36	1			T1	4		T40	1		T315	2
all_levels[14]	auto[0]	423355	1			T2	1		T7	282		T9	34
all_levels[14]	auto[1]	21	1			T106	1		T129	1		T33	2
all_levels[15]	auto[0]	195993	1			T1	1		T2	2		T7	277
all_levels[15]	auto[1]	121	1			T7	1		T14	4		T108	2
all_levels[16]	auto[0]	396046	1			T1	1		T7	331		T9	33
all_levels[16]	auto[1]	17	1			T183	1		T316	1		T162	1
all_levels[17]	auto[0]	238778	1			T7	262		T9	41		T10	3107
all_levels[17]	auto[1]	19	1			T11	1		T118	1		T192	2
all_levels[18]	auto[0]	224768	1			T1	2		T7	263		T9	31
all_levels[18]	auto[1]	31	1			T45	1		T192	1		T217	2
all_levels[19]	auto[0]	272343	1			T7	342		T9	32		T10	3125
all_levels[19]	auto[1]	22	1			T178	1		T312	1		T317	1
all_levels[20]	auto[0]	179301	1			T2	3		T7	373		T9	36
all_levels[20]	auto[1]	18	1			T318	1		T147	1		T319	1
all_levels[21]	auto[0]	196214	1			T7	283		T9	33		T10	3123
all_levels[21]	auto[1]	12	1			T42	1		T320	1		T180	1
all_levels[22]	auto[0]	220664	1			T7	201		T9	29		T10	3106
all_levels[22]	auto[1]	17	1			T104	1		T204	1		T47	2
all_levels[23]	auto[0]	180195	1			T7	262		T9	30		T10	3129
all_levels[23]	auto[1]	17	1			T34	1		T320	1		T313	1
all_levels[24]	auto[0]	185916	1			T2	1		T5	2		T7	311
all_levels[24]	auto[1]	24	1			T121	2		T73	1		T256	1
all_levels[25]	auto[0]	196566	1			T2	2		T5	1		T7	319
all_levels[25]	auto[1]	25	1			T126	1		T183	1		T318	3
all_levels[26]	auto[0]	265868	1			T1	2		T2	1		T5	1
all_levels[26]	auto[1]	26	1			T45	1		T220	1		T162	1
all_levels[27]	auto[0]	257251	1			T2	1		T7	327		T9	29
all_levels[27]	auto[1]	24	1			T196	1		T179	1		T217	1
all_levels[28]	auto[0]	199041	1			T7	555		T9	37		T10	1719
all_levels[28]	auto[1]	21	1			T112	1		T90	1		T95	5
all_levels[29]	auto[0]	179700	1			T1	2		T7	552		T9	40
all_levels[29]	auto[1]	15	1			T182	1		T321	1		T322	2
all_levels[30]	auto[0]	157717	1			T7	401		T9	33		T10	1722
all_levels[30]	auto[1]	13	1			T269	1		T182	1		T176	1
all_levels[31]	auto[0]	747256	1			T2	3		T5	3		T7	1470
all_levels[31]	auto[1]	21	1			T323	3		T212	3		T205	2
all_levels[32]	auto[0]	12838327	1			T3	4		T4	2		T5	4
all_levels[32]	auto[1]	533	1			T3	1		T4	2		T7	1