Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	809	1			T16	4		T71	11		T33	7
all_values[1]	809	1			T16	4		T71	11		T33	7
all_values[2]	809	1			T16	4		T71	11		T33	7
all_values[3]	809	1			T16	4		T71	11		T33	7
all_values[4]	809	1			T16	4		T71	11		T33	7
all_values[5]	809	1			T16	4		T71	11		T33	7
all_values[6]	809	1			T16	4		T71	11		T33	7
all_values[7]	809	1			T16	4		T71	11		T33	7
all_values[8]	809	1			T16	4		T71	11		T33	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3912

1

T16

26

T71

60

T33

36

auto[1]

3369

1

T16

10

T71

39

T33

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2402

1

T16

8

T71

37

T33

22

auto[1]

4879

1

T16

28

T71

62

T33

41

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4353

1

T16

19

T71

63

T33

40

auto[1]

2928

1

T16

17

T71

36

T33

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	248	1			T16	2		T71	3		T33	3
all_values[0]	auto[0]	auto[1]	auto[1]	224	1			T71	3		T33	2		T35	1
all_values[0]	auto[1]	auto[0]	auto[1]	163	1			T16	2		T71	3		T33	1
all_values[0]	auto[1]	auto[1]	auto[1]	174	1			T71	2		T33	1		T35	1
all_values[1]	auto[0]	auto[0]	auto[0]	243	1			T16	2		T71	5		T33	2
all_values[1]	auto[0]	auto[1]	auto[0]	242	1			T71	5		T33	4		T36	1
all_values[1]	auto[1]	auto[0]	auto[1]	195	1			T16	2		T71	1		T35	1
all_values[1]	auto[1]	auto[1]	auto[1]	129	1			T33	1		T35	1		T36	2
all_values[2]	auto[0]	auto[0]	auto[0]	191	1			T16	1		T71	3		T33	4
all_values[2]	auto[0]	auto[0]	auto[1]	76	1			T71	1		T33	1		T35	1
all_values[2]	auto[0]	auto[1]	auto[0]	163	1			T71	2		T35	1		T98	2
all_values[2]	auto[0]	auto[1]	auto[1]	74	1			T36	2		T98	2		T100	2
all_values[2]	auto[1]	auto[0]	auto[1]	177	1			T16	3		T71	4		T33	1
all_values[2]	auto[1]	auto[1]	auto[1]	128	1			T71	1		T33	1		T36	1
all_values[3]	auto[0]	auto[0]	auto[0]	161	1			T16	2		T71	5		T35	2
all_values[3]	auto[0]	auto[0]	auto[1]	89	1			T71	2		T111	1		T100	3
all_values[3]	auto[0]	auto[1]	auto[0]	156	1			T71	1		T33	1		T98	1
all_values[3]	auto[0]	auto[1]	auto[1]	87	1			T33	3		T35	1		T36	1
all_values[3]	auto[1]	auto[0]	auto[1]	183	1			T71	3		T33	3		T35	1
all_values[3]	auto[1]	auto[1]	auto[1]	133	1			T16	2		T36	2		T98	2
all_values[4]	auto[0]	auto[0]	auto[0]	161	1			T16	1		T71	2		T33	3
all_values[4]	auto[0]	auto[0]	auto[1]	97	1			T16	1		T71	1		T33	2
all_values[4]	auto[0]	auto[1]	auto[0]	145	1			T71	1		T98	2		T112	2
all_values[4]	auto[0]	auto[1]	auto[1]	72	1			T16	1		T71	2		T35	1
all_values[4]	auto[1]	auto[0]	auto[1]	194	1			T16	1		T71	2		T33	2
all_values[4]	auto[1]	auto[1]	auto[1]	140	1			T71	3		T35	1		T98	2
all_values[5]	auto[0]	auto[0]	auto[0]	177	1			T71	3		T33	2		T35	2
all_values[5]	auto[0]	auto[0]	auto[1]	78	1			T16	1		T71	1		T111	1
all_values[5]	auto[0]	auto[1]	auto[0]	138	1			T71	1		T33	2		T98	3
all_values[5]	auto[0]	auto[1]	auto[1]	81	1			T71	2		T36	1		T98	3
all_values[5]	auto[1]	auto[0]	auto[1]	166	1			T16	1		T71	2		T33	2
all_values[5]	auto[1]	auto[1]	auto[1]	169	1			T16	2		T71	2		T33	1
all_values[6]	auto[0]	auto[0]	auto[0]	158	1			T71	3		T33	1		T35	1
all_values[6]	auto[0]	auto[0]	auto[1]	99	1			T16	3		T71	1		T36	1
all_values[6]	auto[0]	auto[1]	auto[0]	149	1			T71	4		T33	3		T35	3
all_values[6]	auto[0]	auto[1]	auto[1]	79	1			T71	1		T33	2		T98	2
all_values[6]	auto[1]	auto[0]	auto[1]	187	1			T16	1		T71	2		T36	1
all_values[6]	auto[1]	auto[1]	auto[1]	137	1			T33	1		T36	1		T98	1
all_values[7]	auto[0]	auto[0]	auto[0]	165	1			T16	1		T71	2		T98	4
all_values[7]	auto[0]	auto[0]	auto[1]	95	1			T33	2		T35	1		T98	2
all_values[7]	auto[0]	auto[1]	auto[0]	153	1			T16	1		T36	3		T98	3
all_values[7]	auto[0]	auto[1]	auto[1]	66	1			T16	1		T71	4		T33	1
all_values[7]	auto[1]	auto[0]	auto[1]	197	1			T71	5		T33	2		T35	2
all_values[7]	auto[1]	auto[1]	auto[1]	133	1			T16	1		T33	2		T98	1
all_values[8]	auto[0]	auto[0]	auto[1]	254	1			T16	1		T71	4		T33	1
all_values[8]	auto[0]	auto[1]	auto[1]	232	1			T16	1		T71	1		T33	1
all_values[8]	auto[1]	auto[0]	auto[1]	158	1			T16	1		T71	2		T33	4
all_values[8]	auto[1]	auto[1]	auto[1]	165	1			T16	1		T71	4		T33	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal