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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.53


Total test records in report: 1315
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T1255 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1280498919 Aug 07 04:18:45 PM PDT 24 Aug 07 04:18:46 PM PDT 24 12923089 ps
T1256 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2102699973 Aug 07 04:19:53 PM PDT 24 Aug 07 04:19:54 PM PDT 24 125619909 ps
T1257 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2329424717 Aug 07 04:24:10 PM PDT 24 Aug 07 04:24:11 PM PDT 24 78987034 ps
T1258 /workspace/coverage/cover_reg_top/29.uart_intr_test.1387096819 Aug 07 04:24:24 PM PDT 24 Aug 07 04:24:24 PM PDT 24 14874692 ps
T1259 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2754037080 Aug 07 04:20:31 PM PDT 24 Aug 07 04:20:32 PM PDT 24 185911987 ps
T1260 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1422645577 Aug 07 04:19:51 PM PDT 24 Aug 07 04:19:52 PM PDT 24 21318633 ps
T1261 /workspace/coverage/cover_reg_top/34.uart_intr_test.257617189 Aug 07 04:21:07 PM PDT 24 Aug 07 04:21:08 PM PDT 24 14447841 ps
T1262 /workspace/coverage/cover_reg_top/12.uart_tl_errors.2472104579 Aug 07 04:18:58 PM PDT 24 Aug 07 04:19:00 PM PDT 24 118138011 ps
T1263 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3459676519 Aug 07 04:19:30 PM PDT 24 Aug 07 04:19:31 PM PDT 24 116760036 ps
T1264 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3304222603 Aug 07 04:21:26 PM PDT 24 Aug 07 04:21:27 PM PDT 24 66687393 ps
T1265 /workspace/coverage/cover_reg_top/43.uart_intr_test.1741722712 Aug 07 04:24:01 PM PDT 24 Aug 07 04:24:02 PM PDT 24 29841019 ps
T1266 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2169831845 Aug 07 04:18:56 PM PDT 24 Aug 07 04:18:58 PM PDT 24 97556699 ps
T1267 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.403147280 Aug 07 04:24:05 PM PDT 24 Aug 07 04:24:06 PM PDT 24 15568977 ps
T85 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1956054673 Aug 07 04:20:23 PM PDT 24 Aug 07 04:20:24 PM PDT 24 1256505094 ps
T1268 /workspace/coverage/cover_reg_top/5.uart_intr_test.1728434051 Aug 07 04:18:50 PM PDT 24 Aug 07 04:18:51 PM PDT 24 68753302 ps
T1269 /workspace/coverage/cover_reg_top/25.uart_intr_test.2372058265 Aug 07 04:22:17 PM PDT 24 Aug 07 04:22:18 PM PDT 24 40906971 ps
T1270 /workspace/coverage/cover_reg_top/44.uart_intr_test.1249146917 Aug 07 04:22:31 PM PDT 24 Aug 07 04:22:31 PM PDT 24 14144241 ps
T1271 /workspace/coverage/cover_reg_top/17.uart_tl_errors.1112284058 Aug 07 04:24:11 PM PDT 24 Aug 07 04:24:13 PM PDT 24 46017685 ps
T1272 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1288301158 Aug 07 04:18:51 PM PDT 24 Aug 07 04:18:52 PM PDT 24 83904027 ps
T1273 /workspace/coverage/cover_reg_top/12.uart_intr_test.1821435283 Aug 07 04:20:06 PM PDT 24 Aug 07 04:20:07 PM PDT 24 14622700 ps
T1274 /workspace/coverage/cover_reg_top/2.uart_csr_rw.192766565 Aug 07 04:18:49 PM PDT 24 Aug 07 04:18:49 PM PDT 24 17020082 ps
T1275 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2287968614 Aug 07 04:20:05 PM PDT 24 Aug 07 04:20:06 PM PDT 24 45331172 ps
T58 /workspace/coverage/cover_reg_top/7.uart_csr_rw.1755995835 Aug 07 04:19:53 PM PDT 24 Aug 07 04:19:54 PM PDT 24 44553482 ps
T1276 /workspace/coverage/cover_reg_top/18.uart_tl_errors.3082403505 Aug 07 04:21:06 PM PDT 24 Aug 07 04:21:08 PM PDT 24 167950249 ps
T1277 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.4140918183 Aug 07 04:24:10 PM PDT 24 Aug 07 04:24:11 PM PDT 24 169822263 ps
T1278 /workspace/coverage/cover_reg_top/1.uart_intr_test.3897567748 Aug 07 04:18:46 PM PDT 24 Aug 07 04:18:47 PM PDT 24 61771243 ps
T1279 /workspace/coverage/cover_reg_top/18.uart_intr_test.18635137 Aug 07 04:21:21 PM PDT 24 Aug 07 04:21:22 PM PDT 24 19434435 ps
T1280 /workspace/coverage/cover_reg_top/16.uart_tl_errors.3503484214 Aug 07 04:24:25 PM PDT 24 Aug 07 04:24:27 PM PDT 24 31282015 ps
T1281 /workspace/coverage/cover_reg_top/16.uart_csr_rw.559840673 Aug 07 04:24:24 PM PDT 24 Aug 07 04:24:25 PM PDT 24 13431595 ps
T1282 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2687563217 Aug 07 04:20:06 PM PDT 24 Aug 07 04:20:08 PM PDT 24 104024979 ps
T1283 /workspace/coverage/cover_reg_top/4.uart_csr_rw.2075988205 Aug 07 04:21:18 PM PDT 24 Aug 07 04:21:19 PM PDT 24 22065154 ps
T1284 /workspace/coverage/cover_reg_top/18.uart_csr_rw.369325974 Aug 07 04:24:20 PM PDT 24 Aug 07 04:24:21 PM PDT 24 25428808 ps
T1285 /workspace/coverage/cover_reg_top/1.uart_csr_rw.2857567163 Aug 07 04:18:49 PM PDT 24 Aug 07 04:18:50 PM PDT 24 12834475 ps
T1286 /workspace/coverage/cover_reg_top/38.uart_intr_test.3106359490 Aug 07 04:22:26 PM PDT 24 Aug 07 04:22:27 PM PDT 24 28395542 ps
T1287 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1017439427 Aug 07 04:18:48 PM PDT 24 Aug 07 04:18:50 PM PDT 24 37357843 ps
T1288 /workspace/coverage/cover_reg_top/2.uart_intr_test.1053971338 Aug 07 04:18:46 PM PDT 24 Aug 07 04:18:47 PM PDT 24 53766758 ps
T1289 /workspace/coverage/cover_reg_top/5.uart_csr_rw.2074152004 Aug 07 04:19:51 PM PDT 24 Aug 07 04:19:52 PM PDT 24 65621876 ps
T1290 /workspace/coverage/cover_reg_top/19.uart_csr_rw.2957084422 Aug 07 04:25:00 PM PDT 24 Aug 07 04:25:00 PM PDT 24 150351625 ps
T1291 /workspace/coverage/cover_reg_top/39.uart_intr_test.4102325942 Aug 07 04:22:36 PM PDT 24 Aug 07 04:22:37 PM PDT 24 42624329 ps
T1292 /workspace/coverage/cover_reg_top/28.uart_intr_test.503960875 Aug 07 04:22:29 PM PDT 24 Aug 07 04:22:30 PM PDT 24 18220215 ps
T1293 /workspace/coverage/cover_reg_top/33.uart_intr_test.3792676589 Aug 07 04:21:07 PM PDT 24 Aug 07 04:21:07 PM PDT 24 12990430 ps
T1294 /workspace/coverage/cover_reg_top/48.uart_intr_test.3613404031 Aug 07 04:21:41 PM PDT 24 Aug 07 04:21:41 PM PDT 24 15964872 ps
T1295 /workspace/coverage/cover_reg_top/13.uart_csr_rw.1820128541 Aug 07 04:22:11 PM PDT 24 Aug 07 04:22:11 PM PDT 24 50914337 ps
T1296 /workspace/coverage/cover_reg_top/11.uart_tl_errors.4206779373 Aug 07 04:20:07 PM PDT 24 Aug 07 04:20:08 PM PDT 24 219893662 ps
T1297 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3930353768 Aug 07 04:18:36 PM PDT 24 Aug 07 04:18:38 PM PDT 24 97275378 ps
T80 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.912798830 Aug 07 04:19:53 PM PDT 24 Aug 07 04:19:54 PM PDT 24 144682007 ps
T1298 /workspace/coverage/cover_reg_top/21.uart_intr_test.2405054898 Aug 07 04:24:08 PM PDT 24 Aug 07 04:24:08 PM PDT 24 16896318 ps
T1299 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2840488808 Aug 07 04:18:49 PM PDT 24 Aug 07 04:18:51 PM PDT 24 109182296 ps
T1300 /workspace/coverage/cover_reg_top/11.uart_csr_rw.406838407 Aug 07 04:20:07 PM PDT 24 Aug 07 04:20:07 PM PDT 24 27341470 ps
T1301 /workspace/coverage/cover_reg_top/2.uart_tl_errors.3871435016 Aug 07 04:18:45 PM PDT 24 Aug 07 04:18:47 PM PDT 24 250813069 ps
T1302 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1305660456 Aug 07 04:18:47 PM PDT 24 Aug 07 04:18:48 PM PDT 24 178438563 ps
T1303 /workspace/coverage/cover_reg_top/14.uart_intr_test.2887568877 Aug 07 04:19:51 PM PDT 24 Aug 07 04:19:51 PM PDT 24 28339815 ps
T1304 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3295528117 Aug 07 04:20:07 PM PDT 24 Aug 07 04:20:08 PM PDT 24 55197648 ps
T1305 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1799685692 Aug 07 04:24:11 PM PDT 24 Aug 07 04:24:12 PM PDT 24 268443749 ps
T1306 /workspace/coverage/cover_reg_top/8.uart_csr_rw.1239000717 Aug 07 04:19:52 PM PDT 24 Aug 07 04:19:53 PM PDT 24 36782520 ps
T1307 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2071706689 Aug 07 04:18:36 PM PDT 24 Aug 07 04:18:37 PM PDT 24 16992558 ps
T1308 /workspace/coverage/cover_reg_top/8.uart_tl_errors.3685770939 Aug 07 04:18:50 PM PDT 24 Aug 07 04:18:52 PM PDT 24 38410633 ps
T1309 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1001527117 Aug 07 04:24:21 PM PDT 24 Aug 07 04:24:22 PM PDT 24 104974039 ps
T1310 /workspace/coverage/cover_reg_top/40.uart_intr_test.2743552822 Aug 07 04:22:37 PM PDT 24 Aug 07 04:22:37 PM PDT 24 41669988 ps
T1311 /workspace/coverage/cover_reg_top/3.uart_intr_test.1547332748 Aug 07 04:18:50 PM PDT 24 Aug 07 04:18:51 PM PDT 24 36939656 ps
T1312 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3887491850 Aug 07 04:19:50 PM PDT 24 Aug 07 04:19:52 PM PDT 24 68277800 ps
T1313 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.330946820 Aug 07 04:20:36 PM PDT 24 Aug 07 04:20:37 PM PDT 24 19810723 ps
T81 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.4004394807 Aug 07 04:18:45 PM PDT 24 Aug 07 04:18:46 PM PDT 24 170251533 ps
T1314 /workspace/coverage/cover_reg_top/32.uart_intr_test.2158646855 Aug 07 04:24:16 PM PDT 24 Aug 07 04:24:17 PM PDT 24 14925281 ps
T1315 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2454406380 Aug 07 04:20:06 PM PDT 24 Aug 07 04:20:07 PM PDT 24 46264783 ps

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.1232217287
Short name T7
Test name
Test status
Simulation time 116734989218 ps
CPU time 1124.26 seconds
Started Aug 07 05:55:43 PM PDT 24
Finished Aug 07 06:14:27 PM PDT 24
Peak memory 216548 kb
Host smart-830e1c4f-6c1c-4639-b071-27615612e00d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232217287 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1232217287
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3318252157
Short name T33
Test name
Test status
Simulation time 2097964203847 ps
CPU time 1517.04 seconds
Started Aug 07 05:55:58 PM PDT 24
Finished Aug 07 06:21:15 PM PDT 24
Peak memory 230196 kb
Host smart-ad3c4a03-e236-4968-9c94-8d81edbb298f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318252157 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3318252157
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.4294834976
Short name T20
Test name
Test status
Simulation time 90628690051 ps
CPU time 350.23 seconds
Started Aug 07 05:55:59 PM PDT 24
Finished Aug 07 06:01:49 PM PDT 24
Peak memory 216612 kb
Host smart-9c414dbe-21c6-4a52-b506-b0fd923a53e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294834976 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.4294834976
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_perf.2978601533
Short name T10
Test name
Test status
Simulation time 22544131475 ps
CPU time 399.51 seconds
Started Aug 07 05:53:19 PM PDT 24
Finished Aug 07 05:59:59 PM PDT 24
Peak memory 199880 kb
Host smart-dbf8c7bb-5a5a-4a69-a8a2-72cfcba3f6b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2978601533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2978601533
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/21.uart_stress_all.896974528
Short name T14
Test name
Test status
Simulation time 486923353998 ps
CPU time 1780.9 seconds
Started Aug 07 05:52:28 PM PDT 24
Finished Aug 07 06:22:09 PM PDT 24
Peak memory 208260 kb
Host smart-6be3b696-796f-4bef-ab0f-89287b6460b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896974528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.896974528
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all.3353379543
Short name T129
Test name
Test status
Simulation time 496644676803 ps
CPU time 581.16 seconds
Started Aug 07 05:54:23 PM PDT 24
Finished Aug 07 06:04:04 PM PDT 24
Peak memory 208216 kb
Host smart-b944a7d3-c76b-4b9b-8440-37cec39e3be2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353379543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3353379543
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.757783612
Short name T148
Test name
Test status
Simulation time 421502183695 ps
CPU time 1445.28 seconds
Started Aug 07 05:55:26 PM PDT 24
Finished Aug 07 06:19:31 PM PDT 24
Peak memory 228364 kb
Host smart-badefea3-d7b7-405a-88c3-dc5c92fffadc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757783612 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.757783612
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.410514073
Short name T88
Test name
Test status
Simulation time 126606661 ps
CPU time 0.76 seconds
Started Aug 07 05:51:02 PM PDT 24
Finished Aug 07 05:51:03 PM PDT 24
Peak memory 218220 kb
Host smart-46a5ea22-dc01-4487-86e6-54feb7c20e13
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410514073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.410514073
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_alert_test.3106307831
Short name T86
Test name
Test status
Simulation time 49251996 ps
CPU time 0.65 seconds
Started Aug 07 05:51:04 PM PDT 24
Finished Aug 07 05:51:05 PM PDT 24
Peak memory 195308 kb
Host smart-2b2f545b-b5f8-4d61-a804-a640569b60d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106307831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3106307831
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_stress_all.2560975682
Short name T11
Test name
Test status
Simulation time 647112854573 ps
CPU time 322.28 seconds
Started Aug 07 05:51:46 PM PDT 24
Finished Aug 07 05:57:09 PM PDT 24
Peak memory 199864 kb
Host smart-40835b08-31c2-4f59-94da-c70b95879991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560975682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2560975682
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2499148939
Short name T46
Test name
Test status
Simulation time 104906834580 ps
CPU time 598.84 seconds
Started Aug 07 05:54:59 PM PDT 24
Finished Aug 07 06:04:58 PM PDT 24
Peak memory 199924 kb
Host smart-d2a26683-469f-480a-869d-1183e6772b57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2499148939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2499148939
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3130995254
Short name T47
Test name
Test status
Simulation time 1226957125558 ps
CPU time 733.5 seconds
Started Aug 07 05:51:03 PM PDT 24
Finished Aug 07 06:03:17 PM PDT 24
Peak memory 224592 kb
Host smart-a68cef59-d579-477e-bf9e-20b8cd5f890f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130995254 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3130995254
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_stress_all.3001819000
Short name T112
Test name
Test status
Simulation time 669150213236 ps
CPU time 384.43 seconds
Started Aug 07 05:53:04 PM PDT 24
Finished Aug 07 05:59:28 PM PDT 24
Peak memory 208180 kb
Host smart-1d11c13b-22dd-4f51-83de-79f37d4dd0da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001819000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3001819000
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2284730459
Short name T36
Test name
Test status
Simulation time 93387295123 ps
CPU time 248.66 seconds
Started Aug 07 05:51:51 PM PDT 24
Finished Aug 07 05:56:00 PM PDT 24
Peak memory 208256 kb
Host smart-7c9ff6f7-159d-483f-b203-d8c29e66b051
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284730459 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2284730459
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_full.4231301842
Short name T143
Test name
Test status
Simulation time 134182062069 ps
CPU time 50.05 seconds
Started Aug 07 05:51:32 PM PDT 24
Finished Aug 07 05:52:22 PM PDT 24
Peak memory 199872 kb
Host smart-e50ecb0f-8769-40e7-8c5f-6e8013eeddfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231301842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.4231301842
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3595740957
Short name T84
Test name
Test status
Simulation time 89926646 ps
CPU time 0.98 seconds
Started Aug 07 04:24:22 PM PDT 24
Finished Aug 07 04:24:24 PM PDT 24
Peak memory 198472 kb
Host smart-d36caaf9-22e2-4ef7-8574-c768fce00f7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595740957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3595740957
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.881341658
Short name T220
Test name
Test status
Simulation time 172884781516 ps
CPU time 141.18 seconds
Started Aug 07 05:57:45 PM PDT 24
Finished Aug 07 06:00:07 PM PDT 24
Peak memory 199836 kb
Host smart-742db0da-9406-4bec-921d-1a9e3d57d1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881341658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.881341658
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1516688253
Short name T153
Test name
Test status
Simulation time 558980633129 ps
CPU time 671.98 seconds
Started Aug 07 05:54:04 PM PDT 24
Finished Aug 07 06:05:16 PM PDT 24
Peak memory 216304 kb
Host smart-29be0f4a-0818-41ae-b68f-405922010329
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516688253 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1516688253
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3245735397
Short name T108
Test name
Test status
Simulation time 123217807989 ps
CPU time 105.96 seconds
Started Aug 07 05:53:14 PM PDT 24
Finished Aug 07 05:55:00 PM PDT 24
Peak memory 199884 kb
Host smart-811cd9d1-52d5-45f1-a984-81c97d425b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245735397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3245735397
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2020677939
Short name T150
Test name
Test status
Simulation time 252975057449 ps
CPU time 1803.76 seconds
Started Aug 07 05:55:57 PM PDT 24
Finished Aug 07 06:26:01 PM PDT 24
Peak memory 228204 kb
Host smart-d409458c-ab06-4d83-a189-70a560bd42c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020677939 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2020677939
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2354921251
Short name T140
Test name
Test status
Simulation time 97914430467 ps
CPU time 47.61 seconds
Started Aug 07 05:56:02 PM PDT 24
Finished Aug 07 05:56:50 PM PDT 24
Peak memory 199972 kb
Host smart-170e6b0a-b839-40e4-bba8-65bfbd61ad68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354921251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2354921251
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3405010170
Short name T56
Test name
Test status
Simulation time 22390852 ps
CPU time 0.76 seconds
Started Aug 07 04:18:50 PM PDT 24
Finished Aug 07 04:18:51 PM PDT 24
Peak memory 194408 kb
Host smart-f2c58752-6c18-41b2-a862-d8478bc1f444
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405010170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3405010170
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3614001313
Short name T65
Test name
Test status
Simulation time 18323244 ps
CPU time 0.6 seconds
Started Aug 07 04:20:06 PM PDT 24
Finished Aug 07 04:20:07 PM PDT 24
Peak memory 195692 kb
Host smart-b407f767-d67a-4c08-b1ca-5f00030cc2fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614001313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3614001313
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/default/33.uart_stress_all.3705117482
Short name T313
Test name
Test status
Simulation time 150684521453 ps
CPU time 185.21 seconds
Started Aug 07 05:53:35 PM PDT 24
Finished Aug 07 05:56:40 PM PDT 24
Peak memory 199928 kb
Host smart-7290a054-e8e7-484c-a5c7-45fb53590ef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705117482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3705117482
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3876026257
Short name T49
Test name
Test status
Simulation time 484266908873 ps
CPU time 1417.65 seconds
Started Aug 07 05:55:51 PM PDT 24
Finished Aug 07 06:19:29 PM PDT 24
Peak memory 232908 kb
Host smart-c83bc973-3fb3-408c-9586-5e18fb2d4b01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876026257 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3876026257
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.351095679
Short name T78
Test name
Test status
Simulation time 87295660 ps
CPU time 1.32 seconds
Started Aug 07 04:19:43 PM PDT 24
Finished Aug 07 04:19:44 PM PDT 24
Peak memory 199868 kb
Host smart-fd7b3c8c-ebf6-473c-a3ce-3f3ceadeeaa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351095679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.351095679
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3065310240
Short name T163
Test name
Test status
Simulation time 35023989433 ps
CPU time 40.01 seconds
Started Aug 07 05:57:28 PM PDT 24
Finished Aug 07 05:58:09 PM PDT 24
Peak memory 199844 kb
Host smart-0b96339a-836f-4132-8dcb-57ae7297b049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065310240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3065310240
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_tx_rx.323049024
Short name T287
Test name
Test status
Simulation time 54138566307 ps
CPU time 122.9 seconds
Started Aug 07 05:53:34 PM PDT 24
Finished Aug 07 05:55:37 PM PDT 24
Peak memory 199912 kb
Host smart-269f302a-8ae7-4508-b594-ce349a36bc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323049024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.323049024
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/8.uart_fifo_full.1127171634
Short name T172
Test name
Test status
Simulation time 298722359521 ps
CPU time 87.34 seconds
Started Aug 07 05:51:23 PM PDT 24
Finished Aug 07 05:52:50 PM PDT 24
Peak memory 199912 kb
Host smart-dc006e8e-0e9d-4f37-b562-1fca738131bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127171634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1127171634
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3625856230
Short name T151
Test name
Test status
Simulation time 273615613568 ps
CPU time 171.95 seconds
Started Aug 07 05:56:08 PM PDT 24
Finished Aug 07 05:59:00 PM PDT 24
Peak memory 199904 kb
Host smart-8e498c3a-7865-4460-b627-0f4dd7e1e2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625856230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3625856230
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3309313242
Short name T217
Test name
Test status
Simulation time 260573203140 ps
CPU time 192.3 seconds
Started Aug 07 05:52:07 PM PDT 24
Finished Aug 07 05:55:20 PM PDT 24
Peak memory 199852 kb
Host smart-b9642378-c423-4f2b-a633-44c3026d6b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309313242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3309313242
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1931311648
Short name T284
Test name
Test status
Simulation time 109408282623 ps
CPU time 302.29 seconds
Started Aug 07 05:52:09 PM PDT 24
Finished Aug 07 05:57:11 PM PDT 24
Peak memory 216528 kb
Host smart-e6aa3bd2-ec0c-4d7f-aa08-a548333c0cc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931311648 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1931311648
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1488039328
Short name T170
Test name
Test status
Simulation time 89212484027 ps
CPU time 71.6 seconds
Started Aug 07 05:56:52 PM PDT 24
Finished Aug 07 05:58:04 PM PDT 24
Peak memory 199896 kb
Host smart-4bfd8d22-3349-4ff8-8fb5-e91914a9ea7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488039328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1488039328
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.4004394807
Short name T81
Test name
Test status
Simulation time 170251533 ps
CPU time 0.98 seconds
Started Aug 07 04:18:45 PM PDT 24
Finished Aug 07 04:18:46 PM PDT 24
Peak memory 199196 kb
Host smart-4966ff93-b86e-4454-91aa-79c8848e33ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004394807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.4004394807
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3424853480
Short name T156
Test name
Test status
Simulation time 28507141656 ps
CPU time 17.98 seconds
Started Aug 07 05:56:14 PM PDT 24
Finished Aug 07 05:56:32 PM PDT 24
Peak memory 199892 kb
Host smart-02af0945-f7dc-40c0-b4c1-df2210d5c920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424853480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3424853480
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_perf.4265748439
Short name T43
Test name
Test status
Simulation time 17610342052 ps
CPU time 137.24 seconds
Started Aug 07 05:51:26 PM PDT 24
Finished Aug 07 05:53:43 PM PDT 24
Peak memory 199944 kb
Host smart-3137fd2d-b808-48bb-9363-0a32cbd352b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4265748439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.4265748439
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1850193216
Short name T317
Test name
Test status
Simulation time 29915844341 ps
CPU time 24.58 seconds
Started Aug 07 05:56:53 PM PDT 24
Finished Aug 07 05:57:17 PM PDT 24
Peak memory 199856 kb
Host smart-d57c59f7-c5f2-4400-b617-cec99d534c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850193216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1850193216
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2007148742
Short name T224
Test name
Test status
Simulation time 26054899034 ps
CPU time 32.23 seconds
Started Aug 07 05:57:27 PM PDT 24
Finished Aug 07 05:57:59 PM PDT 24
Peak memory 199920 kb
Host smart-b1c6b508-5185-44b4-968f-262600257f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007148742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2007148742
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1728633124
Short name T4
Test name
Test status
Simulation time 246929858162 ps
CPU time 21.3 seconds
Started Aug 07 05:52:55 PM PDT 24
Finished Aug 07 05:53:16 PM PDT 24
Peak memory 199872 kb
Host smart-a51efac6-eb70-45f9-a0b2-08d00e261f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728633124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1728633124
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1055429081
Short name T183
Test name
Test status
Simulation time 34654987101 ps
CPU time 58.82 seconds
Started Aug 07 05:57:52 PM PDT 24
Finished Aug 07 05:58:51 PM PDT 24
Peak memory 199884 kb
Host smart-ac34a7d3-c096-42da-b970-b4fd97caa807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055429081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1055429081
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1313024953
Short name T123
Test name
Test status
Simulation time 138652040732 ps
CPU time 48.87 seconds
Started Aug 07 05:57:41 PM PDT 24
Finished Aug 07 05:58:30 PM PDT 24
Peak memory 199924 kb
Host smart-f4103a3c-ab34-4d4e-8005-090b60e7fe90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313024953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1313024953
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2554708832
Short name T257
Test name
Test status
Simulation time 104876861378 ps
CPU time 83.45 seconds
Started Aug 07 05:51:25 PM PDT 24
Finished Aug 07 05:52:49 PM PDT 24
Peak memory 199892 kb
Host smart-0faedb78-06aa-417e-865b-442cec6105aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554708832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2554708832
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1780863946
Short name T142
Test name
Test status
Simulation time 93631511975 ps
CPU time 145.28 seconds
Started Aug 07 05:56:07 PM PDT 24
Finished Aug 07 05:58:32 PM PDT 24
Peak memory 199816 kb
Host smart-a62055b4-6143-493c-8f16-01e71c6e98b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780863946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1780863946
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3614026816
Short name T211
Test name
Test status
Simulation time 224239945725 ps
CPU time 108.23 seconds
Started Aug 07 05:56:12 PM PDT 24
Finished Aug 07 05:58:00 PM PDT 24
Peak memory 199940 kb
Host smart-8af935bb-196b-44c8-85bf-0077608606eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614026816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3614026816
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.2683390253
Short name T461
Test name
Test status
Simulation time 32587269402 ps
CPU time 15.97 seconds
Started Aug 07 05:56:10 PM PDT 24
Finished Aug 07 05:56:26 PM PDT 24
Peak memory 199876 kb
Host smart-efe19af0-da70-464b-8a78-2acfb10ced10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683390253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2683390253
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.822531332
Short name T210
Test name
Test status
Simulation time 116354637097 ps
CPU time 31.86 seconds
Started Aug 07 05:56:14 PM PDT 24
Finished Aug 07 05:56:46 PM PDT 24
Peak memory 199856 kb
Host smart-a5b3eb85-5353-4d58-b7c0-fa709d629df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822531332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.822531332
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1735422122
Short name T133
Test name
Test status
Simulation time 72586091473 ps
CPU time 108.01 seconds
Started Aug 07 05:56:15 PM PDT 24
Finished Aug 07 05:58:03 PM PDT 24
Peak memory 199872 kb
Host smart-b9b8e72a-1dce-41b4-82ee-1e65c8a1513b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735422122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1735422122
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1878311189
Short name T195
Test name
Test status
Simulation time 24450761560 ps
CPU time 17.13 seconds
Started Aug 07 05:56:24 PM PDT 24
Finished Aug 07 05:56:42 PM PDT 24
Peak memory 199884 kb
Host smart-19bb9344-613f-464a-8ef8-62fdd851db53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878311189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1878311189
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3141775137
Short name T881
Test name
Test status
Simulation time 20405740971 ps
CPU time 34.42 seconds
Started Aug 07 05:51:47 PM PDT 24
Finished Aug 07 05:52:21 PM PDT 24
Peak memory 199800 kb
Host smart-ff985c2a-6508-46c7-aa86-e3b720733427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141775137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3141775137
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2550327364
Short name T147
Test name
Test status
Simulation time 25345340509 ps
CPU time 10.96 seconds
Started Aug 07 05:56:33 PM PDT 24
Finished Aug 07 05:56:44 PM PDT 24
Peak memory 199796 kb
Host smart-d4c6a334-5861-4490-9688-354ef11928c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550327364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2550327364
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3265104021
Short name T238
Test name
Test status
Simulation time 322540024529 ps
CPU time 193.64 seconds
Started Aug 07 05:57:30 PM PDT 24
Finished Aug 07 06:00:44 PM PDT 24
Peak memory 199944 kb
Host smart-4192a0a8-86a0-4251-afce-9bce4162d077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265104021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3265104021
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3650606143
Short name T503
Test name
Test status
Simulation time 107093748986 ps
CPU time 203.36 seconds
Started Aug 07 05:51:02 PM PDT 24
Finished Aug 07 05:54:26 PM PDT 24
Peak memory 199872 kb
Host smart-d617ca37-b452-445d-bacc-035163a890a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650606143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3650606143
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_stress_all.753518012
Short name T568
Test name
Test status
Simulation time 172420469169 ps
CPU time 303.23 seconds
Started Aug 07 05:51:11 PM PDT 24
Finished Aug 07 05:56:14 PM PDT 24
Peak memory 199896 kb
Host smart-35bbd1e8-9866-4de4-90fc-c6893e96306a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753518012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.753518012
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2154657249
Short name T175
Test name
Test status
Simulation time 156848011988 ps
CPU time 40.78 seconds
Started Aug 07 05:51:27 PM PDT 24
Finished Aug 07 05:52:08 PM PDT 24
Peak memory 199936 kb
Host smart-d4424756-7055-4a56-9ed4-8d8581cc92a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154657249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2154657249
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3728509912
Short name T464
Test name
Test status
Simulation time 9229485083 ps
CPU time 12.34 seconds
Started Aug 07 05:51:35 PM PDT 24
Finished Aug 07 05:51:47 PM PDT 24
Peak memory 200156 kb
Host smart-b8a7fbc3-fcff-465c-8e62-7d9d09993802
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728509912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3728509912
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1666776076
Short name T234
Test name
Test status
Simulation time 140264355542 ps
CPU time 85.57 seconds
Started Aug 07 05:56:07 PM PDT 24
Finished Aug 07 05:57:33 PM PDT 24
Peak memory 199636 kb
Host smart-9694101e-6436-48d3-91f4-2bfccbf1d269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666776076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1666776076
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1933213179
Short name T198
Test name
Test status
Simulation time 174301706966 ps
CPU time 15.81 seconds
Started Aug 07 05:56:14 PM PDT 24
Finished Aug 07 05:56:30 PM PDT 24
Peak memory 199864 kb
Host smart-77824478-1c26-43b5-b138-ffe9d7eaeccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933213179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1933213179
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2690041577
Short name T321
Test name
Test status
Simulation time 111751576514 ps
CPU time 151.65 seconds
Started Aug 07 05:56:19 PM PDT 24
Finished Aug 07 05:58:51 PM PDT 24
Peak memory 199872 kb
Host smart-b5594515-f3ea-4dc0-bd47-1864c5701309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690041577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2690041577
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.575977901
Short name T239
Test name
Test status
Simulation time 120632178559 ps
CPU time 60.44 seconds
Started Aug 07 05:56:20 PM PDT 24
Finished Aug 07 05:57:20 PM PDT 24
Peak memory 199900 kb
Host smart-8e1e35fa-8ed1-42be-8e2f-eae218046cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575977901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.575977901
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.3347569080
Short name T8
Test name
Test status
Simulation time 43731258491 ps
CPU time 17.6 seconds
Started Aug 07 05:56:34 PM PDT 24
Finished Aug 07 05:56:51 PM PDT 24
Peak memory 197996 kb
Host smart-46b87c0e-b31f-43b4-aaa8-a22a71386a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347569080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3347569080
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1134310399
Short name T137
Test name
Test status
Simulation time 39476031557 ps
CPU time 56.71 seconds
Started Aug 07 05:51:53 PM PDT 24
Finished Aug 07 05:52:50 PM PDT 24
Peak memory 199692 kb
Host smart-1aa377f0-7425-4112-94e0-d05597bc88be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134310399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1134310399
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.815854021
Short name T853
Test name
Test status
Simulation time 511525796026 ps
CPU time 989.69 seconds
Started Aug 07 05:51:58 PM PDT 24
Finished Aug 07 06:08:28 PM PDT 24
Peak memory 227248 kb
Host smart-9c0c94d1-919d-46d5-b0f6-121cc20c93fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815854021 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.815854021
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.375694057
Short name T242
Test name
Test status
Simulation time 88813290828 ps
CPU time 13.54 seconds
Started Aug 07 05:56:47 PM PDT 24
Finished Aug 07 05:57:01 PM PDT 24
Peak memory 199952 kb
Host smart-d42357d3-cedf-4a53-b85b-de3ecd92cc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375694057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.375694057
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.1225668700
Short name T93
Test name
Test status
Simulation time 19296461832 ps
CPU time 30.65 seconds
Started Aug 07 05:56:45 PM PDT 24
Finished Aug 07 05:57:16 PM PDT 24
Peak memory 199872 kb
Host smart-3aa3d7e0-ec98-4b89-b4a4-dde190fdbc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225668700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1225668700
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1281180750
Short name T213
Test name
Test status
Simulation time 27992143392 ps
CPU time 20.26 seconds
Started Aug 07 05:56:52 PM PDT 24
Finished Aug 07 05:57:12 PM PDT 24
Peak memory 199824 kb
Host smart-eff6317d-6087-4568-9e60-bd41bae403ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281180750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1281180750
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3250802858
Short name T73
Test name
Test status
Simulation time 92922285746 ps
CPU time 22.47 seconds
Started Aug 07 05:56:53 PM PDT 24
Finished Aug 07 05:57:16 PM PDT 24
Peak memory 199864 kb
Host smart-98cb505b-45b9-4208-9d76-e37778e8d0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250802858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3250802858
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.589643035
Short name T978
Test name
Test status
Simulation time 91991743426 ps
CPU time 154.9 seconds
Started Aug 07 05:56:58 PM PDT 24
Finished Aug 07 05:59:33 PM PDT 24
Peak memory 199752 kb
Host smart-a7eb3cc6-8a27-4a6c-b25f-889294a01aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589643035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.589643035
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2694821854
Short name T241
Test name
Test status
Simulation time 47488996104 ps
CPU time 19.25 seconds
Started Aug 07 05:52:23 PM PDT 24
Finished Aug 07 05:52:43 PM PDT 24
Peak memory 199824 kb
Host smart-1e037f92-fc9e-4300-9223-1b783bf4a557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694821854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2694821854
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.4115600545
Short name T162
Test name
Test status
Simulation time 45681037608 ps
CPU time 39.25 seconds
Started Aug 07 05:57:17 PM PDT 24
Finished Aug 07 05:57:57 PM PDT 24
Peak memory 200152 kb
Host smart-a9c9ad92-fea3-4dc7-9385-deaab72cd06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115600545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.4115600545
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.854854849
Short name T236
Test name
Test status
Simulation time 193957293806 ps
CPU time 254.5 seconds
Started Aug 07 05:57:42 PM PDT 24
Finished Aug 07 06:01:57 PM PDT 24
Peak memory 199816 kb
Host smart-5228c6bd-b6a5-4d9c-9c22-4cfd57641002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854854849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.854854849
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1819120741
Short name T229
Test name
Test status
Simulation time 30889762893 ps
CPU time 55.46 seconds
Started Aug 07 05:57:44 PM PDT 24
Finished Aug 07 05:58:40 PM PDT 24
Peak memory 199904 kb
Host smart-55fdf2e6-f7f9-4add-a59b-f7eceeca48d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819120741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1819120741
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.202905010
Short name T240
Test name
Test status
Simulation time 38571916773 ps
CPU time 17.2 seconds
Started Aug 07 05:54:20 PM PDT 24
Finished Aug 07 05:54:38 PM PDT 24
Peak memory 199824 kb
Host smart-fe432849-fecb-490e-bc99-c3b772a140ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202905010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.202905010
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2413597366
Short name T223
Test name
Test status
Simulation time 46525062128 ps
CPU time 39.67 seconds
Started Aug 07 05:54:45 PM PDT 24
Finished Aug 07 05:55:25 PM PDT 24
Peak memory 199920 kb
Host smart-861609a3-e22d-46e6-bffb-b075037507b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413597366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2413597366
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2064671858
Short name T126
Test name
Test status
Simulation time 141403004114 ps
CPU time 58.42 seconds
Started Aug 07 05:55:31 PM PDT 24
Finished Aug 07 05:56:29 PM PDT 24
Peak memory 199824 kb
Host smart-76a625be-a505-4535-b57b-8919d62b25a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064671858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2064671858
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3458706889
Short name T134
Test name
Test status
Simulation time 122464492444 ps
CPU time 146.94 seconds
Started Aug 07 05:55:57 PM PDT 24
Finished Aug 07 05:58:24 PM PDT 24
Peak memory 199840 kb
Host smart-9fdc1c90-70fd-46ee-a9f1-95129504131b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458706889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3458706889
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1017439427
Short name T1287
Test name
Test status
Simulation time 37357843 ps
CPU time 1.36 seconds
Started Aug 07 04:18:48 PM PDT 24
Finished Aug 07 04:18:50 PM PDT 24
Peak memory 197584 kb
Host smart-11555a26-a36d-42a2-be84-f624989df5f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017439427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1017439427
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1280498919
Short name T1255
Test name
Test status
Simulation time 12923089 ps
CPU time 0.59 seconds
Started Aug 07 04:18:45 PM PDT 24
Finished Aug 07 04:18:46 PM PDT 24
Peak memory 195340 kb
Host smart-2c795902-6a05-4a6b-b801-2bbfbf9faa5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280498919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1280498919
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3459676519
Short name T1263
Test name
Test status
Simulation time 116760036 ps
CPU time 0.72 seconds
Started Aug 07 04:19:30 PM PDT 24
Finished Aug 07 04:19:31 PM PDT 24
Peak memory 199088 kb
Host smart-392801a3-9bf4-4504-bd67-4a4fdc6972f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459676519 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3459676519
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3772471969
Short name T1254
Test name
Test status
Simulation time 50811425 ps
CPU time 0.67 seconds
Started Aug 07 04:18:50 PM PDT 24
Finished Aug 07 04:18:51 PM PDT 24
Peak memory 194728 kb
Host smart-f4b3f186-1c0f-48d9-bee4-08e9245142d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772471969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3772471969
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3819589542
Short name T1222
Test name
Test status
Simulation time 43958714 ps
CPU time 0.61 seconds
Started Aug 07 04:18:47 PM PDT 24
Finished Aug 07 04:18:48 PM PDT 24
Peak memory 193660 kb
Host smart-b9a46231-2800-4be1-b799-4cb700b9a3ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819589542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3819589542
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.826960236
Short name T1226
Test name
Test status
Simulation time 91070365 ps
CPU time 0.66 seconds
Started Aug 07 04:18:46 PM PDT 24
Finished Aug 07 04:18:47 PM PDT 24
Peak memory 196752 kb
Host smart-6287a837-50ae-49a4-a1c7-501fdf743016
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826960236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.826960236
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2209333660
Short name T1180
Test name
Test status
Simulation time 395704145 ps
CPU time 2.18 seconds
Started Aug 07 04:18:37 PM PDT 24
Finished Aug 07 04:18:39 PM PDT 24
Peak memory 200048 kb
Host smart-535ce32b-4866-4fb2-bcf7-8f327b3cc15f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209333660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2209333660
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2432749498
Short name T1217
Test name
Test status
Simulation time 18427486 ps
CPU time 0.79 seconds
Started Aug 07 04:18:37 PM PDT 24
Finished Aug 07 04:18:38 PM PDT 24
Peak memory 196448 kb
Host smart-45698458-7250-409f-a935-d3bfa37d53a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432749498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2432749498
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2169831845
Short name T1266
Test name
Test status
Simulation time 97556699 ps
CPU time 1.42 seconds
Started Aug 07 04:18:56 PM PDT 24
Finished Aug 07 04:18:58 PM PDT 24
Peak memory 197572 kb
Host smart-ff287380-ccee-404e-a090-83b96b4be4ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169831845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2169831845
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3930353768
Short name T1297
Test name
Test status
Simulation time 97275378 ps
CPU time 0.83 seconds
Started Aug 07 04:18:36 PM PDT 24
Finished Aug 07 04:18:38 PM PDT 24
Peak memory 198384 kb
Host smart-05293ba1-6f87-439a-8d60-a9b112171153
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930353768 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3930353768
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2857567163
Short name T1285
Test name
Test status
Simulation time 12834475 ps
CPU time 0.56 seconds
Started Aug 07 04:18:49 PM PDT 24
Finished Aug 07 04:18:50 PM PDT 24
Peak memory 195564 kb
Host smart-e6d3458e-c629-45eb-bf83-e477c7252bbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857567163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2857567163
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3897567748
Short name T1278
Test name
Test status
Simulation time 61771243 ps
CPU time 0.58 seconds
Started Aug 07 04:18:46 PM PDT 24
Finished Aug 07 04:18:47 PM PDT 24
Peak memory 193384 kb
Host smart-261756e4-0ed6-4ad2-9c64-e999171d30ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897567748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3897567748
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.982099996
Short name T1225
Test name
Test status
Simulation time 81003278 ps
CPU time 0.78 seconds
Started Aug 07 04:18:50 PM PDT 24
Finished Aug 07 04:18:51 PM PDT 24
Peak memory 196476 kb
Host smart-bf4215bc-99de-40da-8b4a-b65de2cf3439
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982099996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_
outstanding.982099996
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.754836526
Short name T1246
Test name
Test status
Simulation time 127171997 ps
CPU time 1.34 seconds
Started Aug 07 04:18:45 PM PDT 24
Finished Aug 07 04:18:47 PM PDT 24
Peak memory 199224 kb
Host smart-902e0919-b499-411a-9157-a288cd6b5351
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754836526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.754836526
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1305660456
Short name T1302
Test name
Test status
Simulation time 178438563 ps
CPU time 1.27 seconds
Started Aug 07 04:18:47 PM PDT 24
Finished Aug 07 04:18:48 PM PDT 24
Peak memory 198712 kb
Host smart-3261156a-3aac-43af-8f23-287851f087b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305660456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1305660456
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2443163744
Short name T1207
Test name
Test status
Simulation time 54783212 ps
CPU time 0.87 seconds
Started Aug 07 04:20:28 PM PDT 24
Finished Aug 07 04:20:29 PM PDT 24
Peak memory 200056 kb
Host smart-b505ca1a-ad1d-4f9f-9d84-76b993996381
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443163744 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2443163744
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.763164662
Short name T1219
Test name
Test status
Simulation time 14216786 ps
CPU time 0.55 seconds
Started Aug 07 04:19:52 PM PDT 24
Finished Aug 07 04:19:53 PM PDT 24
Peak memory 194264 kb
Host smart-dc1e3043-f0de-46d5-bcf2-2bf8692951ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763164662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.763164662
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.4082680078
Short name T66
Test name
Test status
Simulation time 68611281 ps
CPU time 0.64 seconds
Started Aug 07 04:24:01 PM PDT 24
Finished Aug 07 04:24:02 PM PDT 24
Peak memory 194912 kb
Host smart-2d337228-cfcf-4890-b2e8-5c7cf2b565b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082680078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.4082680078
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.126440970
Short name T1179
Test name
Test status
Simulation time 38069371 ps
CPU time 0.91 seconds
Started Aug 07 04:19:53 PM PDT 24
Finished Aug 07 04:19:54 PM PDT 24
Peak memory 199772 kb
Host smart-f6733d98-05b7-4d0f-82dc-131e19ec39cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126440970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.126440970
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2027658545
Short name T83
Test name
Test status
Simulation time 100054480 ps
CPU time 0.98 seconds
Started Aug 07 04:19:50 PM PDT 24
Finished Aug 07 04:19:52 PM PDT 24
Peak memory 197732 kb
Host smart-ca6e21a2-6e0d-42a7-a2dd-eeda3047b2fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027658545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2027658545
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.639066184
Short name T1234
Test name
Test status
Simulation time 18868403 ps
CPU time 0.79 seconds
Started Aug 07 04:20:06 PM PDT 24
Finished Aug 07 04:20:07 PM PDT 24
Peak memory 200040 kb
Host smart-f1ee2d6a-713a-4bfc-aa55-daedbb7ad788
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639066184 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.639066184
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.406838407
Short name T1300
Test name
Test status
Simulation time 27341470 ps
CPU time 0.62 seconds
Started Aug 07 04:20:07 PM PDT 24
Finished Aug 07 04:20:07 PM PDT 24
Peak memory 195692 kb
Host smart-11bc83e4-7aa3-44c7-8f12-f3ece635dcc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406838407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.406838407
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2281521095
Short name T1203
Test name
Test status
Simulation time 12904708 ps
CPU time 0.59 seconds
Started Aug 07 04:20:07 PM PDT 24
Finished Aug 07 04:20:08 PM PDT 24
Peak memory 194620 kb
Host smart-d99f41ec-a99e-4713-8f27-a53e241d6b69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281521095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2281521095
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3887491850
Short name T1312
Test name
Test status
Simulation time 68277800 ps
CPU time 0.72 seconds
Started Aug 07 04:19:50 PM PDT 24
Finished Aug 07 04:19:52 PM PDT 24
Peak memory 195580 kb
Host smart-c5f5a552-e6ba-4923-8453-27cc31b3efaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887491850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3887491850
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.4206779373
Short name T1296
Test name
Test status
Simulation time 219893662 ps
CPU time 1.23 seconds
Started Aug 07 04:20:07 PM PDT 24
Finished Aug 07 04:20:08 PM PDT 24
Peak memory 200288 kb
Host smart-6abd0202-a36b-4714-8de6-5cdf11f965b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206779373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.4206779373
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3295528117
Short name T1304
Test name
Test status
Simulation time 55197648 ps
CPU time 0.99 seconds
Started Aug 07 04:20:07 PM PDT 24
Finished Aug 07 04:20:08 PM PDT 24
Peak memory 199400 kb
Host smart-86df8aa5-bc23-49fb-9f81-dcc1bfd82f9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295528117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3295528117
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3167947581
Short name T1242
Test name
Test status
Simulation time 73076780 ps
CPU time 0.91 seconds
Started Aug 07 04:19:43 PM PDT 24
Finished Aug 07 04:19:44 PM PDT 24
Peak memory 200416 kb
Host smart-3e9480f3-8f60-49a9-9fd5-2e20debe4868
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167947581 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3167947581
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2287968614
Short name T1275
Test name
Test status
Simulation time 45331172 ps
CPU time 0.57 seconds
Started Aug 07 04:20:05 PM PDT 24
Finished Aug 07 04:20:06 PM PDT 24
Peak memory 195620 kb
Host smart-7de6aebb-b955-401e-991c-09e587b61170
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287968614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2287968614
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1821435283
Short name T1273
Test name
Test status
Simulation time 14622700 ps
CPU time 0.57 seconds
Started Aug 07 04:20:06 PM PDT 24
Finished Aug 07 04:20:07 PM PDT 24
Peak memory 194612 kb
Host smart-5096f8d0-f5e9-42df-a6fb-3908ba9fbf4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821435283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1821435283
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2120442406
Short name T1247
Test name
Test status
Simulation time 32700788 ps
CPU time 0.75 seconds
Started Aug 07 04:18:56 PM PDT 24
Finished Aug 07 04:18:57 PM PDT 24
Peak memory 196644 kb
Host smart-c3a76149-6853-42a3-9d81-3821830aee0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120442406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2120442406
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2472104579
Short name T1262
Test name
Test status
Simulation time 118138011 ps
CPU time 2.06 seconds
Started Aug 07 04:18:58 PM PDT 24
Finished Aug 07 04:19:00 PM PDT 24
Peak memory 200296 kb
Host smart-d6e62952-046c-4b7a-b541-4d6e0cfb1b80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472104579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2472104579
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.4263218849
Short name T79
Test name
Test status
Simulation time 323798646 ps
CPU time 1.31 seconds
Started Aug 07 04:20:29 PM PDT 24
Finished Aug 07 04:20:30 PM PDT 24
Peak memory 199472 kb
Host smart-80955fb5-0a6a-40da-a0bd-04ea9be558b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263218849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.4263218849
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1799685692
Short name T1305
Test name
Test status
Simulation time 268443749 ps
CPU time 0.85 seconds
Started Aug 07 04:24:11 PM PDT 24
Finished Aug 07 04:24:12 PM PDT 24
Peak memory 199500 kb
Host smart-dbcdc58e-9107-494d-96d1-b1c0d8007a61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799685692 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1799685692
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1820128541
Short name T1295
Test name
Test status
Simulation time 50914337 ps
CPU time 0.61 seconds
Started Aug 07 04:22:11 PM PDT 24
Finished Aug 07 04:22:11 PM PDT 24
Peak memory 195712 kb
Host smart-6a613379-295e-46fb-bf35-7ec574863ad4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820128541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1820128541
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3445730515
Short name T1240
Test name
Test status
Simulation time 35803120 ps
CPU time 0.6 seconds
Started Aug 07 04:20:43 PM PDT 24
Finished Aug 07 04:20:44 PM PDT 24
Peak memory 194616 kb
Host smart-1fd3d057-ebb4-42ff-bab7-0efe301a1b61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445730515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3445730515
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3829633846
Short name T1249
Test name
Test status
Simulation time 35245869 ps
CPU time 0.61 seconds
Started Aug 07 04:24:39 PM PDT 24
Finished Aug 07 04:24:40 PM PDT 24
Peak memory 195576 kb
Host smart-dfdd98fa-b202-4083-b1fd-2cf9d4224a26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829633846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3829633846
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.909501612
Short name T1197
Test name
Test status
Simulation time 520409582 ps
CPU time 1.93 seconds
Started Aug 07 04:24:55 PM PDT 24
Finished Aug 07 04:24:57 PM PDT 24
Peak memory 199924 kb
Host smart-141fa3dc-e2d2-411f-9f14-b36c0ef9a9fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909501612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.909501612
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3508806645
Short name T1191
Test name
Test status
Simulation time 124912203 ps
CPU time 0.84 seconds
Started Aug 07 04:24:46 PM PDT 24
Finished Aug 07 04:24:47 PM PDT 24
Peak memory 198716 kb
Host smart-b846d752-3825-4b9a-a956-2179aed73816
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508806645 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3508806645
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2609737710
Short name T1251
Test name
Test status
Simulation time 41871556 ps
CPU time 0.6 seconds
Started Aug 07 04:20:36 PM PDT 24
Finished Aug 07 04:20:37 PM PDT 24
Peak memory 195596 kb
Host smart-be40aac9-3f90-42ec-ab0b-f01fd7bb089b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609737710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2609737710
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2887568877
Short name T1303
Test name
Test status
Simulation time 28339815 ps
CPU time 0.57 seconds
Started Aug 07 04:19:51 PM PDT 24
Finished Aug 07 04:19:51 PM PDT 24
Peak memory 194632 kb
Host smart-a951e7f5-aaad-401c-9d6f-f038db78cc65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887568877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2887568877
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3646193430
Short name T1200
Test name
Test status
Simulation time 16084756 ps
CPU time 0.7 seconds
Started Aug 07 04:24:42 PM PDT 24
Finished Aug 07 04:24:43 PM PDT 24
Peak memory 196252 kb
Host smart-98307473-8bd3-4ba6-8a2d-3801c39d32dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646193430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3646193430
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.985792415
Short name T1198
Test name
Test status
Simulation time 86329152 ps
CPU time 2.18 seconds
Started Aug 07 04:20:20 PM PDT 24
Finished Aug 07 04:20:22 PM PDT 24
Peak memory 200288 kb
Host smart-9657d036-f0a5-4586-8b7b-5a4bd8682161
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985792415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.985792415
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2415008411
Short name T113
Test name
Test status
Simulation time 176029462 ps
CPU time 0.95 seconds
Started Aug 07 04:24:10 PM PDT 24
Finished Aug 07 04:24:12 PM PDT 24
Peak memory 198352 kb
Host smart-45e69245-8c5f-4fdc-9c21-ea3257d3a30c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415008411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2415008411
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3992939730
Short name T1196
Test name
Test status
Simulation time 107126646 ps
CPU time 0.83 seconds
Started Aug 07 04:23:34 PM PDT 24
Finished Aug 07 04:23:35 PM PDT 24
Peak memory 199948 kb
Host smart-4326e7a3-d9a8-4dd5-bc7b-4c9db2b7f09c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992939730 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3992939730
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.141733663
Short name T1253
Test name
Test status
Simulation time 12478974 ps
CPU time 0.56 seconds
Started Aug 07 04:24:11 PM PDT 24
Finished Aug 07 04:24:12 PM PDT 24
Peak memory 195356 kb
Host smart-f08117ca-3acf-490b-816c-9d33351ea125
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141733663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.141733663
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.1887800082
Short name T1239
Test name
Test status
Simulation time 11229273 ps
CPU time 0.55 seconds
Started Aug 07 04:19:44 PM PDT 24
Finished Aug 07 04:19:45 PM PDT 24
Peak memory 194632 kb
Host smart-cdf976a1-bff3-4b5f-af5f-df818e999671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887800082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1887800082
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.538330910
Short name T70
Test name
Test status
Simulation time 18393359 ps
CPU time 0.74 seconds
Started Aug 07 04:25:00 PM PDT 24
Finished Aug 07 04:25:01 PM PDT 24
Peak memory 197260 kb
Host smart-bad8c467-1733-496b-a831-006b2f61988c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538330910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.538330910
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1632383348
Short name T1213
Test name
Test status
Simulation time 31406501 ps
CPU time 0.94 seconds
Started Aug 07 04:23:04 PM PDT 24
Finished Aug 07 04:23:05 PM PDT 24
Peak memory 200004 kb
Host smart-4045de05-4417-4654-8421-60d55ec85f0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632383348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1632383348
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.4140918183
Short name T1277
Test name
Test status
Simulation time 169822263 ps
CPU time 0.89 seconds
Started Aug 07 04:24:10 PM PDT 24
Finished Aug 07 04:24:11 PM PDT 24
Peak memory 198380 kb
Host smart-ab7d5d5b-a3fc-41cb-abf0-cf72e8e315ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140918183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.4140918183
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.330946820
Short name T1313
Test name
Test status
Simulation time 19810723 ps
CPU time 1.06 seconds
Started Aug 07 04:20:36 PM PDT 24
Finished Aug 07 04:20:37 PM PDT 24
Peak memory 200064 kb
Host smart-eee4cae5-4300-49e0-b1dc-e493854c1c58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330946820 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.330946820
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.559840673
Short name T1281
Test name
Test status
Simulation time 13431595 ps
CPU time 0.57 seconds
Started Aug 07 04:24:24 PM PDT 24
Finished Aug 07 04:24:25 PM PDT 24
Peak memory 194936 kb
Host smart-06a6976a-7f23-417a-9415-4883059dd43c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559840673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.559840673
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.1195276023
Short name T1185
Test name
Test status
Simulation time 47579948 ps
CPU time 0.56 seconds
Started Aug 07 04:20:16 PM PDT 24
Finished Aug 07 04:20:17 PM PDT 24
Peak memory 194612 kb
Host smart-6af5c4d5-f6ee-457d-9300-5287007c3a85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195276023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1195276023
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1713918085
Short name T64
Test name
Test status
Simulation time 28776149 ps
CPU time 0.75 seconds
Started Aug 07 04:24:46 PM PDT 24
Finished Aug 07 04:24:47 PM PDT 24
Peak memory 195988 kb
Host smart-8ed7f2e2-38c4-4ef7-aad1-3093df2f4ba6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713918085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1713918085
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3503484214
Short name T1280
Test name
Test status
Simulation time 31282015 ps
CPU time 1.36 seconds
Started Aug 07 04:24:25 PM PDT 24
Finished Aug 07 04:24:27 PM PDT 24
Peak memory 200112 kb
Host smart-d27ff57a-b63c-4659-b6bc-e8067f3ebff1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503484214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3503484214
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2329424717
Short name T1257
Test name
Test status
Simulation time 78987034 ps
CPU time 0.73 seconds
Started Aug 07 04:24:10 PM PDT 24
Finished Aug 07 04:24:11 PM PDT 24
Peak memory 198636 kb
Host smart-f1f972ed-5bfa-47f5-939b-dd3e44d5ecda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329424717 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2329424717
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3036610498
Short name T69
Test name
Test status
Simulation time 23553204 ps
CPU time 0.58 seconds
Started Aug 07 04:24:05 PM PDT 24
Finished Aug 07 04:24:06 PM PDT 24
Peak memory 194480 kb
Host smart-1fc17aa2-a46e-487c-98b2-58574349b6c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036610498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3036610498
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3329550521
Short name T1227
Test name
Test status
Simulation time 55362927 ps
CPU time 0.59 seconds
Started Aug 07 04:19:53 PM PDT 24
Finished Aug 07 04:19:53 PM PDT 24
Peak memory 194632 kb
Host smart-2b92e410-9283-4335-b8af-d2e9b9bf300d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329550521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3329550521
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3304222603
Short name T1264
Test name
Test status
Simulation time 66687393 ps
CPU time 0.69 seconds
Started Aug 07 04:21:26 PM PDT 24
Finished Aug 07 04:21:27 PM PDT 24
Peak memory 196120 kb
Host smart-3fb0bc6a-6b2e-470b-be19-c4a183ebb849
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304222603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3304222603
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1112284058
Short name T1271
Test name
Test status
Simulation time 46017685 ps
CPU time 2.17 seconds
Started Aug 07 04:24:11 PM PDT 24
Finished Aug 07 04:24:13 PM PDT 24
Peak memory 200000 kb
Host smart-75385604-b239-4478-a210-d03da1825420
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112284058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1112284058
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2754037080
Short name T1259
Test name
Test status
Simulation time 185911987 ps
CPU time 0.94 seconds
Started Aug 07 04:20:31 PM PDT 24
Finished Aug 07 04:20:32 PM PDT 24
Peak memory 199440 kb
Host smart-c1722407-e69b-4a34-88ee-a9f7c6b996f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754037080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2754037080
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.585006825
Short name T1205
Test name
Test status
Simulation time 22656076 ps
CPU time 0.79 seconds
Started Aug 07 04:25:00 PM PDT 24
Finished Aug 07 04:25:01 PM PDT 24
Peak memory 199592 kb
Host smart-208e5579-d111-4783-8f18-ec922e96ca5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585006825 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.585006825
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.369325974
Short name T1284
Test name
Test status
Simulation time 25428808 ps
CPU time 0.59 seconds
Started Aug 07 04:24:20 PM PDT 24
Finished Aug 07 04:24:21 PM PDT 24
Peak memory 195784 kb
Host smart-a003d22d-6a71-48d9-a23f-8d37c089874c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369325974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.369325974
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.18635137
Short name T1279
Test name
Test status
Simulation time 19434435 ps
CPU time 0.62 seconds
Started Aug 07 04:21:21 PM PDT 24
Finished Aug 07 04:21:22 PM PDT 24
Peak memory 194664 kb
Host smart-e66afdbd-5094-4a29-a2a2-d367e94430dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18635137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.18635137
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.403147280
Short name T1267
Test name
Test status
Simulation time 15568977 ps
CPU time 0.6 seconds
Started Aug 07 04:24:05 PM PDT 24
Finished Aug 07 04:24:06 PM PDT 24
Peak memory 194636 kb
Host smart-86d18951-0717-4ca3-849f-1e9ac6ad1e3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403147280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.403147280
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.3082403505
Short name T1276
Test name
Test status
Simulation time 167950249 ps
CPU time 1.46 seconds
Started Aug 07 04:21:06 PM PDT 24
Finished Aug 07 04:21:08 PM PDT 24
Peak memory 200220 kb
Host smart-b30d1e8a-3959-46c6-8f32-abb5b4788ac0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082403505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3082403505
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3499048839
Short name T114
Test name
Test status
Simulation time 394184265 ps
CPU time 1.33 seconds
Started Aug 07 04:24:46 PM PDT 24
Finished Aug 07 04:24:48 PM PDT 24
Peak memory 198304 kb
Host smart-6f9a68e7-2337-440b-bd65-52e5c0b254ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499048839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3499048839
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1001527117
Short name T1309
Test name
Test status
Simulation time 104974039 ps
CPU time 0.87 seconds
Started Aug 07 04:24:21 PM PDT 24
Finished Aug 07 04:24:22 PM PDT 24
Peak memory 199772 kb
Host smart-d7a5e239-ce63-4c73-9867-59585941e76b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001527117 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1001527117
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2957084422
Short name T1290
Test name
Test status
Simulation time 150351625 ps
CPU time 0.55 seconds
Started Aug 07 04:25:00 PM PDT 24
Finished Aug 07 04:25:00 PM PDT 24
Peak memory 195624 kb
Host smart-6174caac-0ff8-4ec9-b696-251fa58b8eb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957084422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2957084422
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2582919060
Short name T1183
Test name
Test status
Simulation time 161136894 ps
CPU time 0.56 seconds
Started Aug 07 04:21:28 PM PDT 24
Finished Aug 07 04:21:29 PM PDT 24
Peak memory 194608 kb
Host smart-2c4cbd89-9332-433c-b310-8152a3de5857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582919060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2582919060
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3218686117
Short name T1232
Test name
Test status
Simulation time 50488227 ps
CPU time 0.76 seconds
Started Aug 07 04:24:34 PM PDT 24
Finished Aug 07 04:24:35 PM PDT 24
Peak memory 195420 kb
Host smart-bee50b62-e7f8-4374-945b-86c97f48227c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218686117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3218686117
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.611757540
Short name T1218
Test name
Test status
Simulation time 29581788 ps
CPU time 1.42 seconds
Started Aug 07 04:21:24 PM PDT 24
Finished Aug 07 04:21:26 PM PDT 24
Peak memory 200248 kb
Host smart-a6fae1d1-df94-4711-a2ac-eb26d8b68a58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611757540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.611757540
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.368891090
Short name T77
Test name
Test status
Simulation time 313091536 ps
CPU time 1.39 seconds
Started Aug 07 04:22:57 PM PDT 24
Finished Aug 07 04:22:59 PM PDT 24
Peak memory 199636 kb
Host smart-57359bf5-f83b-41fb-a0fa-cfcd20b96a5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368891090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.368891090
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3930266260
Short name T1221
Test name
Test status
Simulation time 30627432 ps
CPU time 0.84 seconds
Started Aug 07 04:18:50 PM PDT 24
Finished Aug 07 04:18:51 PM PDT 24
Peak memory 196144 kb
Host smart-d7009673-ba5a-4173-9e66-0910b6e6c7a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930266260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3930266260
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.4158542149
Short name T1199
Test name
Test status
Simulation time 355377250 ps
CPU time 1.47 seconds
Started Aug 07 04:18:47 PM PDT 24
Finished Aug 07 04:18:49 PM PDT 24
Peak memory 198312 kb
Host smart-0ebc078f-8685-4b94-8767-472ca2545b3d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158542149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.4158542149
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1543712794
Short name T1188
Test name
Test status
Simulation time 43005332 ps
CPU time 0.57 seconds
Started Aug 07 04:18:46 PM PDT 24
Finished Aug 07 04:18:47 PM PDT 24
Peak memory 195280 kb
Host smart-c71fee28-6c27-41d7-8a4d-bb37fa684264
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543712794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1543712794
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3955857335
Short name T1230
Test name
Test status
Simulation time 165904353 ps
CPU time 0.78 seconds
Started Aug 07 04:18:49 PM PDT 24
Finished Aug 07 04:18:50 PM PDT 24
Peak memory 199944 kb
Host smart-e17b386d-9e16-4e31-936e-e47c30d94c36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955857335 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3955857335
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.192766565
Short name T1274
Test name
Test status
Simulation time 17020082 ps
CPU time 0.62 seconds
Started Aug 07 04:18:49 PM PDT 24
Finished Aug 07 04:18:49 PM PDT 24
Peak memory 195892 kb
Host smart-b14d0bd0-5fb1-42ec-b1f1-c8a11b2c127b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192766565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.192766565
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1053971338
Short name T1288
Test name
Test status
Simulation time 53766758 ps
CPU time 0.57 seconds
Started Aug 07 04:18:46 PM PDT 24
Finished Aug 07 04:18:47 PM PDT 24
Peak memory 194524 kb
Host smart-0e9ded9c-408e-4e00-9089-1c748361197a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053971338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1053971338
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1289830774
Short name T1243
Test name
Test status
Simulation time 35519083 ps
CPU time 0.64 seconds
Started Aug 07 04:18:37 PM PDT 24
Finished Aug 07 04:18:37 PM PDT 24
Peak memory 194704 kb
Host smart-0da41931-2427-4de3-92c7-78599275b2bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289830774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1289830774
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3871435016
Short name T1301
Test name
Test status
Simulation time 250813069 ps
CPU time 1.31 seconds
Started Aug 07 04:18:45 PM PDT 24
Finished Aug 07 04:18:47 PM PDT 24
Peak memory 199220 kb
Host smart-ea64021a-b679-4333-af03-a747f354746a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871435016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3871435016
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3528263797
Short name T75
Test name
Test status
Simulation time 161134965 ps
CPU time 0.89 seconds
Started Aug 07 04:18:47 PM PDT 24
Finished Aug 07 04:18:48 PM PDT 24
Peak memory 198768 kb
Host smart-18bcb259-aaa8-4ef2-8e80-5c6035ee05f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528263797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3528263797
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.892391094
Short name T1231
Test name
Test status
Simulation time 16141254 ps
CPU time 0.56 seconds
Started Aug 07 04:20:22 PM PDT 24
Finished Aug 07 04:20:23 PM PDT 24
Peak memory 194616 kb
Host smart-0bdd589f-325c-4d48-b9e4-1982a7add3f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892391094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.892391094
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2405054898
Short name T1298
Test name
Test status
Simulation time 16896318 ps
CPU time 0.56 seconds
Started Aug 07 04:24:08 PM PDT 24
Finished Aug 07 04:24:08 PM PDT 24
Peak memory 194216 kb
Host smart-7ee27d24-6e58-4487-a73b-340d3af633fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405054898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2405054898
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1746967506
Short name T1187
Test name
Test status
Simulation time 13644498 ps
CPU time 0.59 seconds
Started Aug 07 04:24:20 PM PDT 24
Finished Aug 07 04:24:21 PM PDT 24
Peak memory 193728 kb
Host smart-5f16ebf8-732f-4944-97c1-e00d874f682a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746967506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1746967506
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.4003141559
Short name T1237
Test name
Test status
Simulation time 49924812 ps
CPU time 0.6 seconds
Started Aug 07 04:24:41 PM PDT 24
Finished Aug 07 04:24:42 PM PDT 24
Peak memory 193988 kb
Host smart-12881bb4-0159-4c52-8c79-465415b18dd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003141559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.4003141559
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.4031488369
Short name T1224
Test name
Test status
Simulation time 15293527 ps
CPU time 0.6 seconds
Started Aug 07 04:19:36 PM PDT 24
Finished Aug 07 04:19:37 PM PDT 24
Peak memory 194632 kb
Host smart-78e54782-dc7c-4fc5-829f-1d157bb9de0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031488369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.4031488369
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2372058265
Short name T1269
Test name
Test status
Simulation time 40906971 ps
CPU time 0.6 seconds
Started Aug 07 04:22:17 PM PDT 24
Finished Aug 07 04:22:18 PM PDT 24
Peak memory 194636 kb
Host smart-84fe48a6-4187-4392-b538-ddbe050d4871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372058265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2372058265
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1632034228
Short name T1192
Test name
Test status
Simulation time 20673543 ps
CPU time 0.54 seconds
Started Aug 07 04:24:41 PM PDT 24
Finished Aug 07 04:24:42 PM PDT 24
Peak memory 193932 kb
Host smart-62ae4821-7734-48c7-85f4-e905032ab821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632034228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1632034228
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.34292998
Short name T1189
Test name
Test status
Simulation time 17525224 ps
CPU time 0.62 seconds
Started Aug 07 04:20:24 PM PDT 24
Finished Aug 07 04:20:24 PM PDT 24
Peak memory 194632 kb
Host smart-05a135f4-4dee-4433-a37d-683905a379a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34292998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.34292998
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.503960875
Short name T1292
Test name
Test status
Simulation time 18220215 ps
CPU time 0.59 seconds
Started Aug 07 04:22:29 PM PDT 24
Finished Aug 07 04:22:30 PM PDT 24
Peak memory 194608 kb
Host smart-4c0a02a5-df1c-4d1c-a1c4-afe543ebfd9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503960875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.503960875
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1387096819
Short name T1258
Test name
Test status
Simulation time 14874692 ps
CPU time 0.57 seconds
Started Aug 07 04:24:24 PM PDT 24
Finished Aug 07 04:24:24 PM PDT 24
Peak memory 194216 kb
Host smart-1d6bd4c7-e33b-488c-b236-79983a561734
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387096819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1387096819
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3143772636
Short name T57
Test name
Test status
Simulation time 57522049 ps
CPU time 0.75 seconds
Started Aug 07 04:18:53 PM PDT 24
Finished Aug 07 04:18:54 PM PDT 24
Peak memory 196656 kb
Host smart-a7ec2608-ef79-4e62-b45f-1985c5addd4a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143772636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3143772636
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1206438655
Short name T1186
Test name
Test status
Simulation time 176472339 ps
CPU time 2.27 seconds
Started Aug 07 04:18:45 PM PDT 24
Finished Aug 07 04:18:47 PM PDT 24
Peak memory 197220 kb
Host smart-bc8d42a9-72ff-43cb-8c57-a7f8c0584533
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206438655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1206438655
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2071706689
Short name T1307
Test name
Test status
Simulation time 16992558 ps
CPU time 0.56 seconds
Started Aug 07 04:18:36 PM PDT 24
Finished Aug 07 04:18:37 PM PDT 24
Peak memory 195248 kb
Host smart-3c213474-09fc-41b9-8b56-c8e0fc760ea6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071706689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2071706689
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2666398302
Short name T1245
Test name
Test status
Simulation time 65994699 ps
CPU time 0.67 seconds
Started Aug 07 04:18:48 PM PDT 24
Finished Aug 07 04:18:49 PM PDT 24
Peak memory 198312 kb
Host smart-f4f40dbb-fbf9-4df6-9b67-e48b771c697e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666398302 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2666398302
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3546452317
Short name T1229
Test name
Test status
Simulation time 33529564 ps
CPU time 0.56 seconds
Started Aug 07 04:18:47 PM PDT 24
Finished Aug 07 04:18:48 PM PDT 24
Peak memory 194980 kb
Host smart-f4808319-66ef-472a-a1a7-fa7dd4bc2f92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546452317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3546452317
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1547332748
Short name T1311
Test name
Test status
Simulation time 36939656 ps
CPU time 0.61 seconds
Started Aug 07 04:18:50 PM PDT 24
Finished Aug 07 04:18:51 PM PDT 24
Peak memory 194164 kb
Host smart-b109819b-790c-4446-8427-012a335478d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547332748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1547332748
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1476593507
Short name T62
Test name
Test status
Simulation time 29088953 ps
CPU time 0.75 seconds
Started Aug 07 04:18:46 PM PDT 24
Finished Aug 07 04:18:47 PM PDT 24
Peak memory 194856 kb
Host smart-76a23766-5c18-4851-acf7-ba0acf01c8bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476593507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1476593507
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2014413348
Short name T1211
Test name
Test status
Simulation time 483349621 ps
CPU time 1.6 seconds
Started Aug 07 04:18:47 PM PDT 24
Finished Aug 07 04:18:49 PM PDT 24
Peak memory 200120 kb
Host smart-2e261b69-7029-45d2-8df6-1f4bdef91510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014413348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2014413348
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1503907910
Short name T76
Test name
Test status
Simulation time 107231281 ps
CPU time 1.27 seconds
Started Aug 07 04:18:48 PM PDT 24
Finished Aug 07 04:18:50 PM PDT 24
Peak memory 199940 kb
Host smart-841bbfaf-e623-4477-86d8-0ff39120a7ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503907910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1503907910
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.419118227
Short name T1181
Test name
Test status
Simulation time 17986608 ps
CPU time 0.58 seconds
Started Aug 07 04:21:48 PM PDT 24
Finished Aug 07 04:21:49 PM PDT 24
Peak memory 194628 kb
Host smart-71cde4a9-5f30-4676-a4da-2126dd5d4bb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419118227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.419118227
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.4200433407
Short name T1215
Test name
Test status
Simulation time 29185736 ps
CPU time 0.56 seconds
Started Aug 07 04:20:36 PM PDT 24
Finished Aug 07 04:20:37 PM PDT 24
Peak memory 194632 kb
Host smart-296ce8d4-a31a-4b56-af1b-99f87ca871c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200433407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.4200433407
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2158646855
Short name T1314
Test name
Test status
Simulation time 14925281 ps
CPU time 0.56 seconds
Started Aug 07 04:24:16 PM PDT 24
Finished Aug 07 04:24:17 PM PDT 24
Peak memory 194596 kb
Host smart-f711a902-0d94-49d7-aeef-d09ed4b9af59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158646855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2158646855
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3792676589
Short name T1293
Test name
Test status
Simulation time 12990430 ps
CPU time 0.56 seconds
Started Aug 07 04:21:07 PM PDT 24
Finished Aug 07 04:21:07 PM PDT 24
Peak memory 194628 kb
Host smart-f36ca850-9e79-4bc0-b0c7-070cc0c27595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792676589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3792676589
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.257617189
Short name T1261
Test name
Test status
Simulation time 14447841 ps
CPU time 0.57 seconds
Started Aug 07 04:21:07 PM PDT 24
Finished Aug 07 04:21:08 PM PDT 24
Peak memory 194628 kb
Host smart-7f083d13-e7c9-4c09-90b7-2edf8c1b3e89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257617189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.257617189
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.742350150
Short name T1210
Test name
Test status
Simulation time 13762234 ps
CPU time 0.56 seconds
Started Aug 07 04:24:17 PM PDT 24
Finished Aug 07 04:24:18 PM PDT 24
Peak memory 194596 kb
Host smart-cd35874c-ff87-4183-b9fd-96d61cd27003
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742350150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.742350150
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3540806959
Short name T1216
Test name
Test status
Simulation time 20639253 ps
CPU time 0.6 seconds
Started Aug 07 04:24:01 PM PDT 24
Finished Aug 07 04:24:02 PM PDT 24
Peak memory 193804 kb
Host smart-4224b3f0-f2ad-487a-9b3b-a0f2fce977d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540806959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3540806959
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1103996728
Short name T1190
Test name
Test status
Simulation time 41369535 ps
CPU time 0.55 seconds
Started Aug 07 04:24:31 PM PDT 24
Finished Aug 07 04:24:31 PM PDT 24
Peak memory 194220 kb
Host smart-ccdda96f-e167-42a7-b160-f5338184a4fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103996728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1103996728
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3106359490
Short name T1286
Test name
Test status
Simulation time 28395542 ps
CPU time 0.55 seconds
Started Aug 07 04:22:26 PM PDT 24
Finished Aug 07 04:22:27 PM PDT 24
Peak memory 194608 kb
Host smart-a8e28b0f-c0d4-464b-af40-89cef373dd85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106359490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3106359490
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.4102325942
Short name T1291
Test name
Test status
Simulation time 42624329 ps
CPU time 0.64 seconds
Started Aug 07 04:22:36 PM PDT 24
Finished Aug 07 04:22:37 PM PDT 24
Peak memory 194616 kb
Host smart-0623621a-9323-4ac5-aa89-cbdce884f156
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102325942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.4102325942
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1895647988
Short name T1201
Test name
Test status
Simulation time 35099990 ps
CPU time 0.66 seconds
Started Aug 07 04:18:50 PM PDT 24
Finished Aug 07 04:18:51 PM PDT 24
Peak memory 195212 kb
Host smart-345d76ea-eb76-4d40-9d43-a6c77e6669f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895647988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1895647988
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2141956400
Short name T1194
Test name
Test status
Simulation time 539899598 ps
CPU time 1.54 seconds
Started Aug 07 04:18:50 PM PDT 24
Finished Aug 07 04:18:52 PM PDT 24
Peak memory 197732 kb
Host smart-fb272533-56ca-4780-aebd-0735f95cdb66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141956400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2141956400
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1422645577
Short name T1260
Test name
Test status
Simulation time 21318633 ps
CPU time 0.6 seconds
Started Aug 07 04:19:51 PM PDT 24
Finished Aug 07 04:19:52 PM PDT 24
Peak memory 194888 kb
Host smart-a8f7eb19-eb18-409c-a7eb-03f7a3db7adb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422645577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1422645577
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2129020869
Short name T1235
Test name
Test status
Simulation time 64831623 ps
CPU time 0.86 seconds
Started Aug 07 04:19:52 PM PDT 24
Finished Aug 07 04:19:53 PM PDT 24
Peak memory 199668 kb
Host smart-e6f9b9a3-aab9-4987-bbd4-be9d5571e5e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129020869 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2129020869
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2075988205
Short name T1283
Test name
Test status
Simulation time 22065154 ps
CPU time 0.61 seconds
Started Aug 07 04:21:18 PM PDT 24
Finished Aug 07 04:21:19 PM PDT 24
Peak memory 195660 kb
Host smart-7e825e1a-db43-409b-9d6e-365eb0927712
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075988205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2075988205
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.4246588709
Short name T1248
Test name
Test status
Simulation time 43785126 ps
CPU time 0.57 seconds
Started Aug 07 04:18:47 PM PDT 24
Finished Aug 07 04:18:48 PM PDT 24
Peak memory 194616 kb
Host smart-9b7fba5a-8340-45ab-8776-99dbe076bc3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246588709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.4246588709
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.465224420
Short name T1252
Test name
Test status
Simulation time 24969113 ps
CPU time 0.67 seconds
Started Aug 07 04:24:34 PM PDT 24
Finished Aug 07 04:24:35 PM PDT 24
Peak memory 194860 kb
Host smart-9b360d74-711d-4855-b8a8-d0fcb7a7c161
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465224420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.465224420
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3339612725
Short name T1233
Test name
Test status
Simulation time 102081524 ps
CPU time 1.35 seconds
Started Aug 07 04:18:44 PM PDT 24
Finished Aug 07 04:18:46 PM PDT 24
Peak memory 199556 kb
Host smart-03cc521f-bbcf-40c2-86f1-169553f83f7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339612725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3339612725
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2030139264
Short name T1206
Test name
Test status
Simulation time 192461604 ps
CPU time 0.96 seconds
Started Aug 07 04:18:45 PM PDT 24
Finished Aug 07 04:18:46 PM PDT 24
Peak memory 199068 kb
Host smart-d3c0464e-6294-4825-8b6e-ef6f7ebb46ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030139264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2030139264
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2743552822
Short name T1310
Test name
Test status
Simulation time 41669988 ps
CPU time 0.59 seconds
Started Aug 07 04:22:37 PM PDT 24
Finished Aug 07 04:22:37 PM PDT 24
Peak memory 194552 kb
Host smart-a4f9a18c-a1e7-4866-bf21-1f1b4e8b0950
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743552822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2743552822
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.887417132
Short name T1184
Test name
Test status
Simulation time 14289707 ps
CPU time 0.6 seconds
Started Aug 07 04:20:55 PM PDT 24
Finished Aug 07 04:20:56 PM PDT 24
Peak memory 194600 kb
Host smart-fdb308c8-053f-495c-b2d6-097ac9880a08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887417132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.887417132
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2810259987
Short name T1250
Test name
Test status
Simulation time 37526610 ps
CPU time 0.56 seconds
Started Aug 07 04:24:18 PM PDT 24
Finished Aug 07 04:24:19 PM PDT 24
Peak memory 194532 kb
Host smart-56136a7b-d1a4-4288-bb91-0bfee50a121d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810259987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2810259987
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1741722712
Short name T1265
Test name
Test status
Simulation time 29841019 ps
CPU time 0.57 seconds
Started Aug 07 04:24:01 PM PDT 24
Finished Aug 07 04:24:02 PM PDT 24
Peak memory 192816 kb
Host smart-57d7b8a0-2c05-44cf-8754-834cad2438da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741722712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1741722712
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.1249146917
Short name T1270
Test name
Test status
Simulation time 14144241 ps
CPU time 0.63 seconds
Started Aug 07 04:22:31 PM PDT 24
Finished Aug 07 04:22:31 PM PDT 24
Peak memory 194564 kb
Host smart-6ec8cd9e-7f7c-4704-a756-1965233d536d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249146917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1249146917
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2614462320
Short name T1241
Test name
Test status
Simulation time 15721563 ps
CPU time 0.56 seconds
Started Aug 07 04:24:01 PM PDT 24
Finished Aug 07 04:24:02 PM PDT 24
Peak memory 192900 kb
Host smart-a79653d7-e5c9-44fd-906c-c6e88c4f7fb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614462320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2614462320
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3590941613
Short name T1236
Test name
Test status
Simulation time 18171258 ps
CPU time 0.57 seconds
Started Aug 07 04:21:02 PM PDT 24
Finished Aug 07 04:21:03 PM PDT 24
Peak memory 194608 kb
Host smart-ca19084c-5593-4eec-9581-1cb8c036da78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590941613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3590941613
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3511772684
Short name T1223
Test name
Test status
Simulation time 11293354 ps
CPU time 0.55 seconds
Started Aug 07 04:21:00 PM PDT 24
Finished Aug 07 04:21:00 PM PDT 24
Peak memory 194608 kb
Host smart-d5065d91-0ac1-4e0d-a3d1-8e301ff57f66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511772684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3511772684
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3613404031
Short name T1294
Test name
Test status
Simulation time 15964872 ps
CPU time 0.55 seconds
Started Aug 07 04:21:41 PM PDT 24
Finished Aug 07 04:21:41 PM PDT 24
Peak memory 194180 kb
Host smart-343c891c-9fa1-4f9d-9752-e4c06a26764a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613404031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3613404031
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3913859703
Short name T1195
Test name
Test status
Simulation time 15324910 ps
CPU time 0.57 seconds
Started Aug 07 04:19:30 PM PDT 24
Finished Aug 07 04:19:31 PM PDT 24
Peak memory 194612 kb
Host smart-9bec944f-4cc9-46f6-a847-66c423e69d16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913859703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3913859703
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1288301158
Short name T1272
Test name
Test status
Simulation time 83904027 ps
CPU time 1.05 seconds
Started Aug 07 04:18:51 PM PDT 24
Finished Aug 07 04:18:52 PM PDT 24
Peak memory 200260 kb
Host smart-8d46eed6-927f-4e49-b2fb-b1b7a442b247
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288301158 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1288301158
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2074152004
Short name T1289
Test name
Test status
Simulation time 65621876 ps
CPU time 0.61 seconds
Started Aug 07 04:19:51 PM PDT 24
Finished Aug 07 04:19:52 PM PDT 24
Peak memory 195120 kb
Host smart-011ddb9f-dd71-41d5-91e5-2944ff452ca5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074152004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2074152004
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1728434051
Short name T1268
Test name
Test status
Simulation time 68753302 ps
CPU time 0.55 seconds
Started Aug 07 04:18:50 PM PDT 24
Finished Aug 07 04:18:51 PM PDT 24
Peak memory 194444 kb
Host smart-1829521a-0c7e-4671-a978-06557ab91f99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728434051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1728434051
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2603281608
Short name T1204
Test name
Test status
Simulation time 19147174 ps
CPU time 0.74 seconds
Started Aug 07 04:18:50 PM PDT 24
Finished Aug 07 04:18:52 PM PDT 24
Peak memory 196232 kb
Host smart-3c57f854-a2c7-4a27-8e56-a27d30bd9350
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603281608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2603281608
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3979569317
Short name T1202
Test name
Test status
Simulation time 459462456 ps
CPU time 2.11 seconds
Started Aug 07 04:19:50 PM PDT 24
Finished Aug 07 04:19:53 PM PDT 24
Peak memory 198668 kb
Host smart-0ecdb970-6490-40f2-bf10-28d901147f5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979569317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3979569317
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2236057873
Short name T115
Test name
Test status
Simulation time 921680394 ps
CPU time 0.96 seconds
Started Aug 07 04:19:52 PM PDT 24
Finished Aug 07 04:19:53 PM PDT 24
Peak memory 197916 kb
Host smart-0ba29f11-f059-4d6a-a2fc-c15464522e39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236057873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2236057873
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2840488808
Short name T1299
Test name
Test status
Simulation time 109182296 ps
CPU time 0.87 seconds
Started Aug 07 04:18:49 PM PDT 24
Finished Aug 07 04:18:51 PM PDT 24
Peak memory 198672 kb
Host smart-2f12779f-533c-4801-b094-74d84e3acfb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840488808 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2840488808
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1268677153
Short name T67
Test name
Test status
Simulation time 18009386 ps
CPU time 0.66 seconds
Started Aug 07 04:24:55 PM PDT 24
Finished Aug 07 04:24:56 PM PDT 24
Peak memory 194812 kb
Host smart-35946ffa-86e4-43c3-a77c-44c45ef3a63b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268677153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1268677153
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.59275637
Short name T1182
Test name
Test status
Simulation time 15627402 ps
CPU time 0.6 seconds
Started Aug 07 04:18:49 PM PDT 24
Finished Aug 07 04:18:50 PM PDT 24
Peak memory 193448 kb
Host smart-d02c5279-39ed-4c80-9721-4bdc60b2229c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59275637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.59275637
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1342194318
Short name T61
Test name
Test status
Simulation time 98330500 ps
CPU time 0.67 seconds
Started Aug 07 04:18:50 PM PDT 24
Finished Aug 07 04:18:52 PM PDT 24
Peak memory 195712 kb
Host smart-c425b872-4fc7-478a-bfa5-91b6b713ce2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342194318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1342194318
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.4088563077
Short name T1193
Test name
Test status
Simulation time 396800288 ps
CPU time 1.3 seconds
Started Aug 07 04:18:50 PM PDT 24
Finished Aug 07 04:18:51 PM PDT 24
Peak memory 199972 kb
Host smart-ffa542ce-00c7-4020-a600-3336e7aeea6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088563077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.4088563077
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2687563217
Short name T1282
Test name
Test status
Simulation time 104024979 ps
CPU time 1.33 seconds
Started Aug 07 04:20:06 PM PDT 24
Finished Aug 07 04:20:08 PM PDT 24
Peak memory 199480 kb
Host smart-0ea22036-9f16-4352-bfe2-17f78ceb1551
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687563217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2687563217
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1043202360
Short name T1238
Test name
Test status
Simulation time 63392697 ps
CPU time 0.67 seconds
Started Aug 07 04:21:18 PM PDT 24
Finished Aug 07 04:21:19 PM PDT 24
Peak memory 197772 kb
Host smart-e95b45ca-30da-4fd4-84ca-c48406e6f74e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043202360 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1043202360
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1755995835
Short name T58
Test name
Test status
Simulation time 44553482 ps
CPU time 0.55 seconds
Started Aug 07 04:19:53 PM PDT 24
Finished Aug 07 04:19:54 PM PDT 24
Peak memory 195464 kb
Host smart-140d5bf0-5e08-4598-b7fe-d3d054a4fbe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755995835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1755995835
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1677389455
Short name T1209
Test name
Test status
Simulation time 13902792 ps
CPU time 0.55 seconds
Started Aug 07 04:20:06 PM PDT 24
Finished Aug 07 04:20:06 PM PDT 24
Peak memory 194572 kb
Host smart-69e5548d-ff76-4201-96d2-873ce4c29b67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677389455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1677389455
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2111373107
Short name T1220
Test name
Test status
Simulation time 12855936 ps
CPU time 0.63 seconds
Started Aug 07 04:21:27 PM PDT 24
Finished Aug 07 04:21:27 PM PDT 24
Peak memory 196128 kb
Host smart-8a4e5265-ad22-4448-a9b4-cb9c4a64764d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111373107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2111373107
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2454406380
Short name T1315
Test name
Test status
Simulation time 46264783 ps
CPU time 1.03 seconds
Started Aug 07 04:20:06 PM PDT 24
Finished Aug 07 04:20:07 PM PDT 24
Peak memory 199988 kb
Host smart-0f788373-cbb2-4d2e-8b1b-1f44e6402369
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454406380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2454406380
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3193719783
Short name T82
Test name
Test status
Simulation time 54449564 ps
CPU time 0.96 seconds
Started Aug 07 04:19:52 PM PDT 24
Finished Aug 07 04:19:53 PM PDT 24
Peak memory 198480 kb
Host smart-8d09217d-245d-4088-9bea-40e51bb9c18e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193719783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3193719783
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2102699973
Short name T1256
Test name
Test status
Simulation time 125619909 ps
CPU time 0.68 seconds
Started Aug 07 04:19:53 PM PDT 24
Finished Aug 07 04:19:54 PM PDT 24
Peak memory 198876 kb
Host smart-88e1ffa3-7d57-4b0a-bfcb-0737d93f1e04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102699973 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2102699973
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1239000717
Short name T1306
Test name
Test status
Simulation time 36782520 ps
CPU time 0.59 seconds
Started Aug 07 04:19:52 PM PDT 24
Finished Aug 07 04:19:53 PM PDT 24
Peak memory 194060 kb
Host smart-4f7b1942-55e9-4dff-bf29-dab7c6cd3f3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239000717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1239000717
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3422446876
Short name T1228
Test name
Test status
Simulation time 52183677 ps
CPU time 0.55 seconds
Started Aug 07 04:19:38 PM PDT 24
Finished Aug 07 04:19:39 PM PDT 24
Peak memory 194636 kb
Host smart-4a47470d-a3a3-4ee6-8f5b-ec0e197ca9a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422446876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3422446876
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2761761502
Short name T63
Test name
Test status
Simulation time 56605022 ps
CPU time 0.63 seconds
Started Aug 07 04:20:06 PM PDT 24
Finished Aug 07 04:20:07 PM PDT 24
Peak memory 195740 kb
Host smart-ae3954f5-1334-427c-9de6-25cc7f7e8918
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761761502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2761761502
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3685770939
Short name T1308
Test name
Test status
Simulation time 38410633 ps
CPU time 1.84 seconds
Started Aug 07 04:18:50 PM PDT 24
Finished Aug 07 04:18:52 PM PDT 24
Peak memory 199128 kb
Host smart-eeba48d8-8f25-4af1-9f85-74621f4e9973
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685770939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3685770939
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1956054673
Short name T85
Test name
Test status
Simulation time 1256505094 ps
CPU time 1.4 seconds
Started Aug 07 04:20:23 PM PDT 24
Finished Aug 07 04:20:24 PM PDT 24
Peak memory 199568 kb
Host smart-f80ed62e-0258-4773-bbbc-c2fb037b396f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956054673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1956054673
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3982056751
Short name T1212
Test name
Test status
Simulation time 38963798 ps
CPU time 0.89 seconds
Started Aug 07 04:19:53 PM PDT 24
Finished Aug 07 04:19:54 PM PDT 24
Peak memory 199816 kb
Host smart-2ba5590e-68e0-4a6c-9a0e-39019401d0fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982056751 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3982056751
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1810357028
Short name T1214
Test name
Test status
Simulation time 16657871 ps
CPU time 0.64 seconds
Started Aug 07 04:19:10 PM PDT 24
Finished Aug 07 04:19:11 PM PDT 24
Peak memory 195336 kb
Host smart-54de2eb7-190b-4c60-a517-53494518385b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810357028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1810357028
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3253314045
Short name T1208
Test name
Test status
Simulation time 71962574 ps
CPU time 0.57 seconds
Started Aug 07 04:20:06 PM PDT 24
Finished Aug 07 04:20:07 PM PDT 24
Peak memory 194592 kb
Host smart-5daf2ea0-4d0a-47f4-8c80-686d31da2bda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253314045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3253314045
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3670556781
Short name T68
Test name
Test status
Simulation time 35171948 ps
CPU time 0.79 seconds
Started Aug 07 04:24:55 PM PDT 24
Finished Aug 07 04:24:56 PM PDT 24
Peak memory 197344 kb
Host smart-a278910e-ffd2-4fd5-a2e3-46a4e43d2d9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670556781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3670556781
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1871461858
Short name T1244
Test name
Test status
Simulation time 1528577546 ps
CPU time 2.45 seconds
Started Aug 07 04:19:54 PM PDT 24
Finished Aug 07 04:19:56 PM PDT 24
Peak memory 200216 kb
Host smart-ad04caf6-0648-46d0-a98e-f2f188b79a8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871461858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1871461858
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.912798830
Short name T80
Test name
Test status
Simulation time 144682007 ps
CPU time 0.93 seconds
Started Aug 07 04:19:53 PM PDT 24
Finished Aug 07 04:19:54 PM PDT 24
Peak memory 199112 kb
Host smart-9291a2de-762d-41da-8eee-c3d993073387
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912798830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.912798830
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1713608741
Short name T428
Test name
Test status
Simulation time 134414967178 ps
CPU time 61.36 seconds
Started Aug 07 05:51:01 PM PDT 24
Finished Aug 07 05:52:03 PM PDT 24
Peak memory 199892 kb
Host smart-4f6831c3-8ab2-4f06-8d6b-1ed255adf8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713608741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1713608741
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.2522153527
Short name T738
Test name
Test status
Simulation time 96209387423 ps
CPU time 74.78 seconds
Started Aug 07 05:50:56 PM PDT 24
Finished Aug 07 05:52:11 PM PDT 24
Peak memory 199880 kb
Host smart-6883a686-6048-4432-bed2-eebeb5be11b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522153527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2522153527
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.692875070
Short name T500
Test name
Test status
Simulation time 35767958898 ps
CPU time 63.26 seconds
Started Aug 07 05:51:02 PM PDT 24
Finished Aug 07 05:52:05 PM PDT 24
Peak memory 199868 kb
Host smart-c83e13dd-525b-451b-9b87-9700569d1229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692875070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.692875070
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.802124760
Short name T1122
Test name
Test status
Simulation time 62987841987 ps
CPU time 13.84 seconds
Started Aug 07 05:51:00 PM PDT 24
Finished Aug 07 05:51:14 PM PDT 24
Peak memory 199804 kb
Host smart-6bae4216-78df-4484-be06-fa8e13b9e45c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802124760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.802124760
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.795317955
Short name T341
Test name
Test status
Simulation time 108924321588 ps
CPU time 767.83 seconds
Started Aug 07 05:51:09 PM PDT 24
Finished Aug 07 06:03:57 PM PDT 24
Peak memory 199940 kb
Host smart-c9fe6a82-8796-4fb2-adda-f8e41e58596c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=795317955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.795317955
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1172265047
Short name T325
Test name
Test status
Simulation time 5706417764 ps
CPU time 10.93 seconds
Started Aug 07 05:51:02 PM PDT 24
Finished Aug 07 05:51:13 PM PDT 24
Peak memory 199908 kb
Host smart-d87c29f3-92aa-4a07-80de-629cb85cfb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172265047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1172265047
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.3922551281
Short name T1008
Test name
Test status
Simulation time 215093008988 ps
CPU time 104.49 seconds
Started Aug 07 05:51:07 PM PDT 24
Finished Aug 07 05:52:52 PM PDT 24
Peak memory 208208 kb
Host smart-5fbf537e-f88f-465f-9dbe-c2d4c491d792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922551281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3922551281
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2715384991
Short name T44
Test name
Test status
Simulation time 11311549816 ps
CPU time 233.94 seconds
Started Aug 07 05:51:06 PM PDT 24
Finished Aug 07 05:55:00 PM PDT 24
Peak memory 199800 kb
Host smart-4be93d7e-6942-4513-a7d5-0dfefdf66adf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2715384991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2715384991
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3752155903
Short name T477
Test name
Test status
Simulation time 7420938176 ps
CPU time 17.93 seconds
Started Aug 07 05:51:00 PM PDT 24
Finished Aug 07 05:51:18 PM PDT 24
Peak memory 197940 kb
Host smart-3b87f8d2-b55b-4529-b1b5-85de6f01ad11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752155903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3752155903
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3942958034
Short name T1090
Test name
Test status
Simulation time 32983572898 ps
CPU time 14.24 seconds
Started Aug 07 05:51:07 PM PDT 24
Finished Aug 07 05:51:21 PM PDT 24
Peak memory 199800 kb
Host smart-29a8c103-3bc7-4ad5-b303-acfcdcd69f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942958034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3942958034
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1793805090
Short name T1083
Test name
Test status
Simulation time 4241348325 ps
CPU time 1.29 seconds
Started Aug 07 05:51:01 PM PDT 24
Finished Aug 07 05:51:03 PM PDT 24
Peak memory 196260 kb
Host smart-b4af1fe5-ff5b-40be-87fe-c21689a22172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793805090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1793805090
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.2848040022
Short name T1074
Test name
Test status
Simulation time 5652223423 ps
CPU time 21.39 seconds
Started Aug 07 05:51:02 PM PDT 24
Finished Aug 07 05:51:23 PM PDT 24
Peak memory 199060 kb
Host smart-617ecd80-9df5-45a4-a7d5-913fd15df0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848040022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2848040022
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.378711720
Short name T981
Test name
Test status
Simulation time 199570922616 ps
CPU time 118.27 seconds
Started Aug 07 05:51:08 PM PDT 24
Finished Aug 07 05:53:07 PM PDT 24
Peak memory 199888 kb
Host smart-3862bf4d-c60f-4bce-be71-6bcedbe3376d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378711720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.378711720
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2392375115
Short name T992
Test name
Test status
Simulation time 3291414957 ps
CPU time 2.35 seconds
Started Aug 07 05:51:07 PM PDT 24
Finished Aug 07 05:51:09 PM PDT 24
Peak memory 199352 kb
Host smart-e9260787-a932-402f-9d0c-984d46c0ba47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392375115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2392375115
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_alert_test.898653340
Short name T1157
Test name
Test status
Simulation time 29420164 ps
CPU time 0.62 seconds
Started Aug 07 05:51:11 PM PDT 24
Finished Aug 07 05:51:12 PM PDT 24
Peak memory 195628 kb
Host smart-a5b0abb1-862c-4e2c-8424-56ea1c3d9e14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898653340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.898653340
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.691402921
Short name T1075
Test name
Test status
Simulation time 136235416290 ps
CPU time 52.08 seconds
Started Aug 07 05:51:04 PM PDT 24
Finished Aug 07 05:51:56 PM PDT 24
Peak memory 199884 kb
Host smart-32982a54-a98c-4e3e-8d1e-46df636ef17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691402921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.691402921
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2286779074
Short name T941
Test name
Test status
Simulation time 196969590531 ps
CPU time 67.38 seconds
Started Aug 07 05:51:04 PM PDT 24
Finished Aug 07 05:52:12 PM PDT 24
Peak memory 199940 kb
Host smart-56711e74-a353-4ffb-acee-1aa559701453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286779074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2286779074
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2930373992
Short name T1124
Test name
Test status
Simulation time 19801559067 ps
CPU time 16.83 seconds
Started Aug 07 05:51:04 PM PDT 24
Finished Aug 07 05:51:21 PM PDT 24
Peak memory 199768 kb
Host smart-bf2afe97-0663-4907-8814-97088e5bd326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930373992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2930373992
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.1343666942
Short name T751
Test name
Test status
Simulation time 36679671352 ps
CPU time 26.96 seconds
Started Aug 07 05:51:01 PM PDT 24
Finished Aug 07 05:51:29 PM PDT 24
Peak memory 198088 kb
Host smart-afae6263-fa26-4ca5-be52-f0f9392a0503
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343666942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1343666942
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2132652688
Short name T9
Test name
Test status
Simulation time 339606671477 ps
CPU time 279.14 seconds
Started Aug 07 05:51:12 PM PDT 24
Finished Aug 07 05:55:51 PM PDT 24
Peak memory 199880 kb
Host smart-452b8aaf-6084-4c14-80d9-6ae23ad59873
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2132652688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2132652688
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3369553498
Short name T598
Test name
Test status
Simulation time 5578641139 ps
CPU time 5.2 seconds
Started Aug 07 05:51:10 PM PDT 24
Finished Aug 07 05:51:16 PM PDT 24
Peak memory 199204 kb
Host smart-c69f0653-2c6b-4c15-a545-af7d4ea71cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369553498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3369553498
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.778571113
Short name T1103
Test name
Test status
Simulation time 118654362112 ps
CPU time 86.77 seconds
Started Aug 07 05:51:05 PM PDT 24
Finished Aug 07 05:52:32 PM PDT 24
Peak memory 200040 kb
Host smart-c75e47f6-32bb-4c9d-a5a0-0e80f09408c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778571113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.778571113
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.1465505290
Short name T698
Test name
Test status
Simulation time 25918917554 ps
CPU time 247.91 seconds
Started Aug 07 05:51:06 PM PDT 24
Finished Aug 07 05:55:14 PM PDT 24
Peak memory 199900 kb
Host smart-d3e3e588-0dc9-410e-8091-ff824bc6c03a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1465505290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1465505290
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.1865139472
Short name T425
Test name
Test status
Simulation time 3144726337 ps
CPU time 6.36 seconds
Started Aug 07 05:51:02 PM PDT 24
Finished Aug 07 05:51:09 PM PDT 24
Peak memory 198008 kb
Host smart-a3ac1684-4212-4e87-b5a7-570b7ca576ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1865139472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1865139472
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2138767161
Short name T109
Test name
Test status
Simulation time 160202961114 ps
CPU time 37.39 seconds
Started Aug 07 05:51:10 PM PDT 24
Finished Aug 07 05:51:47 PM PDT 24
Peak memory 199848 kb
Host smart-256f56b9-a4f5-4de1-a93d-03821ea0fbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138767161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2138767161
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3045355356
Short name T893
Test name
Test status
Simulation time 3216562347 ps
CPU time 5.95 seconds
Started Aug 07 05:51:07 PM PDT 24
Finished Aug 07 05:51:13 PM PDT 24
Peak memory 196480 kb
Host smart-5717cc0d-568e-45a0-bdc9-c630c4b1c512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045355356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3045355356
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3964835030
Short name T87
Test name
Test status
Simulation time 224414201 ps
CPU time 0.81 seconds
Started Aug 07 05:51:12 PM PDT 24
Finished Aug 07 05:51:13 PM PDT 24
Peak memory 218348 kb
Host smart-2313a98b-ff9f-461d-aa9c-125ba7e54122
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964835030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3964835030
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3061096615
Short name T511
Test name
Test status
Simulation time 408194905 ps
CPU time 1.98 seconds
Started Aug 07 05:51:07 PM PDT 24
Finished Aug 07 05:51:09 PM PDT 24
Peak memory 198100 kb
Host smart-b8cd1c12-e896-437d-8e55-7573b0070cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061096615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3061096615
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2452060763
Short name T634
Test name
Test status
Simulation time 80080700586 ps
CPU time 1066.61 seconds
Started Aug 07 05:51:07 PM PDT 24
Finished Aug 07 06:08:54 PM PDT 24
Peak memory 227292 kb
Host smart-1b7e28c1-00ae-4e9f-9a02-df9736f7dd7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452060763 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2452060763
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1452641837
Short name T19
Test name
Test status
Simulation time 3138655509 ps
CPU time 1.74 seconds
Started Aug 07 05:51:11 PM PDT 24
Finished Aug 07 05:51:13 PM PDT 24
Peak memory 199272 kb
Host smart-e3f4481a-cc30-4baa-93bd-59bc8a1d463e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452641837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1452641837
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2342021576
Short name T621
Test name
Test status
Simulation time 3305153768 ps
CPU time 5.35 seconds
Started Aug 07 05:51:04 PM PDT 24
Finished Aug 07 05:51:09 PM PDT 24
Peak memory 196852 kb
Host smart-f5a59547-5769-42b7-94c7-a91b77ad4d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342021576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2342021576
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2485412765
Short name T684
Test name
Test status
Simulation time 22755772 ps
CPU time 0.57 seconds
Started Aug 07 05:51:33 PM PDT 24
Finished Aug 07 05:51:34 PM PDT 24
Peak memory 195588 kb
Host smart-1f172f7f-970d-44b8-9539-b3b06ae56b8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485412765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2485412765
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2747136832
Short name T779
Test name
Test status
Simulation time 137314468596 ps
CPU time 207.19 seconds
Started Aug 07 05:51:29 PM PDT 24
Finished Aug 07 05:54:57 PM PDT 24
Peak memory 199908 kb
Host smart-9e586eb7-4532-48a4-9550-ea2301657a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747136832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2747136832
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.636850956
Short name T466
Test name
Test status
Simulation time 69687999703 ps
CPU time 110.22 seconds
Started Aug 07 05:51:30 PM PDT 24
Finished Aug 07 05:53:21 PM PDT 24
Peak memory 199892 kb
Host smart-647f833d-dfd1-4580-a417-023f2c56c39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636850956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.636850956
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.2391122962
Short name T1100
Test name
Test status
Simulation time 32270596010 ps
CPU time 18.75 seconds
Started Aug 07 05:51:32 PM PDT 24
Finished Aug 07 05:51:51 PM PDT 24
Peak memory 199412 kb
Host smart-219f82c9-4e61-43c7-a762-c12ee9bdbe6e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391122962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2391122962
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3871378571
Short name T457
Test name
Test status
Simulation time 167538362198 ps
CPU time 398.54 seconds
Started Aug 07 05:51:39 PM PDT 24
Finished Aug 07 05:58:18 PM PDT 24
Peak memory 199876 kb
Host smart-d85f4b4b-e2a9-434c-b486-1145439ced12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871378571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3871378571
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2760831979
Short name T440
Test name
Test status
Simulation time 256195413 ps
CPU time 0.66 seconds
Started Aug 07 05:51:38 PM PDT 24
Finished Aug 07 05:51:38 PM PDT 24
Peak memory 195392 kb
Host smart-d4b54ffc-741f-4a65-a3f7-91e9ccaa1b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760831979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2760831979
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.801675241
Short name T858
Test name
Test status
Simulation time 78178951921 ps
CPU time 169.33 seconds
Started Aug 07 05:51:26 PM PDT 24
Finished Aug 07 05:54:15 PM PDT 24
Peak memory 200032 kb
Host smart-7c58704a-75c0-4d5d-a8ee-906e58d1e21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801675241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.801675241
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.1608875506
Short name T251
Test name
Test status
Simulation time 37454643055 ps
CPU time 435.62 seconds
Started Aug 07 05:51:33 PM PDT 24
Finished Aug 07 05:58:49 PM PDT 24
Peak memory 199788 kb
Host smart-4df9ea63-d33f-4617-a2df-52d0c8a76fd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1608875506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1608875506
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1741289611
Short name T575
Test name
Test status
Simulation time 6405250257 ps
CPU time 53.39 seconds
Started Aug 07 05:51:27 PM PDT 24
Finished Aug 07 05:52:20 PM PDT 24
Peak memory 198992 kb
Host smart-c15daef8-bd9c-49ae-aa9e-62eda638ba6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1741289611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1741289611
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3258604848
Short name T842
Test name
Test status
Simulation time 67860489268 ps
CPU time 27.25 seconds
Started Aug 07 05:51:38 PM PDT 24
Finished Aug 07 05:52:05 PM PDT 24
Peak memory 199860 kb
Host smart-a298e7c0-8062-4afe-bb50-bdffac4eb4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258604848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3258604848
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1223435666
Short name T309
Test name
Test status
Simulation time 37857679597 ps
CPU time 29.77 seconds
Started Aug 07 05:51:31 PM PDT 24
Finished Aug 07 05:52:00 PM PDT 24
Peak memory 196116 kb
Host smart-745f83ec-1dc5-41b4-887c-3d153ece4c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223435666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1223435666
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.398615480
Short name T533
Test name
Test status
Simulation time 915283318 ps
CPU time 2.23 seconds
Started Aug 07 05:51:28 PM PDT 24
Finished Aug 07 05:51:31 PM PDT 24
Peak memory 198712 kb
Host smart-1a2153b9-46e7-4d32-bfde-63ab0e4317b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398615480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.398615480
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2383650668
Short name T771
Test name
Test status
Simulation time 34537303245 ps
CPU time 209.44 seconds
Started Aug 07 05:51:36 PM PDT 24
Finished Aug 07 05:55:06 PM PDT 24
Peak memory 215488 kb
Host smart-6a8816e8-c193-4f18-bb8c-0bc8e11b16a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383650668 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2383650668
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3703440588
Short name T248
Test name
Test status
Simulation time 8150200444 ps
CPU time 20.55 seconds
Started Aug 07 05:51:33 PM PDT 24
Finished Aug 07 05:51:54 PM PDT 24
Peak memory 199360 kb
Host smart-374ef158-00c6-4d70-83cb-8d4bba29218a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703440588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3703440588
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2293461179
Short name T690
Test name
Test status
Simulation time 59854747677 ps
CPU time 95 seconds
Started Aug 07 05:51:28 PM PDT 24
Finished Aug 07 05:53:03 PM PDT 24
Peak memory 199880 kb
Host smart-d05f979d-4bd2-4970-9fbb-4756bd45faaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293461179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2293461179
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2729251435
Short name T468
Test name
Test status
Simulation time 14900915990 ps
CPU time 22.88 seconds
Started Aug 07 05:56:01 PM PDT 24
Finished Aug 07 05:56:24 PM PDT 24
Peak memory 199872 kb
Host smart-6c1d52d5-4452-49f6-82ae-6d4d073b50f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729251435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2729251435
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3975824629
Short name T2
Test name
Test status
Simulation time 221290428678 ps
CPU time 56.06 seconds
Started Aug 07 05:56:02 PM PDT 24
Finished Aug 07 05:56:58 PM PDT 24
Peak memory 199820 kb
Host smart-e1b4bb34-5083-4162-a395-88c4d144f81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975824629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3975824629
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2132614207
Short name T453
Test name
Test status
Simulation time 112932137509 ps
CPU time 43.52 seconds
Started Aug 07 05:56:03 PM PDT 24
Finished Aug 07 05:56:47 PM PDT 24
Peak memory 199824 kb
Host smart-1f66fe46-94b8-4fcd-b54f-2b0570022d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132614207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2132614207
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3713930196
Short name T936
Test name
Test status
Simulation time 63508987348 ps
CPU time 109.38 seconds
Started Aug 07 05:56:17 PM PDT 24
Finished Aug 07 05:58:06 PM PDT 24
Peak memory 199832 kb
Host smart-d80f5cfa-c83e-4671-8ba6-6474438acfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713930196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3713930196
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3030305955
Short name T607
Test name
Test status
Simulation time 25686853008 ps
CPU time 33.49 seconds
Started Aug 07 05:56:09 PM PDT 24
Finished Aug 07 05:56:43 PM PDT 24
Peak memory 199900 kb
Host smart-79b892b9-a90a-4361-8727-020baa5b5085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030305955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3030305955
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1821092259
Short name T1132
Test name
Test status
Simulation time 2334144482 ps
CPU time 4.05 seconds
Started Aug 07 05:56:07 PM PDT 24
Finished Aug 07 05:56:12 PM PDT 24
Peak memory 199744 kb
Host smart-8f9fcf0a-43b0-4fac-9814-684d4444f8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821092259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1821092259
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3691949087
Short name T386
Test name
Test status
Simulation time 18151418 ps
CPU time 0.54 seconds
Started Aug 07 05:51:36 PM PDT 24
Finished Aug 07 05:51:37 PM PDT 24
Peak memory 194520 kb
Host smart-1a799ffa-cf8e-433b-a159-7157a22e2070
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691949087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3691949087
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3058719330
Short name T498
Test name
Test status
Simulation time 95551453350 ps
CPU time 73.92 seconds
Started Aug 07 05:51:33 PM PDT 24
Finished Aug 07 05:52:48 PM PDT 24
Peak memory 199912 kb
Host smart-1d35dce6-c211-4fc3-a4db-6c5019a38e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058719330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3058719330
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2590282040
Short name T1168
Test name
Test status
Simulation time 119017159008 ps
CPU time 241.85 seconds
Started Aug 07 05:51:38 PM PDT 24
Finished Aug 07 05:55:40 PM PDT 24
Peak memory 199816 kb
Host smart-0e17607a-a20c-4664-8bed-369884c74bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590282040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2590282040
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2771387481
Short name T512
Test name
Test status
Simulation time 138149656673 ps
CPU time 1259.56 seconds
Started Aug 07 05:51:39 PM PDT 24
Finished Aug 07 06:12:39 PM PDT 24
Peak memory 199876 kb
Host smart-93ee12ae-0e2a-4aa5-aa42-baa73bc06958
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2771387481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2771387481
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.355530112
Short name T22
Test name
Test status
Simulation time 12411914572 ps
CPU time 21.28 seconds
Started Aug 07 05:51:32 PM PDT 24
Finished Aug 07 05:51:54 PM PDT 24
Peak memory 199844 kb
Host smart-4f2cb64c-5a2a-4c97-8cd3-b7d84ea99c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355530112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.355530112
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.216765207
Short name T1040
Test name
Test status
Simulation time 77701392195 ps
CPU time 15.93 seconds
Started Aug 07 05:51:39 PM PDT 24
Finished Aug 07 05:51:56 PM PDT 24
Peak memory 208220 kb
Host smart-e42d4fd1-8568-41a3-9d8f-dce30eac3943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216765207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.216765207
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.839843929
Short name T1104
Test name
Test status
Simulation time 13213074317 ps
CPU time 756.56 seconds
Started Aug 07 05:51:39 PM PDT 24
Finished Aug 07 06:04:16 PM PDT 24
Peak memory 199860 kb
Host smart-ad64fa6b-3ce8-4dc9-8ea7-ae22d9014f15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=839843929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.839843929
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3790811928
Short name T362
Test name
Test status
Simulation time 5388672011 ps
CPU time 20.63 seconds
Started Aug 07 05:51:33 PM PDT 24
Finished Aug 07 05:51:54 PM PDT 24
Peak memory 198724 kb
Host smart-feac3c1a-32d3-4824-90d7-cdcfc2caec76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3790811928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3790811928
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2587150325
Short name T555
Test name
Test status
Simulation time 29274155692 ps
CPU time 13.14 seconds
Started Aug 07 05:51:31 PM PDT 24
Finished Aug 07 05:51:45 PM PDT 24
Peak memory 199612 kb
Host smart-5888d02f-c0be-4fa0-a452-99f02ab7198f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587150325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2587150325
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.4157965503
Short name T848
Test name
Test status
Simulation time 4015627554 ps
CPU time 4.36 seconds
Started Aug 07 05:51:34 PM PDT 24
Finished Aug 07 05:51:39 PM PDT 24
Peak memory 196048 kb
Host smart-7b9aad52-b59d-4b2b-b64d-1d4aba2fecef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157965503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.4157965503
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2566853560
Short name T892
Test name
Test status
Simulation time 5759524687 ps
CPU time 9.28 seconds
Started Aug 07 05:51:33 PM PDT 24
Finished Aug 07 05:51:43 PM PDT 24
Peak memory 199076 kb
Host smart-74da4c82-0c5f-409d-bb7a-73d79b8db56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566853560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2566853560
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1382193321
Short name T739
Test name
Test status
Simulation time 153797799078 ps
CPU time 511.81 seconds
Started Aug 07 05:51:36 PM PDT 24
Finished Aug 07 06:00:08 PM PDT 24
Peak memory 199872 kb
Host smart-9e4ebeb4-fc7f-4d97-9637-ad7981aa2294
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382193321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1382193321
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.337636841
Short name T111
Test name
Test status
Simulation time 95724696932 ps
CPU time 709.59 seconds
Started Aug 07 05:51:32 PM PDT 24
Finished Aug 07 06:03:22 PM PDT 24
Peak memory 224728 kb
Host smart-63f7faba-80c3-4fbb-957b-86ca969ecd20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337636841 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.337636841
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.852370318
Short name T662
Test name
Test status
Simulation time 1139687745 ps
CPU time 1.65 seconds
Started Aug 07 05:51:30 PM PDT 24
Finished Aug 07 05:51:31 PM PDT 24
Peak memory 198416 kb
Host smart-f60b19a5-5e38-4391-b0e6-cd923591c567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852370318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.852370318
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1468271724
Short name T267
Test name
Test status
Simulation time 41175982623 ps
CPU time 61.9 seconds
Started Aug 07 05:51:33 PM PDT 24
Finished Aug 07 05:52:35 PM PDT 24
Peak memory 199840 kb
Host smart-ac15f4e4-ee80-4609-a893-e6e87f18b729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468271724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1468271724
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.72904821
Short name T1111
Test name
Test status
Simulation time 101541301336 ps
CPU time 44.7 seconds
Started Aug 07 05:56:08 PM PDT 24
Finished Aug 07 05:56:53 PM PDT 24
Peak memory 199864 kb
Host smart-ed1ba8f2-bf18-40a8-ba21-d439a28f79a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72904821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.72904821
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.137627440
Short name T974
Test name
Test status
Simulation time 29237773307 ps
CPU time 42.25 seconds
Started Aug 07 05:56:07 PM PDT 24
Finished Aug 07 05:56:50 PM PDT 24
Peak memory 199940 kb
Host smart-2c0dcff6-4929-4a79-9226-8657b4c7c4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137627440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.137627440
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3684933687
Short name T850
Test name
Test status
Simulation time 39709222106 ps
CPU time 51.54 seconds
Started Aug 07 05:56:08 PM PDT 24
Finished Aug 07 05:56:59 PM PDT 24
Peak memory 199892 kb
Host smart-64c0cd99-6a5b-4f5a-8c3a-7466ef3acb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684933687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3684933687
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2674205871
Short name T1085
Test name
Test status
Simulation time 192258137213 ps
CPU time 52.49 seconds
Started Aug 07 05:56:08 PM PDT 24
Finished Aug 07 05:57:01 PM PDT 24
Peak memory 199928 kb
Host smart-efcdc688-7c9d-4876-b2ee-2e03d9c7cea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674205871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2674205871
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.434777808
Short name T530
Test name
Test status
Simulation time 49202882479 ps
CPU time 19.81 seconds
Started Aug 07 05:56:08 PM PDT 24
Finished Aug 07 05:56:28 PM PDT 24
Peak memory 199552 kb
Host smart-5d05f71a-f745-4fda-bb15-33555449da56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434777808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.434777808
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2095939126
Short name T1028
Test name
Test status
Simulation time 103796952926 ps
CPU time 84.86 seconds
Started Aug 07 05:56:15 PM PDT 24
Finished Aug 07 05:57:40 PM PDT 24
Peak memory 199764 kb
Host smart-e54d0349-41e0-40a1-b63f-288b35f46b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095939126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2095939126
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2229965453
Short name T585
Test name
Test status
Simulation time 4903161012 ps
CPU time 9.44 seconds
Started Aug 07 05:56:15 PM PDT 24
Finished Aug 07 05:56:24 PM PDT 24
Peak memory 199876 kb
Host smart-eeac7cc9-d220-4240-a7eb-0c08f3b8bd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229965453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2229965453
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1613329894
Short name T1016
Test name
Test status
Simulation time 53797306189 ps
CPU time 8.18 seconds
Started Aug 07 05:56:13 PM PDT 24
Finished Aug 07 05:56:21 PM PDT 24
Peak memory 199848 kb
Host smart-8ba3fb2a-cea3-4f3a-85fd-c4a76012b100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613329894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1613329894
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.4051748378
Short name T659
Test name
Test status
Simulation time 223211669298 ps
CPU time 84.09 seconds
Started Aug 07 05:56:14 PM PDT 24
Finished Aug 07 05:57:38 PM PDT 24
Peak memory 199932 kb
Host smart-cfa0fa09-3606-408c-bd99-36eef2918231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051748378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.4051748378
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3503811345
Short name T1031
Test name
Test status
Simulation time 49749396 ps
CPU time 0.55 seconds
Started Aug 07 05:51:38 PM PDT 24
Finished Aug 07 05:51:39 PM PDT 24
Peak memory 195296 kb
Host smart-d9f26257-9643-494d-a6ef-4fa3326dea99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503811345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3503811345
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2708291436
Short name T589
Test name
Test status
Simulation time 28610060941 ps
CPU time 21.14 seconds
Started Aug 07 05:51:36 PM PDT 24
Finished Aug 07 05:51:57 PM PDT 24
Peak memory 199856 kb
Host smart-bbc426a3-2370-4669-aa48-560e4497d9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708291436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2708291436
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2719816351
Short name T987
Test name
Test status
Simulation time 100446221293 ps
CPU time 48.42 seconds
Started Aug 07 05:51:34 PM PDT 24
Finished Aug 07 05:52:22 PM PDT 24
Peak memory 199904 kb
Host smart-e5761aa3-87d3-45ad-8b07-a4b843c2dc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719816351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2719816351
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.4111022973
Short name T870
Test name
Test status
Simulation time 55279824351 ps
CPU time 27.84 seconds
Started Aug 07 05:51:32 PM PDT 24
Finished Aug 07 05:52:00 PM PDT 24
Peak memory 199936 kb
Host smart-40a70d3f-96ec-4b76-9ab0-7a138548e360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111022973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.4111022973
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2082574354
Short name T469
Test name
Test status
Simulation time 27907807594 ps
CPU time 14.84 seconds
Started Aug 07 05:51:31 PM PDT 24
Finished Aug 07 05:51:46 PM PDT 24
Peak memory 199820 kb
Host smart-596f9021-5ae2-4c76-b7b2-c0dca1989e99
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082574354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2082574354
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2249917031
Short name T471
Test name
Test status
Simulation time 232062243415 ps
CPU time 374.81 seconds
Started Aug 07 05:51:39 PM PDT 24
Finished Aug 07 05:57:54 PM PDT 24
Peak memory 199860 kb
Host smart-9957e7c6-49d3-4e91-9569-851117f0b65d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2249917031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2249917031
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1954132757
Short name T1110
Test name
Test status
Simulation time 5053857920 ps
CPU time 8.74 seconds
Started Aug 07 05:51:32 PM PDT 24
Finished Aug 07 05:51:41 PM PDT 24
Peak memory 199272 kb
Host smart-2734a5d0-effc-4d25-82f7-ef01807042df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954132757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1954132757
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2983461373
Short name T997
Test name
Test status
Simulation time 25400553344 ps
CPU time 10.85 seconds
Started Aug 07 05:51:38 PM PDT 24
Finished Aug 07 05:51:49 PM PDT 24
Peak memory 198064 kb
Host smart-7ec99ebc-febb-43ee-950b-f230a0f84451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983461373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2983461373
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3435028705
Short name T868
Test name
Test status
Simulation time 7765631660 ps
CPU time 87.59 seconds
Started Aug 07 05:51:37 PM PDT 24
Finished Aug 07 05:53:05 PM PDT 24
Peak memory 199820 kb
Host smart-7fea7c6d-9ccc-4eef-b5a0-26d6519fcd33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3435028705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3435028705
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.265759869
Short name T920
Test name
Test status
Simulation time 6074930109 ps
CPU time 23.93 seconds
Started Aug 07 05:51:38 PM PDT 24
Finished Aug 07 05:52:02 PM PDT 24
Peak memory 199088 kb
Host smart-1b49ab43-7928-465a-9076-15f5f724a596
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=265759869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.265759869
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3692384921
Short name T473
Test name
Test status
Simulation time 26179164083 ps
CPU time 39.99 seconds
Started Aug 07 05:51:33 PM PDT 24
Finished Aug 07 05:52:13 PM PDT 24
Peak memory 199864 kb
Host smart-f07a50f0-c500-4464-92ec-c1e116cd253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692384921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3692384921
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.428229838
Short name T264
Test name
Test status
Simulation time 2843609944 ps
CPU time 5.22 seconds
Started Aug 07 05:51:33 PM PDT 24
Finished Aug 07 05:51:38 PM PDT 24
Peak memory 195720 kb
Host smart-593bba85-464d-4582-bd98-877cb78cfab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428229838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.428229838
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.902429758
Short name T377
Test name
Test status
Simulation time 735099052 ps
CPU time 1.62 seconds
Started Aug 07 05:51:32 PM PDT 24
Finished Aug 07 05:51:34 PM PDT 24
Peak memory 199788 kb
Host smart-e66ffd75-c9c3-4ea0-8210-7ca2f9f68b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902429758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.902429758
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1626799505
Short name T261
Test name
Test status
Simulation time 463926218848 ps
CPU time 512.15 seconds
Started Aug 07 05:51:37 PM PDT 24
Finished Aug 07 06:00:10 PM PDT 24
Peak memory 199940 kb
Host smart-b6decc32-e11b-4252-9206-42d5e7d8f923
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626799505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1626799505
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.274498467
Short name T1056
Test name
Test status
Simulation time 408929793838 ps
CPU time 1070.4 seconds
Started Aug 07 05:51:38 PM PDT 24
Finished Aug 07 06:09:29 PM PDT 24
Peak memory 225812 kb
Host smart-4bcd7c45-051b-4107-8f5d-3002a2fda2e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274498467 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.274498467
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1218611818
Short name T431
Test name
Test status
Simulation time 4537516990 ps
CPU time 1.56 seconds
Started Aug 07 05:51:31 PM PDT 24
Finished Aug 07 05:51:33 PM PDT 24
Peak memory 199400 kb
Host smart-79e97dc4-c4ce-4abb-a725-499e3e86c17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218611818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1218611818
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.4108222490
Short name T691
Test name
Test status
Simulation time 8959973061 ps
CPU time 17.94 seconds
Started Aug 07 05:51:34 PM PDT 24
Finished Aug 07 05:51:52 PM PDT 24
Peak memory 199964 kb
Host smart-36bb0fe7-ae3c-4a9f-afbc-363d6557b35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108222490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.4108222490
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2928809504
Short name T650
Test name
Test status
Simulation time 89701272065 ps
CPU time 136.87 seconds
Started Aug 07 05:56:14 PM PDT 24
Finished Aug 07 05:58:32 PM PDT 24
Peak memory 199900 kb
Host smart-8dabdf11-66b1-4a31-baa7-d14f25830171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928809504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2928809504
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3740392490
Short name T323
Test name
Test status
Simulation time 18391242970 ps
CPU time 9.7 seconds
Started Aug 07 05:56:14 PM PDT 24
Finished Aug 07 05:56:24 PM PDT 24
Peak memory 199784 kb
Host smart-fd635371-e2cb-46c2-9ba8-ece89f9d50af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740392490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3740392490
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3065893626
Short name T727
Test name
Test status
Simulation time 74313272462 ps
CPU time 37.13 seconds
Started Aug 07 05:56:14 PM PDT 24
Finished Aug 07 05:56:52 PM PDT 24
Peak memory 199844 kb
Host smart-5777dbf5-d689-4d60-8372-a067119041d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065893626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3065893626
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.2793636790
Short name T874
Test name
Test status
Simulation time 14025090284 ps
CPU time 13.56 seconds
Started Aug 07 05:56:14 PM PDT 24
Finished Aug 07 05:56:27 PM PDT 24
Peak memory 199844 kb
Host smart-607b9617-e99c-4044-a660-b0677b631e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793636790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2793636790
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1572060570
Short name T413
Test name
Test status
Simulation time 38119933388 ps
CPU time 55.32 seconds
Started Aug 07 05:56:14 PM PDT 24
Finished Aug 07 05:57:10 PM PDT 24
Peak memory 199848 kb
Host smart-31b2546f-a709-4df7-b08b-f3cd1107915c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572060570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1572060570
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2217220640
Short name T186
Test name
Test status
Simulation time 26349626451 ps
CPU time 20.35 seconds
Started Aug 07 05:56:14 PM PDT 24
Finished Aug 07 05:56:34 PM PDT 24
Peak memory 199884 kb
Host smart-f29681e1-e05b-4671-9058-1bd0944c845a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217220640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2217220640
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2161034608
Short name T384
Test name
Test status
Simulation time 29885823 ps
CPU time 0.56 seconds
Started Aug 07 05:51:43 PM PDT 24
Finished Aug 07 05:51:43 PM PDT 24
Peak memory 195272 kb
Host smart-5f214200-04ac-40fb-a6a4-fc6ae8907118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161034608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2161034608
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3988790415
Short name T565
Test name
Test status
Simulation time 63769786773 ps
CPU time 28.88 seconds
Started Aug 07 05:51:39 PM PDT 24
Finished Aug 07 05:52:08 PM PDT 24
Peak memory 200152 kb
Host smart-6e669d53-bb7a-412b-86d4-63aca3a9e933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988790415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3988790415
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1208913415
Short name T481
Test name
Test status
Simulation time 168575646230 ps
CPU time 223.72 seconds
Started Aug 07 05:51:42 PM PDT 24
Finished Aug 07 05:55:26 PM PDT 24
Peak memory 199840 kb
Host smart-b00b8f36-dafd-4377-b1f9-4cf04ba9e86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208913415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1208913415
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1602602302
Short name T145
Test name
Test status
Simulation time 151437978080 ps
CPU time 58.34 seconds
Started Aug 07 05:51:36 PM PDT 24
Finished Aug 07 05:52:34 PM PDT 24
Peak memory 199912 kb
Host smart-b6538ea7-a91e-462a-8a8d-55ceeb0f144d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602602302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1602602302
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.4022895256
Short name T380
Test name
Test status
Simulation time 48553770589 ps
CPU time 20.2 seconds
Started Aug 07 05:51:38 PM PDT 24
Finished Aug 07 05:51:58 PM PDT 24
Peak memory 198788 kb
Host smart-a6f7eb41-3822-44c2-ae5e-8b0938461681
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022895256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.4022895256
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3992622006
Short name T968
Test name
Test status
Simulation time 93807594859 ps
CPU time 287.89 seconds
Started Aug 07 05:51:44 PM PDT 24
Finished Aug 07 05:56:32 PM PDT 24
Peak memory 199904 kb
Host smart-8c2e2d25-7d3b-4b4f-8e28-79ee1c329f35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3992622006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3992622006
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.464793298
Short name T391
Test name
Test status
Simulation time 4750780889 ps
CPU time 3.51 seconds
Started Aug 07 05:51:42 PM PDT 24
Finished Aug 07 05:51:45 PM PDT 24
Peak memory 199948 kb
Host smart-d2ec14e4-9b0b-4131-9cea-d879814864bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464793298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.464793298
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.4270256198
Short name T970
Test name
Test status
Simulation time 53516339295 ps
CPU time 97.53 seconds
Started Aug 07 05:51:36 PM PDT 24
Finished Aug 07 05:53:14 PM PDT 24
Peak memory 199904 kb
Host smart-e56ee2b6-bdc2-4009-ba3a-8f459a3a6cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270256198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.4270256198
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.675610966
Short name T536
Test name
Test status
Simulation time 11118294354 ps
CPU time 150.72 seconds
Started Aug 07 05:51:43 PM PDT 24
Finished Aug 07 05:54:14 PM PDT 24
Peak memory 199880 kb
Host smart-7ee49dab-4ef0-4933-a226-67bbd3803ab3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=675610966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.675610966
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.248779429
Short name T382
Test name
Test status
Simulation time 6872300046 ps
CPU time 22.92 seconds
Started Aug 07 05:51:35 PM PDT 24
Finished Aug 07 05:51:58 PM PDT 24
Peak memory 198000 kb
Host smart-63a257ac-62b2-49af-872c-b3b896c46bec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=248779429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.248779429
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3244944237
Short name T174
Test name
Test status
Simulation time 81958719176 ps
CPU time 36.9 seconds
Started Aug 07 05:51:40 PM PDT 24
Finished Aug 07 05:52:17 PM PDT 24
Peak memory 199952 kb
Host smart-b881723c-8d64-47d4-b7b5-046b22a8be59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244944237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3244944237
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.4273396187
Short name T701
Test name
Test status
Simulation time 4285595551 ps
CPU time 0.97 seconds
Started Aug 07 05:51:38 PM PDT 24
Finished Aug 07 05:51:39 PM PDT 24
Peak memory 196736 kb
Host smart-5002658d-3297-49a4-84ca-980790d496fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273396187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.4273396187
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3836321022
Short name T679
Test name
Test status
Simulation time 10536172579 ps
CPU time 21.66 seconds
Started Aug 07 05:51:40 PM PDT 24
Finished Aug 07 05:52:02 PM PDT 24
Peak memory 199860 kb
Host smart-889cb224-d84a-44cb-abe7-ee4d5e427544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836321022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3836321022
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.2697566949
Short name T600
Test name
Test status
Simulation time 353273892129 ps
CPU time 620.28 seconds
Started Aug 07 05:51:40 PM PDT 24
Finished Aug 07 06:02:00 PM PDT 24
Peak memory 199880 kb
Host smart-817e4be5-821f-40e5-b3a0-9041f8bd56c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697566949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2697566949
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.936041669
Short name T1084
Test name
Test status
Simulation time 400465607587 ps
CPU time 627.82 seconds
Started Aug 07 05:51:42 PM PDT 24
Finished Aug 07 06:02:10 PM PDT 24
Peak memory 216500 kb
Host smart-fd01ebec-595f-416f-ab3b-6bd4ba6e4d75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936041669 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.936041669
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3081292877
Short name T1167
Test name
Test status
Simulation time 1834830243 ps
CPU time 2.52 seconds
Started Aug 07 05:51:43 PM PDT 24
Finished Aug 07 05:51:46 PM PDT 24
Peak memory 199260 kb
Host smart-48d2ed57-5f47-4d33-9609-ac16edfa27f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081292877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3081292877
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1226455440
Short name T628
Test name
Test status
Simulation time 48868586016 ps
CPU time 12.55 seconds
Started Aug 07 05:51:37 PM PDT 24
Finished Aug 07 05:51:50 PM PDT 24
Peak memory 199924 kb
Host smart-0515aee8-4f8c-4e47-9804-481e7a80410b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226455440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1226455440
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2145716981
Short name T630
Test name
Test status
Simulation time 20365399552 ps
CPU time 7.89 seconds
Started Aug 07 05:56:20 PM PDT 24
Finished Aug 07 05:56:28 PM PDT 24
Peak memory 199464 kb
Host smart-ddb6be2c-deaf-4156-ac67-05460d57fada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145716981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2145716981
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3674100693
Short name T120
Test name
Test status
Simulation time 86949535401 ps
CPU time 193.47 seconds
Started Aug 07 05:56:21 PM PDT 24
Finished Aug 07 05:59:34 PM PDT 24
Peak memory 199828 kb
Host smart-e8774312-a004-4d1e-b0a9-cbbcb9b49911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674100693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3674100693
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3966625484
Short name T155
Test name
Test status
Simulation time 62246941270 ps
CPU time 50.85 seconds
Started Aug 07 05:56:20 PM PDT 24
Finished Aug 07 05:57:11 PM PDT 24
Peak memory 199844 kb
Host smart-5000b0d3-5b39-4e8b-ae16-913b644e0373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966625484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3966625484
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2434738371
Short name T576
Test name
Test status
Simulation time 13006656583 ps
CPU time 18.33 seconds
Started Aug 07 05:56:20 PM PDT 24
Finished Aug 07 05:56:39 PM PDT 24
Peak memory 199908 kb
Host smart-fb637f57-e2ed-4e1f-97af-dccd67a62c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434738371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2434738371
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1891366313
Short name T225
Test name
Test status
Simulation time 235741364425 ps
CPU time 77.44 seconds
Started Aug 07 05:56:22 PM PDT 24
Finished Aug 07 05:57:40 PM PDT 24
Peak memory 200152 kb
Host smart-fe3fdce2-150e-4d05-87ea-ec4187c7cdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891366313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1891366313
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.69429094
Short name T820
Test name
Test status
Simulation time 14471189405 ps
CPU time 29.04 seconds
Started Aug 07 05:56:25 PM PDT 24
Finished Aug 07 05:56:54 PM PDT 24
Peak memory 199884 kb
Host smart-c964401a-6806-46f8-8d5f-f6df268da697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69429094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.69429094
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2946810800
Short name T342
Test name
Test status
Simulation time 38939127888 ps
CPU time 49.78 seconds
Started Aug 07 05:56:26 PM PDT 24
Finished Aug 07 05:57:16 PM PDT 24
Peak memory 199740 kb
Host smart-c33627c4-4507-4bc7-8039-b62f05eac83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946810800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2946810800
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.884123425
Short name T354
Test name
Test status
Simulation time 14013490 ps
CPU time 0.63 seconds
Started Aug 07 05:51:47 PM PDT 24
Finished Aug 07 05:51:47 PM PDT 24
Peak memory 195280 kb
Host smart-1f1ec42c-a8d8-48bc-959d-0300c84d2cdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884123425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.884123425
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2856013653
Short name T556
Test name
Test status
Simulation time 122840614752 ps
CPU time 56.88 seconds
Started Aug 07 05:51:42 PM PDT 24
Finished Aug 07 05:52:39 PM PDT 24
Peak memory 199892 kb
Host smart-f654daa2-a72a-43d6-82e4-cb9bf9246dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856013653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2856013653
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.4191761665
Short name T281
Test name
Test status
Simulation time 44461268775 ps
CPU time 64.18 seconds
Started Aug 07 05:51:43 PM PDT 24
Finished Aug 07 05:52:48 PM PDT 24
Peak memory 199792 kb
Host smart-9857e024-651e-4373-b47e-23e4341ffe4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191761665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.4191761665
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_intr.869856644
Short name T465
Test name
Test status
Simulation time 16944555075 ps
CPU time 8.86 seconds
Started Aug 07 05:51:48 PM PDT 24
Finished Aug 07 05:51:57 PM PDT 24
Peak memory 199904 kb
Host smart-dc6a68d9-7c4e-460e-97be-bb63a81d1a60
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869856644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.869856644
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1008520528
Short name T1120
Test name
Test status
Simulation time 87698357294 ps
CPU time 81.61 seconds
Started Aug 07 05:51:46 PM PDT 24
Finished Aug 07 05:53:08 PM PDT 24
Peak memory 199812 kb
Host smart-c762a24e-3ca4-4642-9ca4-59dcb399c696
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1008520528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1008520528
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.4257370022
Short name T787
Test name
Test status
Simulation time 5302617300 ps
CPU time 3.27 seconds
Started Aug 07 05:51:46 PM PDT 24
Finished Aug 07 05:51:50 PM PDT 24
Peak memory 198120 kb
Host smart-5fd1c778-4d47-4a18-82c6-7ea02e18eada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257370022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.4257370022
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3210377224
Short name T652
Test name
Test status
Simulation time 19490867980 ps
CPU time 29.62 seconds
Started Aug 07 05:51:52 PM PDT 24
Finished Aug 07 05:52:22 PM PDT 24
Peak memory 198400 kb
Host smart-c36419d2-2225-4210-9db4-dd8e4aa384cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210377224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3210377224
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.727195476
Short name T480
Test name
Test status
Simulation time 6857839243 ps
CPU time 410.37 seconds
Started Aug 07 05:51:46 PM PDT 24
Finished Aug 07 05:58:37 PM PDT 24
Peak memory 199920 kb
Host smart-2bf8ab41-9d91-4db5-8bb4-715881f027ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=727195476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.727195476
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.4088641139
Short name T351
Test name
Test status
Simulation time 6902112500 ps
CPU time 30.15 seconds
Started Aug 07 05:51:46 PM PDT 24
Finished Aug 07 05:52:16 PM PDT 24
Peak memory 198848 kb
Host smart-fb7f5e87-ba41-4a99-b4a7-304c9091b17d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4088641139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.4088641139
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1504267622
Short name T459
Test name
Test status
Simulation time 78002998212 ps
CPU time 149.45 seconds
Started Aug 07 05:51:48 PM PDT 24
Finished Aug 07 05:54:18 PM PDT 24
Peak memory 199844 kb
Host smart-0a5b3f7b-4fa6-4ce2-9bd2-5bedeff9b351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504267622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1504267622
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3944420572
Short name T418
Test name
Test status
Simulation time 4879725708 ps
CPU time 1.41 seconds
Started Aug 07 05:51:48 PM PDT 24
Finished Aug 07 05:51:49 PM PDT 24
Peak memory 196144 kb
Host smart-fc8bf426-62a5-4f70-b2d2-d545e60339a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944420572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3944420572
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.4060317737
Short name T822
Test name
Test status
Simulation time 251677323 ps
CPU time 1.2 seconds
Started Aug 07 05:51:45 PM PDT 24
Finished Aug 07 05:51:46 PM PDT 24
Peak memory 199748 kb
Host smart-e110f25a-a089-4503-876e-28ae240d4fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060317737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.4060317737
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.4201198015
Short name T626
Test name
Test status
Simulation time 190178613187 ps
CPU time 451.9 seconds
Started Aug 07 05:51:48 PM PDT 24
Finished Aug 07 05:59:20 PM PDT 24
Peak memory 215184 kb
Host smart-acf02c61-79f3-426d-827c-4ed836190518
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201198015 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.4201198015
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.4110439225
Short name T1047
Test name
Test status
Simulation time 6786164789 ps
CPU time 16.39 seconds
Started Aug 07 05:51:49 PM PDT 24
Finished Aug 07 05:52:05 PM PDT 24
Peak memory 199236 kb
Host smart-029deae9-d6ea-41da-9848-675182836757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110439225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.4110439225
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3821095001
Short name T969
Test name
Test status
Simulation time 185649407140 ps
CPU time 44.44 seconds
Started Aug 07 05:51:44 PM PDT 24
Finished Aug 07 05:52:28 PM PDT 24
Peak memory 199856 kb
Host smart-e1ea8ec0-117d-4eb2-8efb-33c4daf3a9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821095001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3821095001
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3257422900
Short name T761
Test name
Test status
Simulation time 58746516982 ps
CPU time 12.43 seconds
Started Aug 07 05:56:27 PM PDT 24
Finished Aug 07 05:56:39 PM PDT 24
Peak memory 199868 kb
Host smart-d872eace-31d9-46f6-9999-51b689220018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257422900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3257422900
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1039624828
Short name T294
Test name
Test status
Simulation time 10984469880 ps
CPU time 8.22 seconds
Started Aug 07 05:56:28 PM PDT 24
Finished Aug 07 05:56:37 PM PDT 24
Peak memory 199880 kb
Host smart-bbb264cc-6370-48a5-b6cd-1743a404b96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039624828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1039624828
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1243526419
Short name T219
Test name
Test status
Simulation time 326244976385 ps
CPU time 235.4 seconds
Started Aug 07 05:56:25 PM PDT 24
Finished Aug 07 06:00:21 PM PDT 24
Peak memory 199896 kb
Host smart-447167bc-3ae5-4327-a738-c1959223f69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243526419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1243526419
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3423150982
Short name T124
Test name
Test status
Simulation time 23125989045 ps
CPU time 31.93 seconds
Started Aug 07 05:56:26 PM PDT 24
Finished Aug 07 05:56:59 PM PDT 24
Peak memory 199896 kb
Host smart-3dbe767f-9eaf-4be5-822b-e776b0e6d8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423150982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3423150982
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.1449805227
Short name T896
Test name
Test status
Simulation time 100308519664 ps
CPU time 63.22 seconds
Started Aug 07 05:56:25 PM PDT 24
Finished Aug 07 05:57:28 PM PDT 24
Peak memory 199904 kb
Host smart-c072705e-5d2e-4ca6-965e-7a48877509fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449805227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1449805227
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2253460671
Short name T964
Test name
Test status
Simulation time 59444831289 ps
CPU time 175.76 seconds
Started Aug 07 05:56:25 PM PDT 24
Finished Aug 07 05:59:21 PM PDT 24
Peak memory 199896 kb
Host smart-87f41cd1-d178-4cca-b567-c76882aad5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253460671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2253460671
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2417110919
Short name T136
Test name
Test status
Simulation time 26284822123 ps
CPU time 23.03 seconds
Started Aug 07 05:56:26 PM PDT 24
Finished Aug 07 05:56:49 PM PDT 24
Peak memory 199844 kb
Host smart-2ad3a96c-17d8-468e-bf78-253a3de1c37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417110919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2417110919
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3008448384
Short name T1155
Test name
Test status
Simulation time 26094484154 ps
CPU time 45.31 seconds
Started Aug 07 05:56:26 PM PDT 24
Finished Aug 07 05:57:11 PM PDT 24
Peak memory 199828 kb
Host smart-c1a50a2c-507a-4a2c-b2b8-39fca752795d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008448384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3008448384
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1988945764
Short name T855
Test name
Test status
Simulation time 104702017519 ps
CPU time 71.54 seconds
Started Aug 07 05:56:24 PM PDT 24
Finished Aug 07 05:57:36 PM PDT 24
Peak memory 199928 kb
Host smart-77589709-c43b-4f6d-90ae-4343d85d9bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988945764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1988945764
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1555114299
Short name T1050
Test name
Test status
Simulation time 13093036 ps
CPU time 0.57 seconds
Started Aug 07 05:51:56 PM PDT 24
Finished Aug 07 05:51:57 PM PDT 24
Peak memory 195552 kb
Host smart-958ee10d-5c2f-4e25-b8fb-2f22f7231195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555114299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1555114299
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.421503588
Short name T772
Test name
Test status
Simulation time 22597370309 ps
CPU time 33.66 seconds
Started Aug 07 05:51:48 PM PDT 24
Finished Aug 07 05:52:22 PM PDT 24
Peak memory 199860 kb
Host smart-b66160fa-75af-4fe7-a0bc-76dae976094b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421503588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.421503588
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.698052983
Short name T441
Test name
Test status
Simulation time 41403362980 ps
CPU time 64.87 seconds
Started Aug 07 05:51:47 PM PDT 24
Finished Aug 07 05:52:52 PM PDT 24
Peak memory 199924 kb
Host smart-488a3614-ba78-4b7d-9165-29f48b0f64f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698052983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.698052983
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.967434895
Short name T869
Test name
Test status
Simulation time 34854641438 ps
CPU time 40.08 seconds
Started Aug 07 05:51:50 PM PDT 24
Finished Aug 07 05:52:30 PM PDT 24
Peak memory 199840 kb
Host smart-f2004900-bead-4aed-a6cb-b9904c944d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967434895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.967434895
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.392088194
Short name T736
Test name
Test status
Simulation time 222873187355 ps
CPU time 168.54 seconds
Started Aug 07 05:51:48 PM PDT 24
Finished Aug 07 05:54:36 PM PDT 24
Peak memory 197972 kb
Host smart-e91b8f09-ee80-469e-8106-d8bd7bda8589
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392088194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.392088194
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2235268856
Short name T1081
Test name
Test status
Simulation time 152816594969 ps
CPU time 1184.06 seconds
Started Aug 07 05:51:54 PM PDT 24
Finished Aug 07 06:11:38 PM PDT 24
Peak memory 199960 kb
Host smart-b34e6b59-46a0-4055-be00-74351eeae457
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2235268856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2235268856
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2371709515
Short name T950
Test name
Test status
Simulation time 6627436294 ps
CPU time 8.48 seconds
Started Aug 07 05:51:54 PM PDT 24
Finished Aug 07 05:52:03 PM PDT 24
Peak memory 199812 kb
Host smart-d9f2d1fd-02a5-4833-959d-76951a5bd9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371709515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2371709515
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1360375511
Short name T256
Test name
Test status
Simulation time 55693240472 ps
CPU time 43.87 seconds
Started Aug 07 05:51:51 PM PDT 24
Finished Aug 07 05:52:35 PM PDT 24
Peak memory 198552 kb
Host smart-beae6bfe-a684-4822-9df0-3b5852f05a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360375511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1360375511
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1838600737
Short name T479
Test name
Test status
Simulation time 16041312369 ps
CPU time 890.42 seconds
Started Aug 07 05:51:59 PM PDT 24
Finished Aug 07 06:06:49 PM PDT 24
Peak memory 199880 kb
Host smart-4226bd23-cd82-4ca8-b510-a49857bc7e66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1838600737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1838600737
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2041451206
Short name T1026
Test name
Test status
Simulation time 2135493565 ps
CPU time 3.31 seconds
Started Aug 07 05:51:48 PM PDT 24
Finished Aug 07 05:51:51 PM PDT 24
Peak memory 197748 kb
Host smart-ffd04dc2-f576-4f9d-a473-1c4a88bd418e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2041451206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2041451206
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.212972467
Short name T547
Test name
Test status
Simulation time 720973696 ps
CPU time 0.96 seconds
Started Aug 07 05:51:51 PM PDT 24
Finished Aug 07 05:51:53 PM PDT 24
Peak memory 195352 kb
Host smart-2bbc52e7-23b1-4267-a300-b05591f044f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212972467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.212972467
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.187466151
Short name T1039
Test name
Test status
Simulation time 484075900 ps
CPU time 1.21 seconds
Started Aug 07 05:51:48 PM PDT 24
Finished Aug 07 05:51:49 PM PDT 24
Peak memory 198172 kb
Host smart-67a54381-76c0-4e80-a9b2-b5c90278b14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187466151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.187466151
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.790721333
Short name T159
Test name
Test status
Simulation time 561195770021 ps
CPU time 408.27 seconds
Started Aug 07 05:51:50 PM PDT 24
Finished Aug 07 05:58:38 PM PDT 24
Peak memory 199860 kb
Host smart-70891054-1569-41d8-860f-606744620158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790721333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.790721333
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1751120562
Short name T246
Test name
Test status
Simulation time 6171651869 ps
CPU time 12.03 seconds
Started Aug 07 05:51:52 PM PDT 24
Finished Aug 07 05:52:04 PM PDT 24
Peak memory 199876 kb
Host smart-8a91ec8d-a28e-4abe-9588-c24ee5c83005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751120562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1751120562
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.931102747
Short name T1043
Test name
Test status
Simulation time 273382879988 ps
CPU time 89.22 seconds
Started Aug 07 05:51:52 PM PDT 24
Finished Aug 07 05:53:21 PM PDT 24
Peak memory 200156 kb
Host smart-35c113dd-cb79-4af5-ac79-c3f75ff175d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931102747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.931102747
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2054581537
Short name T128
Test name
Test status
Simulation time 184598417749 ps
CPU time 142.39 seconds
Started Aug 07 05:56:32 PM PDT 24
Finished Aug 07 05:58:54 PM PDT 24
Peak memory 199864 kb
Host smart-44b25193-a677-4929-995e-2731e913184f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054581537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2054581537
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.159466213
Short name T237
Test name
Test status
Simulation time 53831614788 ps
CPU time 41.46 seconds
Started Aug 07 05:56:31 PM PDT 24
Finished Aug 07 05:57:13 PM PDT 24
Peak memory 199828 kb
Host smart-a6b067cd-7bfb-40de-b63f-780374b1ff49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159466213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.159466213
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3466321893
Short name T1105
Test name
Test status
Simulation time 99259503637 ps
CPU time 118.51 seconds
Started Aug 07 05:56:33 PM PDT 24
Finished Aug 07 05:58:32 PM PDT 24
Peak memory 199800 kb
Host smart-ce73e422-fd75-49b4-aee6-be1be6340efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466321893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3466321893
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2543399403
Short name T806
Test name
Test status
Simulation time 29008282335 ps
CPU time 32.94 seconds
Started Aug 07 05:56:32 PM PDT 24
Finished Aug 07 05:57:05 PM PDT 24
Peak memory 199872 kb
Host smart-ad5c9a15-ce9c-4eb7-a87a-2a6fe707f224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543399403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2543399403
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3148802087
Short name T119
Test name
Test status
Simulation time 13840657658 ps
CPU time 14.59 seconds
Started Aug 07 05:56:33 PM PDT 24
Finished Aug 07 05:56:48 PM PDT 24
Peak memory 199860 kb
Host smart-8c3ce9cb-08b8-4e52-8f5c-3445d6dc011d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148802087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3148802087
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.450934558
Short name T393
Test name
Test status
Simulation time 138141213096 ps
CPU time 229.52 seconds
Started Aug 07 05:56:34 PM PDT 24
Finished Aug 07 06:00:23 PM PDT 24
Peak memory 199780 kb
Host smart-c9076215-8084-4bb9-9210-b4485fb44ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450934558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.450934558
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.719167481
Short name T177
Test name
Test status
Simulation time 57431019014 ps
CPU time 30.25 seconds
Started Aug 07 05:56:31 PM PDT 24
Finished Aug 07 05:57:02 PM PDT 24
Peak memory 199884 kb
Host smart-7120d193-c948-4a93-8858-04c178dfd943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719167481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.719167481
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.412452737
Short name T105
Test name
Test status
Simulation time 118657379693 ps
CPU time 112.78 seconds
Started Aug 07 05:56:34 PM PDT 24
Finished Aug 07 05:58:27 PM PDT 24
Peak memory 199880 kb
Host smart-d99687dd-0b20-4f96-9cb8-45e7dc273d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412452737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.412452737
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1068629923
Short name T462
Test name
Test status
Simulation time 21138082480 ps
CPU time 19.36 seconds
Started Aug 07 05:56:35 PM PDT 24
Finished Aug 07 05:56:55 PM PDT 24
Peak memory 199876 kb
Host smart-f579c6f0-6ed3-4c7d-971c-279fdb647b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068629923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1068629923
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2978313736
Short name T612
Test name
Test status
Simulation time 14338504 ps
CPU time 0.57 seconds
Started Aug 07 05:51:59 PM PDT 24
Finished Aug 07 05:51:59 PM PDT 24
Peak memory 195220 kb
Host smart-236079c6-9044-4ae8-bc18-9267df2d5986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978313736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2978313736
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2178076702
Short name T608
Test name
Test status
Simulation time 16862396851 ps
CPU time 28.86 seconds
Started Aug 07 05:51:54 PM PDT 24
Finished Aug 07 05:52:23 PM PDT 24
Peak memory 199920 kb
Host smart-a7a7c46e-67f1-4241-8e15-747be8b87ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178076702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2178076702
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3012182979
Short name T835
Test name
Test status
Simulation time 132503122494 ps
CPU time 49.92 seconds
Started Aug 07 05:51:59 PM PDT 24
Finished Aug 07 05:52:49 PM PDT 24
Peak memory 199820 kb
Host smart-8bf8d220-6233-4d13-887d-df9c06899192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012182979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3012182979
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1514833592
Short name T996
Test name
Test status
Simulation time 128249184101 ps
CPU time 36.62 seconds
Started Aug 07 05:51:53 PM PDT 24
Finished Aug 07 05:52:29 PM PDT 24
Peak memory 199888 kb
Host smart-22833b38-b981-4901-b76b-77a91a523bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514833592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1514833592
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.3394813905
Short name T1174
Test name
Test status
Simulation time 4113642107 ps
CPU time 7.02 seconds
Started Aug 07 05:51:53 PM PDT 24
Finished Aug 07 05:52:00 PM PDT 24
Peak memory 196748 kb
Host smart-310bc371-2771-456b-b155-1030b7a5dbc9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394813905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3394813905
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2768199287
Short name T763
Test name
Test status
Simulation time 220906771308 ps
CPU time 167.05 seconds
Started Aug 07 05:52:00 PM PDT 24
Finished Aug 07 05:54:48 PM PDT 24
Peak memory 199852 kb
Host smart-1aee9add-a24a-454f-8b90-b4089659a7f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2768199287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2768199287
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3205853211
Short name T999
Test name
Test status
Simulation time 2636713296 ps
CPU time 1.63 seconds
Started Aug 07 05:51:57 PM PDT 24
Finished Aug 07 05:51:58 PM PDT 24
Peak memory 196280 kb
Host smart-767cabd4-6b8d-4317-b33d-5dbb927cc91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205853211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3205853211
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.3487538000
Short name T249
Test name
Test status
Simulation time 39308940297 ps
CPU time 16.51 seconds
Started Aug 07 05:51:54 PM PDT 24
Finished Aug 07 05:52:11 PM PDT 24
Peak memory 199852 kb
Host smart-b7c4f939-5797-4621-a6b5-cba93e76008e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487538000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3487538000
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2808212443
Short name T783
Test name
Test status
Simulation time 5243763955 ps
CPU time 82.93 seconds
Started Aug 07 05:51:57 PM PDT 24
Finished Aug 07 05:53:20 PM PDT 24
Peak memory 199944 kb
Host smart-424aed08-fe9d-4885-aae1-bf02bfb2a030
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2808212443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2808212443
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1916578112
Short name T814
Test name
Test status
Simulation time 6857223374 ps
CPU time 61.53 seconds
Started Aug 07 05:51:59 PM PDT 24
Finished Aug 07 05:53:00 PM PDT 24
Peak memory 197916 kb
Host smart-09233e6e-19aa-4eee-8c93-15d32164d79a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1916578112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1916578112
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.184598450
Short name T977
Test name
Test status
Simulation time 88014088865 ps
CPU time 142.11 seconds
Started Aug 07 05:51:52 PM PDT 24
Finished Aug 07 05:54:15 PM PDT 24
Peak memory 199920 kb
Host smart-3fbcc224-4921-4ee0-ba0f-2df9f4ca8f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184598450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.184598450
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.4197709869
Short name T619
Test name
Test status
Simulation time 35136156016 ps
CPU time 26.7 seconds
Started Aug 07 05:51:52 PM PDT 24
Finished Aug 07 05:52:19 PM PDT 24
Peak memory 195752 kb
Host smart-9b5ff4bd-5f31-47be-a88a-041259636b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197709869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.4197709869
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.970028851
Short name T904
Test name
Test status
Simulation time 5899588549 ps
CPU time 12.09 seconds
Started Aug 07 05:51:53 PM PDT 24
Finished Aug 07 05:52:06 PM PDT 24
Peak memory 199868 kb
Host smart-5e3bdb0f-54b1-431d-988b-b0d11d28026e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970028851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.970028851
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.1558563512
Short name T357
Test name
Test status
Simulation time 180561317548 ps
CPU time 591.36 seconds
Started Aug 07 05:51:57 PM PDT 24
Finished Aug 07 06:01:49 PM PDT 24
Peak memory 208664 kb
Host smart-97c82bf2-ca2d-491f-98e8-a4d18187a86d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558563512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1558563512
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2588142483
Short name T427
Test name
Test status
Simulation time 2581830738 ps
CPU time 3.49 seconds
Started Aug 07 05:51:50 PM PDT 24
Finished Aug 07 05:51:55 PM PDT 24
Peak memory 199580 kb
Host smart-10821408-4fb8-42a3-ada5-593731cc68cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588142483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2588142483
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1858463458
Short name T1087
Test name
Test status
Simulation time 30693730604 ps
CPU time 14.63 seconds
Started Aug 07 05:51:53 PM PDT 24
Finished Aug 07 05:52:08 PM PDT 24
Peak memory 199832 kb
Host smart-432f9da0-8165-4e53-9788-6b587a87701b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858463458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1858463458
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1371317903
Short name T199
Test name
Test status
Simulation time 34444333482 ps
CPU time 29.74 seconds
Started Aug 07 05:56:33 PM PDT 24
Finished Aug 07 05:57:02 PM PDT 24
Peak memory 199924 kb
Host smart-0da65e0e-28c9-48e3-ae69-b776bf3b4bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371317903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1371317903
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2360276381
Short name T754
Test name
Test status
Simulation time 20724808132 ps
CPU time 30.48 seconds
Started Aug 07 05:56:40 PM PDT 24
Finished Aug 07 05:57:11 PM PDT 24
Peak memory 200148 kb
Host smart-af090029-5286-4d4b-aa1e-5ee5aca7edb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360276381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2360276381
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1226362275
Short name T1053
Test name
Test status
Simulation time 24674892633 ps
CPU time 29.34 seconds
Started Aug 07 05:56:42 PM PDT 24
Finished Aug 07 05:57:11 PM PDT 24
Peak memory 199944 kb
Host smart-be895fd1-5bfa-4b89-b3ad-6fea4845133c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226362275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1226362275
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1326537806
Short name T72
Test name
Test status
Simulation time 85930111522 ps
CPU time 43.45 seconds
Started Aug 07 05:56:40 PM PDT 24
Finished Aug 07 05:57:23 PM PDT 24
Peak memory 199844 kb
Host smart-3a1ee70c-7cdf-44d2-a849-3c88fd2501d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326537806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1326537806
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.744973622
Short name T190
Test name
Test status
Simulation time 98896511251 ps
CPU time 146.35 seconds
Started Aug 07 05:56:40 PM PDT 24
Finished Aug 07 05:59:06 PM PDT 24
Peak memory 199780 kb
Host smart-13e8d83c-758a-4b56-a31e-85d16f94639f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744973622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.744973622
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2938344053
Short name T180
Test name
Test status
Simulation time 48976119718 ps
CPU time 124.88 seconds
Started Aug 07 05:56:39 PM PDT 24
Finished Aug 07 05:58:44 PM PDT 24
Peak memory 199928 kb
Host smart-c99e5d7a-5438-466b-94c4-a78802a8ae31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938344053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2938344053
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1364683934
Short name T934
Test name
Test status
Simulation time 23862403469 ps
CPU time 10.82 seconds
Started Aug 07 05:56:38 PM PDT 24
Finished Aug 07 05:56:49 PM PDT 24
Peak memory 199936 kb
Host smart-ad1374ca-2445-4d5e-ba2e-c425d9565cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364683934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1364683934
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.906600671
Short name T104
Test name
Test status
Simulation time 92967077514 ps
CPU time 144.31 seconds
Started Aug 07 05:56:47 PM PDT 24
Finished Aug 07 05:59:11 PM PDT 24
Peak memory 199948 kb
Host smart-30bdd20a-b98a-4295-a60d-0d2f30db6418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906600671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.906600671
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.4209286831
Short name T409
Test name
Test status
Simulation time 110358607020 ps
CPU time 152.49 seconds
Started Aug 07 05:56:47 PM PDT 24
Finished Aug 07 05:59:20 PM PDT 24
Peak memory 199944 kb
Host smart-8b6666d6-f247-41b4-893c-6de3da1c9542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209286831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.4209286831
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2550196876
Short name T27
Test name
Test status
Simulation time 19534296 ps
CPU time 0.58 seconds
Started Aug 07 05:52:03 PM PDT 24
Finished Aug 07 05:52:04 PM PDT 24
Peak memory 195272 kb
Host smart-589085ab-96e3-462a-a429-7776adcf4920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550196876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2550196876
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3277245576
Short name T714
Test name
Test status
Simulation time 94914148591 ps
CPU time 150.46 seconds
Started Aug 07 05:51:58 PM PDT 24
Finished Aug 07 05:54:28 PM PDT 24
Peak memory 199880 kb
Host smart-ad0816df-5259-4001-8e6c-9d9f0c53d979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277245576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3277245576
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1309719595
Short name T455
Test name
Test status
Simulation time 31900638245 ps
CPU time 26.51 seconds
Started Aug 07 05:51:56 PM PDT 24
Finished Aug 07 05:52:23 PM PDT 24
Peak memory 199892 kb
Host smart-733404e0-c053-4461-a005-78b4266b3688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309719595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1309719595
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3711873479
Short name T639
Test name
Test status
Simulation time 19642795023 ps
CPU time 35.33 seconds
Started Aug 07 05:51:58 PM PDT 24
Finished Aug 07 05:52:33 PM PDT 24
Peak memory 199864 kb
Host smart-44359134-bba5-4f9f-9a94-2dbdb1aa27ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711873479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3711873479
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.875274635
Short name T487
Test name
Test status
Simulation time 32708961815 ps
CPU time 20.7 seconds
Started Aug 07 05:52:03 PM PDT 24
Finished Aug 07 05:52:24 PM PDT 24
Peak memory 199880 kb
Host smart-b4724e56-d81c-4304-9b0b-a38427c0e7c3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875274635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.875274635
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.908859157
Short name T437
Test name
Test status
Simulation time 149578023468 ps
CPU time 1398 seconds
Started Aug 07 05:52:04 PM PDT 24
Finished Aug 07 06:15:22 PM PDT 24
Peak memory 199808 kb
Host smart-14e7caa2-e8f8-4b52-8d7c-44035107bf0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=908859157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.908859157
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.191114694
Short name T327
Test name
Test status
Simulation time 2053864070 ps
CPU time 3.85 seconds
Started Aug 07 05:52:05 PM PDT 24
Finished Aug 07 05:52:09 PM PDT 24
Peak memory 196368 kb
Host smart-74a7c405-8d12-46ff-a5be-4eab09d5e4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191114694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.191114694
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3611222399
Short name T844
Test name
Test status
Simulation time 10397379941 ps
CPU time 7.62 seconds
Started Aug 07 05:52:05 PM PDT 24
Finished Aug 07 05:52:13 PM PDT 24
Peak memory 196588 kb
Host smart-69cfdbb0-0379-4a0b-bbc4-12af81135748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611222399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3611222399
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2074865796
Short name T994
Test name
Test status
Simulation time 7385249373 ps
CPU time 39.62 seconds
Started Aug 07 05:52:05 PM PDT 24
Finished Aug 07 05:52:45 PM PDT 24
Peak memory 199880 kb
Host smart-7705ec4d-e653-4964-9a5a-58a513a8ef22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2074865796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2074865796
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2286045043
Short name T1055
Test name
Test status
Simulation time 3165070430 ps
CPU time 19.37 seconds
Started Aug 07 05:52:03 PM PDT 24
Finished Aug 07 05:52:23 PM PDT 24
Peak memory 198200 kb
Host smart-8a127333-00ef-424c-b82f-a6c6d5560a78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2286045043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2286045043
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2901346907
Short name T165
Test name
Test status
Simulation time 57222371927 ps
CPU time 33.13 seconds
Started Aug 07 05:52:01 PM PDT 24
Finished Aug 07 05:52:34 PM PDT 24
Peak memory 199940 kb
Host smart-c46536cd-32d7-41b0-a15e-2f744ec33086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901346907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2901346907
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.896787193
Short name T304
Test name
Test status
Simulation time 3373299437 ps
CPU time 5.18 seconds
Started Aug 07 05:52:03 PM PDT 24
Finished Aug 07 05:52:08 PM PDT 24
Peak memory 196452 kb
Host smart-1333a132-213f-4b88-96be-b2512db3a321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896787193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.896787193
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2481514309
Short name T358
Test name
Test status
Simulation time 900241557 ps
CPU time 2.57 seconds
Started Aug 07 05:51:56 PM PDT 24
Finished Aug 07 05:51:59 PM PDT 24
Peak memory 198144 kb
Host smart-a5bf2689-4b9a-4107-a1d5-ca3d5ff036b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481514309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2481514309
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.573466451
Short name T1049
Test name
Test status
Simulation time 253363433583 ps
CPU time 2245.75 seconds
Started Aug 07 05:52:04 PM PDT 24
Finished Aug 07 06:29:30 PM PDT 24
Peak memory 199920 kb
Host smart-abcca06d-9f41-4f27-9a64-092c786f02cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573466451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.573466451
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1371591384
Short name T832
Test name
Test status
Simulation time 799468996372 ps
CPU time 745.16 seconds
Started Aug 07 05:52:02 PM PDT 24
Finished Aug 07 06:04:28 PM PDT 24
Peak memory 224732 kb
Host smart-4326b69b-0eed-47fd-b1db-3a3ec87bd805
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371591384 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1371591384
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.3295028165
Short name T699
Test name
Test status
Simulation time 659152547 ps
CPU time 2.79 seconds
Started Aug 07 05:52:03 PM PDT 24
Finished Aug 07 05:52:06 PM PDT 24
Peak memory 198772 kb
Host smart-39944ddb-a365-4c9f-971e-0c0a99d00ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295028165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3295028165
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2617780809
Short name T548
Test name
Test status
Simulation time 80905542654 ps
CPU time 34.24 seconds
Started Aug 07 05:51:57 PM PDT 24
Finished Aug 07 05:52:32 PM PDT 24
Peak memory 199924 kb
Host smart-8b97cbca-5612-4a86-a37d-f59a327086e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617780809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2617780809
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.471318468
Short name T785
Test name
Test status
Simulation time 119941228047 ps
CPU time 217.01 seconds
Started Aug 07 05:56:52 PM PDT 24
Finished Aug 07 06:00:30 PM PDT 24
Peak memory 199796 kb
Host smart-e01dd1aa-6de8-4ffa-a80d-88088557d36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471318468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.471318468
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.2914960102
Short name T222
Test name
Test status
Simulation time 16497237192 ps
CPU time 27.85 seconds
Started Aug 07 05:56:47 PM PDT 24
Finished Aug 07 05:57:15 PM PDT 24
Peak memory 199888 kb
Host smart-ab0f8232-38ed-4833-b2c7-a681f46d2b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914960102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2914960102
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2869881706
Short name T1107
Test name
Test status
Simulation time 25371733862 ps
CPU time 9.39 seconds
Started Aug 07 05:56:45 PM PDT 24
Finished Aug 07 05:56:55 PM PDT 24
Peak memory 199552 kb
Host smart-8434fa96-36b8-488e-86ec-e6a599171162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869881706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2869881706
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.4127762310
Short name T446
Test name
Test status
Simulation time 55839440035 ps
CPU time 25.49 seconds
Started Aug 07 05:56:50 PM PDT 24
Finished Aug 07 05:57:16 PM PDT 24
Peak memory 199912 kb
Host smart-45a040a9-e4fb-423e-8002-0ae2da03626f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127762310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.4127762310
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1710767161
Short name T243
Test name
Test status
Simulation time 69882769679 ps
CPU time 16.5 seconds
Started Aug 07 05:56:47 PM PDT 24
Finished Aug 07 05:57:04 PM PDT 24
Peak memory 199816 kb
Host smart-63a82a19-dbbc-4a78-9b38-c4f181f596fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710767161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1710767161
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.551150818
Short name T963
Test name
Test status
Simulation time 94518142392 ps
CPU time 25.94 seconds
Started Aug 07 05:56:46 PM PDT 24
Finished Aug 07 05:57:12 PM PDT 24
Peak memory 199904 kb
Host smart-15866047-364a-411f-aa50-ef9cfcafacc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551150818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.551150818
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1183927941
Short name T1069
Test name
Test status
Simulation time 8958843350 ps
CPU time 16.51 seconds
Started Aug 07 05:56:47 PM PDT 24
Finished Aug 07 05:57:04 PM PDT 24
Peak memory 199884 kb
Host smart-140ed59d-1cad-4f1a-9b7c-fd2cf2f64d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183927941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1183927941
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.449896362
Short name T430
Test name
Test status
Simulation time 40838595705 ps
CPU time 29.41 seconds
Started Aug 07 05:56:47 PM PDT 24
Finished Aug 07 05:57:16 PM PDT 24
Peak memory 199856 kb
Host smart-0cb6cce9-588b-415c-96d6-bfef2bb3e54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449896362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.449896362
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.4034459885
Short name T1011
Test name
Test status
Simulation time 81177659409 ps
CPU time 22.98 seconds
Started Aug 07 05:56:46 PM PDT 24
Finished Aug 07 05:57:09 PM PDT 24
Peak memory 199884 kb
Host smart-2ba07b0e-9084-45db-a0c3-4d5b31d5b8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034459885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.4034459885
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.432210721
Short name T378
Test name
Test status
Simulation time 19044041 ps
CPU time 0.56 seconds
Started Aug 07 05:52:08 PM PDT 24
Finished Aug 07 05:52:09 PM PDT 24
Peak memory 194528 kb
Host smart-5f7ba2dd-4fe6-4ee6-a64d-cf98357e2edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432210721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.432210721
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3520726289
Short name T752
Test name
Test status
Simulation time 124234550456 ps
CPU time 103.25 seconds
Started Aug 07 05:52:07 PM PDT 24
Finished Aug 07 05:53:51 PM PDT 24
Peak memory 199832 kb
Host smart-ad1b9535-5259-4eef-9aa5-7ac86d970b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520726289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3520726289
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.902792214
Short name T458
Test name
Test status
Simulation time 28890491393 ps
CPU time 43.97 seconds
Started Aug 07 05:52:08 PM PDT 24
Finished Aug 07 05:52:52 PM PDT 24
Peak memory 199916 kb
Host smart-6c299f05-c4e1-4811-ba8c-a3ffffe0c7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902792214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.902792214
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_intr.623115622
Short name T363
Test name
Test status
Simulation time 12470146174 ps
CPU time 20.87 seconds
Started Aug 07 05:52:07 PM PDT 24
Finished Aug 07 05:52:28 PM PDT 24
Peak memory 199700 kb
Host smart-9c787288-ab77-4518-96f3-5633c6cd3fa9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623115622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.623115622
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2482262342
Short name T346
Test name
Test status
Simulation time 67963741674 ps
CPU time 212.72 seconds
Started Aug 07 05:52:07 PM PDT 24
Finished Aug 07 05:55:40 PM PDT 24
Peak memory 199828 kb
Host smart-91de26cd-0a29-4597-ae66-b1272e9f515e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2482262342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2482262342
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.191928403
Short name T572
Test name
Test status
Simulation time 1820214340 ps
CPU time 2.44 seconds
Started Aug 07 05:52:08 PM PDT 24
Finished Aug 07 05:52:11 PM PDT 24
Peak memory 197576 kb
Host smart-8cb9ae45-e06b-4c16-8a7d-88561ff70c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191928403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.191928403
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.23283411
Short name T703
Test name
Test status
Simulation time 63889826094 ps
CPU time 94.06 seconds
Started Aug 07 05:52:07 PM PDT 24
Finished Aug 07 05:53:42 PM PDT 24
Peak memory 198564 kb
Host smart-3c54cf6b-6459-4bf9-9338-ccda5054150e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23283411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.23283411
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1078174565
Short name T521
Test name
Test status
Simulation time 18766693130 ps
CPU time 248.13 seconds
Started Aug 07 05:52:12 PM PDT 24
Finished Aug 07 05:56:20 PM PDT 24
Peak memory 199916 kb
Host smart-606cbf8c-8d64-4726-be52-f5fedcbde01a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1078174565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1078174565
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.124983950
Short name T579
Test name
Test status
Simulation time 6788299044 ps
CPU time 25.58 seconds
Started Aug 07 05:52:08 PM PDT 24
Finished Aug 07 05:52:33 PM PDT 24
Peak memory 197756 kb
Host smart-22f230a0-a00b-438d-90a7-e1c0fb27236f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=124983950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.124983950
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2824974288
Short name T894
Test name
Test status
Simulation time 28700859660 ps
CPU time 12.22 seconds
Started Aug 07 05:52:09 PM PDT 24
Finished Aug 07 05:52:21 PM PDT 24
Peak memory 199920 kb
Host smart-816e8b63-d24b-452c-8d2e-bd6645812cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824974288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2824974288
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.398946518
Short name T330
Test name
Test status
Simulation time 3201242440 ps
CPU time 4.34 seconds
Started Aug 07 05:52:09 PM PDT 24
Finished Aug 07 05:52:14 PM PDT 24
Peak memory 195828 kb
Host smart-2a12aeeb-9896-459f-8ed6-83cdf30deb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398946518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.398946518
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.124262450
Short name T675
Test name
Test status
Simulation time 494512641 ps
CPU time 1.53 seconds
Started Aug 07 05:52:03 PM PDT 24
Finished Aug 07 05:52:04 PM PDT 24
Peak memory 198656 kb
Host smart-db264329-f65d-40ae-a360-680e1dfa0a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124262450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.124262450
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3417530705
Short name T961
Test name
Test status
Simulation time 153659325646 ps
CPU time 127.56 seconds
Started Aug 07 05:52:11 PM PDT 24
Finished Aug 07 05:54:18 PM PDT 24
Peak memory 208244 kb
Host smart-b31198ff-3678-46b9-8509-a8041f7ee276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417530705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3417530705
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1074586550
Short name T408
Test name
Test status
Simulation time 12566259636 ps
CPU time 47.03 seconds
Started Aug 07 05:52:08 PM PDT 24
Finished Aug 07 05:52:56 PM PDT 24
Peak memory 199824 kb
Host smart-412c1d57-1e9b-4fa3-a4a8-c67c85e77c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074586550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1074586550
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3774708158
Short name T670
Test name
Test status
Simulation time 278060226111 ps
CPU time 71.37 seconds
Started Aug 07 05:52:07 PM PDT 24
Finished Aug 07 05:53:19 PM PDT 24
Peak memory 199860 kb
Host smart-dff18536-937c-4d89-a1b4-96b65e4706c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774708158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3774708158
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.3760000082
Short name T118
Test name
Test status
Simulation time 15368353001 ps
CPU time 22.96 seconds
Started Aug 07 05:56:46 PM PDT 24
Finished Aug 07 05:57:09 PM PDT 24
Peak memory 199800 kb
Host smart-8e07c6e5-8433-47d4-a9fb-7b77a65eb97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760000082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3760000082
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3971355112
Short name T164
Test name
Test status
Simulation time 16228250820 ps
CPU time 20.47 seconds
Started Aug 07 05:56:46 PM PDT 24
Finished Aug 07 05:57:07 PM PDT 24
Peak memory 199944 kb
Host smart-17427e3b-7e40-46dd-96cf-ec20c56312b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971355112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3971355112
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.288526154
Short name T993
Test name
Test status
Simulation time 162981520000 ps
CPU time 67.11 seconds
Started Aug 07 05:56:45 PM PDT 24
Finished Aug 07 05:57:52 PM PDT 24
Peak memory 199896 kb
Host smart-9b91c9df-b70f-46fd-9faa-d9e6583b903e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288526154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.288526154
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1913559488
Short name T921
Test name
Test status
Simulation time 40447211233 ps
CPU time 18.01 seconds
Started Aug 07 05:56:51 PM PDT 24
Finished Aug 07 05:57:09 PM PDT 24
Peak memory 199852 kb
Host smart-e9f03fac-e40a-4c89-bd33-a8a81b9a7e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913559488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1913559488
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.652606222
Short name T200
Test name
Test status
Simulation time 25886570708 ps
CPU time 45.87 seconds
Started Aug 07 05:56:50 PM PDT 24
Finished Aug 07 05:57:36 PM PDT 24
Peak memory 199924 kb
Host smart-0ff92696-673a-4826-b2de-eccd16b9e81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652606222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.652606222
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.114058382
Short name T1176
Test name
Test status
Simulation time 17316878803 ps
CPU time 27.12 seconds
Started Aug 07 05:56:51 PM PDT 24
Finished Aug 07 05:57:18 PM PDT 24
Peak memory 199796 kb
Host smart-1ad05688-6b0a-4b97-9561-af1a64fc5998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114058382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.114058382
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1251386733
Short name T207
Test name
Test status
Simulation time 10043172742 ps
CPU time 17.53 seconds
Started Aug 07 05:56:55 PM PDT 24
Finished Aug 07 05:57:13 PM PDT 24
Peak memory 199848 kb
Host smart-85a9856d-fc1f-4c41-bfb9-1b023c8c6f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251386733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1251386733
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.136053576
Short name T154
Test name
Test status
Simulation time 28788850652 ps
CPU time 36.32 seconds
Started Aug 07 05:56:52 PM PDT 24
Finished Aug 07 05:57:28 PM PDT 24
Peak memory 199916 kb
Host smart-4fdd7152-c4c1-460b-92fd-9a2b9e63ce82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136053576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.136053576
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2187924940
Short name T795
Test name
Test status
Simulation time 55217591426 ps
CPU time 47.58 seconds
Started Aug 07 05:56:52 PM PDT 24
Finished Aug 07 05:57:40 PM PDT 24
Peak memory 199888 kb
Host smart-dac5026f-49f5-46c1-bf13-85ea3100b22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187924940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2187924940
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.279640563
Short name T92
Test name
Test status
Simulation time 83074410 ps
CPU time 0.54 seconds
Started Aug 07 05:52:11 PM PDT 24
Finished Aug 07 05:52:12 PM PDT 24
Peak memory 194208 kb
Host smart-3f292294-fecf-4248-8376-947d49c20e11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279640563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.279640563
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3396663684
Short name T809
Test name
Test status
Simulation time 88757805921 ps
CPU time 35.04 seconds
Started Aug 07 05:52:09 PM PDT 24
Finished Aug 07 05:52:44 PM PDT 24
Peak memory 199868 kb
Host smart-415d8c08-2443-4fc7-be47-a737029f9a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396663684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3396663684
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1008451203
Short name T570
Test name
Test status
Simulation time 77889856110 ps
CPU time 120.85 seconds
Started Aug 07 05:52:07 PM PDT 24
Finished Aug 07 05:54:08 PM PDT 24
Peak memory 199928 kb
Host smart-89606456-a6c4-40c9-918d-efe5ef62a655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008451203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1008451203
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3517336282
Short name T502
Test name
Test status
Simulation time 105302841195 ps
CPU time 73.05 seconds
Started Aug 07 05:52:15 PM PDT 24
Finished Aug 07 05:53:28 PM PDT 24
Peak memory 199828 kb
Host smart-976749fa-f536-41b1-a839-80b3c2d26fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517336282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3517336282
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3484059245
Short name T271
Test name
Test status
Simulation time 84145832306 ps
CPU time 73.88 seconds
Started Aug 07 05:52:17 PM PDT 24
Finished Aug 07 05:53:31 PM PDT 24
Peak memory 198972 kb
Host smart-5fb88a41-f9f8-4bc5-97cb-20895b7ce43d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484059245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3484059245
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.4142537916
Short name T424
Test name
Test status
Simulation time 54407149669 ps
CPU time 430.86 seconds
Started Aug 07 05:52:17 PM PDT 24
Finished Aug 07 05:59:28 PM PDT 24
Peak memory 198976 kb
Host smart-dec3200b-a813-497c-a638-498980e2d2bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4142537916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.4142537916
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.716315980
Short name T329
Test name
Test status
Simulation time 7715354566 ps
CPU time 6.84 seconds
Started Aug 07 05:52:10 PM PDT 24
Finished Aug 07 05:52:17 PM PDT 24
Peak memory 199836 kb
Host smart-74081cb5-68c2-4a71-b5ad-6d20bd716692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716315980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.716315980
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2099365920
Short name T537
Test name
Test status
Simulation time 71339892011 ps
CPU time 21.9 seconds
Started Aug 07 05:52:15 PM PDT 24
Finished Aug 07 05:52:37 PM PDT 24
Peak memory 198812 kb
Host smart-c9dcbf2a-a2b2-48ee-98e9-d01a0021fc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099365920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2099365920
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3618313376
Short name T817
Test name
Test status
Simulation time 9178574711 ps
CPU time 257.35 seconds
Started Aug 07 05:52:12 PM PDT 24
Finished Aug 07 05:56:30 PM PDT 24
Peak memory 199860 kb
Host smart-8ee504b1-beb7-45d7-a031-6c2343f7442a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3618313376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3618313376
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1564471917
Short name T403
Test name
Test status
Simulation time 5141471003 ps
CPU time 22.64 seconds
Started Aug 07 05:52:11 PM PDT 24
Finished Aug 07 05:52:34 PM PDT 24
Peak memory 198076 kb
Host smart-7d08e39f-f584-4d99-b84f-8aa6e68174da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1564471917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1564471917
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3325218463
Short name T388
Test name
Test status
Simulation time 162808990211 ps
CPU time 22.35 seconds
Started Aug 07 05:52:14 PM PDT 24
Finished Aug 07 05:52:36 PM PDT 24
Peak memory 198376 kb
Host smart-3c68794d-6df8-4988-80b2-1bbc6a07e261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325218463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3325218463
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2969448752
Short name T1119
Test name
Test status
Simulation time 19506142129 ps
CPU time 32.14 seconds
Started Aug 07 05:52:16 PM PDT 24
Finished Aug 07 05:52:49 PM PDT 24
Peak memory 195352 kb
Host smart-1d6af448-e827-41e4-a369-c12ab07a9d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969448752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2969448752
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1627100201
Short name T725
Test name
Test status
Simulation time 257053697 ps
CPU time 1 seconds
Started Aug 07 05:52:08 PM PDT 24
Finished Aug 07 05:52:09 PM PDT 24
Peak memory 198916 kb
Host smart-9c1cff50-d229-4f19-92d7-ac7653c99101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627100201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1627100201
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.3241924421
Short name T442
Test name
Test status
Simulation time 95198712878 ps
CPU time 627.03 seconds
Started Aug 07 05:52:12 PM PDT 24
Finished Aug 07 06:02:40 PM PDT 24
Peak memory 199896 kb
Host smart-f552343c-d47c-4680-8c9d-3afa2aae9e39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241924421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3241924421
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.2805154380
Short name T819
Test name
Test status
Simulation time 488504551697 ps
CPU time 786.97 seconds
Started Aug 07 05:52:12 PM PDT 24
Finished Aug 07 06:05:19 PM PDT 24
Peak memory 229020 kb
Host smart-fe1a1cd5-e45c-4985-a671-ef8577fa9ae2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805154380 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.2805154380
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2896647097
Short name T949
Test name
Test status
Simulation time 1379876803 ps
CPU time 3.19 seconds
Started Aug 07 05:52:12 PM PDT 24
Finished Aug 07 05:52:15 PM PDT 24
Peak memory 198312 kb
Host smart-e9356a4b-64f1-4873-9626-727e8f0719d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896647097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2896647097
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2393398836
Short name T826
Test name
Test status
Simulation time 39109956608 ps
CPU time 16.3 seconds
Started Aug 07 05:52:09 PM PDT 24
Finished Aug 07 05:52:25 PM PDT 24
Peak memory 199664 kb
Host smart-30869196-8baa-49f6-866c-dc086fcc7f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393398836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2393398836
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.53945453
Short name T677
Test name
Test status
Simulation time 63124467059 ps
CPU time 31.97 seconds
Started Aug 07 05:56:53 PM PDT 24
Finished Aug 07 05:57:25 PM PDT 24
Peak memory 199848 kb
Host smart-12dc3683-a911-4a4c-bc3f-5ef580430f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53945453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.53945453
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2017648322
Short name T802
Test name
Test status
Simulation time 20746978587 ps
CPU time 8.36 seconds
Started Aug 07 05:56:51 PM PDT 24
Finished Aug 07 05:56:59 PM PDT 24
Peak memory 199848 kb
Host smart-d689d79b-0912-49bf-adae-cdb9247c9d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017648322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2017648322
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.4274138281
Short name T749
Test name
Test status
Simulation time 61474880756 ps
CPU time 23.96 seconds
Started Aug 07 05:56:51 PM PDT 24
Finished Aug 07 05:57:15 PM PDT 24
Peak memory 199756 kb
Host smart-5559d426-6053-4185-9790-192a43c2ddd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274138281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.4274138281
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1788624440
Short name T95
Test name
Test status
Simulation time 9617125157 ps
CPU time 28.54 seconds
Started Aug 07 05:56:52 PM PDT 24
Finished Aug 07 05:57:21 PM PDT 24
Peak memory 200152 kb
Host smart-067ff081-6f9e-495d-a8a5-c9843ea3b773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788624440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1788624440
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3372164114
Short name T1170
Test name
Test status
Simulation time 24218775768 ps
CPU time 18.62 seconds
Started Aug 07 05:56:58 PM PDT 24
Finished Aug 07 05:57:17 PM PDT 24
Peak memory 199904 kb
Host smart-88ffda53-29f4-46ac-8ead-3ae9a3de5e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372164114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3372164114
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1678658010
Short name T338
Test name
Test status
Simulation time 39379906618 ps
CPU time 15.08 seconds
Started Aug 07 05:57:01 PM PDT 24
Finished Aug 07 05:57:16 PM PDT 24
Peak memory 199892 kb
Host smart-dfdd5cf9-27ab-4ffe-9c84-3cb8825b0bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678658010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1678658010
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.853925490
Short name T364
Test name
Test status
Simulation time 11771652 ps
CPU time 0.57 seconds
Started Aug 07 05:51:07 PM PDT 24
Finished Aug 07 05:51:07 PM PDT 24
Peak memory 195304 kb
Host smart-fe920213-cf0e-4cd6-bee9-00a4c1974bd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853925490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.853925490
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1843531308
Short name T864
Test name
Test status
Simulation time 13684368028 ps
CPU time 25.77 seconds
Started Aug 07 05:51:08 PM PDT 24
Finished Aug 07 05:51:34 PM PDT 24
Peak memory 199916 kb
Host smart-9c1707c8-7135-4a3c-ace9-a33a646d55ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843531308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1843531308
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1172445442
Short name T637
Test name
Test status
Simulation time 143116555237 ps
CPU time 40.93 seconds
Started Aug 07 05:51:11 PM PDT 24
Finished Aug 07 05:51:52 PM PDT 24
Peak memory 199832 kb
Host smart-68973162-859a-4a0a-bbb5-2035cdf45221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172445442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1172445442
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3300006818
Short name T661
Test name
Test status
Simulation time 144829177154 ps
CPU time 37.17 seconds
Started Aug 07 05:51:12 PM PDT 24
Finished Aug 07 05:51:49 PM PDT 24
Peak memory 199880 kb
Host smart-a90ddcad-993e-4369-a7c4-9b47858351e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300006818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3300006818
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3768995678
Short name T742
Test name
Test status
Simulation time 10383126508 ps
CPU time 4.28 seconds
Started Aug 07 05:51:09 PM PDT 24
Finished Aug 07 05:51:13 PM PDT 24
Peak memory 199636 kb
Host smart-e16228d4-fc3d-4860-ac24-0872adbc417c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768995678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3768995678
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2643392547
Short name T359
Test name
Test status
Simulation time 137443211116 ps
CPU time 444.26 seconds
Started Aug 07 05:51:06 PM PDT 24
Finished Aug 07 05:58:30 PM PDT 24
Peak memory 199884 kb
Host smart-c4a68ba4-5245-4ff9-8ab6-0207c633504c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2643392547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2643392547
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3828622500
Short name T1048
Test name
Test status
Simulation time 6298573142 ps
CPU time 5.06 seconds
Started Aug 07 05:51:08 PM PDT 24
Finished Aug 07 05:51:14 PM PDT 24
Peak memory 198420 kb
Host smart-4e671f9e-2413-436f-8680-87e363a4dbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828622500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3828622500
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2213238439
Short name T1061
Test name
Test status
Simulation time 15156429804 ps
CPU time 11.6 seconds
Started Aug 07 05:51:07 PM PDT 24
Finished Aug 07 05:51:18 PM PDT 24
Peak memory 199804 kb
Host smart-62f39727-b30e-4a12-905e-2e1971dcea92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213238439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2213238439
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.1630245152
Short name T796
Test name
Test status
Simulation time 12843240960 ps
CPU time 693.22 seconds
Started Aug 07 05:51:06 PM PDT 24
Finished Aug 07 06:02:39 PM PDT 24
Peak memory 199832 kb
Host smart-8c60c6cc-6786-4e41-b66a-a774d82e3d45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1630245152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1630245152
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.511144131
Short name T588
Test name
Test status
Simulation time 6299611257 ps
CPU time 29.52 seconds
Started Aug 07 05:51:09 PM PDT 24
Finished Aug 07 05:51:39 PM PDT 24
Peak memory 199388 kb
Host smart-ceeed96f-0bcd-41c4-9eaf-8ea980997881
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=511144131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.511144131
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.2508931153
Short name T389
Test name
Test status
Simulation time 66356971217 ps
CPU time 89.69 seconds
Started Aug 07 05:51:06 PM PDT 24
Finished Aug 07 05:52:36 PM PDT 24
Peak memory 199496 kb
Host smart-828cf1e9-ae74-4724-816f-6cc59363886d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508931153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2508931153
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3406705051
Short name T902
Test name
Test status
Simulation time 2715784312 ps
CPU time 4.49 seconds
Started Aug 07 05:51:08 PM PDT 24
Finished Aug 07 05:51:13 PM PDT 24
Peak memory 196420 kb
Host smart-739e5188-b7d7-49a7-93b9-26b762d17592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406705051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3406705051
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.423684561
Short name T28
Test name
Test status
Simulation time 240055361 ps
CPU time 0.81 seconds
Started Aug 07 05:51:10 PM PDT 24
Finished Aug 07 05:51:11 PM PDT 24
Peak memory 218352 kb
Host smart-068e882d-2017-4ee1-8737-7e9aa2124ded
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423684561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.423684561
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.718165334
Short name T546
Test name
Test status
Simulation time 5505150006 ps
CPU time 6.68 seconds
Started Aug 07 05:51:05 PM PDT 24
Finished Aug 07 05:51:12 PM PDT 24
Peak memory 199436 kb
Host smart-615273d5-8376-445a-b0d5-b2066a21c2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718165334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.718165334
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.4138181109
Short name T669
Test name
Test status
Simulation time 241454803147 ps
CPU time 564.54 seconds
Started Aug 07 05:51:12 PM PDT 24
Finished Aug 07 06:00:37 PM PDT 24
Peak memory 199952 kb
Host smart-cd23cea1-ead3-441e-8a17-55a8931fa0d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138181109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.4138181109
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3004746042
Short name T103
Test name
Test status
Simulation time 146991663663 ps
CPU time 512.65 seconds
Started Aug 07 05:51:09 PM PDT 24
Finished Aug 07 05:59:42 PM PDT 24
Peak memory 216404 kb
Host smart-11f2ed86-9de7-48bc-bc9f-bfa2c204bb6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004746042 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3004746042
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.4023440738
Short name T954
Test name
Test status
Simulation time 657406756 ps
CPU time 1.31 seconds
Started Aug 07 05:51:06 PM PDT 24
Finished Aug 07 05:51:07 PM PDT 24
Peak memory 198216 kb
Host smart-5be841b2-3c77-41a9-8a02-293cc0f0b359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023440738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.4023440738
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2142454429
Short name T891
Test name
Test status
Simulation time 6675991648 ps
CPU time 11.56 seconds
Started Aug 07 05:51:08 PM PDT 24
Finished Aug 07 05:51:19 PM PDT 24
Peak memory 197388 kb
Host smart-c2c11157-e518-47e7-8dfe-05ff5e2ee496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142454429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2142454429
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1668610896
Short name T361
Test name
Test status
Simulation time 20339165 ps
CPU time 0.56 seconds
Started Aug 07 05:52:23 PM PDT 24
Finished Aug 07 05:52:24 PM PDT 24
Peak memory 195204 kb
Host smart-91881eb4-1e93-448b-a80d-eb11bc117955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668610896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1668610896
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2400590233
Short name T499
Test name
Test status
Simulation time 46867243213 ps
CPU time 18.39 seconds
Started Aug 07 05:52:19 PM PDT 24
Finished Aug 07 05:52:37 PM PDT 24
Peak memory 199900 kb
Host smart-f637c8d1-5fd3-4a91-b2f5-a928ce67f949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400590233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2400590233
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3048357474
Short name T452
Test name
Test status
Simulation time 18336165764 ps
CPU time 28.92 seconds
Started Aug 07 05:52:18 PM PDT 24
Finished Aug 07 05:52:47 PM PDT 24
Peak memory 199600 kb
Host smart-ee5fa277-d59c-449c-a08f-dfc8fa691cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048357474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3048357474
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2269911270
Short name T916
Test name
Test status
Simulation time 21411394190 ps
CPU time 9.58 seconds
Started Aug 07 05:52:18 PM PDT 24
Finished Aug 07 05:52:28 PM PDT 24
Peak memory 199844 kb
Host smart-bdc2fe8f-a0b5-4406-b1c3-a7b758dfff39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269911270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2269911270
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3772844341
Short name T255
Test name
Test status
Simulation time 30290316845 ps
CPU time 48 seconds
Started Aug 07 05:52:18 PM PDT 24
Finished Aug 07 05:53:06 PM PDT 24
Peak memory 199804 kb
Host smart-63939636-a4a2-428a-858a-0a091f347a95
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772844341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3772844341
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2178329481
Short name T710
Test name
Test status
Simulation time 141012632842 ps
CPU time 442.3 seconds
Started Aug 07 05:52:23 PM PDT 24
Finished Aug 07 05:59:46 PM PDT 24
Peak memory 199804 kb
Host smart-0e0a306c-32f7-4b41-83c4-0c8d9ca00bdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2178329481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2178329481
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2960101536
Short name T328
Test name
Test status
Simulation time 10971784052 ps
CPU time 7.93 seconds
Started Aug 07 05:52:19 PM PDT 24
Finished Aug 07 05:52:27 PM PDT 24
Peak memory 199468 kb
Host smart-6d417d76-10df-4d95-9938-3a327b4673d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960101536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2960101536
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3941653914
Short name T387
Test name
Test status
Simulation time 17582305023 ps
CPU time 6.64 seconds
Started Aug 07 05:52:19 PM PDT 24
Finished Aug 07 05:52:26 PM PDT 24
Peak memory 194456 kb
Host smart-bbe9283e-df46-414b-a539-02b8fdd43971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941653914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3941653914
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.1476441479
Short name T1101
Test name
Test status
Simulation time 19983223114 ps
CPU time 1132.92 seconds
Started Aug 07 05:52:19 PM PDT 24
Finished Aug 07 06:11:12 PM PDT 24
Peak memory 199832 kb
Host smart-319f41d8-63cd-425b-9c9b-ef316bf5be6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1476441479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1476441479
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1799516820
Short name T971
Test name
Test status
Simulation time 4082584415 ps
CPU time 7.74 seconds
Started Aug 07 05:52:20 PM PDT 24
Finished Aug 07 05:52:28 PM PDT 24
Peak memory 198916 kb
Host smart-34d6ed03-adea-4c7b-a873-7a75920967e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1799516820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1799516820
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.410050489
Short name T687
Test name
Test status
Simulation time 277487767399 ps
CPU time 448.31 seconds
Started Aug 07 05:52:19 PM PDT 24
Finished Aug 07 05:59:47 PM PDT 24
Peak memory 199924 kb
Host smart-964418cb-3fbe-4fb5-86e5-49e1ef62bc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410050489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.410050489
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.580146143
Short name T917
Test name
Test status
Simulation time 2060979347 ps
CPU time 3.62 seconds
Started Aug 07 05:52:19 PM PDT 24
Finished Aug 07 05:52:23 PM PDT 24
Peak memory 195396 kb
Host smart-e112bc52-f7f0-4889-97ae-93413386e4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580146143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.580146143
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3504577550
Short name T528
Test name
Test status
Simulation time 732449892 ps
CPU time 1.75 seconds
Started Aug 07 05:52:12 PM PDT 24
Finished Aug 07 05:52:14 PM PDT 24
Peak memory 198408 kb
Host smart-b117da4d-9594-4255-9e6f-fcbb35bafeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504577550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3504577550
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.1088669234
Short name T1066
Test name
Test status
Simulation time 191410006421 ps
CPU time 318.19 seconds
Started Aug 07 05:52:22 PM PDT 24
Finished Aug 07 05:57:41 PM PDT 24
Peak memory 199872 kb
Host smart-5ff7bae8-62a1-4c51-baf8-63d4d8bec898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088669234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1088669234
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.92383315
Short name T54
Test name
Test status
Simulation time 428254382451 ps
CPU time 199.68 seconds
Started Aug 07 05:52:23 PM PDT 24
Finished Aug 07 05:55:43 PM PDT 24
Peak memory 216572 kb
Host smart-2baa0f6f-5f52-4535-b325-02b08724e77a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92383315 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.92383315
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1722096185
Short name T1148
Test name
Test status
Simulation time 832868464 ps
CPU time 2.39 seconds
Started Aug 07 05:52:19 PM PDT 24
Finished Aug 07 05:52:22 PM PDT 24
Peak memory 199836 kb
Host smart-feffb3c8-fa9c-49ea-9d28-5ec7afbb9020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722096185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1722096185
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2033954716
Short name T889
Test name
Test status
Simulation time 19580508903 ps
CPU time 10.13 seconds
Started Aug 07 05:52:13 PM PDT 24
Finished Aug 07 05:52:23 PM PDT 24
Peak memory 199804 kb
Host smart-6ca5fb9f-b771-4f16-b40d-3245b605221b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033954716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2033954716
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3456193627
Short name T202
Test name
Test status
Simulation time 66690975084 ps
CPU time 27.31 seconds
Started Aug 07 05:56:58 PM PDT 24
Finished Aug 07 05:57:25 PM PDT 24
Peak memory 199936 kb
Host smart-eeab1aea-b21c-4fba-b653-78a9e4ca141e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456193627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3456193627
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3988771585
Short name T1113
Test name
Test status
Simulation time 112937901024 ps
CPU time 47.84 seconds
Started Aug 07 05:56:59 PM PDT 24
Finished Aug 07 05:57:47 PM PDT 24
Peak memory 199804 kb
Host smart-e1974f3d-9f91-44c5-8644-e015a3b70838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988771585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3988771585
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.4075144503
Short name T845
Test name
Test status
Simulation time 20420519255 ps
CPU time 28 seconds
Started Aug 07 05:57:02 PM PDT 24
Finished Aug 07 05:57:30 PM PDT 24
Peak memory 199888 kb
Host smart-a29ca76b-cea3-4ddb-9ed5-a1ce973dec51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075144503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.4075144503
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2938203423
Short name T571
Test name
Test status
Simulation time 78176696271 ps
CPU time 18.32 seconds
Started Aug 07 05:56:57 PM PDT 24
Finished Aug 07 05:57:16 PM PDT 24
Peak memory 199920 kb
Host smart-31e70f27-1b20-40a4-8615-f8f7449e4120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938203423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2938203423
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1986406803
Short name T933
Test name
Test status
Simulation time 18601971654 ps
CPU time 32.28 seconds
Started Aug 07 05:56:58 PM PDT 24
Finished Aug 07 05:57:30 PM PDT 24
Peak memory 199912 kb
Host smart-29b5b4ca-fbab-45c1-8f63-669b6a87a953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986406803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1986406803
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.4219701868
Short name T564
Test name
Test status
Simulation time 124379834163 ps
CPU time 86.97 seconds
Started Aug 07 05:56:58 PM PDT 24
Finished Aug 07 05:58:25 PM PDT 24
Peak memory 199840 kb
Host smart-9560d345-1c20-47ac-a94f-a5ebe21a3c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219701868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.4219701868
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1867346621
Short name T400
Test name
Test status
Simulation time 51385988750 ps
CPU time 18.85 seconds
Started Aug 07 05:57:06 PM PDT 24
Finished Aug 07 05:57:25 PM PDT 24
Peak memory 199712 kb
Host smart-bdd80731-cb57-4023-b2e4-0fd548a5e46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867346621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1867346621
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2203543788
Short name T696
Test name
Test status
Simulation time 70166686167 ps
CPU time 26.4 seconds
Started Aug 07 05:57:05 PM PDT 24
Finished Aug 07 05:57:31 PM PDT 24
Peak memory 199644 kb
Host smart-a372b27c-6542-44ac-b70e-e1c100aa0e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203543788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2203543788
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1062360208
Short name T605
Test name
Test status
Simulation time 24903393071 ps
CPU time 42.94 seconds
Started Aug 07 05:57:07 PM PDT 24
Finished Aug 07 05:57:50 PM PDT 24
Peak memory 199864 kb
Host smart-9208347c-622e-4d11-9c4a-b475ecd34481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062360208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1062360208
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1491839426
Short name T774
Test name
Test status
Simulation time 139180261337 ps
CPU time 59.26 seconds
Started Aug 07 05:57:06 PM PDT 24
Finished Aug 07 05:58:06 PM PDT 24
Peak memory 199864 kb
Host smart-038e023b-a57b-4b82-a62d-0ee911c69194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491839426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1491839426
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1073382409
Short name T397
Test name
Test status
Simulation time 12813926 ps
CPU time 0.55 seconds
Started Aug 07 05:52:29 PM PDT 24
Finished Aug 07 05:52:29 PM PDT 24
Peak memory 195300 kb
Host smart-8ad01254-618d-4c30-ab30-35766a59f12e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073382409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1073382409
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.1755436021
Short name T454
Test name
Test status
Simulation time 15426203525 ps
CPU time 23.17 seconds
Started Aug 07 05:52:23 PM PDT 24
Finished Aug 07 05:52:46 PM PDT 24
Peak memory 199832 kb
Host smart-cc50f486-841b-4534-867a-3d220185864e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755436021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1755436021
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.4039814728
Short name T780
Test name
Test status
Simulation time 24343677395 ps
CPU time 45.24 seconds
Started Aug 07 05:52:22 PM PDT 24
Finished Aug 07 05:53:07 PM PDT 24
Peak memory 199852 kb
Host smart-09a9f03c-52ae-480e-a256-adde426c0bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039814728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.4039814728
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_intr.1784937143
Short name T940
Test name
Test status
Simulation time 248890853261 ps
CPU time 51.53 seconds
Started Aug 07 05:52:21 PM PDT 24
Finished Aug 07 05:53:13 PM PDT 24
Peak memory 199892 kb
Host smart-d6a8a99a-e99f-44e2-ac40-b33515398297
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784937143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1784937143
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.940610815
Short name T767
Test name
Test status
Simulation time 68768640976 ps
CPU time 273.14 seconds
Started Aug 07 05:52:24 PM PDT 24
Finished Aug 07 05:56:57 PM PDT 24
Peak memory 199860 kb
Host smart-0824d283-c36e-4635-8a73-756b56de7197
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=940610815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.940610815
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.15896316
Short name T324
Test name
Test status
Simulation time 6471805977 ps
CPU time 4.85 seconds
Started Aug 07 05:52:25 PM PDT 24
Finished Aug 07 05:52:30 PM PDT 24
Peak memory 198624 kb
Host smart-162080df-52a8-46a6-979e-33cc84cc9ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15896316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.15896316
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3540379138
Short name T955
Test name
Test status
Simulation time 55630776297 ps
CPU time 45.05 seconds
Started Aug 07 05:52:21 PM PDT 24
Finished Aug 07 05:53:06 PM PDT 24
Peak memory 208236 kb
Host smart-93e9defa-61a6-4a24-b915-96b9ec659664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540379138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3540379138
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3941506202
Short name T613
Test name
Test status
Simulation time 15126039210 ps
CPU time 182.71 seconds
Started Aug 07 05:52:25 PM PDT 24
Finished Aug 07 05:55:27 PM PDT 24
Peak memory 199892 kb
Host smart-43ba455c-e91c-49c2-ae1e-e448f2e95b9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3941506202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3941506202
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1336307173
Short name T770
Test name
Test status
Simulation time 5435611449 ps
CPU time 41.59 seconds
Started Aug 07 05:52:24 PM PDT 24
Finished Aug 07 05:53:06 PM PDT 24
Peak memory 197768 kb
Host smart-ef45fa2e-8a10-479c-8d7b-59d728a9032a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1336307173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1336307173
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3623446275
Short name T1115
Test name
Test status
Simulation time 98020767838 ps
CPU time 24.2 seconds
Started Aug 07 05:52:21 PM PDT 24
Finished Aug 07 05:52:46 PM PDT 24
Peak memory 199880 kb
Host smart-5aeea0fa-4d5e-4644-a0b9-578d69ab16bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623446275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3623446275
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.340054612
Short name T356
Test name
Test status
Simulation time 1872425730 ps
CPU time 2.02 seconds
Started Aug 07 05:52:21 PM PDT 24
Finished Aug 07 05:52:23 PM PDT 24
Peak memory 195384 kb
Host smart-6dfcabec-2330-48e4-bb8d-369dfe3d92a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340054612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.340054612
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2678063631
Short name T707
Test name
Test status
Simulation time 110233907 ps
CPU time 1.16 seconds
Started Aug 07 05:52:24 PM PDT 24
Finished Aug 07 05:52:25 PM PDT 24
Peak memory 199436 kb
Host smart-11af43ec-7837-4e86-b877-ebfadfa6b417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678063631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2678063631
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.3267206125
Short name T535
Test name
Test status
Simulation time 39432965538 ps
CPU time 501.77 seconds
Started Aug 07 05:52:28 PM PDT 24
Finished Aug 07 06:00:50 PM PDT 24
Peak memory 216500 kb
Host smart-caa06118-6931-4206-a0d7-b808d30251db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267206125 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3267206125
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.4294036371
Short name T373
Test name
Test status
Simulation time 1762647899 ps
CPU time 1.68 seconds
Started Aug 07 05:52:23 PM PDT 24
Finished Aug 07 05:52:24 PM PDT 24
Peak memory 198500 kb
Host smart-caac82bb-9ce2-49e2-9c16-2b7177e15e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294036371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.4294036371
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3332655220
Short name T712
Test name
Test status
Simulation time 90164048983 ps
CPU time 36.54 seconds
Started Aug 07 05:52:24 PM PDT 24
Finished Aug 07 05:53:00 PM PDT 24
Peak memory 199880 kb
Host smart-e33d1a30-c18d-40c3-a561-45197ace7a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332655220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3332655220
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.721258161
Short name T573
Test name
Test status
Simulation time 88353801179 ps
CPU time 33.92 seconds
Started Aug 07 05:57:05 PM PDT 24
Finished Aug 07 05:57:39 PM PDT 24
Peak memory 199668 kb
Host smart-583f8a71-f510-4289-9f20-144282d96fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721258161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.721258161
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.641087468
Short name T117
Test name
Test status
Simulation time 41498969460 ps
CPU time 34.81 seconds
Started Aug 07 05:57:03 PM PDT 24
Finished Aug 07 05:57:38 PM PDT 24
Peak memory 199888 kb
Host smart-0b172605-1a83-4ebf-8de8-d930e7c06575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641087468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.641087468
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3393502407
Short name T747
Test name
Test status
Simulation time 39333275271 ps
CPU time 19.34 seconds
Started Aug 07 05:57:04 PM PDT 24
Finished Aug 07 05:57:23 PM PDT 24
Peak memory 199844 kb
Host smart-65258e8f-f30f-4183-9cbb-e56f9dbb85fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393502407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3393502407
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.384983251
Short name T748
Test name
Test status
Simulation time 55066367401 ps
CPU time 39.96 seconds
Started Aug 07 05:57:06 PM PDT 24
Finished Aug 07 05:57:47 PM PDT 24
Peak memory 199916 kb
Host smart-325d25ff-c329-4edd-9e82-299c878e2166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384983251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.384983251
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2923193186
Short name T1077
Test name
Test status
Simulation time 42461452394 ps
CPU time 18.1 seconds
Started Aug 07 05:57:04 PM PDT 24
Finished Aug 07 05:57:22 PM PDT 24
Peak memory 199932 kb
Host smart-513b8545-c354-41c6-a07c-05c7f571f831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923193186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2923193186
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2592967053
Short name T614
Test name
Test status
Simulation time 35418229115 ps
CPU time 54.15 seconds
Started Aug 07 05:57:06 PM PDT 24
Finished Aug 07 05:58:00 PM PDT 24
Peak memory 199820 kb
Host smart-edd729c6-bd61-4076-b108-c851377f8e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592967053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2592967053
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1698537245
Short name T811
Test name
Test status
Simulation time 235950896722 ps
CPU time 36.86 seconds
Started Aug 07 05:57:09 PM PDT 24
Finished Aug 07 05:57:46 PM PDT 24
Peak memory 199692 kb
Host smart-0bac8c38-7d83-4df7-91c8-741ee27bc2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698537245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1698537245
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.3100257483
Short name T959
Test name
Test status
Simulation time 63895279103 ps
CPU time 20.97 seconds
Started Aug 07 05:57:04 PM PDT 24
Finished Aug 07 05:57:25 PM PDT 24
Peak memory 199884 kb
Host smart-998ac671-90a0-42b7-ab7b-aa462bbff9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100257483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3100257483
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3457348568
Short name T803
Test name
Test status
Simulation time 159415011879 ps
CPU time 28.24 seconds
Started Aug 07 05:57:06 PM PDT 24
Finished Aug 07 05:57:34 PM PDT 24
Peak memory 199892 kb
Host smart-f5c4c9af-3e4d-4522-811a-500472025f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457348568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3457348568
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1838240994
Short name T852
Test name
Test status
Simulation time 120605487719 ps
CPU time 162.52 seconds
Started Aug 07 05:57:04 PM PDT 24
Finished Aug 07 05:59:47 PM PDT 24
Peak memory 199844 kb
Host smart-6db43409-beb9-448c-876e-baf229c6bead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838240994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1838240994
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.746783274
Short name T1139
Test name
Test status
Simulation time 37775860 ps
CPU time 0.54 seconds
Started Aug 07 05:52:34 PM PDT 24
Finished Aug 07 05:52:35 PM PDT 24
Peak memory 194748 kb
Host smart-79d18348-1a0b-4799-b86d-da45744a2c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746783274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.746783274
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3340990963
Short name T813
Test name
Test status
Simulation time 49449588047 ps
CPU time 121 seconds
Started Aug 07 05:52:28 PM PDT 24
Finished Aug 07 05:54:29 PM PDT 24
Peak memory 199748 kb
Host smart-0a138462-4a7a-4b81-ad70-cff2af60aeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340990963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3340990963
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3028469634
Short name T130
Test name
Test status
Simulation time 162952721879 ps
CPU time 28.16 seconds
Started Aug 07 05:52:28 PM PDT 24
Finished Aug 07 05:52:56 PM PDT 24
Peak memory 199856 kb
Host smart-c08d51fa-7d1b-4319-a90e-2638627425dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028469634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3028469634
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2690406230
Short name T432
Test name
Test status
Simulation time 91993702586 ps
CPU time 361 seconds
Started Aug 07 05:52:29 PM PDT 24
Finished Aug 07 05:58:30 PM PDT 24
Peak memory 199840 kb
Host smart-6dbe59ad-552f-4e91-9ca8-0b530733c7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690406230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2690406230
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.799208504
Short name T542
Test name
Test status
Simulation time 40024672642 ps
CPU time 6.59 seconds
Started Aug 07 05:52:29 PM PDT 24
Finished Aug 07 05:52:36 PM PDT 24
Peak memory 197972 kb
Host smart-c8facc29-1a35-4bfc-a3b2-3727383e5909
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799208504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.799208504
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3838704788
Short name T250
Test name
Test status
Simulation time 92544521627 ps
CPU time 749.73 seconds
Started Aug 07 05:52:34 PM PDT 24
Finished Aug 07 06:05:04 PM PDT 24
Peak memory 199892 kb
Host smart-36d32074-66fd-4e71-b272-227d77b94600
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3838704788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3838704788
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2295483325
Short name T6
Test name
Test status
Simulation time 2764904936 ps
CPU time 1.97 seconds
Started Aug 07 05:52:31 PM PDT 24
Finished Aug 07 05:52:33 PM PDT 24
Peak memory 197420 kb
Host smart-3f7a66d7-6924-431e-bd2e-7f7ca6cdc4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295483325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2295483325
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.1109966593
Short name T604
Test name
Test status
Simulation time 82329278840 ps
CPU time 123.6 seconds
Started Aug 07 05:52:30 PM PDT 24
Finished Aug 07 05:54:33 PM PDT 24
Peak memory 199600 kb
Host smart-1e467039-ace1-44d2-8c7a-ee24814b89f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109966593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1109966593
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.4051657412
Short name T544
Test name
Test status
Simulation time 10621735489 ps
CPU time 249.44 seconds
Started Aug 07 05:52:28 PM PDT 24
Finished Aug 07 05:56:37 PM PDT 24
Peak memory 199848 kb
Host smart-ca5e3410-1645-4400-96bc-80d1e6e321c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4051657412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.4051657412
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1569499913
Short name T1092
Test name
Test status
Simulation time 7498426677 ps
CPU time 65.53 seconds
Started Aug 07 05:52:30 PM PDT 24
Finished Aug 07 05:53:36 PM PDT 24
Peak memory 198216 kb
Host smart-d13d17ec-0e60-422d-924a-b7b4ca3b7fd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1569499913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1569499913
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.3399811671
Short name T300
Test name
Test status
Simulation time 165387673401 ps
CPU time 111.38 seconds
Started Aug 07 05:52:30 PM PDT 24
Finished Aug 07 05:54:22 PM PDT 24
Peak memory 199932 kb
Host smart-74cb05dd-dcb5-40fd-bd09-abcadb2b4079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399811671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3399811671
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1014241006
Short name T693
Test name
Test status
Simulation time 45923327655 ps
CPU time 76.59 seconds
Started Aug 07 05:52:30 PM PDT 24
Finished Aug 07 05:53:47 PM PDT 24
Peak memory 196412 kb
Host smart-dcc736ac-5cfc-459c-a18d-4bd044d3eca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014241006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1014241006
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2210612690
Short name T414
Test name
Test status
Simulation time 560972318 ps
CPU time 1.75 seconds
Started Aug 07 05:52:28 PM PDT 24
Finished Aug 07 05:52:30 PM PDT 24
Peak memory 199616 kb
Host smart-c1158324-657d-4631-9af8-b25f44a7188d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210612690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2210612690
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.1151343066
Short name T379
Test name
Test status
Simulation time 21910785679 ps
CPU time 41.77 seconds
Started Aug 07 05:52:32 PM PDT 24
Finished Aug 07 05:53:14 PM PDT 24
Peak memory 199920 kb
Host smart-0ceb6be5-b0f5-48b7-941a-0db0df265616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151343066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1151343066
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3397220400
Short name T494
Test name
Test status
Simulation time 44592429192 ps
CPU time 487.77 seconds
Started Aug 07 05:54:28 PM PDT 24
Finished Aug 07 06:02:36 PM PDT 24
Peak memory 216524 kb
Host smart-5c060f6c-a60d-4ccb-9460-4ba27f46e7fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397220400 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3397220400
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1745528826
Short name T833
Test name
Test status
Simulation time 2946006850 ps
CPU time 2.67 seconds
Started Aug 07 05:52:28 PM PDT 24
Finished Aug 07 05:52:31 PM PDT 24
Peak memory 198680 kb
Host smart-02fa4177-fb26-49ef-b52d-7f321f4befe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745528826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1745528826
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1643953186
Short name T927
Test name
Test status
Simulation time 39676364110 ps
CPU time 49.43 seconds
Started Aug 07 05:52:26 PM PDT 24
Finished Aug 07 05:53:16 PM PDT 24
Peak memory 199864 kb
Host smart-29306d6a-be58-48af-8ffe-00ef218f606d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643953186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1643953186
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1066523324
Short name T404
Test name
Test status
Simulation time 84067758145 ps
CPU time 122 seconds
Started Aug 07 05:57:05 PM PDT 24
Finished Aug 07 05:59:07 PM PDT 24
Peak memory 199856 kb
Host smart-9b801477-38fc-450f-839c-d0168bdf6861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066523324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1066523324
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2525310900
Short name T1044
Test name
Test status
Simulation time 10546168188 ps
CPU time 21.02 seconds
Started Aug 07 05:57:09 PM PDT 24
Finished Aug 07 05:57:31 PM PDT 24
Peak memory 199892 kb
Host smart-63d3635b-c39b-4011-931b-e67e01fcb38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525310900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2525310900
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2666176280
Short name T227
Test name
Test status
Simulation time 34080592072 ps
CPU time 25.36 seconds
Started Aug 07 05:57:11 PM PDT 24
Finished Aug 07 05:57:36 PM PDT 24
Peak memory 199752 kb
Host smart-230d49d6-faed-4612-80d9-8e16009c32a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666176280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2666176280
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2153588233
Short name T206
Test name
Test status
Simulation time 118286675069 ps
CPU time 178.9 seconds
Started Aug 07 05:57:13 PM PDT 24
Finished Aug 07 06:00:12 PM PDT 24
Peak memory 199832 kb
Host smart-d6284d82-2dbf-4df1-9d4a-00bf620532e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153588233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2153588233
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.4046551883
Short name T636
Test name
Test status
Simulation time 149588555856 ps
CPU time 29.81 seconds
Started Aug 07 05:57:10 PM PDT 24
Finished Aug 07 05:57:40 PM PDT 24
Peak memory 199804 kb
Host smart-cdf730b7-9eb8-4253-a7f2-283a1d6581f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046551883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.4046551883
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1771143983
Short name T898
Test name
Test status
Simulation time 168330242330 ps
CPU time 17.2 seconds
Started Aug 07 05:57:12 PM PDT 24
Finished Aug 07 05:57:29 PM PDT 24
Peak memory 199908 kb
Host smart-0bbe91af-e156-44ab-863e-3fb1cf0783bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771143983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1771143983
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1750068021
Short name T482
Test name
Test status
Simulation time 231405925583 ps
CPU time 46.19 seconds
Started Aug 07 05:57:10 PM PDT 24
Finished Aug 07 05:57:56 PM PDT 24
Peak memory 199872 kb
Host smart-3d6d9487-0d1b-436d-85bd-ec6354386292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750068021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1750068021
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3347482228
Short name T215
Test name
Test status
Simulation time 53497694167 ps
CPU time 48.34 seconds
Started Aug 07 05:57:11 PM PDT 24
Finished Aug 07 05:57:59 PM PDT 24
Peak memory 199884 kb
Host smart-9f753256-441f-4c31-8f3e-55027d177e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347482228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3347482228
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3049022578
Short name T895
Test name
Test status
Simulation time 52344937994 ps
CPU time 62.12 seconds
Started Aug 07 05:57:10 PM PDT 24
Finished Aug 07 05:58:12 PM PDT 24
Peak memory 199936 kb
Host smart-f0709082-0ab8-467d-a1bf-dc69243fa1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049022578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3049022578
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2218727103
Short name T561
Test name
Test status
Simulation time 25489579453 ps
CPU time 36.74 seconds
Started Aug 07 05:57:09 PM PDT 24
Finished Aug 07 05:57:46 PM PDT 24
Peak memory 199824 kb
Host smart-e9272eda-874c-4191-af08-a9dc6bf7514a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218727103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2218727103
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2590522416
Short name T401
Test name
Test status
Simulation time 43037330 ps
CPU time 0.57 seconds
Started Aug 07 05:52:40 PM PDT 24
Finished Aug 07 05:52:40 PM PDT 24
Peak memory 194364 kb
Host smart-2027d6c6-8518-4550-8590-2276dd481fc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590522416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2590522416
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1563475250
Short name T886
Test name
Test status
Simulation time 132734615158 ps
CPU time 559.97 seconds
Started Aug 07 05:52:33 PM PDT 24
Finished Aug 07 06:01:53 PM PDT 24
Peak memory 199912 kb
Host smart-b7f9389a-a17a-4f51-84b4-f553db5c517e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563475250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1563475250
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3193467177
Short name T967
Test name
Test status
Simulation time 14008675448 ps
CPU time 21.28 seconds
Started Aug 07 05:52:34 PM PDT 24
Finished Aug 07 05:52:55 PM PDT 24
Peak memory 199596 kb
Host smart-ffb0efc2-5951-4c90-82c1-1fde23ef7c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193467177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3193467177
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3096204334
Short name T179
Test name
Test status
Simulation time 104576552068 ps
CPU time 182.15 seconds
Started Aug 07 05:52:34 PM PDT 24
Finished Aug 07 05:55:37 PM PDT 24
Peak memory 199820 kb
Host smart-ff4c9de0-e6ee-47b8-a984-d3cbf147199d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096204334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3096204334
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.89492669
Short name T854
Test name
Test status
Simulation time 248924837575 ps
CPU time 42.01 seconds
Started Aug 07 05:52:36 PM PDT 24
Finished Aug 07 05:53:18 PM PDT 24
Peak memory 199764 kb
Host smart-1535678f-ff41-46b7-b39e-185abb9c740d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89492669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.89492669
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.3515345983
Short name T519
Test name
Test status
Simulation time 73493399063 ps
CPU time 602.8 seconds
Started Aug 07 05:52:34 PM PDT 24
Finished Aug 07 06:02:37 PM PDT 24
Peak memory 199912 kb
Host smart-15f28f8a-c8d2-49c0-a363-49b74fe02871
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3515345983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3515345983
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2805228587
Short name T423
Test name
Test status
Simulation time 7407599867 ps
CPU time 6.95 seconds
Started Aug 07 05:52:32 PM PDT 24
Finished Aug 07 05:52:39 PM PDT 24
Peak memory 199604 kb
Host smart-19bdf9e7-6081-4ddf-9157-31a3080ee6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805228587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2805228587
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3547804878
Short name T1145
Test name
Test status
Simulation time 94805684160 ps
CPU time 194.57 seconds
Started Aug 07 05:52:33 PM PDT 24
Finished Aug 07 05:55:48 PM PDT 24
Peak memory 199248 kb
Host smart-ae7505a0-4a36-4e8d-8943-449317190d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547804878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3547804878
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.3439255463
Short name T818
Test name
Test status
Simulation time 6087323687 ps
CPU time 294.23 seconds
Started Aug 07 05:52:33 PM PDT 24
Finished Aug 07 05:57:27 PM PDT 24
Peak memory 199848 kb
Host smart-d684d747-94a0-4851-8804-287c8adf43f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3439255463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3439255463
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3669991850
Short name T663
Test name
Test status
Simulation time 5567088017 ps
CPU time 10.81 seconds
Started Aug 07 05:54:22 PM PDT 24
Finished Aug 07 05:54:33 PM PDT 24
Peak memory 198180 kb
Host smart-569d468d-993b-4647-8044-2e87022f376b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3669991850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3669991850
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.4236089442
Short name T501
Test name
Test status
Simulation time 40592020005 ps
CPU time 14.12 seconds
Started Aug 07 05:52:34 PM PDT 24
Finished Aug 07 05:52:48 PM PDT 24
Peak memory 199044 kb
Host smart-a447a156-1ff2-4466-837b-8b7513a2cb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236089442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.4236089442
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2907925960
Short name T1095
Test name
Test status
Simulation time 661173817 ps
CPU time 1.13 seconds
Started Aug 07 05:52:36 PM PDT 24
Finished Aug 07 05:52:37 PM PDT 24
Peak memory 195452 kb
Host smart-5c10e4f1-0466-4d1d-98f4-9f662e886212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907925960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2907925960
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.2532729104
Short name T332
Test name
Test status
Simulation time 532539797 ps
CPU time 2.93 seconds
Started Aug 07 05:52:35 PM PDT 24
Finished Aug 07 05:52:38 PM PDT 24
Peak memory 198492 kb
Host smart-f4c016ea-b916-45a3-b966-38197cb8f656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532729104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2532729104
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.3240055263
Short name T723
Test name
Test status
Simulation time 27073762294 ps
CPU time 58.06 seconds
Started Aug 07 05:52:39 PM PDT 24
Finished Aug 07 05:53:38 PM PDT 24
Peak memory 199860 kb
Host smart-71afb836-497c-42ec-8952-acfa504c7c3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240055263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3240055263
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2391943269
Short name T596
Test name
Test status
Simulation time 167105688355 ps
CPU time 1492.67 seconds
Started Aug 07 05:54:27 PM PDT 24
Finished Aug 07 06:19:20 PM PDT 24
Peak memory 216440 kb
Host smart-3e9b429d-79e2-46ec-ab60-99fc0b0dbed0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391943269 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2391943269
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.78288136
Short name T843
Test name
Test status
Simulation time 1006336689 ps
CPU time 1.96 seconds
Started Aug 07 05:52:31 PM PDT 24
Finished Aug 07 05:52:33 PM PDT 24
Peak memory 198884 kb
Host smart-5d1a95da-6c9a-4e01-b312-6d0afb348c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78288136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.78288136
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3183763161
Short name T272
Test name
Test status
Simulation time 33789611421 ps
CPU time 66.53 seconds
Started Aug 07 05:52:37 PM PDT 24
Finished Aug 07 05:53:44 PM PDT 24
Peak memory 199856 kb
Host smart-de8c196e-26ce-44c8-8e2b-c1f0a06e5e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183763161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3183763161
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.3670079774
Short name T700
Test name
Test status
Simulation time 77415982541 ps
CPU time 345.95 seconds
Started Aug 07 05:57:11 PM PDT 24
Finished Aug 07 06:02:57 PM PDT 24
Peak memory 199900 kb
Host smart-f4248425-2481-4736-9b0c-8be7af371e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670079774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3670079774
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1805773034
Short name T196
Test name
Test status
Simulation time 13559234432 ps
CPU time 11.71 seconds
Started Aug 07 05:57:12 PM PDT 24
Finished Aug 07 05:57:24 PM PDT 24
Peak memory 199836 kb
Host smart-576f4107-876a-4256-8b10-1e0896b5c1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805773034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1805773034
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2434987493
Short name T793
Test name
Test status
Simulation time 53144780821 ps
CPU time 10.03 seconds
Started Aug 07 05:57:16 PM PDT 24
Finished Aug 07 05:57:26 PM PDT 24
Peak memory 199868 kb
Host smart-cbd9c0e5-93f5-4a1d-9311-2179d53fbf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434987493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2434987493
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3904486156
Short name T645
Test name
Test status
Simulation time 102089622968 ps
CPU time 146.95 seconds
Started Aug 07 05:57:18 PM PDT 24
Finished Aug 07 05:59:46 PM PDT 24
Peak memory 199840 kb
Host smart-7c6e6605-dac0-4c8a-bc3f-733be6f7e1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904486156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3904486156
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3600412442
Short name T947
Test name
Test status
Simulation time 36088971216 ps
CPU time 18.1 seconds
Started Aug 07 05:57:16 PM PDT 24
Finished Aug 07 05:57:34 PM PDT 24
Peak memory 199840 kb
Host smart-79402b59-4e97-4a8d-b6af-8889ada887c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600412442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3600412442
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.49876479
Short name T398
Test name
Test status
Simulation time 28718924083 ps
CPU time 31.73 seconds
Started Aug 07 05:57:17 PM PDT 24
Finished Aug 07 05:57:49 PM PDT 24
Peak memory 199856 kb
Host smart-c9547737-8a9e-4df9-981c-c216c4a6e801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49876479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.49876479
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1719963425
Short name T1159
Test name
Test status
Simulation time 70178565223 ps
CPU time 28.42 seconds
Started Aug 07 05:57:17 PM PDT 24
Finished Aug 07 05:57:46 PM PDT 24
Peak memory 199716 kb
Host smart-6825113f-1ba7-4514-b965-dbe47bdf2c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719963425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1719963425
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3509364011
Short name T900
Test name
Test status
Simulation time 7681750206 ps
CPU time 9.09 seconds
Started Aug 07 05:57:19 PM PDT 24
Finished Aug 07 05:57:28 PM PDT 24
Peak memory 199664 kb
Host smart-ca470a19-2423-4b45-9deb-926a95295a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509364011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3509364011
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.1369518786
Short name T91
Test name
Test status
Simulation time 170912592530 ps
CPU time 20.99 seconds
Started Aug 07 05:57:17 PM PDT 24
Finished Aug 07 05:57:38 PM PDT 24
Peak memory 199844 kb
Host smart-9b03e24b-16db-4e12-a150-dd918b134035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369518786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1369518786
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3765305943
Short name T644
Test name
Test status
Simulation time 13343800 ps
CPU time 0.54 seconds
Started Aug 07 05:52:43 PM PDT 24
Finished Aug 07 05:52:44 PM PDT 24
Peak memory 194748 kb
Host smart-69caa09d-6aa5-483c-b428-e19b98664f70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765305943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3765305943
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2583908083
Short name T719
Test name
Test status
Simulation time 51567283138 ps
CPU time 66.13 seconds
Started Aug 07 05:52:39 PM PDT 24
Finished Aug 07 05:53:45 PM PDT 24
Peak memory 199800 kb
Host smart-4a896c4b-5148-4509-8730-2d6616b0c4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583908083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2583908083
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3009800644
Short name T299
Test name
Test status
Simulation time 155898144692 ps
CPU time 45.74 seconds
Started Aug 07 05:52:41 PM PDT 24
Finished Aug 07 05:53:27 PM PDT 24
Peak memory 199856 kb
Host smart-f4523a4b-cc30-4614-a277-27c400a84063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009800644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3009800644
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3260727256
Short name T692
Test name
Test status
Simulation time 30395526657 ps
CPU time 21.73 seconds
Started Aug 07 05:52:40 PM PDT 24
Finished Aug 07 05:53:02 PM PDT 24
Peak memory 199916 kb
Host smart-663ab985-674c-479f-b989-5fc5b2f34198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260727256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3260727256
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.2033633770
Short name T790
Test name
Test status
Simulation time 8386300228 ps
CPU time 3.56 seconds
Started Aug 07 05:52:39 PM PDT 24
Finished Aug 07 05:52:43 PM PDT 24
Peak memory 199772 kb
Host smart-7abc63f6-e3d6-404c-b6ef-1576b34de362
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033633770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2033633770
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1159251487
Short name T527
Test name
Test status
Simulation time 134540690717 ps
CPU time 301.23 seconds
Started Aug 07 05:52:46 PM PDT 24
Finished Aug 07 05:57:47 PM PDT 24
Peak memory 199868 kb
Host smart-2b2b323b-4e65-48b4-a0ca-38d0d4c4f4c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1159251487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1159251487
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1136462826
Short name T744
Test name
Test status
Simulation time 2820176876 ps
CPU time 6.15 seconds
Started Aug 07 05:52:40 PM PDT 24
Finished Aug 07 05:52:46 PM PDT 24
Peak memory 198520 kb
Host smart-b8c5dc34-ebd3-4156-8e30-aee068404202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136462826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1136462826
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.82999142
Short name T1102
Test name
Test status
Simulation time 162455838744 ps
CPU time 84.83 seconds
Started Aug 07 05:52:39 PM PDT 24
Finished Aug 07 05:54:04 PM PDT 24
Peak memory 208144 kb
Host smart-48d9a5d0-a1ea-4fa4-ae08-5658e0adb086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82999142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.82999142
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.99264407
Short name T1109
Test name
Test status
Simulation time 5826471206 ps
CPU time 77.51 seconds
Started Aug 07 05:54:23 PM PDT 24
Finished Aug 07 05:55:41 PM PDT 24
Peak memory 199924 kb
Host smart-a766dba1-e4db-4524-bd4f-49b73a40358b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99264407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.99264407
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1379917929
Short name T365
Test name
Test status
Simulation time 6926486295 ps
CPU time 63.61 seconds
Started Aug 07 05:52:38 PM PDT 24
Finished Aug 07 05:53:42 PM PDT 24
Peak memory 198744 kb
Host smart-6c33650f-49e8-408d-9cc7-c8bcd1bf9858
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1379917929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1379917929
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.3117373991
Short name T370
Test name
Test status
Simulation time 43489711086 ps
CPU time 9.65 seconds
Started Aug 07 05:52:38 PM PDT 24
Finished Aug 07 05:52:47 PM PDT 24
Peak memory 199508 kb
Host smart-b32f3f35-434e-4597-985f-dd956788f3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117373991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3117373991
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1662213732
Short name T463
Test name
Test status
Simulation time 3697105636 ps
CPU time 2.22 seconds
Started Aug 07 05:52:40 PM PDT 24
Finished Aug 07 05:52:42 PM PDT 24
Peak memory 195492 kb
Host smart-8da38d52-4b9c-44a0-8eb7-92017fb25aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662213732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1662213732
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2368751780
Short name T1099
Test name
Test status
Simulation time 268878517 ps
CPU time 1.42 seconds
Started Aug 07 05:52:38 PM PDT 24
Finished Aug 07 05:52:39 PM PDT 24
Peak memory 199728 kb
Host smart-c1b66e9f-7086-48fe-9237-e3f140bf2fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368751780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2368751780
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.714375161
Short name T187
Test name
Test status
Simulation time 62332186839 ps
CPU time 470.05 seconds
Started Aug 07 05:52:44 PM PDT 24
Finished Aug 07 06:00:35 PM PDT 24
Peak memory 224696 kb
Host smart-6cb41492-81ec-4d15-bf2d-f8c7b6f5e630
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714375161 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.714375161
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.906803466
Short name T262
Test name
Test status
Simulation time 874374771 ps
CPU time 2.31 seconds
Started Aug 07 05:52:39 PM PDT 24
Finished Aug 07 05:52:41 PM PDT 24
Peak memory 199816 kb
Host smart-498c60c2-3940-4973-be94-2a78a1df9c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906803466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.906803466
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.991458905
Short name T965
Test name
Test status
Simulation time 6049590200 ps
CPU time 8.2 seconds
Started Aug 07 05:52:38 PM PDT 24
Finished Aug 07 05:52:47 PM PDT 24
Peak memory 198560 kb
Host smart-14961309-8f51-4f5c-8444-38da0d71c00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991458905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.991458905
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1575008967
Short name T1007
Test name
Test status
Simulation time 102071968378 ps
CPU time 186.61 seconds
Started Aug 07 05:57:17 PM PDT 24
Finished Aug 07 06:00:24 PM PDT 24
Peak memory 199820 kb
Host smart-23b33bfe-87b1-4c49-a7a1-3bed5227ed27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575008967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1575008967
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3565228665
Short name T939
Test name
Test status
Simulation time 16340088459 ps
CPU time 24.11 seconds
Started Aug 07 05:57:17 PM PDT 24
Finished Aug 07 05:57:42 PM PDT 24
Peak memory 199920 kb
Host smart-4d807a75-fca5-4240-8560-9c9729b68710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565228665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3565228665
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2769129619
Short name T525
Test name
Test status
Simulation time 236077503502 ps
CPU time 169.06 seconds
Started Aug 07 05:57:17 PM PDT 24
Finished Aug 07 06:00:06 PM PDT 24
Peak memory 199844 kb
Host smart-356736a7-e9d2-4f2b-ad13-00b8c415570d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769129619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2769129619
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.4167815966
Short name T815
Test name
Test status
Simulation time 110547203434 ps
CPU time 24.26 seconds
Started Aug 07 05:57:23 PM PDT 24
Finished Aug 07 05:57:48 PM PDT 24
Peak memory 199844 kb
Host smart-744e7abe-f914-496d-8ace-0eec16e17c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167815966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.4167815966
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2840867019
Short name T197
Test name
Test status
Simulation time 71306303994 ps
CPU time 47.94 seconds
Started Aug 07 05:57:23 PM PDT 24
Finished Aug 07 05:58:11 PM PDT 24
Peak memory 199828 kb
Host smart-126c48de-defc-4812-8466-082221796aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840867019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2840867019
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.857922903
Short name T167
Test name
Test status
Simulation time 6436784531 ps
CPU time 11.59 seconds
Started Aug 07 05:57:29 PM PDT 24
Finished Aug 07 05:57:41 PM PDT 24
Peak memory 199776 kb
Host smart-33447018-dca2-47a6-ae36-542f72aaaca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857922903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.857922903
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2769253862
Short name T1154
Test name
Test status
Simulation time 41733666899 ps
CPU time 35.25 seconds
Started Aug 07 05:57:28 PM PDT 24
Finished Aug 07 05:58:03 PM PDT 24
Peak memory 199844 kb
Host smart-30d65c81-f44b-4acc-ab83-b70db056f7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769253862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2769253862
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3465761000
Short name T485
Test name
Test status
Simulation time 305676721840 ps
CPU time 1009.25 seconds
Started Aug 07 05:57:23 PM PDT 24
Finished Aug 07 06:14:13 PM PDT 24
Peak memory 199928 kb
Host smart-82f9c03c-9df4-4135-bc92-1f18ad8141b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465761000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3465761000
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.28035994
Short name T625
Test name
Test status
Simulation time 80453975632 ps
CPU time 129.1 seconds
Started Aug 07 05:57:29 PM PDT 24
Finished Aug 07 05:59:39 PM PDT 24
Peak memory 199788 kb
Host smart-52e46757-30ea-432b-a419-4cb3f2494542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28035994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.28035994
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1511119156
Short name T623
Test name
Test status
Simulation time 40122370 ps
CPU time 0.55 seconds
Started Aug 07 05:52:51 PM PDT 24
Finished Aug 07 05:52:51 PM PDT 24
Peak memory 195612 kb
Host smart-0e8c7714-f864-4be8-9390-e27924809b22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511119156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1511119156
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.320302543
Short name T1163
Test name
Test status
Simulation time 191600706413 ps
CPU time 35.74 seconds
Started Aug 07 05:52:42 PM PDT 24
Finished Aug 07 05:53:18 PM PDT 24
Peak memory 199920 kb
Host smart-c651818a-b5fb-4e4c-a87d-f5ddceb753b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320302543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.320302543
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.919963901
Short name T166
Test name
Test status
Simulation time 223218530581 ps
CPU time 318.7 seconds
Started Aug 07 05:52:45 PM PDT 24
Finished Aug 07 05:58:03 PM PDT 24
Peak memory 199784 kb
Host smart-82455671-e8f3-4d53-8a78-e497eab0e194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919963901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.919963901
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2104041562
Short name T1036
Test name
Test status
Simulation time 61671446484 ps
CPU time 30.16 seconds
Started Aug 07 05:52:45 PM PDT 24
Finished Aug 07 05:53:16 PM PDT 24
Peak memory 199900 kb
Host smart-2657ef32-5b70-4215-be0f-48ccfff40cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104041562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2104041562
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.779415461
Short name T757
Test name
Test status
Simulation time 36161616017 ps
CPU time 27.67 seconds
Started Aug 07 05:52:45 PM PDT 24
Finished Aug 07 05:53:13 PM PDT 24
Peak memory 199920 kb
Host smart-a2c79f04-009d-4e4a-9bf2-46c0780dafc2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779415461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.779415461
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2995768696
Short name T804
Test name
Test status
Simulation time 319873732536 ps
CPU time 169.56 seconds
Started Aug 07 05:52:45 PM PDT 24
Finished Aug 07 05:55:34 PM PDT 24
Peak memory 199816 kb
Host smart-6ce1c8dd-2925-4519-988f-6f294599640c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995768696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2995768696
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1283967214
Short name T367
Test name
Test status
Simulation time 6212492404 ps
CPU time 7.21 seconds
Started Aug 07 05:54:30 PM PDT 24
Finished Aug 07 05:54:37 PM PDT 24
Peak memory 199516 kb
Host smart-a859f062-415f-4503-9ec3-621a0985bfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283967214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1283967214
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.294542660
Short name T497
Test name
Test status
Simulation time 57948322405 ps
CPU time 45.63 seconds
Started Aug 07 05:52:45 PM PDT 24
Finished Aug 07 05:53:30 PM PDT 24
Peak memory 200048 kb
Host smart-33618ad4-8edc-4786-9af8-b83e7c35f1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294542660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.294542660
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1731844609
Short name T496
Test name
Test status
Simulation time 21108224316 ps
CPU time 80.63 seconds
Started Aug 07 05:52:44 PM PDT 24
Finished Aug 07 05:54:04 PM PDT 24
Peak memory 199820 kb
Host smart-96ea1586-0fd1-4ad1-a283-93366c5e7ce1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1731844609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1731844609
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.4158333776
Short name T591
Test name
Test status
Simulation time 6534729166 ps
CPU time 13.92 seconds
Started Aug 07 05:52:44 PM PDT 24
Finished Aug 07 05:52:58 PM PDT 24
Peak memory 198608 kb
Host smart-fade771e-269b-4a21-9e8d-c13e4aa914e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4158333776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.4158333776
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2585350088
Short name T560
Test name
Test status
Simulation time 192885745075 ps
CPU time 262.62 seconds
Started Aug 07 05:52:45 PM PDT 24
Finished Aug 07 05:57:07 PM PDT 24
Peak memory 199948 kb
Host smart-71e179dd-ff9d-433b-9b8c-6524067826e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585350088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2585350088
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2720321193
Short name T756
Test name
Test status
Simulation time 48994892205 ps
CPU time 33.86 seconds
Started Aug 07 05:52:44 PM PDT 24
Finished Aug 07 05:53:18 PM PDT 24
Peak memory 196248 kb
Host smart-d2ca9ddc-d4f3-44d9-9776-cb30043b6f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720321193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2720321193
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3348614918
Short name T280
Test name
Test status
Simulation time 5351596152 ps
CPU time 13.77 seconds
Started Aug 07 05:52:44 PM PDT 24
Finished Aug 07 05:52:58 PM PDT 24
Peak memory 199876 kb
Host smart-a838c14b-16e2-4506-b2fc-422f39dc1f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348614918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3348614918
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1658874897
Short name T880
Test name
Test status
Simulation time 18083078011 ps
CPU time 10.75 seconds
Started Aug 07 05:52:49 PM PDT 24
Finished Aug 07 05:52:59 PM PDT 24
Peak memory 199880 kb
Host smart-d73751cc-f21a-4636-b24f-70d2af8362f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658874897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1658874897
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.411949924
Short name T905
Test name
Test status
Simulation time 78373131783 ps
CPU time 254.41 seconds
Started Aug 07 05:52:49 PM PDT 24
Finished Aug 07 05:57:03 PM PDT 24
Peak memory 216340 kb
Host smart-72c43da5-3935-44ed-9854-9f1eeaeaa873
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411949924 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.411949924
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.425308888
Short name T746
Test name
Test status
Simulation time 477921375 ps
CPU time 1.45 seconds
Started Aug 07 05:52:43 PM PDT 24
Finished Aug 07 05:52:45 PM PDT 24
Peak memory 198252 kb
Host smart-a6ec1c56-9753-48b6-9b54-ea4052ccedef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425308888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.425308888
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.4069512593
Short name T265
Test name
Test status
Simulation time 69261395990 ps
CPU time 103.82 seconds
Started Aug 07 05:54:22 PM PDT 24
Finished Aug 07 05:56:06 PM PDT 24
Peak memory 199876 kb
Host smart-94ef9f31-a9cc-4559-96d3-85fedb674249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069512593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.4069512593
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.744428469
Short name T834
Test name
Test status
Simulation time 103143066784 ps
CPU time 22.79 seconds
Started Aug 07 05:57:23 PM PDT 24
Finished Aug 07 05:57:46 PM PDT 24
Peak memory 199924 kb
Host smart-8bf3ae24-812f-4dc6-b877-fc7fc430e112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744428469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.744428469
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2011585175
Short name T620
Test name
Test status
Simulation time 44802228000 ps
CPU time 57.77 seconds
Started Aug 07 05:57:22 PM PDT 24
Finished Aug 07 05:58:20 PM PDT 24
Peak memory 199804 kb
Host smart-b04c55b0-7c33-416f-ad1d-e8790d83a8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011585175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2011585175
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2873769495
Short name T474
Test name
Test status
Simulation time 7906798942 ps
CPU time 3.94 seconds
Started Aug 07 05:57:22 PM PDT 24
Finished Aug 07 05:57:27 PM PDT 24
Peak memory 199688 kb
Host smart-bfe176f1-4bdd-4bc9-8d39-2c1e80090a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873769495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2873769495
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.300490693
Short name T226
Test name
Test status
Simulation time 99248786950 ps
CPU time 350.18 seconds
Started Aug 07 05:57:29 PM PDT 24
Finished Aug 07 06:03:19 PM PDT 24
Peak memory 199768 kb
Host smart-33d8306c-c6fc-4138-b8b4-95ad56114709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300490693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.300490693
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2256367305
Short name T515
Test name
Test status
Simulation time 17492678817 ps
CPU time 24.56 seconds
Started Aug 07 05:57:28 PM PDT 24
Finished Aug 07 05:57:52 PM PDT 24
Peak memory 199880 kb
Host smart-4ac836d6-616a-410e-a61e-641d5c6e65c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256367305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2256367305
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3891646388
Short name T360
Test name
Test status
Simulation time 78639142818 ps
CPU time 20.68 seconds
Started Aug 07 05:57:28 PM PDT 24
Finished Aug 07 05:57:49 PM PDT 24
Peak memory 199680 kb
Host smart-5e7ce26a-0e92-4070-9811-6991ff145638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891646388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3891646388
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1230692587
Short name T168
Test name
Test status
Simulation time 29810490719 ps
CPU time 17.84 seconds
Started Aug 07 05:57:29 PM PDT 24
Finished Aug 07 05:57:47 PM PDT 24
Peak memory 199904 kb
Host smart-1c6039e3-1dc3-4d7d-8a01-788739f305a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230692587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1230692587
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1385251581
Short name T178
Test name
Test status
Simulation time 7502262057 ps
CPU time 12.66 seconds
Started Aug 07 05:57:29 PM PDT 24
Finished Aug 07 05:57:42 PM PDT 24
Peak memory 199320 kb
Host smart-301467ff-cf3e-4e1d-bf9b-3037a2c78d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385251581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1385251581
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3034678497
Short name T1015
Test name
Test status
Simulation time 37426177 ps
CPU time 0.56 seconds
Started Aug 07 05:52:56 PM PDT 24
Finished Aug 07 05:52:56 PM PDT 24
Peak memory 194676 kb
Host smart-e3ed7746-1653-4337-9bdd-0d990933e247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034678497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3034678497
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3942518601
Short name T859
Test name
Test status
Simulation time 34464743021 ps
CPU time 13.64 seconds
Started Aug 07 05:52:48 PM PDT 24
Finished Aug 07 05:53:02 PM PDT 24
Peak memory 199916 kb
Host smart-c36f6b42-e722-4269-a049-64ad016f8f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942518601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3942518601
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2437227135
Short name T1041
Test name
Test status
Simulation time 20662250406 ps
CPU time 31.96 seconds
Started Aug 07 05:52:48 PM PDT 24
Finished Aug 07 05:53:20 PM PDT 24
Peak memory 199948 kb
Host smart-3543b3df-7cb4-471a-832f-7d551e2f873f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437227135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2437227135
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1616795401
Short name T203
Test name
Test status
Simulation time 169861769650 ps
CPU time 408.3 seconds
Started Aug 07 05:52:50 PM PDT 24
Finished Aug 07 05:59:38 PM PDT 24
Peak memory 199788 kb
Host smart-17024ea6-cb6e-4f41-be12-9277d9ba0aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616795401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1616795401
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.560360506
Short name T15
Test name
Test status
Simulation time 14450921908 ps
CPU time 23.8 seconds
Started Aug 07 05:52:49 PM PDT 24
Finished Aug 07 05:53:12 PM PDT 24
Peak memory 196608 kb
Host smart-0155c275-d5d5-4fb8-a578-136ce64fbb1f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560360506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.560360506
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1230866777
Short name T514
Test name
Test status
Simulation time 83616474116 ps
CPU time 851.17 seconds
Started Aug 07 05:52:58 PM PDT 24
Finished Aug 07 06:07:10 PM PDT 24
Peak memory 199828 kb
Host smart-f35ae865-0195-4bc7-821e-282c5f5c4f16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1230866777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1230866777
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2276696456
Short name T755
Test name
Test status
Simulation time 7172071617 ps
CPU time 13.33 seconds
Started Aug 07 05:52:48 PM PDT 24
Finished Aug 07 05:53:01 PM PDT 24
Peak memory 199924 kb
Host smart-b0155306-a90a-40f7-b159-4a8cf425f5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276696456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2276696456
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1397551626
Short name T550
Test name
Test status
Simulation time 28158594397 ps
CPU time 12.15 seconds
Started Aug 07 05:52:49 PM PDT 24
Finished Aug 07 05:53:01 PM PDT 24
Peak memory 199792 kb
Host smart-95b35f10-f59b-4a39-a61b-d3e8f4413d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397551626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1397551626
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3991928048
Short name T778
Test name
Test status
Simulation time 13615539131 ps
CPU time 169.28 seconds
Started Aug 07 05:52:56 PM PDT 24
Finished Aug 07 05:55:46 PM PDT 24
Peak memory 199716 kb
Host smart-c5631ddf-2193-4642-9b64-3d66291171b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3991928048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3991928048
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1487571591
Short name T394
Test name
Test status
Simulation time 4295003481 ps
CPU time 18.92 seconds
Started Aug 07 05:52:50 PM PDT 24
Finished Aug 07 05:53:09 PM PDT 24
Peak memory 199388 kb
Host smart-8734ea89-43e0-4d4e-a925-2233792ef737
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1487571591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1487571591
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.450729003
Short name T831
Test name
Test status
Simulation time 212635391881 ps
CPU time 314.57 seconds
Started Aug 07 05:52:50 PM PDT 24
Finished Aug 07 05:58:04 PM PDT 24
Peak memory 199828 kb
Host smart-9154fb0f-54c1-4037-82db-d6ca28d76fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450729003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.450729003
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1825685635
Short name T1079
Test name
Test status
Simulation time 3067504570 ps
CPU time 5.2 seconds
Started Aug 07 05:52:47 PM PDT 24
Finished Aug 07 05:52:53 PM PDT 24
Peak memory 196392 kb
Host smart-cde8c212-bbf0-4974-ac70-1d6560aa73c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825685635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1825685635
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2187934674
Short name T1175
Test name
Test status
Simulation time 703203972 ps
CPU time 1.45 seconds
Started Aug 07 05:54:27 PM PDT 24
Finished Aug 07 05:54:29 PM PDT 24
Peak memory 199764 kb
Host smart-830fac98-5189-414a-aa00-af0d7da0a692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187934674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2187934674
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3320292181
Short name T1131
Test name
Test status
Simulation time 354584083709 ps
CPU time 560.09 seconds
Started Aug 07 05:52:57 PM PDT 24
Finished Aug 07 06:02:17 PM PDT 24
Peak memory 199812 kb
Host smart-80725555-6e47-4203-9605-7613dc08fafc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320292181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3320292181
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.4202548768
Short name T988
Test name
Test status
Simulation time 36595983519 ps
CPU time 540.96 seconds
Started Aug 07 05:52:55 PM PDT 24
Finished Aug 07 06:01:56 PM PDT 24
Peak memory 210932 kb
Host smart-63236c55-0e32-45d3-a6d3-badd401b1944
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202548768 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.4202548768
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1098437522
Short name T275
Test name
Test status
Simulation time 540884620 ps
CPU time 1.85 seconds
Started Aug 07 05:52:48 PM PDT 24
Finished Aug 07 05:52:50 PM PDT 24
Peak memory 198632 kb
Host smart-0a3b1db8-6d27-40b0-a083-0cc70249ac59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098437522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1098437522
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1132124270
Short name T786
Test name
Test status
Simulation time 26450902810 ps
CPU time 42.4 seconds
Started Aug 07 05:54:27 PM PDT 24
Finished Aug 07 05:55:10 PM PDT 24
Peak memory 199916 kb
Host smart-e5b298de-8422-46a0-8a50-5dba99d31827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132124270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1132124270
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.692726731
Short name T201
Test name
Test status
Simulation time 25061796257 ps
CPU time 53.9 seconds
Started Aug 07 05:57:26 PM PDT 24
Finished Aug 07 05:58:20 PM PDT 24
Peak memory 199900 kb
Host smart-61c96788-2031-4b8f-9a38-5c9feb16e22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692726731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.692726731
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.4278328075
Short name T1080
Test name
Test status
Simulation time 23807393339 ps
CPU time 33.08 seconds
Started Aug 07 05:57:27 PM PDT 24
Finished Aug 07 05:58:00 PM PDT 24
Peak memory 199932 kb
Host smart-49687c83-4a35-4251-889a-a850482f1d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278328075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.4278328075
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1048310854
Short name T1068
Test name
Test status
Simulation time 106075534475 ps
CPU time 45.43 seconds
Started Aug 07 05:57:30 PM PDT 24
Finished Aug 07 05:58:16 PM PDT 24
Peak memory 199852 kb
Host smart-d6fae5b0-ae9f-4195-ad46-e358ae51fee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048310854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1048310854
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1478712721
Short name T235
Test name
Test status
Simulation time 49072342046 ps
CPU time 37.65 seconds
Started Aug 07 05:57:27 PM PDT 24
Finished Aug 07 05:58:05 PM PDT 24
Peak memory 199880 kb
Host smart-d85a0947-9a2f-48a5-8a29-90f152f04931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478712721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1478712721
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.724471830
Short name T935
Test name
Test status
Simulation time 174750159648 ps
CPU time 112.75 seconds
Started Aug 07 05:57:30 PM PDT 24
Finished Aug 07 05:59:22 PM PDT 24
Peak memory 200080 kb
Host smart-f6d18fcd-39bd-4d5c-82e4-ecf9b3a7567a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724471830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.724471830
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3640018510
Short name T666
Test name
Test status
Simulation time 79460340087 ps
CPU time 412.04 seconds
Started Aug 07 05:57:31 PM PDT 24
Finished Aug 07 06:04:23 PM PDT 24
Peak memory 199912 kb
Host smart-ad7ceeeb-a9b2-47fb-9fd4-903afc7f366a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640018510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3640018510
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.48049328
Short name T208
Test name
Test status
Simulation time 16192540284 ps
CPU time 25.07 seconds
Started Aug 07 05:57:29 PM PDT 24
Finished Aug 07 05:57:54 PM PDT 24
Peak memory 199896 kb
Host smart-e67a6fa3-110b-4a89-8e48-f5ebc8b85aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48049328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.48049328
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.4076819389
Short name T732
Test name
Test status
Simulation time 78058083970 ps
CPU time 13.81 seconds
Started Aug 07 05:57:28 PM PDT 24
Finished Aug 07 05:57:42 PM PDT 24
Peak memory 199784 kb
Host smart-e0b77fff-d9ac-4443-b429-ef6adb24ad60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076819389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.4076819389
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2579250068
Short name T216
Test name
Test status
Simulation time 58139263285 ps
CPU time 25.25 seconds
Started Aug 07 05:57:51 PM PDT 24
Finished Aug 07 05:58:16 PM PDT 24
Peak memory 199884 kb
Host smart-3e35d798-22bd-4ed1-a62e-ae5d40638f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579250068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2579250068
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3944699171
Short name T1136
Test name
Test status
Simulation time 25471336 ps
CPU time 0.57 seconds
Started Aug 07 05:53:03 PM PDT 24
Finished Aug 07 05:53:03 PM PDT 24
Peak memory 195296 kb
Host smart-f47342a6-c049-49a6-b5ed-6815731b1722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944699171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3944699171
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.2644826379
Short name T866
Test name
Test status
Simulation time 200154095556 ps
CPU time 65.43 seconds
Started Aug 07 05:52:56 PM PDT 24
Finished Aug 07 05:54:02 PM PDT 24
Peak memory 199916 kb
Host smart-5a667351-41f0-447c-8fff-3086d22f929e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644826379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2644826379
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.981789689
Short name T374
Test name
Test status
Simulation time 31738791983 ps
CPU time 48.56 seconds
Started Aug 07 05:52:58 PM PDT 24
Finished Aug 07 05:53:46 PM PDT 24
Peak memory 199908 kb
Host smart-88e09e36-67eb-46a7-a5d9-1ccac3036bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981789689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.981789689
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_intr.800087678
Short name T396
Test name
Test status
Simulation time 9184922119 ps
CPU time 20.1 seconds
Started Aug 07 05:52:55 PM PDT 24
Finished Aug 07 05:53:15 PM PDT 24
Peak memory 199788 kb
Host smart-6dc0ec9a-8b54-44f1-9d55-c431ddd20d98
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800087678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.800087678
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3542041479
Short name T383
Test name
Test status
Simulation time 84171224269 ps
CPU time 499.28 seconds
Started Aug 07 05:54:28 PM PDT 24
Finished Aug 07 06:02:48 PM PDT 24
Peak memory 199816 kb
Host smart-18c0e34f-321a-4d22-a643-4057dcd2c30e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3542041479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3542041479
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2090887207
Short name T1029
Test name
Test status
Simulation time 6507227563 ps
CPU time 6.6 seconds
Started Aug 07 05:53:05 PM PDT 24
Finished Aug 07 05:53:11 PM PDT 24
Peak memory 198416 kb
Host smart-f91fe1be-76df-4d96-91d0-bb3d17658b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090887207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2090887207
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.814419173
Short name T1147
Test name
Test status
Simulation time 112185212798 ps
CPU time 66.71 seconds
Started Aug 07 05:52:59 PM PDT 24
Finished Aug 07 05:54:06 PM PDT 24
Peak memory 198656 kb
Host smart-b5e0205a-41c8-41b3-8550-e1a38ff92c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814419173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.814419173
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1131023453
Short name T914
Test name
Test status
Simulation time 13819817105 ps
CPU time 812.16 seconds
Started Aug 07 05:53:04 PM PDT 24
Finished Aug 07 06:06:36 PM PDT 24
Peak memory 199864 kb
Host smart-4bd92cdf-5d7c-4d56-add8-e186f6f9a797
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1131023453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1131023453
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1012740274
Short name T74
Test name
Test status
Simulation time 6219623238 ps
CPU time 15 seconds
Started Aug 07 05:52:55 PM PDT 24
Finished Aug 07 05:53:10 PM PDT 24
Peak memory 197972 kb
Host smart-d66b52d2-b09b-481d-95c5-c92bfdfda523
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1012740274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1012740274
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2777841625
Short name T541
Test name
Test status
Simulation time 35881849151 ps
CPU time 22.3 seconds
Started Aug 07 05:54:24 PM PDT 24
Finished Aug 07 05:54:46 PM PDT 24
Peak memory 199908 kb
Host smart-83ae3270-6aa2-4bee-a715-3625b79b9859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777841625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2777841625
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1654707792
Short name T990
Test name
Test status
Simulation time 1799536989 ps
CPU time 3.5 seconds
Started Aug 07 05:53:03 PM PDT 24
Finished Aug 07 05:53:07 PM PDT 24
Peak memory 195596 kb
Host smart-9cf360f8-59d6-46e3-8ec6-853875209afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654707792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1654707792
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2586868292
Short name T553
Test name
Test status
Simulation time 685360408 ps
CPU time 1.47 seconds
Started Aug 07 05:52:55 PM PDT 24
Finished Aug 07 05:52:57 PM PDT 24
Peak memory 198228 kb
Host smart-677b77d8-1387-4f10-a999-124be15b6dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586868292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2586868292
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.126349776
Short name T194
Test name
Test status
Simulation time 231149424661 ps
CPU time 242.63 seconds
Started Aug 07 05:54:31 PM PDT 24
Finished Aug 07 05:58:34 PM PDT 24
Peak memory 199880 kb
Host smart-a5dbb895-0d73-4b23-9cce-81627366e5a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126349776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.126349776
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1323888615
Short name T1010
Test name
Test status
Simulation time 300223657453 ps
CPU time 803 seconds
Started Aug 07 05:53:07 PM PDT 24
Finished Aug 07 06:06:30 PM PDT 24
Peak memory 224700 kb
Host smart-4b08318b-8670-4e6d-b6ad-e3910613b144
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323888615 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1323888615
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2858521309
Short name T310
Test name
Test status
Simulation time 932011323 ps
CPU time 2.9 seconds
Started Aug 07 05:53:06 PM PDT 24
Finished Aug 07 05:53:09 PM PDT 24
Peak memory 199360 kb
Host smart-e02ce602-4f07-437f-b603-6da9ff0064ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858521309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2858521309
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.518760103
Short name T676
Test name
Test status
Simulation time 8831793095 ps
CPU time 11.93 seconds
Started Aug 07 05:52:57 PM PDT 24
Finished Aug 07 05:53:09 PM PDT 24
Peak memory 199652 kb
Host smart-a8e716da-4525-4c38-a951-1c9c9075cacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518760103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.518760103
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.4210462886
Short name T269
Test name
Test status
Simulation time 4442500715 ps
CPU time 8.2 seconds
Started Aug 07 05:57:43 PM PDT 24
Finished Aug 07 05:57:51 PM PDT 24
Peak memory 199892 kb
Host smart-40b749ac-bcc7-497b-9827-db0835d7a572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210462886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.4210462886
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1246068858
Short name T1140
Test name
Test status
Simulation time 48145995665 ps
CPU time 17.12 seconds
Started Aug 07 05:57:41 PM PDT 24
Finished Aug 07 05:57:59 PM PDT 24
Peak memory 199656 kb
Host smart-cc59d58d-bf0c-4c6d-ba3e-56d9f5734279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246068858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1246068858
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3438701025
Short name T1126
Test name
Test status
Simulation time 31768312511 ps
CPU time 24.64 seconds
Started Aug 07 05:57:40 PM PDT 24
Finished Aug 07 05:58:05 PM PDT 24
Peak memory 199924 kb
Host smart-9a9119d0-4771-42ac-8465-afc82d6288b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438701025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3438701025
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3188206107
Short name T417
Test name
Test status
Simulation time 21172213841 ps
CPU time 31.05 seconds
Started Aug 07 05:57:57 PM PDT 24
Finished Aug 07 05:58:29 PM PDT 24
Peak memory 199852 kb
Host smart-f8988e47-7a5a-4d77-a26f-1d19703712cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188206107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3188206107
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.4222712228
Short name T228
Test name
Test status
Simulation time 28586012751 ps
CPU time 24.75 seconds
Started Aug 07 05:57:42 PM PDT 24
Finished Aug 07 05:58:07 PM PDT 24
Peak memory 199904 kb
Host smart-db0d4f75-15a9-4fd5-b0ad-13f4b48a0589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222712228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.4222712228
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1655057981
Short name T444
Test name
Test status
Simulation time 44618558753 ps
CPU time 11.34 seconds
Started Aug 07 05:57:40 PM PDT 24
Finished Aug 07 05:57:52 PM PDT 24
Peak memory 199932 kb
Host smart-5833f764-b54d-4a81-9649-22998cc09e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655057981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1655057981
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3746382538
Short name T1133
Test name
Test status
Simulation time 40587393281 ps
CPU time 17.01 seconds
Started Aug 07 05:57:40 PM PDT 24
Finished Aug 07 05:57:57 PM PDT 24
Peak memory 199816 kb
Host smart-560d2887-738f-49a9-977e-0a40321f9ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746382538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3746382538
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.286032810
Short name T399
Test name
Test status
Simulation time 2703528790 ps
CPU time 4.19 seconds
Started Aug 07 05:57:41 PM PDT 24
Finished Aug 07 05:57:46 PM PDT 24
Peak memory 199440 kb
Host smart-b358643b-eee5-4dbd-b909-601b8362c635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286032810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.286032810
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.696607941
Short name T26
Test name
Test status
Simulation time 28049958 ps
CPU time 0.58 seconds
Started Aug 07 05:53:03 PM PDT 24
Finished Aug 07 05:53:03 PM PDT 24
Peak memory 194248 kb
Host smart-438c2b87-1509-4e78-8b2a-3fb3a6cda998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696607941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.696607941
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1295040851
Short name T998
Test name
Test status
Simulation time 119155935901 ps
CPU time 48.47 seconds
Started Aug 07 05:53:03 PM PDT 24
Finished Aug 07 05:53:51 PM PDT 24
Peak memory 199788 kb
Host smart-38433515-d325-4948-9981-4261e74f10f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295040851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1295040851
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.456864436
Short name T944
Test name
Test status
Simulation time 134698459022 ps
CPU time 40.77 seconds
Started Aug 07 05:53:03 PM PDT 24
Finished Aug 07 05:53:44 PM PDT 24
Peak memory 199780 kb
Host smart-be912b79-fdfa-49f2-9cf7-484a8b5a66cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456864436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.456864436
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2142017083
Short name T204
Test name
Test status
Simulation time 31544973341 ps
CPU time 12.24 seconds
Started Aug 07 05:54:28 PM PDT 24
Finished Aug 07 05:54:40 PM PDT 24
Peak memory 199904 kb
Host smart-1f5e3cbe-76cd-4b22-9750-6ecdd260a856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142017083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2142017083
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.904499046
Short name T873
Test name
Test status
Simulation time 44753854559 ps
CPU time 67.87 seconds
Started Aug 07 05:54:23 PM PDT 24
Finished Aug 07 05:55:31 PM PDT 24
Peak memory 199780 kb
Host smart-d682aaf4-6833-49a5-afeb-4b360301ff58
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904499046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.904499046
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3409986064
Short name T1177
Test name
Test status
Simulation time 99704912127 ps
CPU time 737.57 seconds
Started Aug 07 05:53:03 PM PDT 24
Finished Aug 07 06:05:21 PM PDT 24
Peak memory 199892 kb
Host smart-e49dbade-7489-4156-9de4-155e174df6ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3409986064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3409986064
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2042383051
Short name T450
Test name
Test status
Simulation time 6308181285 ps
CPU time 14.06 seconds
Started Aug 07 05:53:02 PM PDT 24
Finished Aug 07 05:53:16 PM PDT 24
Peak memory 199504 kb
Host smart-70243cc9-c05b-44b9-8e58-e77f51f5a227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042383051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2042383051
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.1975015679
Short name T1152
Test name
Test status
Simulation time 33461689936 ps
CPU time 61.5 seconds
Started Aug 07 05:53:07 PM PDT 24
Finished Aug 07 05:54:08 PM PDT 24
Peak memory 208264 kb
Host smart-70bc733a-b4eb-4a1a-8c57-f531ee90ba7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975015679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1975015679
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1690940300
Short name T888
Test name
Test status
Simulation time 19666103049 ps
CPU time 553.59 seconds
Started Aug 07 05:53:02 PM PDT 24
Finished Aug 07 06:02:16 PM PDT 24
Peak memory 199932 kb
Host smart-1b75a3d1-9de4-46c3-8ae5-4c19af9a2063
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1690940300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1690940300
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2154629629
Short name T769
Test name
Test status
Simulation time 2941072527 ps
CPU time 9.15 seconds
Started Aug 07 05:53:04 PM PDT 24
Finished Aug 07 05:53:13 PM PDT 24
Peak memory 198316 kb
Host smart-572f5821-b70a-4b8c-a2da-932917fe4b61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2154629629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2154629629
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2324552390
Short name T475
Test name
Test status
Simulation time 76268920729 ps
CPU time 32.07 seconds
Started Aug 07 05:53:03 PM PDT 24
Finished Aug 07 05:53:35 PM PDT 24
Peak memory 199900 kb
Host smart-89184f80-ae1e-4d02-81f6-407e5df52c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324552390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2324552390
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.650176601
Short name T336
Test name
Test status
Simulation time 6708326316 ps
CPU time 9.41 seconds
Started Aug 07 05:53:03 PM PDT 24
Finished Aug 07 05:53:13 PM PDT 24
Peak memory 196036 kb
Host smart-26eb0bd4-49a5-445a-841b-eca85a36d8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650176601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.650176601
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3659647753
Short name T1030
Test name
Test status
Simulation time 719912565 ps
CPU time 1.74 seconds
Started Aug 07 05:53:04 PM PDT 24
Finished Aug 07 05:53:06 PM PDT 24
Peak memory 198868 kb
Host smart-9e955225-c1ef-4cd6-a904-6fc053ae1375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659647753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3659647753
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1326565897
Short name T910
Test name
Test status
Simulation time 14234588398 ps
CPU time 545.65 seconds
Started Aug 07 05:53:03 PM PDT 24
Finished Aug 07 06:02:09 PM PDT 24
Peak memory 215556 kb
Host smart-bb8d4e14-e911-442b-99db-62699c56b2c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326565897 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1326565897
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2529122270
Short name T878
Test name
Test status
Simulation time 8685157427 ps
CPU time 6.3 seconds
Started Aug 07 05:54:35 PM PDT 24
Finished Aug 07 05:54:41 PM PDT 24
Peak memory 199252 kb
Host smart-35dcfd62-ca40-4457-9c13-3b2987b6baaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529122270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2529122270
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2303707649
Short name T945
Test name
Test status
Simulation time 77126219051 ps
CPU time 226.12 seconds
Started Aug 07 05:53:04 PM PDT 24
Finished Aug 07 05:56:50 PM PDT 24
Peak memory 199840 kb
Host smart-98f3aa7b-13ce-4a40-bafd-0a97d9a702c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303707649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2303707649
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3377760859
Short name T617
Test name
Test status
Simulation time 186460679397 ps
CPU time 69.12 seconds
Started Aug 07 05:58:42 PM PDT 24
Finished Aug 07 05:59:51 PM PDT 24
Peak memory 199860 kb
Host smart-fbfe7906-59b3-4a80-b1d0-18c12f5d14e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377760859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3377760859
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.566160995
Short name T651
Test name
Test status
Simulation time 75115426923 ps
CPU time 130.88 seconds
Started Aug 07 05:57:42 PM PDT 24
Finished Aug 07 05:59:53 PM PDT 24
Peak memory 199956 kb
Host smart-4986dd06-1efb-442a-b77c-5d108f8fdff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566160995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.566160995
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1279903529
Short name T419
Test name
Test status
Simulation time 78571863293 ps
CPU time 53.97 seconds
Started Aug 07 05:57:41 PM PDT 24
Finished Aug 07 05:58:35 PM PDT 24
Peak memory 199892 kb
Host smart-4746e2aa-f4b2-457a-ace6-aa4866721c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279903529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1279903529
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2361764924
Short name T460
Test name
Test status
Simulation time 83069114188 ps
CPU time 70.7 seconds
Started Aug 07 05:57:51 PM PDT 24
Finished Aug 07 05:59:02 PM PDT 24
Peak memory 199824 kb
Host smart-2496f79f-1b9c-4b75-86dc-20b5f75849dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361764924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2361764924
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.24570535
Short name T139
Test name
Test status
Simulation time 282218937527 ps
CPU time 23.62 seconds
Started Aug 07 05:57:41 PM PDT 24
Finished Aug 07 05:58:05 PM PDT 24
Peak memory 199892 kb
Host smart-6269a23e-9b27-4e61-a006-487ce231b1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24570535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.24570535
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2128676506
Short name T438
Test name
Test status
Simulation time 45793287230 ps
CPU time 35.7 seconds
Started Aug 07 05:57:43 PM PDT 24
Finished Aug 07 05:58:18 PM PDT 24
Peak memory 199888 kb
Host smart-d36ab848-3fac-4f02-8f19-0fbb726618cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128676506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2128676506
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2251222661
Short name T489
Test name
Test status
Simulation time 28139023306 ps
CPU time 12.53 seconds
Started Aug 07 05:57:45 PM PDT 24
Finished Aug 07 05:57:57 PM PDT 24
Peak memory 199940 kb
Host smart-fb335888-fc1d-45ce-b3dc-c5e609759253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251222661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2251222661
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3798514796
Short name T125
Test name
Test status
Simulation time 54846870695 ps
CPU time 58.88 seconds
Started Aug 07 05:57:42 PM PDT 24
Finished Aug 07 05:58:41 PM PDT 24
Peak memory 199824 kb
Host smart-60f290f2-4572-461c-84aa-d8bc0c007d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798514796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3798514796
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2745375309
Short name T422
Test name
Test status
Simulation time 20104908989 ps
CPU time 17.33 seconds
Started Aug 07 05:58:45 PM PDT 24
Finished Aug 07 05:59:02 PM PDT 24
Peak memory 199892 kb
Host smart-594b985e-6047-49c1-8a6b-900b49225d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745375309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2745375309
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2996370441
Short name T797
Test name
Test status
Simulation time 12957721 ps
CPU time 0.57 seconds
Started Aug 07 05:53:09 PM PDT 24
Finished Aug 07 05:53:10 PM PDT 24
Peak memory 195584 kb
Host smart-4ab6fc86-2719-43e4-97b6-3973e764b427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996370441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2996370441
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2209307261
Short name T673
Test name
Test status
Simulation time 111713562867 ps
CPU time 128.63 seconds
Started Aug 07 05:53:07 PM PDT 24
Finished Aug 07 05:55:16 PM PDT 24
Peak memory 199888 kb
Host smart-fb300d68-94b9-4d15-8fe5-a7b980e33143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209307261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2209307261
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.958156755
Short name T962
Test name
Test status
Simulation time 250680782000 ps
CPU time 72.41 seconds
Started Aug 07 05:53:10 PM PDT 24
Finished Aug 07 05:54:22 PM PDT 24
Peak memory 199900 kb
Host smart-5517b996-5955-4f5e-9a57-bd6e9f59c71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958156755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.958156755
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.4184432224
Short name T258
Test name
Test status
Simulation time 88418562307 ps
CPU time 19.89 seconds
Started Aug 07 05:53:10 PM PDT 24
Finished Aug 07 05:53:30 PM PDT 24
Peak memory 199884 kb
Host smart-01f2f757-d511-4242-8f75-8b644f3b1e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184432224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.4184432224
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2806987796
Short name T922
Test name
Test status
Simulation time 132166884419 ps
CPU time 120.48 seconds
Started Aug 07 05:53:12 PM PDT 24
Finished Aug 07 05:55:12 PM PDT 24
Peak memory 199856 kb
Host smart-183fad37-7a87-4771-9687-a136940e434a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806987796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2806987796
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1255616099
Short name T643
Test name
Test status
Simulation time 89650196371 ps
CPU time 302.65 seconds
Started Aug 07 05:54:39 PM PDT 24
Finished Aug 07 05:59:42 PM PDT 24
Peak memory 199840 kb
Host smart-df59afe8-71e8-4d83-8626-59f8fd039e99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1255616099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1255616099
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1518949420
Short name T862
Test name
Test status
Simulation time 4893817307 ps
CPU time 8.97 seconds
Started Aug 07 05:53:11 PM PDT 24
Finished Aug 07 05:53:20 PM PDT 24
Peak memory 199572 kb
Host smart-b1836557-2188-40e9-9e02-658dc0d22667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518949420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1518949420
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.239027648
Short name T1112
Test name
Test status
Simulation time 18986283135 ps
CPU time 29.88 seconds
Started Aug 07 05:53:11 PM PDT 24
Finished Aug 07 05:53:41 PM PDT 24
Peak memory 197932 kb
Host smart-47c6177b-b9c5-4a8c-bc8c-ab3ba857be7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239027648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.239027648
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.4275235984
Short name T302
Test name
Test status
Simulation time 22314484549 ps
CPU time 276.07 seconds
Started Aug 07 05:53:11 PM PDT 24
Finished Aug 07 05:57:47 PM PDT 24
Peak memory 199832 kb
Host smart-f9eab168-749c-43be-aca0-5d1ce12eba47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4275235984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.4275235984
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2715516028
Short name T911
Test name
Test status
Simulation time 7235822490 ps
CPU time 70.59 seconds
Started Aug 07 05:53:10 PM PDT 24
Finished Aug 07 05:54:20 PM PDT 24
Peak memory 198192 kb
Host smart-7571d4c1-b777-401b-b174-9b449409d533
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2715516028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2715516028
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3430755335
Short name T554
Test name
Test status
Simulation time 108769544019 ps
CPU time 214.47 seconds
Started Aug 07 05:53:12 PM PDT 24
Finished Aug 07 05:56:47 PM PDT 24
Peak memory 199392 kb
Host smart-a4c15d7b-9ca5-4863-a3b1-29198c26fffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430755335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3430755335
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2746611711
Short name T821
Test name
Test status
Simulation time 5096873696 ps
CPU time 2.65 seconds
Started Aug 07 05:53:09 PM PDT 24
Finished Aug 07 05:53:12 PM PDT 24
Peak memory 196792 kb
Host smart-e8481334-2b07-4801-9e45-03d712e710d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746611711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2746611711
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3765091729
Short name T720
Test name
Test status
Simulation time 491328117 ps
CPU time 1.55 seconds
Started Aug 07 05:53:01 PM PDT 24
Finished Aug 07 05:53:02 PM PDT 24
Peak memory 199484 kb
Host smart-c0205808-7455-4949-8ab0-13b02d59b7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765091729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3765091729
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.1419536638
Short name T71
Test name
Test status
Simulation time 53356673240 ps
CPU time 25.91 seconds
Started Aug 07 05:53:12 PM PDT 24
Finished Aug 07 05:53:38 PM PDT 24
Peak memory 199900 kb
Host smart-06e08727-7937-4537-abd4-ef31b0e0f816
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419536638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1419536638
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2190504919
Short name T51
Test name
Test status
Simulation time 493736167830 ps
CPU time 1294.65 seconds
Started Aug 07 05:53:10 PM PDT 24
Finished Aug 07 06:14:45 PM PDT 24
Peak memory 227396 kb
Host smart-431b7fce-a655-44e8-bdd7-b7b50cc4707a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190504919 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2190504919
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.451257882
Short name T263
Test name
Test status
Simulation time 653203011 ps
CPU time 2.44 seconds
Started Aug 07 05:53:09 PM PDT 24
Finished Aug 07 05:53:12 PM PDT 24
Peak memory 198928 kb
Host smart-8577514e-19f1-4676-b796-b50c09c9f904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451257882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.451257882
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.4089466306
Short name T316
Test name
Test status
Simulation time 19232700950 ps
CPU time 14.88 seconds
Started Aug 07 05:53:04 PM PDT 24
Finished Aug 07 05:53:19 PM PDT 24
Peak memory 197160 kb
Host smart-473d2e04-ef8f-4b79-8bb3-101f38efa100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089466306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.4089466306
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1228936652
Short name T912
Test name
Test status
Simulation time 137266203099 ps
CPU time 12.64 seconds
Started Aug 07 05:57:42 PM PDT 24
Finished Aug 07 05:57:54 PM PDT 24
Peak memory 199844 kb
Host smart-7b904095-2922-4a8c-8237-e2d2a6a4fdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228936652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1228936652
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1640375000
Short name T320
Test name
Test status
Simulation time 48353938800 ps
CPU time 43.02 seconds
Started Aug 07 05:57:41 PM PDT 24
Finished Aug 07 05:58:25 PM PDT 24
Peak memory 199916 kb
Host smart-be3cfe30-ce80-47f0-b057-080e853615a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640375000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1640375000
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1709584904
Short name T233
Test name
Test status
Simulation time 5264503593 ps
CPU time 4.3 seconds
Started Aug 07 05:57:44 PM PDT 24
Finished Aug 07 05:57:49 PM PDT 24
Peak memory 199912 kb
Host smart-4bcb7a49-821c-4df5-a305-fa38c646aefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709584904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1709584904
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.122409326
Short name T45
Test name
Test status
Simulation time 24246482563 ps
CPU time 43.11 seconds
Started Aug 07 05:57:46 PM PDT 24
Finished Aug 07 05:58:30 PM PDT 24
Peak memory 199872 kb
Host smart-0a201c46-b21b-4006-96db-c537f6d5afd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122409326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.122409326
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2708095383
Short name T592
Test name
Test status
Simulation time 214287093455 ps
CPU time 174.41 seconds
Started Aug 07 05:57:48 PM PDT 24
Finished Aug 07 06:00:43 PM PDT 24
Peak memory 199864 kb
Host smart-7e1b8029-6531-4937-bc87-e94ad9506126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708095383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2708095383
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3397542462
Short name T1073
Test name
Test status
Simulation time 52736461789 ps
CPU time 84.51 seconds
Started Aug 07 05:57:44 PM PDT 24
Finished Aug 07 05:59:09 PM PDT 24
Peak memory 199912 kb
Host smart-25dfd625-1771-4159-a7d6-50e41f71e864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397542462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3397542462
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3179457398
Short name T654
Test name
Test status
Simulation time 80817918256 ps
CPU time 50.7 seconds
Started Aug 07 05:57:45 PM PDT 24
Finished Aug 07 05:58:35 PM PDT 24
Peak memory 199928 kb
Host smart-6f2276c2-59c6-42a5-b33c-3938a3dfebda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179457398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3179457398
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3461298405
Short name T733
Test name
Test status
Simulation time 57973837541 ps
CPU time 15.34 seconds
Started Aug 07 05:57:52 PM PDT 24
Finished Aug 07 05:58:08 PM PDT 24
Peak memory 199704 kb
Host smart-cc557cd2-8268-4f2d-8c09-f60cc3dd559f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461298405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3461298405
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3139953919
Short name T376
Test name
Test status
Simulation time 42908865 ps
CPU time 0.58 seconds
Started Aug 07 05:51:16 PM PDT 24
Finished Aug 07 05:51:17 PM PDT 24
Peak memory 195244 kb
Host smart-a4a1867a-0d18-446f-9661-66a2bede83d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139953919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3139953919
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.261613408
Short name T1014
Test name
Test status
Simulation time 33157744626 ps
CPU time 52.09 seconds
Started Aug 07 05:51:10 PM PDT 24
Finished Aug 07 05:52:02 PM PDT 24
Peak memory 199840 kb
Host smart-fee480b2-bd93-4eba-b214-e95a49156278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261613408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.261613408
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2864225014
Short name T734
Test name
Test status
Simulation time 141791226559 ps
CPU time 61.63 seconds
Started Aug 07 05:51:09 PM PDT 24
Finished Aug 07 05:52:11 PM PDT 24
Peak memory 199912 kb
Host smart-ecf267ec-a977-4a25-a34f-6b12c080e848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864225014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2864225014
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.748097324
Short name T205
Test name
Test status
Simulation time 84866675087 ps
CPU time 32.21 seconds
Started Aug 07 05:51:11 PM PDT 24
Finished Aug 07 05:51:43 PM PDT 24
Peak memory 199912 kb
Host smart-934a32d4-b23c-44c8-9245-76e07d553db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748097324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.748097324
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1401175340
Short name T531
Test name
Test status
Simulation time 158872360098 ps
CPU time 128.55 seconds
Started Aug 07 05:51:07 PM PDT 24
Finished Aug 07 05:53:15 PM PDT 24
Peak memory 199724 kb
Host smart-ea7f8ee4-7655-469c-9f72-ab328c705628
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401175340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1401175340
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3231753952
Short name T534
Test name
Test status
Simulation time 130440583006 ps
CPU time 367.35 seconds
Started Aug 07 05:51:12 PM PDT 24
Finished Aug 07 05:57:20 PM PDT 24
Peak memory 199844 kb
Host smart-85b6d443-ed07-4fb0-b92a-052d93b52222
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3231753952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3231753952
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2802050045
Short name T434
Test name
Test status
Simulation time 2631039526 ps
CPU time 5.7 seconds
Started Aug 07 05:51:13 PM PDT 24
Finished Aug 07 05:51:19 PM PDT 24
Peak memory 198056 kb
Host smart-bb71be0f-59af-4206-b9be-7dca0bb6ddee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802050045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2802050045
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3425851968
Short name T371
Test name
Test status
Simulation time 33778637075 ps
CPU time 16.7 seconds
Started Aug 07 05:51:09 PM PDT 24
Finished Aug 07 05:51:26 PM PDT 24
Peak memory 199856 kb
Host smart-a06e580e-229e-4737-963a-698f0c6196ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425851968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3425851968
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.668901657
Short name T583
Test name
Test status
Simulation time 17471053629 ps
CPU time 193.31 seconds
Started Aug 07 05:51:12 PM PDT 24
Finished Aug 07 05:54:25 PM PDT 24
Peak memory 199880 kb
Host smart-ed782570-d1c7-47fd-821c-0f2f9e034e24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=668901657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.668901657
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2240230079
Short name T1178
Test name
Test status
Simulation time 6687139625 ps
CPU time 14.92 seconds
Started Aug 07 05:51:10 PM PDT 24
Finished Aug 07 05:51:25 PM PDT 24
Peak memory 198756 kb
Host smart-f3c2d66a-2c12-4919-815e-9411d1fae055
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2240230079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2240230079
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.4209061130
Short name T664
Test name
Test status
Simulation time 125895999829 ps
CPU time 44.2 seconds
Started Aug 07 05:51:13 PM PDT 24
Finished Aug 07 05:51:57 PM PDT 24
Peak memory 199888 kb
Host smart-8da17485-4773-4f8d-8ca9-62fd28f18407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209061130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.4209061130
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.940904393
Short name T601
Test name
Test status
Simulation time 3057934489 ps
CPU time 1.1 seconds
Started Aug 07 05:51:14 PM PDT 24
Finished Aug 07 05:51:15 PM PDT 24
Peak memory 195864 kb
Host smart-3969cd50-d2cf-48a3-b80c-5daf24c3c702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940904393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.940904393
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3451818822
Short name T30
Test name
Test status
Simulation time 58237758 ps
CPU time 0.86 seconds
Started Aug 07 05:51:11 PM PDT 24
Finished Aug 07 05:51:12 PM PDT 24
Peak memory 218324 kb
Host smart-e24fdfd4-b782-4773-af00-fcf307665768
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451818822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3451818822
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.2249321715
Short name T586
Test name
Test status
Simulation time 462740180 ps
CPU time 1.87 seconds
Started Aug 07 05:51:08 PM PDT 24
Finished Aug 07 05:51:10 PM PDT 24
Peak memory 198380 kb
Host smart-733012d3-7caf-4210-9259-29bfc96e9b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249321715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2249321715
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.494437983
Short name T293
Test name
Test status
Simulation time 369947738129 ps
CPU time 188.69 seconds
Started Aug 07 05:51:17 PM PDT 24
Finished Aug 07 05:54:25 PM PDT 24
Peak memory 208328 kb
Host smart-b581dd02-d70e-4c13-8322-72544cc623fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494437983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.494437983
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2184897045
Short name T443
Test name
Test status
Simulation time 237792220002 ps
CPU time 1234.01 seconds
Started Aug 07 05:51:15 PM PDT 24
Finished Aug 07 06:11:49 PM PDT 24
Peak memory 224552 kb
Host smart-ccaa1348-4f4f-4b21-b919-0f93c01c5d00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184897045 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2184897045
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2099314378
Short name T632
Test name
Test status
Simulation time 1126249329 ps
CPU time 2.45 seconds
Started Aug 07 05:51:15 PM PDT 24
Finished Aug 07 05:51:17 PM PDT 24
Peak memory 198612 kb
Host smart-c2948e3d-5e36-4774-93fa-74362f0c0cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099314378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2099314378
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2425896437
Short name T753
Test name
Test status
Simulation time 26567214976 ps
CPU time 46.15 seconds
Started Aug 07 05:51:09 PM PDT 24
Finished Aug 07 05:51:56 PM PDT 24
Peak memory 199832 kb
Host smart-a65b1546-0dc5-412a-a0c3-eb634a2c79e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425896437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2425896437
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.4005081511
Short name T508
Test name
Test status
Simulation time 46951494 ps
CPU time 0.54 seconds
Started Aug 07 05:54:33 PM PDT 24
Finished Aug 07 05:54:34 PM PDT 24
Peak memory 195628 kb
Host smart-5a67e856-6157-4756-842e-c64ded2ec987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005081511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.4005081511
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.4000843932
Short name T551
Test name
Test status
Simulation time 109636855647 ps
CPU time 47.87 seconds
Started Aug 07 05:53:10 PM PDT 24
Finished Aug 07 05:53:58 PM PDT 24
Peak memory 199840 kb
Host smart-df34ca64-3839-47aa-82b1-18cb8e3280fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000843932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.4000843932
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.886553457
Short name T706
Test name
Test status
Simulation time 17932246171 ps
CPU time 24.04 seconds
Started Aug 07 05:53:10 PM PDT 24
Finished Aug 07 05:53:34 PM PDT 24
Peak memory 199852 kb
Host smart-20894736-6643-422e-88fa-b56593d12be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886553457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.886553457
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2161828847
Short name T668
Test name
Test status
Simulation time 191432599688 ps
CPU time 38.24 seconds
Started Aug 07 05:54:31 PM PDT 24
Finished Aug 07 05:55:09 PM PDT 24
Peak memory 199780 kb
Host smart-2be2d4e2-ca54-49fb-914c-a5c9cc38efc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161828847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2161828847
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.1670226025
Short name T867
Test name
Test status
Simulation time 30983233871 ps
CPU time 42.82 seconds
Started Aug 07 05:53:12 PM PDT 24
Finished Aug 07 05:53:55 PM PDT 24
Peak memory 199732 kb
Host smart-58b320e0-2f35-4725-96a5-8556ba6ad39a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670226025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1670226025
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.704334750
Short name T827
Test name
Test status
Simulation time 151270106545 ps
CPU time 349.01 seconds
Started Aug 07 05:53:16 PM PDT 24
Finished Aug 07 05:59:05 PM PDT 24
Peak memory 199896 kb
Host smart-ade313cd-c175-4066-87fe-f942c59ac350
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=704334750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.704334750
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2891621218
Short name T1121
Test name
Test status
Simulation time 4816310571 ps
CPU time 5.52 seconds
Started Aug 07 05:53:15 PM PDT 24
Finished Aug 07 05:53:20 PM PDT 24
Peak memory 199588 kb
Host smart-013f4358-2edc-4cb8-a763-f2aaab6f9020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891621218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2891621218
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2434041494
Short name T1005
Test name
Test status
Simulation time 81342758196 ps
CPU time 140.87 seconds
Started Aug 07 05:53:10 PM PDT 24
Finished Aug 07 05:55:31 PM PDT 24
Peak memory 208196 kb
Host smart-1aaf394b-c6b9-466e-aa37-199ed0072fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434041494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2434041494
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.4284839777
Short name T439
Test name
Test status
Simulation time 10605664788 ps
CPU time 152.43 seconds
Started Aug 07 05:53:16 PM PDT 24
Finished Aug 07 05:55:48 PM PDT 24
Peak memory 199888 kb
Host smart-238b765f-70a0-46f1-8653-36e711c0741a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4284839777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.4284839777
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.367002126
Short name T1151
Test name
Test status
Simulation time 5282668789 ps
CPU time 44.05 seconds
Started Aug 07 05:53:10 PM PDT 24
Finished Aug 07 05:53:54 PM PDT 24
Peak memory 198100 kb
Host smart-75e7a751-5bac-47d6-b7a3-a78ce6280e67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=367002126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.367002126
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1372432728
Short name T838
Test name
Test status
Simulation time 28086991951 ps
CPU time 44.55 seconds
Started Aug 07 05:53:15 PM PDT 24
Finished Aug 07 05:54:00 PM PDT 24
Peak memory 199844 kb
Host smart-a1240770-056a-4ff4-8c77-d1cf3c2f8387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372432728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1372432728
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.4291547425
Short name T343
Test name
Test status
Simulation time 4780323098 ps
CPU time 1.34 seconds
Started Aug 07 05:53:15 PM PDT 24
Finished Aug 07 05:53:17 PM PDT 24
Peak memory 196052 kb
Host smart-8f9449b6-0e8f-4024-8034-0aef19969692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291547425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.4291547425
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1734693994
Short name T274
Test name
Test status
Simulation time 937530461 ps
CPU time 2.93 seconds
Started Aug 07 05:53:10 PM PDT 24
Finished Aug 07 05:53:13 PM PDT 24
Peak memory 198912 kb
Host smart-3af2d506-e7ba-406a-bfda-74f1c8cebe65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734693994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1734693994
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3313390880
Short name T1022
Test name
Test status
Simulation time 304478355278 ps
CPU time 60.38 seconds
Started Aug 07 05:53:15 PM PDT 24
Finished Aug 07 05:54:16 PM PDT 24
Peak memory 199872 kb
Host smart-c50e7c92-1739-44ba-8a34-82ae70fa3a5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313390880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3313390880
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3635444506
Short name T1143
Test name
Test status
Simulation time 133507801013 ps
CPU time 666.38 seconds
Started Aug 07 05:53:14 PM PDT 24
Finished Aug 07 06:04:21 PM PDT 24
Peak memory 216548 kb
Host smart-c3e571de-aea6-429a-972b-7eec241ce6e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635444506 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3635444506
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1020798091
Short name T372
Test name
Test status
Simulation time 1290197644 ps
CPU time 2.42 seconds
Started Aug 07 05:54:24 PM PDT 24
Finished Aug 07 05:54:26 PM PDT 24
Peak memory 198828 kb
Host smart-be2c0692-10bc-408e-96af-2b4fda6ea3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020798091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1020798091
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2884913542
Short name T861
Test name
Test status
Simulation time 46729800381 ps
CPU time 75.54 seconds
Started Aug 07 05:53:09 PM PDT 24
Finished Aug 07 05:54:25 PM PDT 24
Peak memory 199908 kb
Host smart-52104b70-4b8b-4185-a4cb-3b332e99138e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884913542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2884913542
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1739079040
Short name T25
Test name
Test status
Simulation time 62946777 ps
CPU time 0.56 seconds
Started Aug 07 05:53:21 PM PDT 24
Finished Aug 07 05:53:22 PM PDT 24
Peak memory 195264 kb
Host smart-736a6669-f19a-4999-912b-25e1d4c2b24d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739079040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1739079040
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2563951022
Short name T760
Test name
Test status
Simulation time 22913285383 ps
CPU time 8.34 seconds
Started Aug 07 05:53:14 PM PDT 24
Finished Aug 07 05:53:22 PM PDT 24
Peak memory 199832 kb
Host smart-9558f9a8-60e1-4f78-922f-11c3a5484614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563951022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2563951022
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3690568450
Short name T923
Test name
Test status
Simulation time 10328599496 ps
CPU time 15.73 seconds
Started Aug 07 05:53:16 PM PDT 24
Finished Aug 07 05:53:32 PM PDT 24
Peak memory 199892 kb
Host smart-45ef0d4e-f61b-4897-92b2-a388e9b21b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690568450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3690568450
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_intr.3806686608
Short name T282
Test name
Test status
Simulation time 31984543985 ps
CPU time 29.01 seconds
Started Aug 07 05:54:34 PM PDT 24
Finished Aug 07 05:55:03 PM PDT 24
Peak memory 199944 kb
Host smart-e987c692-143c-477d-89e4-76943a5691ab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806686608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3806686608
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3363121053
Short name T1114
Test name
Test status
Simulation time 327444057138 ps
CPU time 155.03 seconds
Started Aug 07 05:53:20 PM PDT 24
Finished Aug 07 05:55:55 PM PDT 24
Peak memory 199828 kb
Host smart-a826daf7-c2f4-4116-ae60-bb7ca90481fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3363121053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3363121053
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1776564090
Short name T777
Test name
Test status
Simulation time 144186616 ps
CPU time 0.72 seconds
Started Aug 07 05:53:22 PM PDT 24
Finished Aug 07 05:53:23 PM PDT 24
Peak memory 195980 kb
Host smart-7263040a-be6d-4d3a-b30c-e25a2603ed5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776564090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1776564090
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.1330416268
Short name T1162
Test name
Test status
Simulation time 23741906482 ps
CPU time 38.52 seconds
Started Aug 07 05:53:17 PM PDT 24
Finished Aug 07 05:53:55 PM PDT 24
Peak memory 198564 kb
Host smart-964eb773-3002-4289-891c-60ece23e1d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330416268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1330416268
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.4024297446
Short name T1018
Test name
Test status
Simulation time 5054330875 ps
CPU time 18.57 seconds
Started Aug 07 05:53:13 PM PDT 24
Finished Aug 07 05:53:32 PM PDT 24
Peak memory 198088 kb
Host smart-d15683c9-3d4a-4d30-bbfe-fcb80a401966
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4024297446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.4024297446
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.2405137081
Short name T580
Test name
Test status
Simulation time 35620586522 ps
CPU time 29.94 seconds
Started Aug 07 05:53:23 PM PDT 24
Finished Aug 07 05:53:53 PM PDT 24
Peak memory 199772 kb
Host smart-4df6086e-18f5-4982-afd9-72a38ff5dd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405137081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.2405137081
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.4239427646
Short name T711
Test name
Test status
Simulation time 722117893 ps
CPU time 1.78 seconds
Started Aug 07 05:53:18 PM PDT 24
Finished Aug 07 05:53:20 PM PDT 24
Peak memory 195308 kb
Host smart-2188422c-2fef-40a4-97f4-4bf686b67c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239427646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.4239427646
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.4092279475
Short name T449
Test name
Test status
Simulation time 471111437 ps
CPU time 1.08 seconds
Started Aug 07 05:54:28 PM PDT 24
Finished Aug 07 05:54:29 PM PDT 24
Peak memory 198700 kb
Host smart-313e4360-7e39-49f0-9058-e0bf0666099a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092279475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.4092279475
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3588480708
Short name T847
Test name
Test status
Simulation time 290054276711 ps
CPU time 118.48 seconds
Started Aug 07 05:53:21 PM PDT 24
Finished Aug 07 05:55:20 PM PDT 24
Peak memory 199812 kb
Host smart-0ca76bb2-3846-4e21-8693-9e149f2d67b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588480708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3588480708
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1669164883
Short name T1042
Test name
Test status
Simulation time 144569543381 ps
CPU time 515.53 seconds
Started Aug 07 05:53:21 PM PDT 24
Finished Aug 07 06:01:57 PM PDT 24
Peak memory 216324 kb
Host smart-fdc8abf2-f1c6-4b5f-aa8f-fcb92d0bcdd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669164883 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1669164883
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1228613075
Short name T1137
Test name
Test status
Simulation time 1597216523 ps
CPU time 2.27 seconds
Started Aug 07 05:53:23 PM PDT 24
Finished Aug 07 05:53:25 PM PDT 24
Peak memory 198320 kb
Host smart-c19f5d8f-3f28-44ce-bd83-e94bd18ddfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228613075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1228613075
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.555879346
Short name T395
Test name
Test status
Simulation time 8933914459 ps
CPU time 5.12 seconds
Started Aug 07 05:53:18 PM PDT 24
Finished Aug 07 05:53:23 PM PDT 24
Peak memory 199620 kb
Host smart-add6c7ff-80f7-484b-93e1-c3359d9adff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555879346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.555879346
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1026644967
Short name T830
Test name
Test status
Simulation time 14603883 ps
CPU time 0.57 seconds
Started Aug 07 05:54:39 PM PDT 24
Finished Aug 07 05:54:40 PM PDT 24
Peak memory 195632 kb
Host smart-62b43483-a3ab-4b4f-8122-d7d14a235591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026644967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1026644967
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.723348174
Short name T381
Test name
Test status
Simulation time 26199986740 ps
CPU time 44.8 seconds
Started Aug 07 05:53:21 PM PDT 24
Finished Aug 07 05:54:06 PM PDT 24
Peak memory 199804 kb
Host smart-939fefce-ab84-4af1-aaf5-a44a10787219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723348174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.723348174
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1896968177
Short name T943
Test name
Test status
Simulation time 146700698623 ps
CPU time 57.02 seconds
Started Aug 07 05:53:22 PM PDT 24
Finished Aug 07 05:54:20 PM PDT 24
Peak memory 199888 kb
Host smart-49e29870-6754-40ee-bc14-570025dac016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896968177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1896968177
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.56546399
Short name T285
Test name
Test status
Simulation time 54827262747 ps
CPU time 86.24 seconds
Started Aug 07 05:53:21 PM PDT 24
Finished Aug 07 05:54:47 PM PDT 24
Peak memory 199904 kb
Host smart-c6edfe7d-5f83-473d-8dfa-8808601d3313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56546399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.56546399
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2284160924
Short name T908
Test name
Test status
Simulation time 108912923491 ps
CPU time 34.34 seconds
Started Aug 07 05:53:20 PM PDT 24
Finished Aug 07 05:53:54 PM PDT 24
Peak memory 199068 kb
Host smart-89a7487f-5983-4163-a0dc-71305a56b213
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284160924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2284160924
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2865006173
Short name T1038
Test name
Test status
Simulation time 165054526316 ps
CPU time 275.29 seconds
Started Aug 07 05:53:27 PM PDT 24
Finished Aug 07 05:58:02 PM PDT 24
Peak memory 199884 kb
Host smart-a32eced4-abec-4067-8534-734f9f557a1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2865006173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2865006173
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2600026100
Short name T375
Test name
Test status
Simulation time 7033521092 ps
CPU time 18.32 seconds
Started Aug 07 05:53:26 PM PDT 24
Finished Aug 07 05:53:44 PM PDT 24
Peak memory 199620 kb
Host smart-b21787b1-be0b-4e3d-b7c4-cfb5fe9b9ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600026100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2600026100
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3988821703
Short name T116
Test name
Test status
Simulation time 101537840038 ps
CPU time 50.3 seconds
Started Aug 07 05:53:22 PM PDT 24
Finished Aug 07 05:54:12 PM PDT 24
Peak memory 200000 kb
Host smart-f7fb05f8-bdf0-44e9-a56a-72303150f839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988821703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3988821703
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.4217882115
Short name T745
Test name
Test status
Simulation time 30895788545 ps
CPU time 1178.6 seconds
Started Aug 07 05:53:24 PM PDT 24
Finished Aug 07 06:13:03 PM PDT 24
Peak memory 199804 kb
Host smart-c676d738-d2fa-4d12-a24a-0ed525a3804d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4217882115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.4217882115
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2818452205
Short name T695
Test name
Test status
Simulation time 3038863192 ps
CPU time 7.07 seconds
Started Aug 07 05:53:19 PM PDT 24
Finished Aug 07 05:53:26 PM PDT 24
Peak memory 198040 kb
Host smart-97884971-2a8b-4031-8cdc-b1b240756bed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2818452205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2818452205
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1916017574
Short name T152
Test name
Test status
Simulation time 27361141702 ps
CPU time 12.14 seconds
Started Aug 07 05:53:18 PM PDT 24
Finished Aug 07 05:53:31 PM PDT 24
Peak memory 199744 kb
Host smart-93323252-e7ea-4ee2-95b4-1001e92843fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916017574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1916017574
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.4234209843
Short name T1060
Test name
Test status
Simulation time 4333371730 ps
CPU time 2.23 seconds
Started Aug 07 05:53:20 PM PDT 24
Finished Aug 07 05:53:23 PM PDT 24
Peak memory 196204 kb
Host smart-bd17ac10-bfa4-4042-97e1-810e4ad3b268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234209843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.4234209843
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3674764838
Short name T31
Test name
Test status
Simulation time 744111514 ps
CPU time 1.8 seconds
Started Aug 07 05:53:20 PM PDT 24
Finished Aug 07 05:53:22 PM PDT 24
Peak memory 199512 kb
Host smart-ab3a9c14-da4f-4b18-b202-c8c4db682b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674764838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3674764838
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.901232341
Short name T765
Test name
Test status
Simulation time 257831689296 ps
CPU time 352.01 seconds
Started Aug 07 05:53:27 PM PDT 24
Finished Aug 07 05:59:19 PM PDT 24
Peak memory 208232 kb
Host smart-618c55aa-35c3-4580-8c31-1167a63c94e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901232341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.901232341
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1558708369
Short name T32
Test name
Test status
Simulation time 29109959178 ps
CPU time 355.84 seconds
Started Aug 07 05:53:27 PM PDT 24
Finished Aug 07 05:59:23 PM PDT 24
Peak memory 211860 kb
Host smart-cf48053a-4cf3-4c14-bc65-555a1ced46bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558708369 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1558708369
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.910856032
Short name T559
Test name
Test status
Simulation time 3535954016 ps
CPU time 1.63 seconds
Started Aug 07 05:53:27 PM PDT 24
Finished Aug 07 05:53:29 PM PDT 24
Peak memory 199472 kb
Host smart-c9d6567e-8ca9-45bb-9599-cb73da56b8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910856032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.910856032
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3315146536
Short name T472
Test name
Test status
Simulation time 55111073023 ps
CPU time 76.74 seconds
Started Aug 07 05:53:22 PM PDT 24
Finished Aug 07 05:54:39 PM PDT 24
Peak memory 199928 kb
Host smart-5e0ef73a-a679-4a5a-8dd4-2db58e607f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315146536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3315146536
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1780606699
Short name T718
Test name
Test status
Simulation time 35663544 ps
CPU time 0.55 seconds
Started Aug 07 05:53:34 PM PDT 24
Finished Aug 07 05:53:35 PM PDT 24
Peak memory 195300 kb
Host smart-2ed251f6-93c2-4068-903b-92ddc4155768
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780606699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1780606699
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.936531351
Short name T926
Test name
Test status
Simulation time 108680636227 ps
CPU time 223.25 seconds
Started Aug 07 05:53:31 PM PDT 24
Finished Aug 07 05:57:15 PM PDT 24
Peak memory 199896 kb
Host smart-de620115-27a6-43a9-b511-3b70b0ede84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936531351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.936531351
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.755927997
Short name T292
Test name
Test status
Simulation time 44662633979 ps
CPU time 40.6 seconds
Started Aug 07 05:53:31 PM PDT 24
Finished Aug 07 05:54:12 PM PDT 24
Peak memory 199832 kb
Host smart-caa0f7e3-c137-48c8-9dca-5e8bd5dffb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755927997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.755927997
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.4214561758
Short name T121
Test name
Test status
Simulation time 82252577797 ps
CPU time 17.6 seconds
Started Aug 07 05:53:28 PM PDT 24
Finished Aug 07 05:53:46 PM PDT 24
Peak memory 199884 kb
Host smart-fa222999-5404-4c83-bdeb-e2acadc3f535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214561758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.4214561758
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.178584089
Short name T97
Test name
Test status
Simulation time 13921711098 ps
CPU time 25.39 seconds
Started Aug 07 05:53:29 PM PDT 24
Finished Aug 07 05:53:55 PM PDT 24
Peak memory 199796 kb
Host smart-1fe3f169-a8f0-4838-a841-f7cee669212c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178584089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.178584089
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.207124044
Short name T640
Test name
Test status
Simulation time 71430593138 ps
CPU time 128.24 seconds
Started Aug 07 05:53:32 PM PDT 24
Finished Aug 07 05:55:40 PM PDT 24
Peak memory 199924 kb
Host smart-6e1968aa-3c71-4c4a-aeaa-9eb7363b6805
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=207124044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.207124044
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.4290918022
Short name T715
Test name
Test status
Simulation time 3344069738 ps
CPU time 1.14 seconds
Started Aug 07 05:53:36 PM PDT 24
Finished Aug 07 05:53:37 PM PDT 24
Peak memory 195728 kb
Host smart-1eb6a518-edca-4906-8cee-3a16acf82233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290918022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.4290918022
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.1591773439
Short name T689
Test name
Test status
Simulation time 129749432726 ps
CPU time 52.18 seconds
Started Aug 07 05:53:54 PM PDT 24
Finished Aug 07 05:54:47 PM PDT 24
Peak memory 200144 kb
Host smart-eb26de3b-5207-471d-b25c-c18b0d1eba08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591773439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1591773439
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3311901561
Short name T958
Test name
Test status
Simulation time 24938668102 ps
CPU time 294.43 seconds
Started Aug 07 05:53:35 PM PDT 24
Finished Aug 07 05:58:29 PM PDT 24
Peak memory 199916 kb
Host smart-94a697ff-0efa-47c5-a904-004bd009dd05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3311901561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3311901561
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2965637644
Short name T344
Test name
Test status
Simulation time 3701043502 ps
CPU time 7.89 seconds
Started Aug 07 05:54:29 PM PDT 24
Finished Aug 07 05:54:37 PM PDT 24
Peak memory 197944 kb
Host smart-bdf7beb2-d9e4-4bd2-aed7-59c2660d026e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2965637644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2965637644
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.103093131
Short name T567
Test name
Test status
Simulation time 67509831283 ps
CPU time 97.74 seconds
Started Aug 07 05:53:36 PM PDT 24
Finished Aug 07 05:55:14 PM PDT 24
Peak memory 199912 kb
Host smart-c436abc1-ecf5-4a28-b3e4-390fd6b7e55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103093131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.103093131
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.245430850
Short name T782
Test name
Test status
Simulation time 2307675079 ps
CPU time 4.14 seconds
Started Aug 07 05:53:25 PM PDT 24
Finished Aug 07 05:53:30 PM PDT 24
Peak memory 195552 kb
Host smart-4a3ade7e-89fb-43f5-bb47-af9e0038a1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245430850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.245430850
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3290911264
Short name T672
Test name
Test status
Simulation time 105249031 ps
CPU time 0.87 seconds
Started Aug 07 05:53:29 PM PDT 24
Finished Aug 07 05:53:30 PM PDT 24
Peak memory 197004 kb
Host smart-c930e37f-2e59-4d09-b734-16242ece8249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290911264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3290911264
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1373792167
Short name T897
Test name
Test status
Simulation time 32892555213 ps
CPU time 384.21 seconds
Started Aug 07 05:53:31 PM PDT 24
Finished Aug 07 05:59:56 PM PDT 24
Peak memory 216288 kb
Host smart-cb4611cb-1011-4d15-ba52-4146611d4403
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373792167 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1373792167
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2589069461
Short name T986
Test name
Test status
Simulation time 1099729999 ps
CPU time 4.9 seconds
Started Aug 07 05:53:33 PM PDT 24
Finished Aug 07 05:53:38 PM PDT 24
Peak memory 199608 kb
Host smart-f41ff898-d739-4776-9539-bf87a23afd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589069461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2589069461
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.352318058
Short name T1032
Test name
Test status
Simulation time 43592599084 ps
CPU time 19.91 seconds
Started Aug 07 05:53:28 PM PDT 24
Finished Aug 07 05:53:48 PM PDT 24
Peak memory 199808 kb
Host smart-eaf46763-fdf3-4884-ba03-d2147da044db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352318058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.352318058
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1314074779
Short name T871
Test name
Test status
Simulation time 13671809 ps
CPU time 0.56 seconds
Started Aug 07 05:53:41 PM PDT 24
Finished Aug 07 05:53:41 PM PDT 24
Peak memory 194256 kb
Host smart-85283e8a-d1c7-45c2-9126-7825634bf557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314074779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1314074779
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1664101984
Short name T925
Test name
Test status
Simulation time 110610535203 ps
CPU time 132.87 seconds
Started Aug 07 05:53:34 PM PDT 24
Finished Aug 07 05:55:47 PM PDT 24
Peak memory 199884 kb
Host smart-2593c432-989d-479b-b022-1ec641869caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664101984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1664101984
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.4186462686
Short name T132
Test name
Test status
Simulation time 57314714228 ps
CPU time 81.22 seconds
Started Aug 07 05:54:27 PM PDT 24
Finished Aug 07 05:55:49 PM PDT 24
Peak memory 199892 kb
Host smart-508076ce-aa85-400c-b24f-629fb18f76c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186462686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.4186462686
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1001532002
Short name T708
Test name
Test status
Simulation time 46691896272 ps
CPU time 19.56 seconds
Started Aug 07 05:53:34 PM PDT 24
Finished Aug 07 05:53:54 PM PDT 24
Peak memory 199896 kb
Host smart-8e7de0dd-ad25-47dd-b5d5-ea99712ea971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001532002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1001532002
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3967640358
Short name T1138
Test name
Test status
Simulation time 368407740812 ps
CPU time 163.44 seconds
Started Aug 07 05:53:47 PM PDT 24
Finished Aug 07 05:56:30 PM PDT 24
Peak memory 200152 kb
Host smart-cbaf1905-0f1a-4b1e-9f26-2065ba7e634f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967640358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3967640358
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.339523487
Short name T1046
Test name
Test status
Simulation time 93667812161 ps
CPU time 407.84 seconds
Started Aug 07 05:53:42 PM PDT 24
Finished Aug 07 06:00:30 PM PDT 24
Peak memory 199896 kb
Host smart-2a6cb33e-2ab0-42cb-88cf-b3ae4b819c57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=339523487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.339523487
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1981972942
Short name T1142
Test name
Test status
Simulation time 6833107562 ps
CPU time 5.29 seconds
Started Aug 07 05:54:30 PM PDT 24
Finished Aug 07 05:54:35 PM PDT 24
Peak memory 198860 kb
Host smart-f1b5fc77-30e7-4b45-81c7-bfae849233cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981972942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1981972942
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1254625360
Short name T1089
Test name
Test status
Simulation time 75352229731 ps
CPU time 181.52 seconds
Started Aug 07 05:53:40 PM PDT 24
Finished Aug 07 05:56:42 PM PDT 24
Peak memory 199156 kb
Host smart-7cb89ea3-f40a-4859-9836-96bde253eeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254625360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1254625360
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.3968394670
Short name T704
Test name
Test status
Simulation time 2520353779 ps
CPU time 79.95 seconds
Started Aug 07 05:53:39 PM PDT 24
Finished Aug 07 05:54:59 PM PDT 24
Peak memory 199832 kb
Host smart-9859c745-d943-4b9f-8103-e540254ef930
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3968394670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3968394670
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.850264554
Short name T366
Test name
Test status
Simulation time 6357611248 ps
CPU time 13.75 seconds
Started Aug 07 05:53:39 PM PDT 24
Finished Aug 07 05:53:53 PM PDT 24
Peak memory 198084 kb
Host smart-05fc1a9e-9199-4533-b7c9-061981000b22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=850264554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.850264554
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1209243088
Short name T1057
Test name
Test status
Simulation time 54251690459 ps
CPU time 73.57 seconds
Started Aug 07 05:53:39 PM PDT 24
Finished Aug 07 05:54:53 PM PDT 24
Peak memory 198696 kb
Host smart-aeaaceaf-22b8-4ed2-9823-af203a9951a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209243088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1209243088
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.720140907
Short name T1160
Test name
Test status
Simulation time 29605974178 ps
CPU time 5.27 seconds
Started Aug 07 05:53:40 PM PDT 24
Finished Aug 07 05:53:45 PM PDT 24
Peak memory 196192 kb
Host smart-5f234aa5-6bbb-40f4-9a97-b070d4b7aa0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720140907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.720140907
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3645247430
Short name T602
Test name
Test status
Simulation time 708927450 ps
CPU time 1.24 seconds
Started Aug 07 05:53:33 PM PDT 24
Finished Aug 07 05:53:34 PM PDT 24
Peak memory 198596 kb
Host smart-48f327b6-b0e5-4bc9-bec7-c2be2875e3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645247430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3645247430
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.18485990
Short name T266
Test name
Test status
Simulation time 268804744602 ps
CPU time 198.39 seconds
Started Aug 07 05:53:39 PM PDT 24
Finished Aug 07 05:56:57 PM PDT 24
Peak memory 199820 kb
Host smart-3fa03fe3-6826-4340-a505-93961f9d28d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18485990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.18485990
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2630890641
Short name T887
Test name
Test status
Simulation time 121873848676 ps
CPU time 856.54 seconds
Started Aug 07 05:53:47 PM PDT 24
Finished Aug 07 06:08:04 PM PDT 24
Peak memory 216408 kb
Host smart-b7d1f1a1-c547-42b5-b6f7-aeb6aab50b9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630890641 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2630890641
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.584795571
Short name T1098
Test name
Test status
Simulation time 232937594 ps
CPU time 0.99 seconds
Started Aug 07 05:53:40 PM PDT 24
Finished Aug 07 05:53:42 PM PDT 24
Peak memory 197788 kb
Host smart-3ed18e0a-e608-4dd4-b046-c44f6930b525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584795571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.584795571
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_alert_test.3220197035
Short name T983
Test name
Test status
Simulation time 45903396 ps
CPU time 0.56 seconds
Started Aug 07 05:53:47 PM PDT 24
Finished Aug 07 05:53:48 PM PDT 24
Peak memory 195276 kb
Host smart-f086dd6c-b272-4abc-addf-95e6798d75a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220197035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3220197035
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3018886408
Short name T705
Test name
Test status
Simulation time 262316138482 ps
CPU time 557.34 seconds
Started Aug 07 05:53:47 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 200128 kb
Host smart-ea3b17cd-7704-409c-aed8-bf0144e01ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018886408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3018886408
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3577168613
Short name T1125
Test name
Test status
Simulation time 8993699596 ps
CPU time 4.25 seconds
Started Aug 07 05:53:39 PM PDT 24
Finished Aug 07 05:53:43 PM PDT 24
Peak memory 199432 kb
Host smart-84e732a0-5303-47ef-86b0-8930b618496a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577168613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3577168613
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2541643228
Short name T582
Test name
Test status
Simulation time 73660977637 ps
CPU time 21.89 seconds
Started Aug 07 05:53:46 PM PDT 24
Finished Aug 07 05:54:08 PM PDT 24
Peak memory 200152 kb
Host smart-7e3cc79e-172a-45d1-8dfa-5296ffd9825c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541643228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2541643228
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3722016294
Short name T402
Test name
Test status
Simulation time 19556129622 ps
CPU time 34.56 seconds
Started Aug 07 05:54:43 PM PDT 24
Finished Aug 07 05:55:17 PM PDT 24
Peak memory 199892 kb
Host smart-ed4f8c01-e6d5-4caf-9fc9-1030888b553d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722016294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3722016294
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.1670690069
Short name T368
Test name
Test status
Simulation time 71249081982 ps
CPU time 79.53 seconds
Started Aug 07 05:54:39 PM PDT 24
Finished Aug 07 05:55:59 PM PDT 24
Peak memory 199848 kb
Host smart-1000272a-b215-4e8a-8cbd-3bf8a5105331
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1670690069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1670690069
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3409394114
Short name T1003
Test name
Test status
Simulation time 8438175939 ps
CPU time 16.66 seconds
Started Aug 07 05:53:48 PM PDT 24
Finished Aug 07 05:54:05 PM PDT 24
Peak memory 199836 kb
Host smart-7cafa2fb-5eba-4ce3-bcc7-0bf3a62656f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409394114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3409394114
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.3651944337
Short name T40
Test name
Test status
Simulation time 70973905582 ps
CPU time 153.24 seconds
Started Aug 07 05:53:46 PM PDT 24
Finished Aug 07 05:56:19 PM PDT 24
Peak memory 200084 kb
Host smart-af91e4eb-52f0-4bd5-9c7d-fa0f394da1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651944337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3651944337
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3253784565
Short name T728
Test name
Test status
Simulation time 13850037530 ps
CPU time 867.39 seconds
Started Aug 07 05:53:47 PM PDT 24
Finished Aug 07 06:08:14 PM PDT 24
Peak memory 199924 kb
Host smart-f9ef7d1c-57f5-43a3-b192-4b624dc70ac3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3253784565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3253784565
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.922268891
Short name T660
Test name
Test status
Simulation time 5528100790 ps
CPU time 7.23 seconds
Started Aug 07 05:53:39 PM PDT 24
Finished Aug 07 05:53:47 PM PDT 24
Peak memory 198912 kb
Host smart-5dc245d4-7dec-4c07-9ce4-7152030d3ed0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=922268891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.922268891
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2787900667
Short name T627
Test name
Test status
Simulation time 107401273500 ps
CPU time 81 seconds
Started Aug 07 05:54:39 PM PDT 24
Finished Aug 07 05:56:00 PM PDT 24
Peak memory 199972 kb
Host smart-7145d8ac-1be3-4059-9082-ba2031252b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787900667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2787900667
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.363465798
Short name T254
Test name
Test status
Simulation time 40497935960 ps
CPU time 62.56 seconds
Started Aug 07 05:53:47 PM PDT 24
Finished Aug 07 05:54:50 PM PDT 24
Peak memory 196232 kb
Host smart-5d01834e-16a3-4766-a203-64787a709ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363465798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.363465798
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3187758890
Short name T743
Test name
Test status
Simulation time 6332716564 ps
CPU time 6.61 seconds
Started Aug 07 05:53:38 PM PDT 24
Finished Aug 07 05:53:44 PM PDT 24
Peak memory 199844 kb
Host smart-f2d6b36f-7823-4ade-bb6b-42380ac21941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187758890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3187758890
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2243570818
Short name T221
Test name
Test status
Simulation time 348658957962 ps
CPU time 583.92 seconds
Started Aug 07 05:53:49 PM PDT 24
Finished Aug 07 06:03:33 PM PDT 24
Peak memory 208192 kb
Host smart-1da608f7-a10b-41e8-83c3-11ad64fe7099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243570818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2243570818
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.606955172
Short name T741
Test name
Test status
Simulation time 68179760220 ps
CPU time 192.78 seconds
Started Aug 07 05:53:47 PM PDT 24
Finished Aug 07 05:56:59 PM PDT 24
Peak memory 215588 kb
Host smart-b54d1382-6550-440c-a6b5-c57fb4120ab0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606955172 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.606955172
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2179713870
Short name T1072
Test name
Test status
Simulation time 794187385 ps
CPU time 2.83 seconds
Started Aug 07 05:53:45 PM PDT 24
Finished Aug 07 05:53:48 PM PDT 24
Peak memory 199840 kb
Host smart-21061e30-fd96-409c-895a-ba1b6cd5c98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179713870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2179713870
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2723370062
Short name T937
Test name
Test status
Simulation time 6871916507 ps
CPU time 3.34 seconds
Started Aug 07 05:53:39 PM PDT 24
Finished Aug 07 05:53:43 PM PDT 24
Peak memory 196744 kb
Host smart-40a23381-f5bb-4a45-a88e-4b869773067f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723370062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2723370062
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.1123148824
Short name T972
Test name
Test status
Simulation time 13082594 ps
CPU time 0.54 seconds
Started Aug 07 05:53:53 PM PDT 24
Finished Aug 07 05:53:54 PM PDT 24
Peak memory 194524 kb
Host smart-af1257e3-a317-4417-8785-84dc0685139a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123148824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1123148824
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.500507525
Short name T909
Test name
Test status
Simulation time 48526188267 ps
CPU time 92.83 seconds
Started Aug 07 05:53:45 PM PDT 24
Finished Aug 07 05:55:18 PM PDT 24
Peak memory 199836 kb
Host smart-da69c64e-aaef-4e3e-b172-33b67a736fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500507525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.500507525
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2138686972
Short name T956
Test name
Test status
Simulation time 52834433754 ps
CPU time 39.49 seconds
Started Aug 07 05:53:51 PM PDT 24
Finished Aug 07 05:54:30 PM PDT 24
Peak memory 199620 kb
Host smart-9075795a-58d5-4106-ae48-8d46108eb256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138686972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2138686972
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.928491165
Short name T141
Test name
Test status
Simulation time 78007503342 ps
CPU time 31.22 seconds
Started Aug 07 05:53:53 PM PDT 24
Finished Aug 07 05:54:24 PM PDT 24
Peak memory 199864 kb
Host smart-aaf14ced-9ab7-42aa-a016-2f2de2c118b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928491165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.928491165
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.508846043
Short name T89
Test name
Test status
Simulation time 8221157425 ps
CPU time 3.99 seconds
Started Aug 07 05:54:10 PM PDT 24
Finished Aug 07 05:54:14 PM PDT 24
Peak memory 196696 kb
Host smart-efcaf9a4-be97-4e02-969f-5c2e8607b7d3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508846043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.508846043
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2533260748
Short name T801
Test name
Test status
Simulation time 199177136654 ps
CPU time 497.63 seconds
Started Aug 07 05:53:54 PM PDT 24
Finished Aug 07 06:02:12 PM PDT 24
Peak memory 199884 kb
Host smart-0e4da1ab-74a3-4055-a078-c7142af92bd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533260748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2533260748
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1270145895
Short name T331
Test name
Test status
Simulation time 695618033 ps
CPU time 1 seconds
Started Aug 07 05:53:53 PM PDT 24
Finished Aug 07 05:53:55 PM PDT 24
Peak memory 196116 kb
Host smart-de2b52a2-c67b-43ea-acf7-f96c96ff050c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270145895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1270145895
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2816865762
Short name T740
Test name
Test status
Simulation time 37515632069 ps
CPU time 31.14 seconds
Started Aug 07 05:53:50 PM PDT 24
Finished Aug 07 05:54:21 PM PDT 24
Peak memory 200084 kb
Host smart-b2fa7ee7-1723-4c7e-a99b-3ff44dbc3371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816865762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2816865762
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1106231317
Short name T390
Test name
Test status
Simulation time 10477944195 ps
CPU time 157.21 seconds
Started Aug 07 05:54:39 PM PDT 24
Finished Aug 07 05:57:17 PM PDT 24
Peak memory 199852 kb
Host smart-fa5b02e9-4ba0-4829-bab5-c5c9525159d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1106231317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1106231317
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3752851317
Short name T618
Test name
Test status
Simulation time 7234905112 ps
CPU time 16.17 seconds
Started Aug 07 05:53:51 PM PDT 24
Finished Aug 07 05:54:08 PM PDT 24
Peak memory 199124 kb
Host smart-e215903d-44b9-4593-a987-87b54eb94379
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752851317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3752851317
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.4107931280
Short name T244
Test name
Test status
Simulation time 30374373108 ps
CPU time 13.62 seconds
Started Aug 07 05:53:51 PM PDT 24
Finished Aug 07 05:54:05 PM PDT 24
Peak memory 199832 kb
Host smart-bf1f7875-3d48-4a78-b584-8c67e8aa753f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107931280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.4107931280
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3772206571
Short name T490
Test name
Test status
Simulation time 3334381561 ps
CPU time 6.04 seconds
Started Aug 07 05:53:52 PM PDT 24
Finished Aug 07 05:53:58 PM PDT 24
Peak memory 196144 kb
Host smart-8662800e-f3a2-4a1d-adfe-2d0494434f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772206571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3772206571
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1968036021
Short name T1027
Test name
Test status
Simulation time 160385383 ps
CPU time 0.84 seconds
Started Aug 07 05:53:48 PM PDT 24
Finished Aug 07 05:53:49 PM PDT 24
Peak memory 197016 kb
Host smart-04168525-3cac-4a3b-a33b-fc1f3f79f383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968036021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1968036021
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.3086843143
Short name T1012
Test name
Test status
Simulation time 305031491113 ps
CPU time 777.16 seconds
Started Aug 07 05:53:51 PM PDT 24
Finished Aug 07 06:06:49 PM PDT 24
Peak memory 199888 kb
Host smart-39954d5e-fa83-4932-8182-e3640e9d50c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086843143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3086843143
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1995476484
Short name T729
Test name
Test status
Simulation time 151616316649 ps
CPU time 669.34 seconds
Started Aug 07 05:53:53 PM PDT 24
Finished Aug 07 06:05:03 PM PDT 24
Peak memory 224748 kb
Host smart-cadc52a3-6959-43aa-b2e4-c3130184ac44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995476484 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1995476484
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2743864837
Short name T982
Test name
Test status
Simulation time 822968863 ps
CPU time 2.47 seconds
Started Aug 07 05:53:51 PM PDT 24
Finished Aug 07 05:53:54 PM PDT 24
Peak memory 198264 kb
Host smart-4aa66f54-d166-4ce8-bcb3-c64a8e09984b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743864837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2743864837
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1697827076
Short name T562
Test name
Test status
Simulation time 12737059398 ps
CPU time 19.12 seconds
Started Aug 07 05:53:49 PM PDT 24
Finished Aug 07 05:54:08 PM PDT 24
Peak memory 199864 kb
Host smart-24edd986-c86a-4f47-9d5b-fea51655f6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697827076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1697827076
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1449531011
Short name T1033
Test name
Test status
Simulation time 11822148 ps
CPU time 0.53 seconds
Started Aug 07 05:53:59 PM PDT 24
Finished Aug 07 05:54:00 PM PDT 24
Peak memory 195272 kb
Host smart-fc95adc4-5750-40db-9ff6-102bfe1193c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449531011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1449531011
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2900469961
Short name T682
Test name
Test status
Simulation time 89840875445 ps
CPU time 36.07 seconds
Started Aug 07 05:53:51 PM PDT 24
Finished Aug 07 05:54:27 PM PDT 24
Peak memory 199888 kb
Host smart-7ae7eae6-2916-487e-a5ae-004dd35ddcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900469961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2900469961
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.344514295
Short name T849
Test name
Test status
Simulation time 41402937801 ps
CPU time 45.03 seconds
Started Aug 07 05:53:53 PM PDT 24
Finished Aug 07 05:54:38 PM PDT 24
Peak memory 199900 kb
Host smart-69791c6f-0df9-4ae8-85b3-e7e97251f2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344514295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.344514295
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.67107638
Short name T353
Test name
Test status
Simulation time 27431312467 ps
CPU time 23.39 seconds
Started Aug 07 05:53:53 PM PDT 24
Finished Aug 07 05:54:17 PM PDT 24
Peak memory 199912 kb
Host smart-e31ec31c-befc-441d-b43a-bc484e850b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67107638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.67107638
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.3388214126
Short name T985
Test name
Test status
Simulation time 7749604968 ps
CPU time 10.99 seconds
Started Aug 07 05:53:51 PM PDT 24
Finished Aug 07 05:54:02 PM PDT 24
Peak memory 196704 kb
Host smart-ceaab59f-b828-476e-a9a9-2a26fb1e8f73
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388214126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.3388214126
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.171238035
Short name T932
Test name
Test status
Simulation time 96881767561 ps
CPU time 917.69 seconds
Started Aug 07 05:53:55 PM PDT 24
Finished Aug 07 06:09:12 PM PDT 24
Peak memory 199892 kb
Host smart-32c3b5a1-6f43-412b-a235-35c2097c580e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=171238035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.171238035
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.851150136
Short name T648
Test name
Test status
Simulation time 7036447391 ps
CPU time 12.34 seconds
Started Aug 07 05:53:56 PM PDT 24
Finished Aug 07 05:54:09 PM PDT 24
Peak memory 198604 kb
Host smart-0d4a540f-660d-467e-9205-c05818b21d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851150136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.851150136
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2306300939
Short name T791
Test name
Test status
Simulation time 69265568048 ps
CPU time 121.48 seconds
Started Aug 07 05:53:52 PM PDT 24
Finished Aug 07 05:55:54 PM PDT 24
Peak memory 198784 kb
Host smart-e23b085a-0c6b-48b9-bf8b-893fad2ad13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306300939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2306300939
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.309753201
Short name T606
Test name
Test status
Simulation time 13438930253 ps
CPU time 305.18 seconds
Started Aug 07 05:53:56 PM PDT 24
Finished Aug 07 05:59:01 PM PDT 24
Peak memory 199896 kb
Host smart-489ae76f-63ec-4fce-8c88-700c137f36b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=309753201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.309753201
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3875791561
Short name T13
Test name
Test status
Simulation time 2637962961 ps
CPU time 16.48 seconds
Started Aug 07 05:53:52 PM PDT 24
Finished Aug 07 05:54:08 PM PDT 24
Peak memory 198904 kb
Host smart-a5bfb480-3c50-4bb2-af61-3035fff632db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3875791561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3875791561
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.774942411
Short name T569
Test name
Test status
Simulation time 33113208538 ps
CPU time 33.51 seconds
Started Aug 07 05:54:05 PM PDT 24
Finished Aug 07 05:54:38 PM PDT 24
Peak memory 199912 kb
Host smart-be0082dc-0e6a-4d8b-a25b-ebb6db145816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774942411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.774942411
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1761899499
Short name T768
Test name
Test status
Simulation time 1694847334 ps
CPU time 1.94 seconds
Started Aug 07 05:54:25 PM PDT 24
Finished Aug 07 05:54:27 PM PDT 24
Peak memory 195388 kb
Host smart-420006a1-b000-4526-8a3d-723e2096f786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761899499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1761899499
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.195747086
Short name T952
Test name
Test status
Simulation time 6221360176 ps
CPU time 23.64 seconds
Started Aug 07 05:53:51 PM PDT 24
Finished Aug 07 05:54:15 PM PDT 24
Peak memory 199708 kb
Host smart-00ba8601-31ad-4bec-9c7c-81bc289131c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195747086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.195747086
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.4056842557
Short name T191
Test name
Test status
Simulation time 405161070639 ps
CPU time 508.27 seconds
Started Aug 07 05:53:57 PM PDT 24
Finished Aug 07 06:02:25 PM PDT 24
Peak memory 199876 kb
Host smart-7c68de6b-8504-4ac5-920f-b9e013db204f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056842557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.4056842557
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2967040271
Short name T865
Test name
Test status
Simulation time 252539864654 ps
CPU time 942.4 seconds
Started Aug 07 05:54:10 PM PDT 24
Finished Aug 07 06:09:53 PM PDT 24
Peak memory 224756 kb
Host smart-7da138b2-a59d-45ad-be0f-40c15394449f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967040271 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2967040271
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3176793680
Short name T776
Test name
Test status
Simulation time 550183275 ps
CPU time 1.71 seconds
Started Aug 07 05:53:57 PM PDT 24
Finished Aug 07 05:53:59 PM PDT 24
Peak memory 199268 kb
Host smart-d7e42bd7-8e67-49dc-ba42-bd9025cea962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176793680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3176793680
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3709071922
Short name T1021
Test name
Test status
Simulation time 151398130030 ps
CPU time 164.55 seconds
Started Aug 07 05:53:52 PM PDT 24
Finished Aug 07 05:56:36 PM PDT 24
Peak memory 199884 kb
Host smart-7bc7b356-ecc5-48a4-ba81-2d0826abb6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709071922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3709071922
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1635315745
Short name T1117
Test name
Test status
Simulation time 39284576 ps
CPU time 0.57 seconds
Started Aug 07 05:54:06 PM PDT 24
Finished Aug 07 05:54:07 PM PDT 24
Peak memory 195580 kb
Host smart-8165e536-ece6-4306-b1ab-be697cca49e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635315745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1635315745
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2323185969
Short name T1052
Test name
Test status
Simulation time 302161257198 ps
CPU time 318 seconds
Started Aug 07 05:54:01 PM PDT 24
Finished Aug 07 05:59:19 PM PDT 24
Peak memory 200152 kb
Host smart-7e6702ce-ba30-442d-b951-6f5a8f36caee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323185969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2323185969
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1796750526
Short name T930
Test name
Test status
Simulation time 71342076508 ps
CPU time 37.03 seconds
Started Aug 07 05:53:57 PM PDT 24
Finished Aug 07 05:54:34 PM PDT 24
Peak memory 199848 kb
Host smart-ede9a3d4-0af4-49de-9b80-6f8d21fd033f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796750526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1796750526
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2337735031
Short name T318
Test name
Test status
Simulation time 293866756283 ps
CPU time 37.87 seconds
Started Aug 07 05:53:58 PM PDT 24
Finished Aug 07 05:54:36 PM PDT 24
Peak memory 199852 kb
Host smart-2139c16f-e79a-42ea-9384-9c9017f3e22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337735031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2337735031
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3743516220
Short name T39
Test name
Test status
Simulation time 216910351175 ps
CPU time 357.42 seconds
Started Aug 07 05:53:57 PM PDT 24
Finished Aug 07 05:59:54 PM PDT 24
Peak memory 199944 kb
Host smart-7f412d3d-54cb-45bd-84f9-b34c4e843af8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743516220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3743516220
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1342394772
Short name T352
Test name
Test status
Simulation time 53260337420 ps
CPU time 107.27 seconds
Started Aug 07 05:54:04 PM PDT 24
Finished Aug 07 05:55:52 PM PDT 24
Peak memory 199844 kb
Host smart-58d5bab4-b5e2-42b1-bf08-d97986d831a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342394772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1342394772
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1109533865
Short name T529
Test name
Test status
Simulation time 9568370510 ps
CPU time 11.51 seconds
Started Aug 07 05:54:04 PM PDT 24
Finished Aug 07 05:54:16 PM PDT 24
Peak memory 199868 kb
Host smart-d9d5a3d4-72d0-44e2-9d5b-f5ad8a25a769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109533865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1109533865
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1738103540
Short name T491
Test name
Test status
Simulation time 13948097488 ps
CPU time 23.34 seconds
Started Aug 07 05:53:57 PM PDT 24
Finished Aug 07 05:54:20 PM PDT 24
Peak memory 200028 kb
Host smart-344af7f9-1a3f-4f2d-8073-6457de9acc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738103540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1738103540
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1306140630
Short name T1091
Test name
Test status
Simulation time 12235173166 ps
CPU time 643.02 seconds
Started Aug 07 05:54:04 PM PDT 24
Finished Aug 07 06:04:47 PM PDT 24
Peak memory 199916 kb
Host smart-da96b47c-4d29-4572-bd59-fbb9f514fa89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1306140630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1306140630
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.4068997255
Short name T24
Test name
Test status
Simulation time 7050690091 ps
CPU time 64.74 seconds
Started Aug 07 05:53:59 PM PDT 24
Finished Aug 07 05:55:04 PM PDT 24
Peak memory 198060 kb
Host smart-9cee4f09-df64-4e64-bd79-54605ca496d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4068997255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.4068997255
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2089142469
Short name T805
Test name
Test status
Simulation time 45346652933 ps
CPU time 74.31 seconds
Started Aug 07 05:53:57 PM PDT 24
Finished Aug 07 05:55:11 PM PDT 24
Peak memory 199908 kb
Host smart-48a99059-6df4-4cac-a714-cd9345928b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089142469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2089142469
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3750225728
Short name T929
Test name
Test status
Simulation time 46396471097 ps
CPU time 76.63 seconds
Started Aug 07 05:54:27 PM PDT 24
Finished Aug 07 05:55:43 PM PDT 24
Peak memory 196784 kb
Host smart-e55dd39f-b41d-46bf-94ad-f100559c33e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750225728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3750225728
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2894578845
Short name T260
Test name
Test status
Simulation time 286129207 ps
CPU time 1.89 seconds
Started Aug 07 05:53:59 PM PDT 24
Finished Aug 07 05:54:01 PM PDT 24
Peak memory 198540 kb
Host smart-f852aecb-0324-45a6-8560-9d3aa0f15ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894578845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2894578845
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.2188615140
Short name T16
Test name
Test status
Simulation time 69527307135 ps
CPU time 31.23 seconds
Started Aug 07 05:54:08 PM PDT 24
Finished Aug 07 05:54:39 PM PDT 24
Peak memory 199852 kb
Host smart-f577b91c-02dd-4335-b868-ff238e7b1463
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188615140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2188615140
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.874090055
Short name T290
Test name
Test status
Simulation time 7287830707 ps
CPU time 14.04 seconds
Started Aug 07 05:54:04 PM PDT 24
Finished Aug 07 05:54:18 PM PDT 24
Peak memory 199848 kb
Host smart-a81744dc-51d0-48d6-a7b8-c4e95b9a7e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874090055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.874090055
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2477480662
Short name T984
Test name
Test status
Simulation time 36794265426 ps
CPU time 27.75 seconds
Started Aug 07 05:53:59 PM PDT 24
Finished Aug 07 05:54:27 PM PDT 24
Peak memory 199892 kb
Host smart-ba6cc7ad-5318-461c-971b-bad47b2ac7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477480662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2477480662
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2309563025
Short name T416
Test name
Test status
Simulation time 15324709 ps
CPU time 0.52 seconds
Started Aug 07 05:54:10 PM PDT 24
Finished Aug 07 05:54:11 PM PDT 24
Peak memory 194548 kb
Host smart-95501050-5592-4fe7-ad3a-588e3e10bb63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309563025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2309563025
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.4025015561
Short name T781
Test name
Test status
Simulation time 29298359149 ps
CPU time 52.49 seconds
Started Aug 07 05:54:03 PM PDT 24
Finished Aug 07 05:54:56 PM PDT 24
Peak memory 199912 kb
Host smart-a47fbac2-84f7-44fd-9fd1-c66d3b1fde9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025015561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.4025015561
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2109846916
Short name T671
Test name
Test status
Simulation time 29506324613 ps
CPU time 48.09 seconds
Started Aug 07 05:54:04 PM PDT 24
Finished Aug 07 05:54:52 PM PDT 24
Peak memory 199880 kb
Host smart-b0d78659-a349-4e1e-ab53-a3a764e3c790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109846916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2109846916
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2590758998
Short name T784
Test name
Test status
Simulation time 26798349736 ps
CPU time 48.59 seconds
Started Aug 07 05:54:02 PM PDT 24
Finished Aug 07 05:54:51 PM PDT 24
Peak memory 199832 kb
Host smart-3b91b4df-8754-4024-b5fa-1b31c950ece6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590758998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2590758998
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3835822245
Short name T538
Test name
Test status
Simulation time 40345079389 ps
CPU time 19.55 seconds
Started Aug 07 05:54:10 PM PDT 24
Finished Aug 07 05:54:30 PM PDT 24
Peak memory 199828 kb
Host smart-7e41bfb6-2c35-466a-ac41-dc8c6a355032
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835822245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3835822245
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.4220781581
Short name T335
Test name
Test status
Simulation time 168421337217 ps
CPU time 278.4 seconds
Started Aug 07 05:54:11 PM PDT 24
Finished Aug 07 05:58:49 PM PDT 24
Peak memory 199892 kb
Host smart-3802f7e6-b084-405a-903f-ee21ddbca6af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4220781581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.4220781581
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3550804264
Short name T1006
Test name
Test status
Simulation time 842584507 ps
CPU time 1.1 seconds
Started Aug 07 05:54:09 PM PDT 24
Finished Aug 07 05:54:11 PM PDT 24
Peak memory 197156 kb
Host smart-7405d5f0-9427-4b8d-a952-e6cd8d1ddebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550804264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3550804264
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3739188343
Short name T1017
Test name
Test status
Simulation time 109756401636 ps
CPU time 50.55 seconds
Started Aug 07 05:54:15 PM PDT 24
Finished Aug 07 05:55:06 PM PDT 24
Peak memory 199972 kb
Host smart-a6d39eb1-3ee4-42f2-949c-647d25902103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739188343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3739188343
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.280085948
Short name T526
Test name
Test status
Simulation time 17370611743 ps
CPU time 651.36 seconds
Started Aug 07 05:54:09 PM PDT 24
Finished Aug 07 06:05:01 PM PDT 24
Peak memory 199860 kb
Host smart-453b0dfc-9b71-4b5b-ab37-9917787c2d5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=280085948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.280085948
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1697393341
Short name T593
Test name
Test status
Simulation time 7246210568 ps
CPU time 10.97 seconds
Started Aug 07 05:54:04 PM PDT 24
Finished Aug 07 05:54:15 PM PDT 24
Peak memory 197980 kb
Host smart-37199a82-cb8f-47bb-9f38-9cc6318aa67a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1697393341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1697393341
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.4119855594
Short name T724
Test name
Test status
Simulation time 16471577203 ps
CPU time 11.6 seconds
Started Aug 07 05:54:10 PM PDT 24
Finished Aug 07 05:54:21 PM PDT 24
Peak memory 199196 kb
Host smart-a725a0ab-36db-4a47-915e-42cfb41baeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119855594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.4119855594
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1997847435
Short name T1094
Test name
Test status
Simulation time 4121298154 ps
CPU time 1.08 seconds
Started Aug 07 05:54:10 PM PDT 24
Finished Aug 07 05:54:12 PM PDT 24
Peak memory 196240 kb
Host smart-d2746594-04a8-4b00-b444-ca72ec45cf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997847435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1997847435
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.54262600
Short name T448
Test name
Test status
Simulation time 133067966 ps
CPU time 1 seconds
Started Aug 07 05:54:02 PM PDT 24
Finished Aug 07 05:54:03 PM PDT 24
Peak memory 198304 kb
Host smart-40f464cb-6978-4d95-a94a-480996e60b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54262600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.54262600
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3262076613
Short name T773
Test name
Test status
Simulation time 333901560120 ps
CPU time 614.81 seconds
Started Aug 07 05:54:09 PM PDT 24
Finished Aug 07 06:04:24 PM PDT 24
Peak memory 199936 kb
Host smart-208caaa6-29dd-4a28-82e1-18db67d5191a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262076613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3262076613
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1140738757
Short name T60
Test name
Test status
Simulation time 239953851473 ps
CPU time 709.37 seconds
Started Aug 07 05:54:12 PM PDT 24
Finished Aug 07 06:06:02 PM PDT 24
Peak memory 216396 kb
Host smart-2cbf48a8-7c8d-48b1-acda-80f222afc91e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140738757 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1140738757
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1726372161
Short name T1150
Test name
Test status
Simulation time 8580070556 ps
CPU time 5.73 seconds
Started Aug 07 05:54:14 PM PDT 24
Finished Aug 07 05:54:20 PM PDT 24
Peak memory 199652 kb
Host smart-c2a8b047-4a4c-410f-803c-94cd602adfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726372161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1726372161
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.3510122890
Short name T314
Test name
Test status
Simulation time 2836349199 ps
CPU time 4.91 seconds
Started Aug 07 05:54:05 PM PDT 24
Finished Aug 07 05:54:10 PM PDT 24
Peak memory 197376 kb
Host smart-a2f2c22a-11ee-4e5e-951b-06d1c2c92880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510122890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3510122890
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3597782208
Short name T872
Test name
Test status
Simulation time 18699088 ps
CPU time 0.57 seconds
Started Aug 07 05:51:17 PM PDT 24
Finished Aug 07 05:51:17 PM PDT 24
Peak memory 195244 kb
Host smart-3be7a64d-48df-4476-82de-f1cf9152862f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597782208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3597782208
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.790766545
Short name T1165
Test name
Test status
Simulation time 116624077663 ps
CPU time 160.84 seconds
Started Aug 07 05:51:14 PM PDT 24
Finished Aug 07 05:53:55 PM PDT 24
Peak memory 199824 kb
Host smart-d1a1e4e6-91fc-4532-b5f0-78c019c3d376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790766545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.790766545
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.2132524730
Short name T876
Test name
Test status
Simulation time 49041454202 ps
CPU time 36.66 seconds
Started Aug 07 05:51:17 PM PDT 24
Finished Aug 07 05:51:53 PM PDT 24
Peak memory 199856 kb
Host smart-b3098e9f-c93a-4816-af15-d26d8db48166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132524730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2132524730
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.429251418
Short name T1
Test name
Test status
Simulation time 11525435991 ps
CPU time 15.1 seconds
Started Aug 07 05:51:14 PM PDT 24
Finished Aug 07 05:51:29 PM PDT 24
Peak memory 199812 kb
Host smart-59686cdc-ec85-4f57-b0a8-b974902dfdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429251418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.429251418
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.117852734
Short name T665
Test name
Test status
Simulation time 212427544807 ps
CPU time 142.35 seconds
Started Aug 07 05:51:11 PM PDT 24
Finished Aug 07 05:53:33 PM PDT 24
Peak memory 198464 kb
Host smart-f3177867-e1f2-4f1d-bfab-d34436619555
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117852734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.117852734
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.51223100
Short name T1059
Test name
Test status
Simulation time 103140210836 ps
CPU time 772.96 seconds
Started Aug 07 05:51:16 PM PDT 24
Finished Aug 07 06:04:10 PM PDT 24
Peak memory 199864 kb
Host smart-1f320d3a-dc74-4e9c-8f85-30c36db1d793
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=51223100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.51223100
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3787616310
Short name T518
Test name
Test status
Simulation time 8917642070 ps
CPU time 6.55 seconds
Started Aug 07 05:51:10 PM PDT 24
Finished Aug 07 05:51:16 PM PDT 24
Peak memory 199332 kb
Host smart-7bfad0f5-c5ac-4da9-a2fb-a19184d6b4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787616310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3787616310
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3000617455
Short name T506
Test name
Test status
Simulation time 113509406574 ps
CPU time 100.47 seconds
Started Aug 07 05:51:16 PM PDT 24
Finished Aug 07 05:52:57 PM PDT 24
Peak memory 199860 kb
Host smart-cdf43eb3-e7c8-45c2-b39a-1cb74b32f18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000617455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3000617455
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1232727008
Short name T794
Test name
Test status
Simulation time 10598405741 ps
CPU time 537.6 seconds
Started Aug 07 05:51:12 PM PDT 24
Finished Aug 07 06:00:10 PM PDT 24
Peak memory 199820 kb
Host smart-68022b46-a305-411f-a3d6-d2f8114c5c71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1232727008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1232727008
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2979221508
Short name T451
Test name
Test status
Simulation time 4758432693 ps
CPU time 39.97 seconds
Started Aug 07 05:51:11 PM PDT 24
Finished Aug 07 05:51:51 PM PDT 24
Peak memory 198664 kb
Host smart-cb822ded-b321-4f06-a80a-9754a98041d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979221508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2979221508
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2797862718
Short name T476
Test name
Test status
Simulation time 35191649152 ps
CPU time 17.4 seconds
Started Aug 07 05:51:15 PM PDT 24
Finished Aug 07 05:51:32 PM PDT 24
Peak memory 199796 kb
Host smart-08ead905-ecf5-4708-bbe4-f08568c462fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797862718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2797862718
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1007826936
Short name T405
Test name
Test status
Simulation time 2849061859 ps
CPU time 1.85 seconds
Started Aug 07 05:51:15 PM PDT 24
Finished Aug 07 05:51:17 PM PDT 24
Peak memory 196416 kb
Host smart-ee37f330-f348-4d12-8474-13bdc7eb8295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007826936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1007826936
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3442115358
Short name T29
Test name
Test status
Simulation time 107054636 ps
CPU time 0.94 seconds
Started Aug 07 05:51:10 PM PDT 24
Finished Aug 07 05:51:11 PM PDT 24
Peak memory 218304 kb
Host smart-8c1f6ef3-a9be-460e-8a5a-a747adf09cd1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442115358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3442115358
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2123869056
Short name T1076
Test name
Test status
Simulation time 6222705030 ps
CPU time 27.13 seconds
Started Aug 07 05:51:10 PM PDT 24
Finished Aug 07 05:51:37 PM PDT 24
Peak memory 199860 kb
Host smart-80209242-ad61-4d40-8c7b-b6e404adca28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123869056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2123869056
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.686247104
Short name T979
Test name
Test status
Simulation time 271916485459 ps
CPU time 1309.9 seconds
Started Aug 07 05:51:15 PM PDT 24
Finished Aug 07 06:13:05 PM PDT 24
Peak memory 199932 kb
Host smart-d0431152-7a32-46cb-aaa7-366c5748ff77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686247104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.686247104
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3206121517
Short name T12
Test name
Test status
Simulation time 25874337415 ps
CPU time 58.93 seconds
Started Aug 07 05:51:14 PM PDT 24
Finished Aug 07 05:52:13 PM PDT 24
Peak memory 215616 kb
Host smart-2d8cfceb-4f00-4775-ab12-ab795d191b7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206121517 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3206121517
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.958149136
Short name T18
Test name
Test status
Simulation time 523658411 ps
CPU time 1.88 seconds
Started Aug 07 05:51:14 PM PDT 24
Finished Aug 07 05:51:16 PM PDT 24
Peak memory 198532 kb
Host smart-0ac0f82f-a22e-4932-92e6-edbbcf317ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958149136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.958149136
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3450536515
Short name T291
Test name
Test status
Simulation time 34771104013 ps
CPU time 65.04 seconds
Started Aug 07 05:51:10 PM PDT 24
Finished Aug 07 05:52:15 PM PDT 24
Peak memory 199892 kb
Host smart-03425ad2-4506-4d2e-9a38-24524a4f180e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450536515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3450536515
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2707987306
Short name T574
Test name
Test status
Simulation time 25648164 ps
CPU time 0.58 seconds
Started Aug 07 05:54:22 PM PDT 24
Finished Aug 07 05:54:23 PM PDT 24
Peak memory 195328 kb
Host smart-d966ef37-0362-4052-9bb2-3be724b76980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707987306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2707987306
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1555948757
Short name T1035
Test name
Test status
Simulation time 120984371016 ps
CPU time 45.33 seconds
Started Aug 07 05:54:18 PM PDT 24
Finished Aug 07 05:55:04 PM PDT 24
Peak memory 199880 kb
Host smart-52e9a5e3-f5b1-4bdd-9d9b-9df4b553930d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555948757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1555948757
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1657157140
Short name T277
Test name
Test status
Simulation time 100594277864 ps
CPU time 59.16 seconds
Started Aug 07 05:54:16 PM PDT 24
Finished Aug 07 05:55:16 PM PDT 24
Peak memory 199940 kb
Host smart-d3087731-11c3-4e51-b081-afd24205fe09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657157140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1657157140
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.635778100
Short name T674
Test name
Test status
Simulation time 199034068387 ps
CPU time 317.81 seconds
Started Aug 07 05:54:17 PM PDT 24
Finished Aug 07 05:59:35 PM PDT 24
Peak memory 199832 kb
Host smart-b8fd78a8-acf5-4a9e-92ed-9d40a96d1d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635778100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.635778100
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2886679665
Short name T1086
Test name
Test status
Simulation time 16184950651 ps
CPU time 7.59 seconds
Started Aug 07 05:54:15 PM PDT 24
Finished Aug 07 05:54:23 PM PDT 24
Peak memory 199588 kb
Host smart-6e5e11d9-3cac-4255-864e-3073c259d1ac
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886679665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2886679665
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3914797564
Short name T1025
Test name
Test status
Simulation time 137442120354 ps
CPU time 1447.19 seconds
Started Aug 07 05:54:16 PM PDT 24
Finished Aug 07 06:18:24 PM PDT 24
Peak memory 199904 kb
Host smart-76b41201-4559-43ce-860c-4dd776c5f0b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3914797564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3914797564
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3902620983
Short name T467
Test name
Test status
Simulation time 5903589108 ps
CPU time 10.14 seconds
Started Aug 07 05:54:16 PM PDT 24
Finished Aug 07 05:54:26 PM PDT 24
Peak memory 198480 kb
Host smart-9619ed8f-e951-4494-b5eb-6b82bdde3eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902620983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3902620983
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.3587072762
Short name T942
Test name
Test status
Simulation time 226559228668 ps
CPU time 112.13 seconds
Started Aug 07 05:54:16 PM PDT 24
Finished Aug 07 05:56:09 PM PDT 24
Peak memory 199924 kb
Host smart-6f92c198-3c58-4f62-b9da-4a2672919374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587072762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.3587072762
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.1346594332
Short name T1004
Test name
Test status
Simulation time 21581013496 ps
CPU time 598.57 seconds
Started Aug 07 05:54:17 PM PDT 24
Finished Aug 07 06:04:16 PM PDT 24
Peak memory 199888 kb
Host smart-27669925-819a-47fb-ade7-2f2bbf6e4aae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1346594332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1346594332
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1625755416
Short name T635
Test name
Test status
Simulation time 4855830432 ps
CPU time 18.49 seconds
Started Aug 07 05:54:16 PM PDT 24
Finished Aug 07 05:54:34 PM PDT 24
Peak memory 199852 kb
Host smart-d57c087f-86ec-4520-aa4b-13556b5fc19a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1625755416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1625755416
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.574207351
Short name T1171
Test name
Test status
Simulation time 154734024006 ps
CPU time 240.42 seconds
Started Aug 07 05:54:16 PM PDT 24
Finished Aug 07 05:58:17 PM PDT 24
Peak memory 199800 kb
Host smart-141aa6d4-7adb-4cb3-b1fd-cfec63397d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574207351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.574207351
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.837997616
Short name T435
Test name
Test status
Simulation time 4023057337 ps
CPU time 6.12 seconds
Started Aug 07 05:54:18 PM PDT 24
Finished Aug 07 05:54:25 PM PDT 24
Peak memory 196444 kb
Host smart-e4cdfdc1-4a04-47f7-8ed6-1cc4f7ecd436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837997616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.837997616
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3812266855
Short name T840
Test name
Test status
Simulation time 11578189537 ps
CPU time 17.92 seconds
Started Aug 07 05:54:09 PM PDT 24
Finished Aug 07 05:54:27 PM PDT 24
Peak memory 199848 kb
Host smart-7a524520-4f4f-4f80-89b0-67a73dfaa5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812266855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3812266855
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.1278522206
Short name T890
Test name
Test status
Simulation time 237497413477 ps
CPU time 726.14 seconds
Started Aug 07 05:54:22 PM PDT 24
Finished Aug 07 06:06:28 PM PDT 24
Peak memory 199844 kb
Host smart-6f3de3f6-d993-44aa-925d-fb1fb77a4b87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278522206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1278522206
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.4036638276
Short name T433
Test name
Test status
Simulation time 79727441347 ps
CPU time 926.92 seconds
Started Aug 07 05:54:22 PM PDT 24
Finished Aug 07 06:09:49 PM PDT 24
Peak memory 222332 kb
Host smart-996adca7-410f-4b58-b365-77ce9128b8e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036638276 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.4036638276
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3245255958
Short name T289
Test name
Test status
Simulation time 1276343214 ps
CPU time 1.57 seconds
Started Aug 07 05:54:18 PM PDT 24
Finished Aug 07 05:54:20 PM PDT 24
Peak memory 198260 kb
Host smart-bace9b9a-c763-4a99-ae8c-e6d0f9bc1f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245255958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3245255958
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1308647879
Short name T641
Test name
Test status
Simulation time 44074650884 ps
CPU time 74.12 seconds
Started Aug 07 05:54:17 PM PDT 24
Finished Aug 07 05:55:31 PM PDT 24
Peak memory 199836 kb
Host smart-3efcac03-f776-4699-a201-07275176e323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308647879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1308647879
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.3552015221
Short name T726
Test name
Test status
Simulation time 30756944 ps
CPU time 0.55 seconds
Started Aug 07 05:54:34 PM PDT 24
Finished Aug 07 05:54:35 PM PDT 24
Peak memory 195296 kb
Host smart-c7e5780a-c450-499f-b68a-e044b424b452
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552015221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3552015221
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1043758571
Short name T131
Test name
Test status
Simulation time 99799014250 ps
CPU time 68.33 seconds
Started Aug 07 05:54:23 PM PDT 24
Finished Aug 07 05:55:31 PM PDT 24
Peak memory 199852 kb
Host smart-d8abfaa6-ac7e-4f85-8ae3-6d366993bf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043758571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1043758571
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2275150352
Short name T160
Test name
Test status
Simulation time 98595583500 ps
CPU time 17.62 seconds
Started Aug 07 05:54:21 PM PDT 24
Finished Aug 07 05:54:39 PM PDT 24
Peak memory 199872 kb
Host smart-9a513039-1b4c-42bf-88d5-64bcd7a3551e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275150352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2275150352
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_intr.2267319483
Short name T17
Test name
Test status
Simulation time 63766587727 ps
CPU time 41.34 seconds
Started Aug 07 05:54:28 PM PDT 24
Finished Aug 07 05:55:10 PM PDT 24
Peak memory 199916 kb
Host smart-1bc51081-0b22-4dff-96ec-280c780bd9b2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267319483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2267319483
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2924145304
Short name T270
Test name
Test status
Simulation time 100081487695 ps
CPU time 426.1 seconds
Started Aug 07 05:54:28 PM PDT 24
Finished Aug 07 06:01:34 PM PDT 24
Peak memory 199892 kb
Host smart-8e6a4775-0ecf-443f-bfda-1cd01c16605b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2924145304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2924145304
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.2923866727
Short name T722
Test name
Test status
Simulation time 3858530904 ps
CPU time 5.18 seconds
Started Aug 07 05:54:21 PM PDT 24
Finished Aug 07 05:54:27 PM PDT 24
Peak memory 199856 kb
Host smart-6f5b31ff-13c8-4303-865b-b066f8b78b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923866727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.2923866727
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.47611917
Short name T863
Test name
Test status
Simulation time 323767166744 ps
CPU time 112.94 seconds
Started Aug 07 05:54:22 PM PDT 24
Finished Aug 07 05:56:15 PM PDT 24
Peak memory 208268 kb
Host smart-15f2f94c-1c7b-494d-bb19-9d9b4ea043aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47611917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.47611917
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.1017598424
Short name T973
Test name
Test status
Simulation time 16495538205 ps
CPU time 915.81 seconds
Started Aug 07 05:54:23 PM PDT 24
Finished Aug 07 06:09:39 PM PDT 24
Peak memory 199892 kb
Host smart-a003d5a2-583d-475e-90c7-5533f9261090
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1017598424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1017598424
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.404306430
Short name T349
Test name
Test status
Simulation time 1390548209 ps
CPU time 1.13 seconds
Started Aug 07 05:54:22 PM PDT 24
Finished Aug 07 05:54:23 PM PDT 24
Peak memory 195472 kb
Host smart-06f6815e-afe4-4dc8-ba40-7a91c0bbf81d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=404306430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.404306430
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.388636216
Short name T737
Test name
Test status
Simulation time 256404504274 ps
CPU time 229.97 seconds
Started Aug 07 05:54:22 PM PDT 24
Finished Aug 07 05:58:12 PM PDT 24
Peak memory 199916 kb
Host smart-8a1333ff-0706-4013-9078-378f9ee0a8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388636216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.388636216
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.4284372844
Short name T407
Test name
Test status
Simulation time 2964600849 ps
CPU time 1.48 seconds
Started Aug 07 05:54:21 PM PDT 24
Finished Aug 07 05:54:23 PM PDT 24
Peak memory 195916 kb
Host smart-d846b7e9-cd07-407a-a479-e721d1892c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284372844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.4284372844
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.872535841
Short name T807
Test name
Test status
Simulation time 6257657537 ps
CPU time 10.04 seconds
Started Aug 07 05:54:23 PM PDT 24
Finished Aug 07 05:54:33 PM PDT 24
Peak memory 199160 kb
Host smart-aaecd785-c92b-4f33-bb68-afab50ffc3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872535841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.872535841
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1637117759
Short name T655
Test name
Test status
Simulation time 433173309206 ps
CPU time 202 seconds
Started Aug 07 05:54:31 PM PDT 24
Finished Aug 07 05:57:53 PM PDT 24
Peak memory 199828 kb
Host smart-ec65d897-6248-4fb8-b2d2-412fde7ba6f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637117759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1637117759
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.4250961029
Short name T101
Test name
Test status
Simulation time 55854253226 ps
CPU time 291.78 seconds
Started Aug 07 05:54:23 PM PDT 24
Finished Aug 07 05:59:15 PM PDT 24
Peak memory 215772 kb
Host smart-1c11fce6-f407-41c9-8c2c-f9b1e972b43e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250961029 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.4250961029
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2100401446
Short name T510
Test name
Test status
Simulation time 7079757287 ps
CPU time 27.4 seconds
Started Aug 07 05:54:29 PM PDT 24
Finished Aug 07 05:54:56 PM PDT 24
Peak memory 199812 kb
Host smart-e28d0c49-d66e-4be1-9fec-2f45257619d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100401446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2100401446
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.630772124
Short name T1037
Test name
Test status
Simulation time 46977958048 ps
CPU time 42.59 seconds
Started Aug 07 05:54:23 PM PDT 24
Finished Aug 07 05:55:05 PM PDT 24
Peak memory 199756 kb
Host smart-9d75c244-b2ab-4ae8-8bfb-62f368d44da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630772124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.630772124
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.345190150
Short name T447
Test name
Test status
Simulation time 17425429 ps
CPU time 0.56 seconds
Started Aug 07 05:54:33 PM PDT 24
Finished Aug 07 05:54:33 PM PDT 24
Peak memory 195280 kb
Host smart-8f6ce9c0-9ac5-4ac0-a93f-74d7ba8a4b79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345190150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.345190150
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.975541159
Short name T903
Test name
Test status
Simulation time 106896972045 ps
CPU time 55.04 seconds
Started Aug 07 05:54:30 PM PDT 24
Finished Aug 07 05:55:25 PM PDT 24
Peak memory 199832 kb
Host smart-db153b6b-da15-4110-bf58-222fa7a1b3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975541159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.975541159
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.4134933361
Short name T298
Test name
Test status
Simulation time 25341149278 ps
CPU time 48.04 seconds
Started Aug 07 05:54:28 PM PDT 24
Finished Aug 07 05:55:16 PM PDT 24
Peak memory 199856 kb
Host smart-cbdd40c6-4b5a-4ea0-876f-316f2c048e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134933361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.4134933361
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1912109061
Short name T185
Test name
Test status
Simulation time 33960040130 ps
CPU time 23.49 seconds
Started Aug 07 05:54:34 PM PDT 24
Finished Aug 07 05:54:58 PM PDT 24
Peak memory 199932 kb
Host smart-c2d22f44-a8c3-4903-9c3a-bc9d26434324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912109061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1912109061
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2843277607
Short name T857
Test name
Test status
Simulation time 55112749583 ps
CPU time 90.69 seconds
Started Aug 07 05:54:28 PM PDT 24
Finished Aug 07 05:55:58 PM PDT 24
Peak memory 199876 kb
Host smart-00e706cf-485c-49ef-b793-d07d09ae4dec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843277607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2843277607
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2106065888
Short name T1078
Test name
Test status
Simulation time 87296243165 ps
CPU time 737.78 seconds
Started Aug 07 05:54:34 PM PDT 24
Finished Aug 07 06:06:52 PM PDT 24
Peak memory 199928 kb
Host smart-a1e0b617-6f17-4f65-ae07-4292e5fa318b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2106065888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2106065888
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.641979301
Short name T1020
Test name
Test status
Simulation time 3226771446 ps
CPU time 3.97 seconds
Started Aug 07 05:54:34 PM PDT 24
Finished Aug 07 05:54:38 PM PDT 24
Peak memory 199908 kb
Host smart-3d537c60-a7f8-48d1-926e-5711c222a746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641979301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.641979301
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2681565774
Short name T1135
Test name
Test status
Simulation time 144597041813 ps
CPU time 51.24 seconds
Started Aug 07 05:54:29 PM PDT 24
Finished Aug 07 05:55:21 PM PDT 24
Peak memory 198872 kb
Host smart-79d7aa7a-de52-490f-8052-7888408816df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681565774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2681565774
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3198304970
Short name T697
Test name
Test status
Simulation time 11719717516 ps
CPU time 424.61 seconds
Started Aug 07 05:54:34 PM PDT 24
Finished Aug 07 06:01:39 PM PDT 24
Peak memory 199832 kb
Host smart-a589be32-dcc6-4c0b-8275-2c4c904773ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3198304970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3198304970
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.1352769183
Short name T412
Test name
Test status
Simulation time 1166453007 ps
CPU time 2.56 seconds
Started Aug 07 05:54:34 PM PDT 24
Finished Aug 07 05:54:37 PM PDT 24
Peak memory 197708 kb
Host smart-2314d4f6-cf90-4156-aa41-7dd746c538ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1352769183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1352769183
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1439380717
Short name T483
Test name
Test status
Simulation time 29123253482 ps
CPU time 71.35 seconds
Started Aug 07 05:54:34 PM PDT 24
Finished Aug 07 05:55:46 PM PDT 24
Peak memory 199936 kb
Host smart-a27c62d8-027d-4a50-91af-9bf7274b434b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439380717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1439380717
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.608829734
Short name T295
Test name
Test status
Simulation time 34149656996 ps
CPU time 55 seconds
Started Aug 07 05:54:28 PM PDT 24
Finished Aug 07 05:55:24 PM PDT 24
Peak memory 195960 kb
Host smart-8cd35205-e20e-48ab-a50c-8b7afa75681f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608829734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.608829734
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3034312799
Short name T566
Test name
Test status
Simulation time 282933939 ps
CPU time 1.13 seconds
Started Aug 07 05:54:29 PM PDT 24
Finished Aug 07 05:54:30 PM PDT 24
Peak memory 198644 kb
Host smart-a67db3b5-cdea-48c6-89bd-09fe3991f423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034312799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3034312799
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2133606715
Short name T252
Test name
Test status
Simulation time 83124034114 ps
CPU time 301.3 seconds
Started Aug 07 05:54:34 PM PDT 24
Finished Aug 07 05:59:36 PM PDT 24
Peak memory 199888 kb
Host smart-d46f9603-d588-4244-90d6-7f6e6b99324e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133606715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2133606715
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3407013967
Short name T306
Test name
Test status
Simulation time 24639875003 ps
CPU time 413.75 seconds
Started Aug 07 05:54:33 PM PDT 24
Finished Aug 07 06:01:27 PM PDT 24
Peak memory 216396 kb
Host smart-bdc5b223-dd5d-4672-bcdb-095aab5a4dd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407013967 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3407013967
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.846161945
Short name T385
Test name
Test status
Simulation time 1745503897 ps
CPU time 3.98 seconds
Started Aug 07 05:54:34 PM PDT 24
Finished Aug 07 05:54:39 PM PDT 24
Peak memory 198276 kb
Host smart-f8c6e653-6825-4b6a-a41f-1ecc4e4a380b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846161945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.846161945
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.171250758
Short name T882
Test name
Test status
Simulation time 91444661571 ps
CPU time 33.41 seconds
Started Aug 07 05:54:29 PM PDT 24
Finished Aug 07 05:55:02 PM PDT 24
Peak memory 199916 kb
Host smart-1fac32a2-f178-486a-b68d-10060291a4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171250758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.171250758
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1533448358
Short name T615
Test name
Test status
Simulation time 12824251 ps
CPU time 0.57 seconds
Started Aug 07 05:54:49 PM PDT 24
Finished Aug 07 05:54:50 PM PDT 24
Peak memory 195268 kb
Host smart-c591f7bd-3f78-4cd4-8c8c-b6816769081b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533448358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1533448358
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.823787734
Short name T1172
Test name
Test status
Simulation time 27744031020 ps
CPU time 47.44 seconds
Started Aug 07 05:54:34 PM PDT 24
Finished Aug 07 05:55:22 PM PDT 24
Peak memory 199880 kb
Host smart-132c7ac8-4992-4f5f-bd80-1a6982de820b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823787734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.823787734
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.4077245571
Short name T276
Test name
Test status
Simulation time 21371876802 ps
CPU time 32.98 seconds
Started Aug 07 05:54:37 PM PDT 24
Finished Aug 07 05:55:10 PM PDT 24
Peak memory 198048 kb
Host smart-73bd124a-8d90-480d-9570-1771b9e6779b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077245571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.4077245571
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2738878525
Short name T829
Test name
Test status
Simulation time 70885675498 ps
CPU time 28.24 seconds
Started Aug 07 05:54:42 PM PDT 24
Finished Aug 07 05:55:10 PM PDT 24
Peak memory 199896 kb
Host smart-07e2d677-9c68-4c64-9a31-a1dcdfb5b982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738878525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2738878525
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.2425905721
Short name T94
Test name
Test status
Simulation time 12862130342 ps
CPU time 8.81 seconds
Started Aug 07 05:54:41 PM PDT 24
Finished Aug 07 05:54:50 PM PDT 24
Peak memory 199948 kb
Host smart-34ee80ce-ceae-476c-b626-5f14d736d1f3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425905721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2425905721
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.21538863
Short name T1164
Test name
Test status
Simulation time 118357610237 ps
CPU time 285.44 seconds
Started Aug 07 05:54:44 PM PDT 24
Finished Aug 07 05:59:29 PM PDT 24
Peak memory 199920 kb
Host smart-bf54d9e4-96f0-4d76-846e-dc30c5f23759
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21538863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.21538863
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3340521538
Short name T1134
Test name
Test status
Simulation time 10591619082 ps
CPU time 15.38 seconds
Started Aug 07 05:54:43 PM PDT 24
Finished Aug 07 05:54:59 PM PDT 24
Peak memory 199320 kb
Host smart-c192e7dc-cbfe-4e14-82a8-f4713333e7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340521538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3340521538
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1272154965
Short name T517
Test name
Test status
Simulation time 134076331884 ps
CPU time 90.38 seconds
Started Aug 07 05:54:41 PM PDT 24
Finished Aug 07 05:56:12 PM PDT 24
Peak memory 200172 kb
Host smart-76c1ee12-3d80-4fcc-9c2d-0c360e8dfb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272154965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1272154965
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.3226215598
Short name T296
Test name
Test status
Simulation time 18016196859 ps
CPU time 70.33 seconds
Started Aug 07 05:54:40 PM PDT 24
Finished Aug 07 05:55:51 PM PDT 24
Peak memory 199856 kb
Host smart-5b7c3527-78a0-4b76-bbed-f8d660d59211
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3226215598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3226215598
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2114294534
Short name T308
Test name
Test status
Simulation time 6164343413 ps
CPU time 14.46 seconds
Started Aug 07 05:54:40 PM PDT 24
Finished Aug 07 05:54:55 PM PDT 24
Peak memory 198724 kb
Host smart-937f4f0a-dc7d-48da-a488-83afc5a79ef5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2114294534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2114294534
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.836425079
Short name T885
Test name
Test status
Simulation time 20087978256 ps
CPU time 29.43 seconds
Started Aug 07 05:54:41 PM PDT 24
Finished Aug 07 05:55:10 PM PDT 24
Peak memory 199600 kb
Host smart-e7436544-6eb1-4a12-a29f-4bef74bdd993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836425079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.836425079
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.686838864
Short name T278
Test name
Test status
Simulation time 42112340958 ps
CPU time 37.14 seconds
Started Aug 07 05:54:44 PM PDT 24
Finished Aug 07 05:55:21 PM PDT 24
Peak memory 196188 kb
Host smart-f4a3e881-7251-4199-920e-05f5842aa4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686838864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.686838864
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.117042691
Short name T326
Test name
Test status
Simulation time 678436496 ps
CPU time 1.75 seconds
Started Aug 07 05:54:34 PM PDT 24
Finished Aug 07 05:54:36 PM PDT 24
Peak memory 199796 kb
Host smart-5be88929-df8d-4d0d-a5ed-c8762e838fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117042691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.117042691
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.731898946
Short name T283
Test name
Test status
Simulation time 245846688854 ps
CPU time 567.96 seconds
Started Aug 07 05:54:46 PM PDT 24
Finished Aug 07 06:04:14 PM PDT 24
Peak memory 208208 kb
Host smart-d38a25a8-29f9-4527-9ec1-278f2d6b2c1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731898946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.731898946
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.528273472
Short name T100
Test name
Test status
Simulation time 140550680624 ps
CPU time 549.02 seconds
Started Aug 07 05:54:41 PM PDT 24
Finished Aug 07 06:03:50 PM PDT 24
Peak memory 224744 kb
Host smart-998e8982-62b9-4aaf-a785-245ff5e66242
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528273472 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.528273472
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3346570811
Short name T557
Test name
Test status
Simulation time 2945763200 ps
CPU time 2.26 seconds
Started Aug 07 05:54:44 PM PDT 24
Finished Aug 07 05:54:46 PM PDT 24
Peak memory 199144 kb
Host smart-d28ee48a-2fbc-473e-adcd-e9008a5797e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346570811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3346570811
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1299160162
Short name T1158
Test name
Test status
Simulation time 21262830946 ps
CPU time 26.67 seconds
Started Aug 07 05:54:37 PM PDT 24
Finished Aug 07 05:55:04 PM PDT 24
Peak memory 199704 kb
Host smart-a885d7cf-0c81-4452-8d2f-9172342f7866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299160162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1299160162
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.38725666
Short name T345
Test name
Test status
Simulation time 10910947 ps
CPU time 0.57 seconds
Started Aug 07 05:54:53 PM PDT 24
Finished Aug 07 05:54:53 PM PDT 24
Peak memory 195560 kb
Host smart-974d2b19-1bcb-43a9-9ec0-d68416e0cc5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38725666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.38725666
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.542743324
Short name T41
Test name
Test status
Simulation time 79996337363 ps
CPU time 39.6 seconds
Started Aug 07 05:54:45 PM PDT 24
Finished Aug 07 05:55:25 PM PDT 24
Peak memory 199912 kb
Host smart-28c35af7-ed78-4ef3-9516-945cbd32a038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542743324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.542743324
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1247326426
Short name T504
Test name
Test status
Simulation time 43683431891 ps
CPU time 61.77 seconds
Started Aug 07 05:54:46 PM PDT 24
Finished Aug 07 05:55:48 PM PDT 24
Peak memory 199468 kb
Host smart-ad70a911-3934-41a5-a1ff-cb5b1efc79d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247326426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1247326426
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_intr.528180168
Short name T578
Test name
Test status
Simulation time 222955838772 ps
CPU time 74.95 seconds
Started Aug 07 05:54:47 PM PDT 24
Finished Aug 07 05:56:02 PM PDT 24
Peak memory 197132 kb
Host smart-9f6e513b-7195-478b-a3ee-97beb981fdb7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528180168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.528180168
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.153081284
Short name T657
Test name
Test status
Simulation time 273700058169 ps
CPU time 146.6 seconds
Started Aug 07 05:54:45 PM PDT 24
Finished Aug 07 05:57:12 PM PDT 24
Peak memory 199784 kb
Host smart-4e9d326c-5ce5-4bd6-ae7a-f8b6424cdff5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=153081284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.153081284
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1656972939
Short name T1093
Test name
Test status
Simulation time 4223598194 ps
CPU time 3.92 seconds
Started Aug 07 05:54:45 PM PDT 24
Finished Aug 07 05:54:50 PM PDT 24
Peak memory 198764 kb
Host smart-e20cf724-7796-4439-a76f-8a9563982f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656972939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1656972939
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.596583085
Short name T253
Test name
Test status
Simulation time 78333197095 ps
CPU time 52.49 seconds
Started Aug 07 05:54:47 PM PDT 24
Finished Aug 07 05:55:40 PM PDT 24
Peak memory 199416 kb
Host smart-87c9e6bd-2af1-4dc3-a091-bdf9a5066dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596583085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.596583085
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2998030622
Short name T539
Test name
Test status
Simulation time 11236836298 ps
CPU time 282.02 seconds
Started Aug 07 05:54:46 PM PDT 24
Finished Aug 07 05:59:28 PM PDT 24
Peak memory 199888 kb
Host smart-5d8c940a-dce4-4761-989d-a8d8853dce30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2998030622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2998030622
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3249542331
Short name T609
Test name
Test status
Simulation time 1503340065 ps
CPU time 1.81 seconds
Started Aug 07 05:54:46 PM PDT 24
Finished Aug 07 05:54:48 PM PDT 24
Peak memory 197988 kb
Host smart-e4af662e-7a6a-40b1-a815-5ddb04a8cf9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3249542331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3249542331
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3271480280
Short name T347
Test name
Test status
Simulation time 45114429208 ps
CPU time 22.23 seconds
Started Aug 07 05:54:45 PM PDT 24
Finished Aug 07 05:55:08 PM PDT 24
Peak memory 199824 kb
Host smart-95ba155d-6f5a-41b9-80da-96ab7cc4617d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271480280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3271480280
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1950892258
Short name T812
Test name
Test status
Simulation time 2990734560 ps
CPU time 2.72 seconds
Started Aug 07 05:54:45 PM PDT 24
Finished Aug 07 05:54:48 PM PDT 24
Peak memory 196692 kb
Host smart-0017a151-effb-41a6-b982-4446ed9e0d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950892258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1950892258
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2304070625
Short name T334
Test name
Test status
Simulation time 718052593 ps
CPU time 1.8 seconds
Started Aug 07 05:54:47 PM PDT 24
Finished Aug 07 05:54:49 PM PDT 24
Peak memory 198628 kb
Host smart-277a2543-789e-4e81-a867-c40f575bfa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304070625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2304070625
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2087444494
Short name T1130
Test name
Test status
Simulation time 298056670647 ps
CPU time 842.49 seconds
Started Aug 07 05:54:48 PM PDT 24
Finished Aug 07 06:08:50 PM PDT 24
Peak memory 199936 kb
Host smart-696f0232-a04a-4bc4-a45b-f58363c0cb9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087444494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2087444494
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.2007170465
Short name T877
Test name
Test status
Simulation time 39811777408 ps
CPU time 194.83 seconds
Started Aug 07 05:54:46 PM PDT 24
Finished Aug 07 05:58:01 PM PDT 24
Peak memory 208264 kb
Host smart-b509b4c1-4e00-453a-940a-32888bf8c41d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007170465 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2007170465
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.524976790
Short name T495
Test name
Test status
Simulation time 1896021419 ps
CPU time 1.49 seconds
Started Aug 07 05:54:47 PM PDT 24
Finished Aug 07 05:54:49 PM PDT 24
Peak memory 196892 kb
Host smart-e7f00259-7707-4bab-b138-c1b0a2eff7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524976790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.524976790
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2912399974
Short name T808
Test name
Test status
Simulation time 87497474416 ps
CPU time 40 seconds
Started Aug 07 05:54:45 PM PDT 24
Finished Aug 07 05:55:25 PM PDT 24
Peak memory 199908 kb
Host smart-9b3ca09f-336b-4a0b-a8a8-926ed46e0554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912399974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2912399974
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3859576352
Short name T713
Test name
Test status
Simulation time 12907716 ps
CPU time 0.57 seconds
Started Aug 07 05:54:59 PM PDT 24
Finished Aug 07 05:55:00 PM PDT 24
Peak memory 195528 kb
Host smart-9250bb3c-d241-43a0-80df-cd822aee487b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859576352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3859576352
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3125063851
Short name T484
Test name
Test status
Simulation time 69136492958 ps
CPU time 24.75 seconds
Started Aug 07 05:54:53 PM PDT 24
Finished Aug 07 05:55:18 PM PDT 24
Peak memory 199856 kb
Host smart-78452909-3538-47f3-a9fa-32541e0b51fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125063851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3125063851
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2944300378
Short name T516
Test name
Test status
Simulation time 44120918841 ps
CPU time 26.65 seconds
Started Aug 07 05:54:51 PM PDT 24
Finished Aug 07 05:55:18 PM PDT 24
Peak memory 199896 kb
Host smart-b47e235a-4fc3-4085-a03e-8342b71c661f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944300378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2944300378
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2798424765
Short name T146
Test name
Test status
Simulation time 143110614414 ps
CPU time 59.01 seconds
Started Aug 07 05:54:54 PM PDT 24
Finished Aug 07 05:55:53 PM PDT 24
Peak memory 199824 kb
Host smart-5c5be9c8-a013-44db-b144-fe31ac4ec706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798424765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2798424765
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3337869877
Short name T642
Test name
Test status
Simulation time 54451960184 ps
CPU time 24.34 seconds
Started Aug 07 05:54:54 PM PDT 24
Finished Aug 07 05:55:18 PM PDT 24
Peak memory 199920 kb
Host smart-4d2a2748-2852-4990-b833-6547a3dce1e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337869877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3337869877
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_loopback.50794751
Short name T856
Test name
Test status
Simulation time 9766943089 ps
CPU time 8.66 seconds
Started Aug 07 05:54:57 PM PDT 24
Finished Aug 07 05:55:06 PM PDT 24
Peak memory 199664 kb
Host smart-cf43367a-0041-4866-b191-d41da2c9d429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50794751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.50794751
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1898356693
Short name T841
Test name
Test status
Simulation time 120657273467 ps
CPU time 165.65 seconds
Started Aug 07 05:54:54 PM PDT 24
Finished Aug 07 05:57:40 PM PDT 24
Peak memory 200040 kb
Host smart-9bb158ff-3e48-4505-8b6a-1a0c272eb661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898356693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1898356693
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.56301331
Short name T411
Test name
Test status
Simulation time 12905689936 ps
CPU time 732.67 seconds
Started Aug 07 05:54:53 PM PDT 24
Finished Aug 07 06:07:06 PM PDT 24
Peak memory 199828 kb
Host smart-10f0428e-6d3c-4dbe-85c4-cfd21b1dcc27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56301331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.56301331
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3125107376
Short name T1065
Test name
Test status
Simulation time 4937558252 ps
CPU time 11.91 seconds
Started Aug 07 05:54:57 PM PDT 24
Finished Aug 07 05:55:09 PM PDT 24
Peak memory 199352 kb
Host smart-bef3ff92-6aa0-4b33-9965-fc9b185eb66d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3125107376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3125107376
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.52553350
Short name T1144
Test name
Test status
Simulation time 31592917496 ps
CPU time 47.86 seconds
Started Aug 07 05:54:56 PM PDT 24
Finished Aug 07 05:55:44 PM PDT 24
Peak memory 199880 kb
Host smart-b2b6a81f-45d5-4112-8575-0f221bd44074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52553350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.52553350
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2885417446
Short name T1118
Test name
Test status
Simulation time 3505014362 ps
CPU time 6.14 seconds
Started Aug 07 05:54:55 PM PDT 24
Finished Aug 07 05:55:01 PM PDT 24
Peak memory 196472 kb
Host smart-c4f23b9d-5170-4437-b5c2-f303a1357ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885417446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2885417446
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.99478745
Short name T1153
Test name
Test status
Simulation time 11097248184 ps
CPU time 38.29 seconds
Started Aug 07 05:54:54 PM PDT 24
Finished Aug 07 05:55:32 PM PDT 24
Peak memory 199724 kb
Host smart-90fd6424-61dd-4b6f-a06b-28bb390e101f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99478745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.99478745
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.1785241629
Short name T800
Test name
Test status
Simulation time 19788190141 ps
CPU time 31.42 seconds
Started Aug 07 05:55:00 PM PDT 24
Finished Aug 07 05:55:31 PM PDT 24
Peak memory 199972 kb
Host smart-4219ff5f-177a-45db-a942-925692eaa413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785241629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1785241629
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.772198063
Short name T52
Test name
Test status
Simulation time 179358424915 ps
CPU time 1256.73 seconds
Started Aug 07 05:54:59 PM PDT 24
Finished Aug 07 06:15:56 PM PDT 24
Peak memory 216412 kb
Host smart-a669e4fb-987a-41e7-8e2b-bd43c1744a02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772198063 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.772198063
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.756399573
Short name T1067
Test name
Test status
Simulation time 1063073361 ps
CPU time 3.37 seconds
Started Aug 07 05:54:55 PM PDT 24
Finished Aug 07 05:54:58 PM PDT 24
Peak memory 198776 kb
Host smart-bfa870fc-7bf7-43a6-9df6-313685619413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756399573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.756399573
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3395368524
Short name T259
Test name
Test status
Simulation time 98234468156 ps
CPU time 43.42 seconds
Started Aug 07 05:54:54 PM PDT 24
Finished Aug 07 05:55:37 PM PDT 24
Peak memory 199780 kb
Host smart-08505dff-07d3-4ca7-9102-b12cd872b23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395368524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3395368524
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2483261284
Short name T901
Test name
Test status
Simulation time 11338419 ps
CPU time 0.55 seconds
Started Aug 07 05:55:08 PM PDT 24
Finished Aug 07 05:55:08 PM PDT 24
Peak memory 195344 kb
Host smart-60631753-7f7e-432f-9f49-bb12cd0128af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483261284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2483261284
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2980144521
Short name T899
Test name
Test status
Simulation time 35717327004 ps
CPU time 60.2 seconds
Started Aug 07 05:55:08 PM PDT 24
Finished Aug 07 05:56:08 PM PDT 24
Peak memory 199880 kb
Host smart-2c90a79e-c397-4918-9b15-ce67c927e22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980144521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2980144521
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3862319263
Short name T445
Test name
Test status
Simulation time 13029314404 ps
CPU time 6.67 seconds
Started Aug 07 05:54:59 PM PDT 24
Finished Aug 07 05:55:06 PM PDT 24
Peak memory 199916 kb
Host smart-e71610d7-32ed-40d3-8c9d-cb4bb3a8eadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862319263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3862319263
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1402906353
Short name T1108
Test name
Test status
Simulation time 5492798495 ps
CPU time 9.47 seconds
Started Aug 07 05:55:14 PM PDT 24
Finished Aug 07 05:55:23 PM PDT 24
Peak memory 199528 kb
Host smart-b5b0b475-710d-4f68-b423-c85005679342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402906353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1402906353
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.89062223
Short name T683
Test name
Test status
Simulation time 12790903815 ps
CPU time 3.32 seconds
Started Aug 07 05:54:59 PM PDT 24
Finished Aug 07 05:55:03 PM PDT 24
Peak memory 197792 kb
Host smart-72730f0a-cbc3-4824-885c-c12aa591a357
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89062223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.89062223
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.836570758
Short name T631
Test name
Test status
Simulation time 68341015645 ps
CPU time 378.12 seconds
Started Aug 07 05:55:00 PM PDT 24
Finished Aug 07 06:01:18 PM PDT 24
Peak memory 199912 kb
Host smart-b7ea8d9a-772f-4b91-b0cb-5b869e141f0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=836570758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.836570758
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.1030484832
Short name T750
Test name
Test status
Simulation time 6865071699 ps
CPU time 10.18 seconds
Started Aug 07 05:54:59 PM PDT 24
Finished Aug 07 05:55:09 PM PDT 24
Peak memory 198420 kb
Host smart-0cea13ee-92ce-465d-8fb6-7b4cbc20c384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030484832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1030484832
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.2095093274
Short name T42
Test name
Test status
Simulation time 91785457754 ps
CPU time 50.25 seconds
Started Aug 07 05:54:57 PM PDT 24
Finished Aug 07 05:55:48 PM PDT 24
Peak memory 199928 kb
Host smart-9b099ff9-b80c-4223-af42-4611ed54f5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095093274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2095093274
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.4056536677
Short name T828
Test name
Test status
Simulation time 1577335973 ps
CPU time 62.65 seconds
Started Aug 07 05:54:59 PM PDT 24
Finished Aug 07 05:56:02 PM PDT 24
Peak memory 199884 kb
Host smart-04f94cf2-5975-4811-8d36-c3674acff8d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056536677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.4056536677
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3836667597
Short name T488
Test name
Test status
Simulation time 4413530956 ps
CPU time 9.64 seconds
Started Aug 07 05:55:01 PM PDT 24
Finished Aug 07 05:55:11 PM PDT 24
Peak memory 198712 kb
Host smart-ce3fc8da-6b83-4842-a13d-4f85ee1fcdcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3836667597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3836667597
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2315594485
Short name T436
Test name
Test status
Simulation time 135920018593 ps
CPU time 230.53 seconds
Started Aug 07 05:55:09 PM PDT 24
Finished Aug 07 05:59:00 PM PDT 24
Peak memory 199948 kb
Host smart-23068bb9-2bdb-41f1-9707-9363789f5502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315594485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2315594485
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3144986271
Short name T646
Test name
Test status
Simulation time 5984165714 ps
CPU time 2.64 seconds
Started Aug 07 05:55:01 PM PDT 24
Finished Aug 07 05:55:04 PM PDT 24
Peak memory 196084 kb
Host smart-d236f999-4d03-4210-9257-01cac8feead9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144986271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3144986271
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3690575927
Short name T348
Test name
Test status
Simulation time 503335615 ps
CPU time 1.19 seconds
Started Aug 07 05:54:59 PM PDT 24
Finished Aug 07 05:55:00 PM PDT 24
Peak memory 198420 kb
Host smart-30f30b49-9a9b-45c2-8fbc-44b0a2704aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690575927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3690575927
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.889331925
Short name T915
Test name
Test status
Simulation time 72100972030 ps
CPU time 212.09 seconds
Started Aug 07 05:54:58 PM PDT 24
Finished Aug 07 05:58:30 PM PDT 24
Peak memory 199996 kb
Host smart-e4ca1454-1654-494d-91ee-5622d8bd99fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889331925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.889331925
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.262578242
Short name T1058
Test name
Test status
Simulation time 60267488193 ps
CPU time 1671.66 seconds
Started Aug 07 05:54:59 PM PDT 24
Finished Aug 07 06:22:51 PM PDT 24
Peak memory 216388 kb
Host smart-9972e458-c2b9-4ce3-b65b-204ae3f0ae78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262578242 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.262578242
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3335779140
Short name T721
Test name
Test status
Simulation time 12878016099 ps
CPU time 36.01 seconds
Started Aug 07 05:54:59 PM PDT 24
Finished Aug 07 05:55:35 PM PDT 24
Peak memory 199812 kb
Host smart-1a62f199-1243-4694-9363-110b9fec0666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335779140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3335779140
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3440528889
Short name T762
Test name
Test status
Simulation time 15881809893 ps
CPU time 35.41 seconds
Started Aug 07 05:55:14 PM PDT 24
Finished Aug 07 05:55:49 PM PDT 24
Peak memory 199928 kb
Host smart-d6ba77df-8b68-445a-8c0a-a6f9aabb7177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440528889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3440528889
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3940975415
Short name T678
Test name
Test status
Simulation time 79723156 ps
CPU time 0.54 seconds
Started Aug 07 05:55:05 PM PDT 24
Finished Aug 07 05:55:06 PM PDT 24
Peak memory 195268 kb
Host smart-44d80d7f-beb5-40df-88b6-ef2e8bab6496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940975415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3940975415
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.526330050
Short name T989
Test name
Test status
Simulation time 17961229649 ps
CPU time 14.91 seconds
Started Aug 07 05:55:09 PM PDT 24
Finished Aug 07 05:55:24 PM PDT 24
Peak memory 199924 kb
Host smart-acfc7aa2-79d9-4a2f-8dda-adf2802d4ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526330050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.526330050
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3236047704
Short name T107
Test name
Test status
Simulation time 231029404223 ps
CPU time 76.61 seconds
Started Aug 07 05:55:14 PM PDT 24
Finished Aug 07 05:56:30 PM PDT 24
Peak memory 199972 kb
Host smart-79cde5a0-a96f-43b8-bd82-cc06d5c9be9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236047704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3236047704
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.455630566
Short name T297
Test name
Test status
Simulation time 40560304348 ps
CPU time 19.16 seconds
Started Aug 07 05:55:14 PM PDT 24
Finished Aug 07 05:55:33 PM PDT 24
Peak memory 199948 kb
Host smart-5b005c57-f1ab-45b2-80b0-7f12de59d4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455630566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.455630566
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1872820668
Short name T355
Test name
Test status
Simulation time 8548576172 ps
CPU time 13.7 seconds
Started Aug 07 05:55:06 PM PDT 24
Finished Aug 07 05:55:20 PM PDT 24
Peak memory 199844 kb
Host smart-bf1046ae-3cb9-474b-9da4-8cb4cb1c56ee
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872820668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1872820668
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.731189489
Short name T1045
Test name
Test status
Simulation time 98523521014 ps
CPU time 809.33 seconds
Started Aug 07 05:55:07 PM PDT 24
Finished Aug 07 06:08:37 PM PDT 24
Peak memory 199880 kb
Host smart-8b8cc1a9-86e5-4cb0-b7a7-1ec877e762b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=731189489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.731189489
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2086178412
Short name T1173
Test name
Test status
Simulation time 9327956065 ps
CPU time 3.31 seconds
Started Aug 07 05:55:07 PM PDT 24
Finished Aug 07 05:55:10 PM PDT 24
Peak memory 199908 kb
Host smart-1adf0af5-28d6-4f26-8d52-f72c5bf76fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086178412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2086178412
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.464088423
Short name T680
Test name
Test status
Simulation time 35359782085 ps
CPU time 56.32 seconds
Started Aug 07 05:55:05 PM PDT 24
Finished Aug 07 05:56:01 PM PDT 24
Peak memory 200032 kb
Host smart-4d35c962-9e4e-4244-ae3f-7d350b941927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464088423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.464088423
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1227651437
Short name T1156
Test name
Test status
Simulation time 4450374927 ps
CPU time 62.8 seconds
Started Aug 07 05:55:06 PM PDT 24
Finished Aug 07 05:56:09 PM PDT 24
Peak memory 199820 kb
Host smart-c0712994-c0ae-46b8-895b-7fba4dce519e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1227651437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1227651437
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.4073057306
Short name T549
Test name
Test status
Simulation time 3619783554 ps
CPU time 5.96 seconds
Started Aug 07 05:55:06 PM PDT 24
Finished Aug 07 05:55:12 PM PDT 24
Peak memory 198532 kb
Host smart-dcbb1199-7744-43a0-9ad3-ebe20a309f20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4073057306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.4073057306
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.398662032
Short name T957
Test name
Test status
Simulation time 155783830720 ps
CPU time 64.12 seconds
Started Aug 07 05:55:07 PM PDT 24
Finished Aug 07 05:56:11 PM PDT 24
Peak memory 199732 kb
Host smart-b174a73f-01e9-4ee1-b13f-87f1a479c9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398662032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.398662032
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1692023349
Short name T415
Test name
Test status
Simulation time 3282917939 ps
CPU time 1.82 seconds
Started Aug 07 05:55:06 PM PDT 24
Finished Aug 07 05:55:07 PM PDT 24
Peak memory 196424 kb
Host smart-b77a1b99-0220-4191-9451-3921b2e32c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692023349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1692023349
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2026968839
Short name T764
Test name
Test status
Simulation time 265628710 ps
CPU time 1.77 seconds
Started Aug 07 05:54:59 PM PDT 24
Finished Aug 07 05:55:01 PM PDT 24
Peak memory 198340 kb
Host smart-3fb1c8cd-7042-42b0-90bb-d5aa69432c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026968839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2026968839
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.262486408
Short name T919
Test name
Test status
Simulation time 294696400764 ps
CPU time 145.49 seconds
Started Aug 07 05:55:06 PM PDT 24
Finished Aug 07 05:57:31 PM PDT 24
Peak memory 200048 kb
Host smart-3fb269cf-3b0b-49d4-9420-d5578eb5b4fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262486408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.262486408
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1807554829
Short name T59
Test name
Test status
Simulation time 176868346127 ps
CPU time 476.64 seconds
Started Aug 07 05:55:08 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 216420 kb
Host smart-8d07f755-f591-40d9-9ca7-cf79943c39d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807554829 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1807554829
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.246684390
Short name T731
Test name
Test status
Simulation time 6708540013 ps
CPU time 26.67 seconds
Started Aug 07 05:55:05 PM PDT 24
Finished Aug 07 05:55:32 PM PDT 24
Peak memory 199652 kb
Host smart-60ac79af-9c0f-4c0c-ac1e-ad2daa0aa095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246684390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.246684390
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2748095110
Short name T603
Test name
Test status
Simulation time 3417846032 ps
CPU time 5.39 seconds
Started Aug 07 05:55:00 PM PDT 24
Finished Aug 07 05:55:05 PM PDT 24
Peak memory 196648 kb
Host smart-b0ea3eb6-47db-4e0d-833b-9ce6855dbfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748095110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2748095110
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.441567578
Short name T594
Test name
Test status
Simulation time 51410350 ps
CPU time 0.54 seconds
Started Aug 07 05:55:12 PM PDT 24
Finished Aug 07 05:55:12 PM PDT 24
Peak memory 195308 kb
Host smart-55cdd94d-9ac4-47a6-b75c-5040cfb9b220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441567578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.441567578
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.819335716
Short name T1097
Test name
Test status
Simulation time 117093819422 ps
CPU time 138.54 seconds
Started Aug 07 05:55:12 PM PDT 24
Finished Aug 07 05:57:31 PM PDT 24
Peak memory 199824 kb
Host smart-488b2240-7d0e-4227-a30b-4da5cd7a9a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819335716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.819335716
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.4220596690
Short name T5
Test name
Test status
Simulation time 88937170589 ps
CPU time 40.4 seconds
Started Aug 07 05:55:13 PM PDT 24
Finished Aug 07 05:55:53 PM PDT 24
Peak memory 199744 kb
Host smart-3ab9e228-22d6-41c4-b78e-6d7a58096be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220596690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.4220596690
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1247477354
Short name T212
Test name
Test status
Simulation time 74537185170 ps
CPU time 64.17 seconds
Started Aug 07 05:55:12 PM PDT 24
Finished Aug 07 05:56:17 PM PDT 24
Peak memory 199856 kb
Host smart-a5d3e5cc-0c04-427c-8387-3c4c7bbc028c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247477354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1247477354
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.801380383
Short name T799
Test name
Test status
Simulation time 36614553392 ps
CPU time 26.69 seconds
Started Aug 07 05:55:11 PM PDT 24
Finished Aug 07 05:55:38 PM PDT 24
Peak memory 199908 kb
Host smart-8599272e-2a58-467a-a08d-a5d77486a438
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801380383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.801380383
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3590718965
Short name T1141
Test name
Test status
Simulation time 73984077723 ps
CPU time 201.73 seconds
Started Aug 07 05:55:15 PM PDT 24
Finished Aug 07 05:58:37 PM PDT 24
Peak memory 199860 kb
Host smart-83f93b7c-36bd-40c8-b40e-298fd27a75f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3590718965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3590718965
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.249561189
Short name T1088
Test name
Test status
Simulation time 7055667537 ps
CPU time 8.67 seconds
Started Aug 07 05:55:13 PM PDT 24
Finished Aug 07 05:55:22 PM PDT 24
Peak memory 199048 kb
Host smart-a2b5a720-4e13-4cb5-b8a2-1ca024789199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249561189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.249561189
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1625171910
Short name T1062
Test name
Test status
Simulation time 71476447392 ps
CPU time 64.66 seconds
Started Aug 07 05:55:11 PM PDT 24
Finished Aug 07 05:56:16 PM PDT 24
Peak memory 198940 kb
Host smart-22de81ff-a5dc-4b2a-a38f-e0e7e47f148f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625171910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1625171910
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2010798091
Short name T507
Test name
Test status
Simulation time 3382036172 ps
CPU time 43.9 seconds
Started Aug 07 05:55:13 PM PDT 24
Finished Aug 07 05:55:57 PM PDT 24
Peak memory 199948 kb
Host smart-0a95c4f9-ae20-457c-a514-8884a6ad5226
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2010798091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2010798091
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2073288168
Short name T392
Test name
Test status
Simulation time 5370199444 ps
CPU time 4.18 seconds
Started Aug 07 05:55:12 PM PDT 24
Finished Aug 07 05:55:16 PM PDT 24
Peak memory 198964 kb
Host smart-ab7b234a-1b39-4017-b860-8c6584fd995d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2073288168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2073288168
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2513140290
Short name T938
Test name
Test status
Simulation time 99650600221 ps
CPU time 39.9 seconds
Started Aug 07 05:55:14 PM PDT 24
Finished Aug 07 05:55:54 PM PDT 24
Peak memory 199816 kb
Host smart-920d3ec3-4a82-4228-b024-12ec71dcfa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513140290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2513140290
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.414536617
Short name T303
Test name
Test status
Simulation time 33419270978 ps
CPU time 55.56 seconds
Started Aug 07 05:55:13 PM PDT 24
Finished Aug 07 05:56:09 PM PDT 24
Peak memory 196240 kb
Host smart-6f898b21-801e-4955-9800-e27ff618a461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414536617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.414536617
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3626984229
Short name T716
Test name
Test status
Simulation time 932761401 ps
CPU time 3.01 seconds
Started Aug 07 05:55:13 PM PDT 24
Finished Aug 07 05:55:16 PM PDT 24
Peak memory 199324 kb
Host smart-ba2fa654-7780-4bef-921a-68bf5f3b50f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626984229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3626984229
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.512631894
Short name T1106
Test name
Test status
Simulation time 339452750893 ps
CPU time 446.63 seconds
Started Aug 07 05:55:12 PM PDT 24
Finished Aug 07 06:02:38 PM PDT 24
Peak memory 199900 kb
Host smart-af6a941a-5d50-4d2d-a7d3-d3bc25903f2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512631894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.512631894
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3712771661
Short name T38
Test name
Test status
Simulation time 57375479148 ps
CPU time 151.67 seconds
Started Aug 07 05:55:14 PM PDT 24
Finished Aug 07 05:57:45 PM PDT 24
Peak memory 216404 kb
Host smart-9a634bd5-6853-4a61-8ac9-b605eaedf3d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712771661 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3712771661
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.4117242136
Short name T907
Test name
Test status
Simulation time 900639889 ps
CPU time 2.3 seconds
Started Aug 07 05:55:13 PM PDT 24
Finished Aug 07 05:55:15 PM PDT 24
Peak memory 199440 kb
Host smart-59081182-9a03-4a61-9707-a31d7ab26a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117242136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.4117242136
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1056949117
Short name T584
Test name
Test status
Simulation time 5836180844 ps
CPU time 8.75 seconds
Started Aug 07 05:55:13 PM PDT 24
Finished Aug 07 05:55:22 PM PDT 24
Peak memory 197192 kb
Host smart-05fb79d1-ce8b-4a5b-90b8-79f2736aebd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056949117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1056949117
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.474141149
Short name T694
Test name
Test status
Simulation time 40530115 ps
CPU time 0.55 seconds
Started Aug 07 05:55:26 PM PDT 24
Finished Aug 07 05:55:27 PM PDT 24
Peak memory 195580 kb
Host smart-04665e6b-1508-42e5-b9a0-8cf5fccaa68b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474141149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.474141149
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.469000407
Short name T552
Test name
Test status
Simulation time 19040112482 ps
CPU time 29.47 seconds
Started Aug 07 05:55:18 PM PDT 24
Finished Aug 07 05:55:48 PM PDT 24
Peak memory 199856 kb
Host smart-3321470c-80cd-42e4-8b37-a53577ae9a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469000407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.469000407
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.4056180601
Short name T875
Test name
Test status
Simulation time 133785100716 ps
CPU time 186.82 seconds
Started Aug 07 05:55:16 PM PDT 24
Finished Aug 07 05:58:23 PM PDT 24
Peak memory 199808 kb
Host smart-aa9e8083-294d-4f87-8943-6e40e79a2b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056180601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.4056180601
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.426910774
Short name T96
Test name
Test status
Simulation time 15242864861 ps
CPU time 20.72 seconds
Started Aug 07 05:55:17 PM PDT 24
Finished Aug 07 05:55:38 PM PDT 24
Peak memory 199776 kb
Host smart-83856ea0-2f77-4234-898e-ca266720fcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426910774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.426910774
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3890898996
Short name T951
Test name
Test status
Simulation time 3978467692 ps
CPU time 9.19 seconds
Started Aug 07 05:55:19 PM PDT 24
Finished Aug 07 05:55:28 PM PDT 24
Peak memory 199828 kb
Host smart-5352b24c-0cb5-4051-8c94-2c405ef53e13
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890898996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3890898996
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3608212652
Short name T1013
Test name
Test status
Simulation time 76882001327 ps
CPU time 257.15 seconds
Started Aug 07 05:55:25 PM PDT 24
Finished Aug 07 05:59:42 PM PDT 24
Peak memory 199860 kb
Host smart-965de669-7190-4b31-aa3d-ec4fe453fd95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3608212652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3608212652
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2199951510
Short name T1051
Test name
Test status
Simulation time 2344815720 ps
CPU time 4.22 seconds
Started Aug 07 05:55:25 PM PDT 24
Finished Aug 07 05:55:29 PM PDT 24
Peak memory 198944 kb
Host smart-e4ba32e5-2c5f-4bf4-90c4-463d45d5ce33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199951510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2199951510
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1938285701
Short name T563
Test name
Test status
Simulation time 143587839745 ps
CPU time 56.53 seconds
Started Aug 07 05:55:19 PM PDT 24
Finished Aug 07 05:56:15 PM PDT 24
Peak memory 199508 kb
Host smart-4ad251c6-51d9-46e6-b74c-c8eb897a9ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938285701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1938285701
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1829960797
Short name T421
Test name
Test status
Simulation time 8291850073 ps
CPU time 105.19 seconds
Started Aug 07 05:55:26 PM PDT 24
Finished Aug 07 05:57:11 PM PDT 24
Peak memory 199912 kb
Host smart-343718e9-24f7-4987-92c9-0587ffe37d9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1829960797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1829960797
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1876145544
Short name T913
Test name
Test status
Simulation time 2689227189 ps
CPU time 2.23 seconds
Started Aug 07 05:55:17 PM PDT 24
Finished Aug 07 05:55:20 PM PDT 24
Peak memory 198172 kb
Host smart-6c42f238-bed8-4c9e-9abf-08e0f893f4c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1876145544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1876145544
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3743470852
Short name T161
Test name
Test status
Simulation time 89743825987 ps
CPU time 356.04 seconds
Started Aug 07 05:55:17 PM PDT 24
Finished Aug 07 06:01:13 PM PDT 24
Peak memory 199880 kb
Host smart-6a35f03c-8e01-47af-8d42-048e3e2c31aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743470852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3743470852
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.133999915
Short name T966
Test name
Test status
Simulation time 2904009134 ps
CPU time 5.05 seconds
Started Aug 07 05:55:18 PM PDT 24
Finished Aug 07 05:55:23 PM PDT 24
Peak memory 195988 kb
Host smart-6eebc789-6a37-415c-8911-620447e97fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133999915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.133999915
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.100069597
Short name T369
Test name
Test status
Simulation time 650950016 ps
CPU time 3.86 seconds
Started Aug 07 05:55:18 PM PDT 24
Finished Aug 07 05:55:22 PM PDT 24
Peak memory 198780 kb
Host smart-5e4200ca-19ac-43dc-ad46-234954a17fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100069597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.100069597
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.56139857
Short name T616
Test name
Test status
Simulation time 182807905758 ps
CPU time 250.05 seconds
Started Aug 07 05:55:26 PM PDT 24
Finished Aug 07 05:59:36 PM PDT 24
Peak memory 208276 kb
Host smart-41ad92dc-dc66-4c0e-b2f5-721967738612
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56139857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.56139857
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.3219195161
Short name T173
Test name
Test status
Simulation time 236147827567 ps
CPU time 886.83 seconds
Started Aug 07 05:55:25 PM PDT 24
Finished Aug 07 06:10:12 PM PDT 24
Peak memory 216620 kb
Host smart-f3203bc4-b2bc-4c0e-8200-7b85978e1bb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219195161 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.3219195161
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2860694827
Short name T766
Test name
Test status
Simulation time 885943441 ps
CPU time 2.42 seconds
Started Aug 07 05:55:25 PM PDT 24
Finished Aug 07 05:55:28 PM PDT 24
Peak memory 198720 kb
Host smart-4310dc5b-f3b1-406c-b491-8b2d17c5d841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860694827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2860694827
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.752168985
Short name T860
Test name
Test status
Simulation time 33323943494 ps
CPU time 18.07 seconds
Started Aug 07 05:55:18 PM PDT 24
Finished Aug 07 05:55:36 PM PDT 24
Peak memory 199896 kb
Host smart-b12d8dc0-9608-4053-a355-197105b4aa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752168985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.752168985
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2801883711
Short name T1082
Test name
Test status
Simulation time 12121756 ps
CPU time 0.54 seconds
Started Aug 07 05:51:17 PM PDT 24
Finished Aug 07 05:51:17 PM PDT 24
Peak memory 195560 kb
Host smart-bbebddea-99aa-46fe-a868-2508f57f88ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801883711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2801883711
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2758020489
Short name T846
Test name
Test status
Simulation time 144225497292 ps
CPU time 64.84 seconds
Started Aug 07 05:51:20 PM PDT 24
Finished Aug 07 05:52:25 PM PDT 24
Peak memory 199856 kb
Host smart-d0a5c1a7-67ae-4588-8678-093f0836ead5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758020489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2758020489
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2674532026
Short name T879
Test name
Test status
Simulation time 86264901293 ps
CPU time 32.69 seconds
Started Aug 07 05:51:16 PM PDT 24
Finished Aug 07 05:51:49 PM PDT 24
Peak memory 199772 kb
Host smart-a5e2740d-77ee-4961-9c68-bb6cf732d6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674532026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2674532026
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.41115054
Short name T3
Test name
Test status
Simulation time 21158426363 ps
CPU time 31.74 seconds
Started Aug 07 05:51:16 PM PDT 24
Finished Aug 07 05:51:48 PM PDT 24
Peak memory 199672 kb
Host smart-30b738a0-3178-4bf0-ba35-48f33a746f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41115054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.41115054
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.494653834
Short name T1000
Test name
Test status
Simulation time 131089960416 ps
CPU time 244.66 seconds
Started Aug 07 05:51:18 PM PDT 24
Finished Aug 07 05:55:23 PM PDT 24
Peak memory 199872 kb
Host smart-b2da7da7-6b0d-4f42-b312-f6f8f61e63d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=494653834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.494653834
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3838761631
Short name T1071
Test name
Test status
Simulation time 14500411683 ps
CPU time 21.09 seconds
Started Aug 07 05:51:15 PM PDT 24
Finished Aug 07 05:51:36 PM PDT 24
Peak memory 199876 kb
Host smart-660313b4-862c-48e7-81c3-06a388669ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838761631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3838761631
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.574803587
Short name T758
Test name
Test status
Simulation time 135286698251 ps
CPU time 131.63 seconds
Started Aug 07 05:51:16 PM PDT 24
Finished Aug 07 05:53:28 PM PDT 24
Peak memory 199840 kb
Host smart-fb5da396-fca5-43f9-9c95-a05cfae8b25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574803587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.574803587
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.598513705
Short name T543
Test name
Test status
Simulation time 7039183269 ps
CPU time 79.83 seconds
Started Aug 07 05:51:18 PM PDT 24
Finished Aug 07 05:52:38 PM PDT 24
Peak memory 199812 kb
Host smart-0ac931e7-14b7-4eb8-a97c-53b210e60707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=598513705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.598513705
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3510775510
Short name T685
Test name
Test status
Simulation time 2546188704 ps
CPU time 3.43 seconds
Started Aug 07 05:51:20 PM PDT 24
Finished Aug 07 05:51:24 PM PDT 24
Peak memory 199136 kb
Host smart-3f8eddd6-435c-485f-97f3-8637fca23de4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3510775510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3510775510
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.84643242
Short name T558
Test name
Test status
Simulation time 277741629382 ps
CPU time 95.36 seconds
Started Aug 07 05:51:17 PM PDT 24
Finished Aug 07 05:52:53 PM PDT 24
Peak memory 199772 kb
Host smart-95b6b4ea-e666-4716-978e-7b7aa9e133e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84643242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.84643242
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3008558785
Short name T1127
Test name
Test status
Simulation time 30450209360 ps
CPU time 50.81 seconds
Started Aug 07 05:51:20 PM PDT 24
Finished Aug 07 05:52:11 PM PDT 24
Peak memory 196308 kb
Host smart-6a6e062d-4322-46b1-ab48-e74af61fb56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008558785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3008558785
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2513193842
Short name T1001
Test name
Test status
Simulation time 544861681 ps
CPU time 4.97 seconds
Started Aug 07 05:51:13 PM PDT 24
Finished Aug 07 05:51:18 PM PDT 24
Peak memory 199520 kb
Host smart-402a3cd6-2219-4cc3-9c4c-f7567a2bda65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513193842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2513193842
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.212225964
Short name T505
Test name
Test status
Simulation time 16845342931 ps
CPU time 12.8 seconds
Started Aug 07 05:51:18 PM PDT 24
Finished Aug 07 05:51:30 PM PDT 24
Peak memory 199848 kb
Host smart-69bb8311-9136-4c92-aa4d-85a82f6f2768
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212225964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.212225964
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2699499359
Short name T1161
Test name
Test status
Simulation time 15126045471 ps
CPU time 204.59 seconds
Started Aug 07 05:51:20 PM PDT 24
Finished Aug 07 05:54:44 PM PDT 24
Peak memory 208172 kb
Host smart-2ce5bea2-e244-4073-8dea-aa18df3f871c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699499359 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2699499359
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1422413668
Short name T273
Test name
Test status
Simulation time 683554862 ps
CPU time 1.78 seconds
Started Aug 07 05:51:17 PM PDT 24
Finished Aug 07 05:51:19 PM PDT 24
Peak memory 199828 kb
Host smart-8c6ac699-e0bd-4284-b443-d7cbfc20aa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422413668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1422413668
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.4198709700
Short name T759
Test name
Test status
Simulation time 51178066257 ps
CPU time 79.21 seconds
Started Aug 07 05:51:14 PM PDT 24
Finished Aug 07 05:52:33 PM PDT 24
Peak memory 199816 kb
Host smart-038015c6-1334-4534-b3a5-c3454c981cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198709700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.4198709700
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.4191552461
Short name T624
Test name
Test status
Simulation time 30985635046 ps
CPU time 29.52 seconds
Started Aug 07 05:55:26 PM PDT 24
Finished Aug 07 05:55:56 PM PDT 24
Peak memory 199932 kb
Host smart-d6b72dd2-9f27-4917-a0b0-2922d7af526b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191552461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.4191552461
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.4143509027
Short name T918
Test name
Test status
Simulation time 180319321626 ps
CPU time 99.82 seconds
Started Aug 07 05:55:25 PM PDT 24
Finished Aug 07 05:57:05 PM PDT 24
Peak memory 199916 kb
Host smart-0039e4f7-6992-4fdd-a665-e1bf0cc42207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143509027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.4143509027
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3051153526
Short name T948
Test name
Test status
Simulation time 202442358896 ps
CPU time 917.58 seconds
Started Aug 07 05:55:27 PM PDT 24
Finished Aug 07 06:10:44 PM PDT 24
Peak memory 226916 kb
Host smart-15050511-f5ee-42db-9758-1eb49afa9252
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051153526 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3051153526
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3211257114
Short name T420
Test name
Test status
Simulation time 17986119126 ps
CPU time 31.73 seconds
Started Aug 07 05:55:26 PM PDT 24
Finished Aug 07 05:55:58 PM PDT 24
Peak memory 199916 kb
Host smart-35118aa9-9d74-409f-92a2-38183cc9670a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211257114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3211257114
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3399058812
Short name T581
Test name
Test status
Simulation time 16949748733 ps
CPU time 213.42 seconds
Started Aug 07 05:55:25 PM PDT 24
Finished Aug 07 05:58:58 PM PDT 24
Peak memory 216500 kb
Host smart-cbfe4ce4-2dd0-46e2-8c86-092fc1a74fce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399058812 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3399058812
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.2610237811
Short name T149
Test name
Test status
Simulation time 45963521236 ps
CPU time 63.74 seconds
Started Aug 07 05:55:25 PM PDT 24
Finished Aug 07 05:56:29 PM PDT 24
Peak memory 199908 kb
Host smart-32039d0b-509f-4937-9b1c-f16b1084a3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610237811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2610237811
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3329537676
Short name T523
Test name
Test status
Simulation time 121939892165 ps
CPU time 324.58 seconds
Started Aug 07 05:55:25 PM PDT 24
Finished Aug 07 06:00:50 PM PDT 24
Peak memory 215900 kb
Host smart-705aa905-3bff-4c5a-970d-c65d1f26139c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329537676 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3329537676
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1421179675
Short name T305
Test name
Test status
Simulation time 50720429956 ps
CPU time 514.09 seconds
Started Aug 07 05:55:31 PM PDT 24
Finished Aug 07 06:04:05 PM PDT 24
Peak memory 216120 kb
Host smart-8e19c98d-7982-49a5-8514-fd2dfe8cc92a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421179675 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1421179675
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3299506036
Short name T816
Test name
Test status
Simulation time 15177205736 ps
CPU time 17.76 seconds
Started Aug 07 05:55:32 PM PDT 24
Finished Aug 07 05:55:50 PM PDT 24
Peak memory 199772 kb
Host smart-68f01131-1fd9-4eb3-92c2-94307965cc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299506036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3299506036
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3873604621
Short name T307
Test name
Test status
Simulation time 91948815327 ps
CPU time 1414.09 seconds
Started Aug 07 05:55:31 PM PDT 24
Finished Aug 07 06:19:05 PM PDT 24
Peak memory 232868 kb
Host smart-afc3b1e4-b165-41b4-8cee-a5f5c8bf7606
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873604621 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3873604621
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3133986051
Short name T456
Test name
Test status
Simulation time 24468321972 ps
CPU time 78.95 seconds
Started Aug 07 05:55:31 PM PDT 24
Finished Aug 07 05:56:50 PM PDT 24
Peak memory 199912 kb
Host smart-d9b7acfe-c0e5-4703-b297-32b3a9ca1e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133986051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3133986051
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3859672475
Short name T268
Test name
Test status
Simulation time 154867110404 ps
CPU time 509.42 seconds
Started Aug 07 05:55:32 PM PDT 24
Finished Aug 07 06:04:02 PM PDT 24
Peak memory 216364 kb
Host smart-0bfb96d7-4897-465d-801d-1249bfebe470
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859672475 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3859672475
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.1172341910
Short name T231
Test name
Test status
Simulation time 151973073856 ps
CPU time 77.19 seconds
Started Aug 07 05:55:34 PM PDT 24
Finished Aug 07 05:56:51 PM PDT 24
Peak memory 199520 kb
Host smart-911e4a67-93f2-4eeb-9729-af2017c8131d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172341910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1172341910
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1032209413
Short name T587
Test name
Test status
Simulation time 52964398101 ps
CPU time 1609.53 seconds
Started Aug 07 05:55:31 PM PDT 24
Finished Aug 07 06:22:21 PM PDT 24
Peak memory 215420 kb
Host smart-61e859aa-e600-4177-811f-23dcfa053da6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032209413 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1032209413
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3204805738
Short name T622
Test name
Test status
Simulation time 101688878586 ps
CPU time 153.62 seconds
Started Aug 07 05:55:31 PM PDT 24
Finished Aug 07 05:58:05 PM PDT 24
Peak memory 199956 kb
Host smart-3d3d8303-cea0-440c-abea-b390f9ac9957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204805738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3204805738
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3883797303
Short name T995
Test name
Test status
Simulation time 24413382408 ps
CPU time 316.64 seconds
Started Aug 07 05:55:33 PM PDT 24
Finished Aug 07 06:00:50 PM PDT 24
Peak memory 216292 kb
Host smart-684f2058-b49a-44dc-957e-c9e4a88dcfaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883797303 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3883797303
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1907113155
Short name T312
Test name
Test status
Simulation time 29935182282 ps
CPU time 56.93 seconds
Started Aug 07 05:55:39 PM PDT 24
Finished Aug 07 05:56:36 PM PDT 24
Peak memory 199932 kb
Host smart-7a050f9e-e897-4569-b31f-bf23dbe6d930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907113155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1907113155
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1998693253
Short name T1129
Test name
Test status
Simulation time 54623100750 ps
CPU time 505.3 seconds
Started Aug 07 05:55:37 PM PDT 24
Finished Aug 07 06:04:03 PM PDT 24
Peak memory 216424 kb
Host smart-117e09de-0c9e-4669-a2a7-fcaf08da98c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998693253 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1998693253
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1790060650
Short name T953
Test name
Test status
Simulation time 15419463 ps
CPU time 0.6 seconds
Started Aug 07 05:51:29 PM PDT 24
Finished Aug 07 05:51:30 PM PDT 24
Peak memory 195296 kb
Host smart-5c5ae3ad-3ef7-41a9-b34e-57db0e9c4061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790060650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1790060650
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3493598446
Short name T1002
Test name
Test status
Simulation time 79877922643 ps
CPU time 58.04 seconds
Started Aug 07 05:51:19 PM PDT 24
Finished Aug 07 05:52:17 PM PDT 24
Peak memory 199916 kb
Host smart-e672801f-d4c6-4bda-a75d-f4d0a4b033d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493598446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3493598446
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2905535149
Short name T406
Test name
Test status
Simulation time 21513245322 ps
CPU time 18.54 seconds
Started Aug 07 05:51:19 PM PDT 24
Finished Aug 07 05:51:37 PM PDT 24
Peak memory 199880 kb
Host smart-42ba1500-2813-4fb8-8182-85cb70f96f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905535149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2905535149
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.4283781705
Short name T158
Test name
Test status
Simulation time 96962220573 ps
CPU time 38.87 seconds
Started Aug 07 05:51:17 PM PDT 24
Finished Aug 07 05:51:56 PM PDT 24
Peak memory 199904 kb
Host smart-b016fd51-7bfb-49f1-afa4-ed1cdc47b1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283781705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.4283781705
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2362831990
Short name T21
Test name
Test status
Simulation time 106601718306 ps
CPU time 69.3 seconds
Started Aug 07 05:51:16 PM PDT 24
Finished Aug 07 05:52:26 PM PDT 24
Peak memory 199932 kb
Host smart-e771b6e3-8b58-4987-92cf-f672c5dcb912
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362831990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2362831990
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1820076536
Short name T532
Test name
Test status
Simulation time 179981302670 ps
CPU time 330.39 seconds
Started Aug 07 05:51:21 PM PDT 24
Finished Aug 07 05:56:52 PM PDT 24
Peak memory 199856 kb
Host smart-4599b4c5-7376-4517-b4f9-82eb18c3fd0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1820076536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1820076536
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.4117428480
Short name T340
Test name
Test status
Simulation time 6030548084 ps
CPU time 11.71 seconds
Started Aug 07 05:51:23 PM PDT 24
Finished Aug 07 05:51:35 PM PDT 24
Peak memory 198716 kb
Host smart-4cc9e82f-85b7-4f97-9700-3b6d1de2c621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117428480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.4117428480
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.4281754028
Short name T1149
Test name
Test status
Simulation time 75170493980 ps
CPU time 57.2 seconds
Started Aug 07 05:51:15 PM PDT 24
Finished Aug 07 05:52:12 PM PDT 24
Peak memory 199864 kb
Host smart-0d0c03f0-d09c-4b0f-a07f-df7ceffd4419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281754028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.4281754028
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.2550769972
Short name T788
Test name
Test status
Simulation time 16724471270 ps
CPU time 237.75 seconds
Started Aug 07 05:51:22 PM PDT 24
Finished Aug 07 05:55:20 PM PDT 24
Peak memory 199872 kb
Host smart-6620df5a-907d-45dd-8e88-93c9e1658485
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2550769972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2550769972
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2323479760
Short name T610
Test name
Test status
Simulation time 5667894311 ps
CPU time 13 seconds
Started Aug 07 05:51:17 PM PDT 24
Finished Aug 07 05:51:30 PM PDT 24
Peak memory 198068 kb
Host smart-1209d920-f80e-429e-9686-41655f856af2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2323479760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2323479760
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3235158375
Short name T789
Test name
Test status
Simulation time 125391161361 ps
CPU time 285.32 seconds
Started Aug 07 05:51:22 PM PDT 24
Finished Aug 07 05:56:07 PM PDT 24
Peak memory 199872 kb
Host smart-fdfa5943-5927-45d8-ab7a-53c6995afaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235158375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3235158375
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.72958630
Short name T656
Test name
Test status
Simulation time 47346798292 ps
CPU time 72.46 seconds
Started Aug 07 05:51:25 PM PDT 24
Finished Aug 07 05:52:37 PM PDT 24
Peak memory 196436 kb
Host smart-65d91447-c092-4008-b24b-3a19e33bce8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72958630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.72958630
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.141079151
Short name T775
Test name
Test status
Simulation time 426925446 ps
CPU time 1.7 seconds
Started Aug 07 05:51:16 PM PDT 24
Finished Aug 07 05:51:18 PM PDT 24
Peak memory 198872 kb
Host smart-1968769a-8852-4c1d-8123-bdd8102ea90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141079151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.141079151
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.3855860420
Short name T138
Test name
Test status
Simulation time 77135648080 ps
CPU time 119.96 seconds
Started Aug 07 05:51:21 PM PDT 24
Finished Aug 07 05:53:21 PM PDT 24
Peak memory 199936 kb
Host smart-5dfc2315-5afd-44d9-b19e-bbaf6f76121b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855860420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3855860420
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1623855075
Short name T99
Test name
Test status
Simulation time 24701835658 ps
CPU time 217.51 seconds
Started Aug 07 05:51:26 PM PDT 24
Finished Aug 07 05:55:03 PM PDT 24
Peak memory 215572 kb
Host smart-65b7fe9c-4025-4c7f-abbb-d14dad1329a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623855075 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1623855075
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3899938049
Short name T429
Test name
Test status
Simulation time 7898533075 ps
CPU time 8.11 seconds
Started Aug 07 05:51:25 PM PDT 24
Finished Aug 07 05:51:34 PM PDT 24
Peak memory 199952 kb
Host smart-cac5129c-d60b-4a4c-9fa5-4ef8e1c331b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899938049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3899938049
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.810684991
Short name T486
Test name
Test status
Simulation time 65932052300 ps
CPU time 106.63 seconds
Started Aug 07 05:51:17 PM PDT 24
Finished Aug 07 05:53:03 PM PDT 24
Peak memory 199916 kb
Host smart-c9a74e41-ec41-43f4-97d2-cdb294b22ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810684991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.810684991
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.355502009
Short name T991
Test name
Test status
Simulation time 149774408663 ps
CPU time 33.19 seconds
Started Aug 07 05:55:39 PM PDT 24
Finished Aug 07 05:56:12 PM PDT 24
Peak memory 199636 kb
Host smart-dbc80cca-f24f-4dd0-a5cc-0f44c650787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355502009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.355502009
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1924522943
Short name T35
Test name
Test status
Simulation time 135012188229 ps
CPU time 438.68 seconds
Started Aug 07 05:55:37 PM PDT 24
Finished Aug 07 06:02:56 PM PDT 24
Peak memory 216448 kb
Host smart-a97da0c2-6a50-4ea5-ac64-094f406b4d83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924522943 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1924522943
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1366406636
Short name T232
Test name
Test status
Simulation time 165944181379 ps
CPU time 184.48 seconds
Started Aug 07 05:55:36 PM PDT 24
Finished Aug 07 05:58:41 PM PDT 24
Peak memory 199908 kb
Host smart-e8b5585b-9d48-4648-b206-bc53bbbdf2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366406636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1366406636
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.609260921
Short name T98
Test name
Test status
Simulation time 43377967211 ps
CPU time 554.99 seconds
Started Aug 07 05:55:39 PM PDT 24
Finished Aug 07 06:04:54 PM PDT 24
Peak memory 216432 kb
Host smart-ce2ba361-77d0-4951-8228-3e1b6de9d876
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609260921 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.609260921
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.685401377
Short name T1024
Test name
Test status
Simulation time 108094623396 ps
CPU time 196.63 seconds
Started Aug 07 05:55:40 PM PDT 24
Finished Aug 07 05:58:56 PM PDT 24
Peak memory 199828 kb
Host smart-ffe52b09-55b5-484a-abc4-155fa392c7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685401377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.685401377
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3436942273
Short name T883
Test name
Test status
Simulation time 46402869901 ps
CPU time 850.92 seconds
Started Aug 07 05:55:40 PM PDT 24
Finished Aug 07 06:09:51 PM PDT 24
Peak memory 216412 kb
Host smart-1e00fc7d-aae4-4c1d-91ac-37a9a8d32650
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436942273 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3436942273
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.411320054
Short name T702
Test name
Test status
Simulation time 90030553163 ps
CPU time 44.26 seconds
Started Aug 07 05:55:40 PM PDT 24
Finished Aug 07 05:56:24 PM PDT 24
Peak memory 199916 kb
Host smart-1efbf9e6-7fdc-4634-9d5e-85a1145b749c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411320054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.411320054
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.658075419
Short name T735
Test name
Test status
Simulation time 10621587295 ps
CPU time 110.41 seconds
Started Aug 07 05:55:43 PM PDT 24
Finished Aug 07 05:57:34 PM PDT 24
Peak memory 216436 kb
Host smart-ee7647d3-7a4d-4336-830e-b5f1acde3ce8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658075419 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.658075419
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.1125164580
Short name T214
Test name
Test status
Simulation time 19939145021 ps
CPU time 32.83 seconds
Started Aug 07 05:55:38 PM PDT 24
Finished Aug 07 05:56:11 PM PDT 24
Peak memory 199688 kb
Host smart-00037acb-66bd-4f5a-a37c-577fec61d43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125164580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1125164580
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.2201186918
Short name T37
Test name
Test status
Simulation time 81850430431 ps
CPU time 1173.97 seconds
Started Aug 07 05:55:37 PM PDT 24
Finished Aug 07 06:15:11 PM PDT 24
Peak memory 223364 kb
Host smart-6892a661-6594-4ea9-8d91-7526aef2fb2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201186918 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2201186918
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2272760661
Short name T209
Test name
Test status
Simulation time 104205935657 ps
CPU time 97.15 seconds
Started Aug 07 05:55:37 PM PDT 24
Finished Aug 07 05:57:14 PM PDT 24
Peak memory 199936 kb
Host smart-d82f536d-7bf0-47a2-8aa4-f20fe32001b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272760661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2272760661
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3280982978
Short name T597
Test name
Test status
Simulation time 439830204299 ps
CPU time 416.8 seconds
Started Aug 07 05:55:38 PM PDT 24
Finished Aug 07 06:02:35 PM PDT 24
Peak memory 225776 kb
Host smart-40324e4a-a9f3-4f87-a940-edcbf61dbc57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280982978 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3280982978
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1040149777
Short name T906
Test name
Test status
Simulation time 211925081878 ps
CPU time 324.67 seconds
Started Aug 07 05:55:38 PM PDT 24
Finished Aug 07 06:01:02 PM PDT 24
Peak memory 199864 kb
Host smart-a8761356-8243-484d-9c7f-fda56ef808f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040149777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1040149777
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3098623524
Short name T286
Test name
Test status
Simulation time 42769044577 ps
CPU time 90.5 seconds
Started Aug 07 05:55:38 PM PDT 24
Finished Aug 07 05:57:09 PM PDT 24
Peak memory 199888 kb
Host smart-c4947e42-7d68-41b6-a5d3-fd307ebb25f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098623524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3098623524
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.159000300
Short name T311
Test name
Test status
Simulation time 83477152998 ps
CPU time 751.32 seconds
Started Aug 07 05:55:36 PM PDT 24
Finished Aug 07 06:08:07 PM PDT 24
Peak memory 212316 kb
Host smart-5a9c579a-e40c-4ff4-b75b-b26b9f5d60a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159000300 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.159000300
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.722686345
Short name T1123
Test name
Test status
Simulation time 16467862065 ps
CPU time 28.03 seconds
Started Aug 07 05:55:38 PM PDT 24
Finished Aug 07 05:56:06 PM PDT 24
Peak memory 199856 kb
Host smart-7d8468da-6031-4548-9b12-71aef7871691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722686345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.722686345
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2192406855
Short name T319
Test name
Test status
Simulation time 23476411606 ps
CPU time 49.64 seconds
Started Aug 07 05:55:44 PM PDT 24
Finished Aug 07 05:56:34 PM PDT 24
Peak memory 199912 kb
Host smart-590d2936-6cdf-4206-8413-e2833edfca49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192406855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2192406855
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3344471379
Short name T931
Test name
Test status
Simulation time 66452004556 ps
CPU time 525.94 seconds
Started Aug 07 05:55:42 PM PDT 24
Finished Aug 07 06:04:28 PM PDT 24
Peak memory 224712 kb
Host smart-37fb61f4-2bab-4527-bd1c-71f033a86d13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344471379 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3344471379
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1159484529
Short name T410
Test name
Test status
Simulation time 42279832 ps
CPU time 0.56 seconds
Started Aug 07 05:51:26 PM PDT 24
Finished Aug 07 05:51:26 PM PDT 24
Peak memory 195568 kb
Host smart-f94bafe3-31d0-401b-9488-8a4c794f6315
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159484529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1159484529
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.465558181
Short name T247
Test name
Test status
Simulation time 285271380363 ps
CPU time 21.2 seconds
Started Aug 07 05:51:21 PM PDT 24
Finished Aug 07 05:51:42 PM PDT 24
Peak memory 199848 kb
Host smart-9ff13922-cc6b-4c20-a24f-a6e6a36f1a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465558181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.465558181
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1113111130
Short name T350
Test name
Test status
Simulation time 66322490778 ps
CPU time 108.81 seconds
Started Aug 07 05:51:20 PM PDT 24
Finished Aug 07 05:53:09 PM PDT 24
Peak memory 199876 kb
Host smart-6397a0e9-df0f-4227-a0f4-a73b89895233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113111130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1113111130
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2485180534
Short name T157
Test name
Test status
Simulation time 32986804851 ps
CPU time 27.17 seconds
Started Aug 07 05:51:22 PM PDT 24
Finished Aug 07 05:51:49 PM PDT 24
Peak memory 199836 kb
Host smart-f0d52b42-cd60-47f5-809e-7aebb4771f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485180534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2485180534
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1623609827
Short name T595
Test name
Test status
Simulation time 7949808189 ps
CPU time 14.09 seconds
Started Aug 07 05:51:21 PM PDT 24
Finished Aug 07 05:51:36 PM PDT 24
Peak memory 199976 kb
Host smart-857e7794-d29b-48ce-857b-57a3edd1ff43
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623609827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1623609827
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1767555647
Short name T339
Test name
Test status
Simulation time 106318073450 ps
CPU time 618.92 seconds
Started Aug 07 05:51:25 PM PDT 24
Finished Aug 07 06:01:44 PM PDT 24
Peak memory 199260 kb
Host smart-7e068127-c282-4851-8a0c-62bee17aa64c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767555647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1767555647
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1803985155
Short name T333
Test name
Test status
Simulation time 2135893309 ps
CPU time 1.6 seconds
Started Aug 07 05:51:24 PM PDT 24
Finished Aug 07 05:51:26 PM PDT 24
Peak memory 196000 kb
Host smart-00f0689e-c5fc-4b59-befd-10194d429f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803985155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1803985155
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2220871906
Short name T522
Test name
Test status
Simulation time 105336609387 ps
CPU time 114.47 seconds
Started Aug 07 05:51:26 PM PDT 24
Finished Aug 07 05:53:20 PM PDT 24
Peak memory 199184 kb
Host smart-774bace7-d1c5-4ce8-8af9-27da55fa2993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220871906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2220871906
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1965972961
Short name T1128
Test name
Test status
Simulation time 2849089589 ps
CPU time 19.68 seconds
Started Aug 07 05:51:25 PM PDT 24
Finished Aug 07 05:51:45 PM PDT 24
Peak memory 197484 kb
Host smart-265bd225-7589-40bf-a2fa-ca2baaedbe99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1965972961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1965972961
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3914923586
Short name T144
Test name
Test status
Simulation time 39468905884 ps
CPU time 65.98 seconds
Started Aug 07 05:51:23 PM PDT 24
Finished Aug 07 05:52:29 PM PDT 24
Peak memory 199772 kb
Host smart-b68bb852-a1ff-4150-bafd-873ffdb0a22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914923586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3914923586
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3657481825
Short name T288
Test name
Test status
Simulation time 53647527168 ps
CPU time 78.34 seconds
Started Aug 07 05:51:24 PM PDT 24
Finished Aug 07 05:52:42 PM PDT 24
Peak memory 196176 kb
Host smart-1c8f5beb-f148-402f-8d87-5296d7b6465a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657481825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3657481825
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3693934713
Short name T611
Test name
Test status
Simulation time 430362566 ps
CPU time 1.99 seconds
Started Aug 07 05:51:20 PM PDT 24
Finished Aug 07 05:51:22 PM PDT 24
Peak memory 199632 kb
Host smart-515bf25a-4448-4d3c-b4d8-028c77db9c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693934713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3693934713
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.4118867137
Short name T975
Test name
Test status
Simulation time 137787146693 ps
CPU time 138.48 seconds
Started Aug 07 05:51:25 PM PDT 24
Finished Aug 07 05:53:43 PM PDT 24
Peak memory 208280 kb
Host smart-61436df7-955b-402b-852e-7fbb9ad01150
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118867137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.4118867137
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.1272927707
Short name T928
Test name
Test status
Simulation time 662478935235 ps
CPU time 566.65 seconds
Started Aug 07 05:51:23 PM PDT 24
Finished Aug 07 06:00:50 PM PDT 24
Peak memory 216428 kb
Host smart-f6fd2feb-7500-4996-bf48-195bd0e7fc54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272927707 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1272927707
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2890775141
Short name T1023
Test name
Test status
Simulation time 1218829790 ps
CPU time 1.64 seconds
Started Aug 07 05:51:22 PM PDT 24
Finished Aug 07 05:51:23 PM PDT 24
Peak memory 198492 kb
Host smart-99662b9a-8266-4c80-b78e-aa0e9be86388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890775141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2890775141
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2037852628
Short name T1169
Test name
Test status
Simulation time 209534677759 ps
CPU time 59.9 seconds
Started Aug 07 05:55:46 PM PDT 24
Finished Aug 07 05:56:46 PM PDT 24
Peak memory 199872 kb
Host smart-a0a84c88-ac2f-4f98-ba94-9cbf361b3787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037852628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2037852628
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2035227463
Short name T53
Test name
Test status
Simulation time 97049429036 ps
CPU time 1234.87 seconds
Started Aug 07 05:55:45 PM PDT 24
Finished Aug 07 06:16:20 PM PDT 24
Peak memory 225208 kb
Host smart-ecce481b-3f04-4157-ac21-ddb35232b747
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035227463 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2035227463
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.4190296432
Short name T192
Test name
Test status
Simulation time 93107856179 ps
CPU time 148.07 seconds
Started Aug 07 05:55:45 PM PDT 24
Finished Aug 07 05:58:13 PM PDT 24
Peak memory 199872 kb
Host smart-6779b8bd-7f82-4f9a-b6c5-59c6150f6767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190296432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.4190296432
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2078383169
Short name T1009
Test name
Test status
Simulation time 48861892419 ps
CPU time 451.35 seconds
Started Aug 07 05:55:46 PM PDT 24
Finished Aug 07 06:03:17 PM PDT 24
Peak memory 216080 kb
Host smart-8f61d9a8-dc68-494d-8096-2fe545fc4c71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078383169 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2078383169
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1822431544
Short name T315
Test name
Test status
Simulation time 15496321858 ps
CPU time 14.23 seconds
Started Aug 07 05:55:45 PM PDT 24
Finished Aug 07 05:55:59 PM PDT 24
Peak memory 199952 kb
Host smart-f3b8a48c-95f5-42a3-ae1e-fd769ae93fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822431544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1822431544
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3972756374
Short name T810
Test name
Test status
Simulation time 47759602175 ps
CPU time 589.56 seconds
Started Aug 07 05:55:45 PM PDT 24
Finished Aug 07 06:05:35 PM PDT 24
Peak memory 216632 kb
Host smart-31eddb7c-548a-4729-9d67-837e6b2ede86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972756374 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3972756374
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.4286424308
Short name T90
Test name
Test status
Simulation time 116652165514 ps
CPU time 47.95 seconds
Started Aug 07 05:55:42 PM PDT 24
Finished Aug 07 05:56:30 PM PDT 24
Peak memory 199884 kb
Host smart-76ac48de-a2ab-4b51-be81-58e5dca1cb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286424308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.4286424308
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.944679168
Short name T976
Test name
Test status
Simulation time 60480939345 ps
CPU time 541.79 seconds
Started Aug 07 05:55:43 PM PDT 24
Finished Aug 07 06:04:45 PM PDT 24
Peak memory 228096 kb
Host smart-78a642e6-e441-4af7-b20a-951cfd1457b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944679168 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.944679168
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.423109118
Short name T924
Test name
Test status
Simulation time 195750079329 ps
CPU time 68.24 seconds
Started Aug 07 05:55:43 PM PDT 24
Finished Aug 07 05:56:51 PM PDT 24
Peak memory 199916 kb
Host smart-850d9b4a-ddc4-4447-9efb-cddce97d2488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423109118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.423109118
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1277232768
Short name T48
Test name
Test status
Simulation time 162388348579 ps
CPU time 827.33 seconds
Started Aug 07 05:55:43 PM PDT 24
Finished Aug 07 06:09:30 PM PDT 24
Peak memory 224652 kb
Host smart-6c575359-eb3a-470b-9966-c21471ffca60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277232768 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1277232768
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2767599294
Short name T230
Test name
Test status
Simulation time 70671914230 ps
CPU time 23.89 seconds
Started Aug 07 05:55:44 PM PDT 24
Finished Aug 07 05:56:08 PM PDT 24
Peak memory 199912 kb
Host smart-0558da23-b4c4-4af7-8fa4-39cea31ea46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767599294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2767599294
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.875671813
Short name T629
Test name
Test status
Simulation time 28852835992 ps
CPU time 95.01 seconds
Started Aug 07 05:55:46 PM PDT 24
Finished Aug 07 05:57:21 PM PDT 24
Peak memory 210560 kb
Host smart-2c5227ba-612b-40e2-8bc8-a177996912eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875671813 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.875671813
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3024745400
Short name T188
Test name
Test status
Simulation time 82590166932 ps
CPU time 55.12 seconds
Started Aug 07 05:55:42 PM PDT 24
Finished Aug 07 05:56:37 PM PDT 24
Peak memory 199900 kb
Host smart-6ddacde1-90a8-4d7c-a5e3-0d8c947c44e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024745400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3024745400
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.4100579696
Short name T851
Test name
Test status
Simulation time 387410306463 ps
CPU time 1127.48 seconds
Started Aug 07 05:55:46 PM PDT 24
Finished Aug 07 06:14:33 PM PDT 24
Peak memory 232896 kb
Host smart-ececa305-1c07-4ba4-a091-6750d4e1967d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100579696 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.4100579696
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1114021945
Short name T884
Test name
Test status
Simulation time 12732318324 ps
CPU time 6.71 seconds
Started Aug 07 05:55:45 PM PDT 24
Finished Aug 07 05:55:52 PM PDT 24
Peak memory 199872 kb
Host smart-7c7db73c-ff5a-4a39-983d-46f28299632a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114021945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1114021945
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.4020085920
Short name T102
Test name
Test status
Simulation time 40916235109 ps
CPU time 172.44 seconds
Started Aug 07 05:55:42 PM PDT 24
Finished Aug 07 05:58:35 PM PDT 24
Peak memory 215912 kb
Host smart-5ac4ec6d-9fd9-4b8a-8299-4e5a5f145ad3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020085920 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.4020085920
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3357442493
Short name T322
Test name
Test status
Simulation time 22365577974 ps
CPU time 34.84 seconds
Started Aug 07 05:55:43 PM PDT 24
Finished Aug 07 05:56:18 PM PDT 24
Peak memory 199720 kb
Host smart-84deb6dd-b75d-4097-979a-9cd13bef6bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357442493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3357442493
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3407700511
Short name T492
Test name
Test status
Simulation time 177849535375 ps
CPU time 284.92 seconds
Started Aug 07 05:55:52 PM PDT 24
Finished Aug 07 06:00:37 PM PDT 24
Peak memory 199920 kb
Host smart-13ffd47b-22cb-49ab-8cb2-2305ad3b33a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407700511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3407700511
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1386612264
Short name T798
Test name
Test status
Simulation time 59730239403 ps
CPU time 339.94 seconds
Started Aug 07 05:55:49 PM PDT 24
Finished Aug 07 06:01:29 PM PDT 24
Peak memory 216024 kb
Host smart-7a5fe67c-067c-4d38-91da-5fa1f9057369
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386612264 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1386612264
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3909474627
Short name T478
Test name
Test status
Simulation time 29438469 ps
CPU time 0.55 seconds
Started Aug 07 05:51:28 PM PDT 24
Finished Aug 07 05:51:29 PM PDT 24
Peak memory 195584 kb
Host smart-3603b256-d1c6-4aff-bad7-6b999ce6e34b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909474627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3909474627
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2246812287
Short name T122
Test name
Test status
Simulation time 19955475116 ps
CPU time 15.2 seconds
Started Aug 07 05:51:23 PM PDT 24
Finished Aug 07 05:51:39 PM PDT 24
Peak memory 199892 kb
Host smart-d3204e20-f99b-4e3b-ac25-9ce05fd3e045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246812287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2246812287
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1168672864
Short name T181
Test name
Test status
Simulation time 16683716731 ps
CPU time 7.2 seconds
Started Aug 07 05:51:24 PM PDT 24
Finished Aug 07 05:51:31 PM PDT 24
Peak memory 199840 kb
Host smart-b9def98f-63fc-45d0-aaf9-6140d95a3ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168672864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1168672864
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.700598374
Short name T653
Test name
Test status
Simulation time 22137796985 ps
CPU time 19.81 seconds
Started Aug 07 05:51:23 PM PDT 24
Finished Aug 07 05:51:43 PM PDT 24
Peak memory 199928 kb
Host smart-b44c2a48-dd81-484d-a9fd-3cf1df0e74cd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700598374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.700598374
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.674940404
Short name T509
Test name
Test status
Simulation time 127238503689 ps
CPU time 251.94 seconds
Started Aug 07 05:51:22 PM PDT 24
Finished Aug 07 05:55:34 PM PDT 24
Peak memory 199884 kb
Host smart-509d9b54-970f-48cb-a321-2dfa9df11aa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=674940404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.674940404
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2327018432
Short name T638
Test name
Test status
Simulation time 264349960 ps
CPU time 0.65 seconds
Started Aug 07 05:51:28 PM PDT 24
Finished Aug 07 05:51:29 PM PDT 24
Peak memory 195408 kb
Host smart-10ad0362-edbe-4d64-be63-8dc7388e061d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327018432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2327018432
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2297830563
Short name T301
Test name
Test status
Simulation time 158108772855 ps
CPU time 77.84 seconds
Started Aug 07 05:51:25 PM PDT 24
Finished Aug 07 05:52:43 PM PDT 24
Peak memory 199264 kb
Host smart-88aad116-7b89-4cfa-beb4-634f3b7d1581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297830563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2297830563
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.1785529107
Short name T824
Test name
Test status
Simulation time 10317564555 ps
CPU time 163.38 seconds
Started Aug 07 05:51:28 PM PDT 24
Finished Aug 07 05:54:11 PM PDT 24
Peak memory 199852 kb
Host smart-80d0755e-f24e-4e44-9a09-660281a3ca6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1785529107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1785529107
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2953396420
Short name T590
Test name
Test status
Simulation time 2243583619 ps
CPU time 3.7 seconds
Started Aug 07 05:51:28 PM PDT 24
Finished Aug 07 05:51:31 PM PDT 24
Peak memory 198196 kb
Host smart-1e5a9f5e-ec16-44ff-9427-6aebd3d121a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2953396420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2953396420
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.700572277
Short name T169
Test name
Test status
Simulation time 110826586156 ps
CPU time 67.81 seconds
Started Aug 07 05:51:24 PM PDT 24
Finished Aug 07 05:52:32 PM PDT 24
Peak memory 199892 kb
Host smart-63752f6a-e52c-4120-9508-e8f7d897dd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700572277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.700572277
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1911993637
Short name T681
Test name
Test status
Simulation time 3412801326 ps
CPU time 5.74 seconds
Started Aug 07 05:51:27 PM PDT 24
Finished Aug 07 05:51:32 PM PDT 24
Peak memory 196388 kb
Host smart-eb33ce58-bc63-4a5b-b349-7fa235c18bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911993637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1911993637
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3952650052
Short name T649
Test name
Test status
Simulation time 5824881489 ps
CPU time 4.19 seconds
Started Aug 07 05:51:24 PM PDT 24
Finished Aug 07 05:51:28 PM PDT 24
Peak memory 199140 kb
Host smart-65f42cfe-f140-494d-9895-49425f41b35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952650052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3952650052
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2426197345
Short name T184
Test name
Test status
Simulation time 233906797209 ps
CPU time 166.24 seconds
Started Aug 07 05:51:24 PM PDT 24
Finished Aug 07 05:54:10 PM PDT 24
Peak memory 215436 kb
Host smart-5b4b6658-9a34-4f3b-9fd8-e9bbffae3809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426197345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2426197345
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.943122826
Short name T577
Test name
Test status
Simulation time 204751830599 ps
CPU time 1097.86 seconds
Started Aug 07 05:51:27 PM PDT 24
Finished Aug 07 06:09:45 PM PDT 24
Peak memory 232204 kb
Host smart-3d3ec4f7-5289-450d-8d8c-04c23dc8a606
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943122826 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.943122826
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.4148917718
Short name T823
Test name
Test status
Simulation time 2226940118 ps
CPU time 2.52 seconds
Started Aug 07 05:51:28 PM PDT 24
Finished Aug 07 05:51:31 PM PDT 24
Peak memory 198376 kb
Host smart-87e5ff7f-3260-4690-952c-8ae00f24a152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148917718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.4148917718
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3764750467
Short name T839
Test name
Test status
Simulation time 23199738980 ps
CPU time 43.93 seconds
Started Aug 07 05:51:21 PM PDT 24
Finished Aug 07 05:52:06 PM PDT 24
Peak memory 199804 kb
Host smart-8f3cac88-ab89-4874-93b8-2dc4e761762d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764750467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3764750467
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.4211339749
Short name T825
Test name
Test status
Simulation time 120375776998 ps
CPU time 294.69 seconds
Started Aug 07 05:55:51 PM PDT 24
Finished Aug 07 06:00:45 PM PDT 24
Peak memory 199856 kb
Host smart-e58ce23c-d758-46b3-b67d-5ecc502a0574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211339749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.4211339749
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2598969762
Short name T1063
Test name
Test status
Simulation time 186927435565 ps
CPU time 1280.98 seconds
Started Aug 07 05:55:49 PM PDT 24
Finished Aug 07 06:17:10 PM PDT 24
Peak memory 216136 kb
Host smart-8f7d1876-ced5-4e87-9ae5-5e6a2589e75c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598969762 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2598969762
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.335010924
Short name T960
Test name
Test status
Simulation time 21817285941 ps
CPU time 38.63 seconds
Started Aug 07 05:55:49 PM PDT 24
Finished Aug 07 05:56:28 PM PDT 24
Peak memory 199896 kb
Host smart-dbc5775a-edac-47c3-bab0-af51101e81e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335010924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.335010924
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.821858187
Short name T709
Test name
Test status
Simulation time 43784293780 ps
CPU time 462.05 seconds
Started Aug 07 05:55:50 PM PDT 24
Finished Aug 07 06:03:32 PM PDT 24
Peak memory 216508 kb
Host smart-240901dd-ea7c-4f86-adac-2f7057b1f08c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821858187 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.821858187
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.773855862
Short name T633
Test name
Test status
Simulation time 12164113850 ps
CPU time 22.04 seconds
Started Aug 07 05:55:49 PM PDT 24
Finished Aug 07 05:56:11 PM PDT 24
Peak memory 199824 kb
Host smart-3e125b4e-7725-4118-9740-fc54671aa9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773855862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.773855862
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.2697298853
Short name T730
Test name
Test status
Simulation time 143521676869 ps
CPU time 574.36 seconds
Started Aug 07 05:55:51 PM PDT 24
Finished Aug 07 06:05:25 PM PDT 24
Peak memory 216584 kb
Host smart-cdb41992-8514-400a-be7d-1a08d8dc4dc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697298853 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.2697298853
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2369335758
Short name T1034
Test name
Test status
Simulation time 102521785628 ps
CPU time 34.32 seconds
Started Aug 07 05:55:48 PM PDT 24
Finished Aug 07 05:56:23 PM PDT 24
Peak memory 199884 kb
Host smart-91ab49cc-72a0-4267-842b-3fa727372582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369335758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2369335758
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3406817515
Short name T171
Test name
Test status
Simulation time 230703084528 ps
CPU time 174.68 seconds
Started Aug 07 05:55:49 PM PDT 24
Finished Aug 07 05:58:44 PM PDT 24
Peak memory 216404 kb
Host smart-c15f8ae2-c78f-4d18-87cc-440b232a850f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406817515 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3406817515
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3357192817
Short name T218
Test name
Test status
Simulation time 173665663561 ps
CPU time 27.88 seconds
Started Aug 07 05:55:50 PM PDT 24
Finished Aug 07 05:56:18 PM PDT 24
Peak memory 199476 kb
Host smart-ffeff025-6eb0-4f16-b109-bb59af8dfb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357192817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3357192817
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1280028223
Short name T946
Test name
Test status
Simulation time 31652757251 ps
CPU time 1176.8 seconds
Started Aug 07 05:55:50 PM PDT 24
Finished Aug 07 06:15:28 PM PDT 24
Peak memory 216572 kb
Host smart-42feac71-3846-4212-aca0-205c60a4fec2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280028223 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1280028223
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.882043720
Short name T189
Test name
Test status
Simulation time 151970143146 ps
CPU time 36.1 seconds
Started Aug 07 05:55:58 PM PDT 24
Finished Aug 07 05:56:34 PM PDT 24
Peak memory 199864 kb
Host smart-94c84998-5f22-4ebb-bcaf-7112f9838a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882043720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.882043720
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1232145412
Short name T520
Test name
Test status
Simulation time 162517963373 ps
CPU time 62.77 seconds
Started Aug 07 05:55:56 PM PDT 24
Finished Aug 07 05:56:59 PM PDT 24
Peak memory 199904 kb
Host smart-cfc7fccd-8869-4ec4-95aa-b0d6c3291365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232145412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1232145412
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.241355252
Short name T1096
Test name
Test status
Simulation time 96659043254 ps
CPU time 1188.94 seconds
Started Aug 07 05:55:57 PM PDT 24
Finished Aug 07 06:15:46 PM PDT 24
Peak memory 224736 kb
Host smart-bf8cf523-956b-41a7-8b36-7f1efafe5033
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241355252 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.241355252
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2917670326
Short name T470
Test name
Test status
Simulation time 17666935360 ps
CPU time 38.06 seconds
Started Aug 07 05:55:55 PM PDT 24
Finished Aug 07 05:56:33 PM PDT 24
Peak memory 199796 kb
Host smart-1d74c1a2-63ff-44f5-9a4b-18e09360fc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917670326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2917670326
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3266642082
Short name T717
Test name
Test status
Simulation time 20324495223 ps
CPU time 186.67 seconds
Started Aug 07 05:55:56 PM PDT 24
Finished Aug 07 05:59:02 PM PDT 24
Peak memory 216476 kb
Host smart-71a452a5-2beb-46e3-92ff-faeef68837a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266642082 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3266642082
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3024407094
Short name T182
Test name
Test status
Simulation time 52405668755 ps
CPU time 69.07 seconds
Started Aug 07 05:55:56 PM PDT 24
Finished Aug 07 05:57:06 PM PDT 24
Peak memory 199880 kb
Host smart-d76cb686-01e9-44e3-856d-6905c1404227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024407094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3024407094
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2673904880
Short name T1166
Test name
Test status
Simulation time 175740271074 ps
CPU time 1157.18 seconds
Started Aug 07 05:55:58 PM PDT 24
Finished Aug 07 06:15:16 PM PDT 24
Peak memory 226388 kb
Host smart-4d1232d2-6307-4f2e-a7ba-5764defbf564
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673904880 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2673904880
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.98795891
Short name T426
Test name
Test status
Simulation time 11621229 ps
CPU time 0.54 seconds
Started Aug 07 05:51:26 PM PDT 24
Finished Aug 07 05:51:27 PM PDT 24
Peak memory 194752 kb
Host smart-4e6fb6a9-2ae3-4e34-b58c-b24f6c01853f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98795891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.98795891
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1372630533
Short name T837
Test name
Test status
Simulation time 208851317489 ps
CPU time 81.56 seconds
Started Aug 07 05:51:33 PM PDT 24
Finished Aug 07 05:52:55 PM PDT 24
Peak memory 199856 kb
Host smart-7bfc93b0-b54f-4b36-9707-dae4f62367da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372630533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1372630533
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2535691391
Short name T686
Test name
Test status
Simulation time 70609145781 ps
CPU time 147.94 seconds
Started Aug 07 05:51:33 PM PDT 24
Finished Aug 07 05:54:01 PM PDT 24
Peak memory 199844 kb
Host smart-de58bbda-ece1-4eec-b62f-3a1c6909a3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535691391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2535691391
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1763441907
Short name T493
Test name
Test status
Simulation time 50943646549 ps
CPU time 21.76 seconds
Started Aug 07 05:51:27 PM PDT 24
Finished Aug 07 05:51:49 PM PDT 24
Peak memory 199888 kb
Host smart-4887cd7b-a0ef-4c37-8afb-4a28d9185144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763441907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1763441907
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2509167532
Short name T110
Test name
Test status
Simulation time 31354071055 ps
CPU time 32.83 seconds
Started Aug 07 05:51:24 PM PDT 24
Finished Aug 07 05:51:57 PM PDT 24
Peak memory 199860 kb
Host smart-019d095f-7d99-4894-94cc-5f778a0445b0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509167532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2509167532
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.4131960476
Short name T524
Test name
Test status
Simulation time 70472204352 ps
CPU time 168.31 seconds
Started Aug 07 05:51:27 PM PDT 24
Finished Aug 07 05:54:16 PM PDT 24
Peak memory 199848 kb
Host smart-9579636c-ff08-48c7-a62b-7d83a425a1be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4131960476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.4131960476
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1495604580
Short name T23
Test name
Test status
Simulation time 5551616922 ps
CPU time 1.78 seconds
Started Aug 07 05:51:27 PM PDT 24
Finished Aug 07 05:51:29 PM PDT 24
Peak memory 199300 kb
Host smart-0daea5e6-ba63-4075-bc9a-803dcaf12a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495604580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1495604580
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.103045293
Short name T836
Test name
Test status
Simulation time 46739600439 ps
CPU time 73.89 seconds
Started Aug 07 05:51:28 PM PDT 24
Finished Aug 07 05:52:42 PM PDT 24
Peak memory 200024 kb
Host smart-ad7c234d-c377-4a9f-ae74-e7ee7e1284d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103045293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.103045293
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.2723887720
Short name T792
Test name
Test status
Simulation time 10841974263 ps
CPU time 539.91 seconds
Started Aug 07 05:51:28 PM PDT 24
Finished Aug 07 06:00:28 PM PDT 24
Peak memory 199904 kb
Host smart-1422727b-f5cc-490d-b6e1-f47798df0c8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2723887720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2723887720
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.4124608184
Short name T337
Test name
Test status
Simulation time 6502231252 ps
CPU time 10.11 seconds
Started Aug 07 05:51:29 PM PDT 24
Finished Aug 07 05:51:39 PM PDT 24
Peak memory 199160 kb
Host smart-49d4311c-854e-4db5-8a9f-9131149a9659
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4124608184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.4124608184
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.413633092
Short name T245
Test name
Test status
Simulation time 50397129662 ps
CPU time 67.73 seconds
Started Aug 07 05:51:28 PM PDT 24
Finished Aug 07 05:52:36 PM PDT 24
Peak memory 199832 kb
Host smart-8113850d-213d-42fc-a5ec-5a060257dcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413633092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.413633092
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3550425287
Short name T1070
Test name
Test status
Simulation time 5154008615 ps
CPU time 2.53 seconds
Started Aug 07 05:51:31 PM PDT 24
Finished Aug 07 05:51:33 PM PDT 24
Peak memory 196216 kb
Host smart-c796e97d-3da5-4d2c-a70c-3cd369b4ad15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550425287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3550425287
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.703908507
Short name T279
Test name
Test status
Simulation time 655492571 ps
CPU time 1.78 seconds
Started Aug 07 05:51:33 PM PDT 24
Finished Aug 07 05:51:35 PM PDT 24
Peak memory 199300 kb
Host smart-84002feb-141a-47ae-95ea-8d3c67088963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703908507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.703908507
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.521235286
Short name T545
Test name
Test status
Simulation time 193914683840 ps
CPU time 562.49 seconds
Started Aug 07 05:51:28 PM PDT 24
Finished Aug 07 06:00:51 PM PDT 24
Peak memory 199844 kb
Host smart-9b7c4bcd-10f4-45ae-94b4-dbe246adb3b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521235286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.521235286
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3063832813
Short name T34
Test name
Test status
Simulation time 65877220409 ps
CPU time 316.72 seconds
Started Aug 07 05:51:28 PM PDT 24
Finished Aug 07 05:56:45 PM PDT 24
Peak memory 216340 kb
Host smart-d8c9e3d2-c5fb-41e1-beaf-b3228030819f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063832813 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3063832813
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3324567690
Short name T513
Test name
Test status
Simulation time 1287347207 ps
CPU time 5.31 seconds
Started Aug 07 05:51:31 PM PDT 24
Finished Aug 07 05:51:36 PM PDT 24
Peak memory 199628 kb
Host smart-0768caef-4787-4ff3-984b-c9b05b77ca4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324567690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3324567690
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.998714087
Short name T1146
Test name
Test status
Simulation time 177089922533 ps
CPU time 87.36 seconds
Started Aug 07 05:51:26 PM PDT 24
Finished Aug 07 05:52:54 PM PDT 24
Peak memory 199960 kb
Host smart-8e740c83-8a32-43b5-8ab9-c7f813d11e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998714087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.998714087
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.633239205
Short name T127
Test name
Test status
Simulation time 130958879648 ps
CPU time 58.74 seconds
Started Aug 07 05:55:56 PM PDT 24
Finished Aug 07 05:56:55 PM PDT 24
Peak memory 199908 kb
Host smart-347f9544-fcbf-45ad-ad2a-117a925022a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633239205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.633239205
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1931011500
Short name T1054
Test name
Test status
Simulation time 39591326562 ps
CPU time 276.52 seconds
Started Aug 07 05:55:55 PM PDT 24
Finished Aug 07 06:00:32 PM PDT 24
Peak memory 216552 kb
Host smart-fd5881cd-75b5-4915-a128-999f0cdf8feb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931011500 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1931011500
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1611879643
Short name T1064
Test name
Test status
Simulation time 42439629510 ps
CPU time 15.39 seconds
Started Aug 07 05:55:57 PM PDT 24
Finished Aug 07 05:56:13 PM PDT 24
Peak memory 199476 kb
Host smart-11abe10f-1ce2-4a3e-8139-982fec8a06bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611879643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1611879643
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.542773498
Short name T176
Test name
Test status
Simulation time 190706733949 ps
CPU time 954.99 seconds
Started Aug 07 05:55:56 PM PDT 24
Finished Aug 07 06:11:51 PM PDT 24
Peak memory 216608 kb
Host smart-ee11f60d-0f0c-4957-817f-cd9ec06b89af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542773498 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.542773498
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2096814609
Short name T599
Test name
Test status
Simulation time 248843064786 ps
CPU time 80.3 seconds
Started Aug 07 05:55:56 PM PDT 24
Finished Aug 07 05:57:16 PM PDT 24
Peak memory 199924 kb
Host smart-e876f7df-cfa8-4255-b6c6-872964285257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096814609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2096814609
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1087062023
Short name T135
Test name
Test status
Simulation time 52082324133 ps
CPU time 95.18 seconds
Started Aug 07 05:55:56 PM PDT 24
Finished Aug 07 05:57:32 PM PDT 24
Peak memory 199880 kb
Host smart-69e1953d-99e6-43c4-8bc9-73f1b35081bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087062023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1087062023
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.924631870
Short name T540
Test name
Test status
Simulation time 725532392417 ps
CPU time 759.87 seconds
Started Aug 07 05:55:57 PM PDT 24
Finished Aug 07 06:08:37 PM PDT 24
Peak memory 216348 kb
Host smart-89556ae0-1139-4efb-8a01-be244f8fdc65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924631870 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.924631870
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.472063723
Short name T106
Test name
Test status
Simulation time 109228309666 ps
CPU time 25.76 seconds
Started Aug 07 05:56:02 PM PDT 24
Finished Aug 07 05:56:28 PM PDT 24
Peak memory 199848 kb
Host smart-8c3df965-057a-4abc-baf2-7ef44ba64d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472063723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.472063723
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.848106719
Short name T647
Test name
Test status
Simulation time 50174319017 ps
CPU time 219.89 seconds
Started Aug 07 05:56:01 PM PDT 24
Finished Aug 07 05:59:41 PM PDT 24
Peak memory 208236 kb
Host smart-7dc271d0-58dd-45d4-ac67-4735c26eed8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848106719 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.848106719
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.135918478
Short name T980
Test name
Test status
Simulation time 55535972171 ps
CPU time 73.78 seconds
Started Aug 07 05:56:01 PM PDT 24
Finished Aug 07 05:57:15 PM PDT 24
Peak memory 199740 kb
Host smart-08282054-b51b-44d1-b5af-6becd0f4d435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135918478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.135918478
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2404682916
Short name T55
Test name
Test status
Simulation time 103887239638 ps
CPU time 884.16 seconds
Started Aug 07 05:56:02 PM PDT 24
Finished Aug 07 06:10:46 PM PDT 24
Peak memory 224836 kb
Host smart-a575209f-fc25-4385-9e74-81fd4bfd0602
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404682916 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2404682916
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1442248283
Short name T658
Test name
Test status
Simulation time 49006106294 ps
CPU time 29.5 seconds
Started Aug 07 05:56:01 PM PDT 24
Finished Aug 07 05:56:30 PM PDT 24
Peak memory 199940 kb
Host smart-a30f991c-81b3-4838-bea2-f5b398b70730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442248283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1442248283
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2170422280
Short name T1116
Test name
Test status
Simulation time 104568726565 ps
CPU time 485.56 seconds
Started Aug 07 05:56:02 PM PDT 24
Finished Aug 07 06:04:08 PM PDT 24
Peak memory 216228 kb
Host smart-d604f647-64fb-4fd7-b005-1b68a39063a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170422280 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2170422280
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1623263183
Short name T50
Test name
Test status
Simulation time 215668096224 ps
CPU time 936.22 seconds
Started Aug 07 05:56:03 PM PDT 24
Finished Aug 07 06:11:40 PM PDT 24
Peak memory 225688 kb
Host smart-b2a39465-a2d8-4a33-a0bd-1378f3b056da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623263183 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1623263183
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1351935239
Short name T193
Test name
Test status
Simulation time 69813182263 ps
CPU time 114.68 seconds
Started Aug 07 05:56:02 PM PDT 24
Finished Aug 07 05:57:56 PM PDT 24
Peak memory 199852 kb
Host smart-ac7b487e-4d8a-47ee-b1d2-78c86b9f2c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351935239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1351935239
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.2085931473
Short name T1019
Test name
Test status
Simulation time 318000415313 ps
CPU time 786.94 seconds
Started Aug 07 05:56:02 PM PDT 24
Finished Aug 07 06:09:09 PM PDT 24
Peak memory 224780 kb
Host smart-7ec2780f-180e-4506-8b14-7a1d4e3cbf58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085931473 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.2085931473
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1582757040
Short name T688
Test name
Test status
Simulation time 61693415629 ps
CPU time 70.21 seconds
Started Aug 07 05:56:02 PM PDT 24
Finished Aug 07 05:57:12 PM PDT 24
Peak memory 199944 kb
Host smart-c708509d-5352-4aa8-a67e-a439008dfbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582757040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1582757040
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2278479832
Short name T667
Test name
Test status
Simulation time 77898909113 ps
CPU time 1290.25 seconds
Started Aug 07 05:56:01 PM PDT 24
Finished Aug 07 06:17:32 PM PDT 24
Peak memory 225392 kb
Host smart-81f749fe-2f51-4eb1-85a6-d92d1de01f1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278479832 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2278479832
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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