Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	97086	1			T1	65		T2	2		T3	16
all_values[1]	97086	1			T1	65		T2	2		T3	16
all_values[2]	97086	1			T1	65		T2	2		T3	16
all_values[3]	97086	1			T1	65		T2	2		T3	16
all_values[4]	97086	1			T1	65		T2	2		T3	16
all_values[5]	97086	1			T1	65		T2	2		T3	16
all_values[6]	97086	1			T1	65		T2	2		T3	16
all_values[7]	97086	1			T1	65		T2	2		T3	16
all_values[8]	97086	1			T1	65		T2	2		T3	16

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

445301

1

T1

230

T2

18

T3

68

auto[1]

428473

1

T1

355

T3

76

T4

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

789400

1

T1

579

T2

13

T3

140

auto[1]

84374

1

T1

6

T2

5

T3

4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	28159	1			T1	63		T3	3		T6	238
all_values[0]	auto[0]	auto[1]	21239	1			T2	2		T6	75		T7	38
all_values[0]	auto[1]	auto[0]	28189	1			T3	12		T6	287		T7	49
all_values[0]	auto[1]	auto[1]	19499	1			T1	2		T3	1		T4	1
all_values[1]	auto[0]	auto[0]	47075	1			T1	42		T2	2		T3	14
all_values[1]	auto[0]	auto[1]	1865	1			T6	1		T7	12		T9	6
all_values[1]	auto[1]	auto[0]	46328	1			T1	23		T3	2		T6	223
all_values[1]	auto[1]	auto[1]	1818	1			T6	3		T7	1		T9	10
all_values[2]	auto[0]	auto[0]	48351	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2816	1			T1	1		T2	1		T6	4
all_values[2]	auto[1]	auto[0]	43320	1			T1	62		T3	13		T4	1
all_values[2]	auto[1]	auto[1]	2599	1			T1	1		T3	2		T6	7
all_values[3]	auto[0]	auto[0]	47278	1			T1	27		T2	2		T3	12
all_values[3]	auto[0]	auto[1]	354	1			T6	3		T7	4		T14	3
all_values[3]	auto[1]	auto[0]	49132	1			T1	38		T3	4		T6	373
all_values[3]	auto[1]	auto[1]	322	1			T6	1		T7	2		T12	1
all_values[4]	auto[0]	auto[0]	50183	1			T1	65		T2	2		T3	6
all_values[4]	auto[0]	auto[1]	398	1			T7	8		T14	3		T16	6
all_values[4]	auto[1]	auto[0]	45981	1			T3	10		T4	1		T6	406
all_values[4]	auto[1]	auto[1]	524	1			T7	3		T14	3		T15	5
all_values[5]	auto[0]	auto[0]	49402	1			T1	4		T2	2		T3	9
all_values[5]	auto[0]	auto[1]	200	1			T6	2		T7	6		T14	2
all_values[5]	auto[1]	auto[0]	47290	1			T1	61		T3	7		T6	157
all_values[5]	auto[1]	auto[1]	194	1			T6	1		T7	6		T14	4
all_values[6]	auto[0]	auto[0]	48900	1			T1	25		T2	2		T3	1
all_values[6]	auto[0]	auto[1]	210	1			T7	8		T14	3		T28	1
all_values[6]	auto[1]	auto[0]	47803	1			T1	40		T3	15		T4	1
all_values[6]	auto[1]	auto[1]	173	1			T6	4		T7	2		T14	2
all_values[7]	auto[0]	auto[0]	48936	1			T1	2		T2	2		T3	11
all_values[7]	auto[0]	auto[1]	356	1			T7	2		T14	1		T40	3
all_values[7]	auto[1]	auto[0]	47439	1			T1	63		T3	5		T4	1
all_values[7]	auto[1]	auto[1]	355	1			T7	5		T14	2		T19	1
all_values[8]	auto[0]	auto[0]	34072	1			T3	11		T6	266		T7	44
all_values[8]	auto[0]	auto[1]	15507	1			T2	2		T4	1		T6	20
all_values[8]	auto[1]	auto[0]	31562	1			T1	63		T3	4		T6	286
all_values[8]	auto[1]	auto[1]	15945	1			T1	2		T3	1		T6	46