Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2531

1

T1

1

T2

1

T3

1

auto[UartRx]

2531

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4468	1			T1	2		T2	2		T3	2
values[1]	61	1			T7	1		T30	1		T31	1
values[2]	61	1			T7	1		T14	2		T27	1
values[3]	52	1			T6	2		T7	2		T14	1
values[4]	53	1			T27	1		T30	1		T31	2
values[5]	50	1			T6	1		T14	2		T30	2
values[6]	57	1			T26	2		T28	1		T29	1
values[7]	55	1			T6	1		T14	1		T28	1
values[8]	60	1			T6	1		T13	1		T27	1
values[9]	56	1			T6	2		T14	1		T26	1
values[10]	60	1			T6	2		T14	1		T119	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2326	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	18	1			T30	1		T31	1		T119	1
auto[UartTx]	values[2]	17	1			T29	1		T332	1		T143	2
auto[UartTx]	values[3]	25	1			T6	2		T7	2		T13	1
auto[UartTx]	values[4]	19	1			T27	1		T30	1		T31	1
auto[UartTx]	values[5]	14	1			T30	1		T119	1		T143	1
auto[UartTx]	values[6]	18	1			T26	1		T30	2		T106	1
auto[UartTx]	values[7]	23	1			T31	1		T119	1		T277	1
auto[UartTx]	values[8]	22	1			T13	1		T28	1		T105	1
auto[UartTx]	values[9]	22	1			T6	1		T143	1		T108	1
auto[UartTx]	values[10]	17	1			T14	1		T146	1		T333	1
auto[UartRx]	values[0]	2142	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	43	1			T7	1		T105	1		T332	1
auto[UartRx]	values[2]	44	1			T7	1		T14	2		T27	1
auto[UartRx]	values[3]	27	1			T14	1		T28	1		T29	1
auto[UartRx]	values[4]	34	1			T31	1		T106	1		T276	2
auto[UartRx]	values[5]	36	1			T6	1		T14	2		T30	1
auto[UartRx]	values[6]	39	1			T26	1		T28	1		T29	1
auto[UartRx]	values[7]	32	1			T6	1		T14	1		T28	1
auto[UartRx]	values[8]	38	1			T6	1		T27	1		T29	2
auto[UartRx]	values[9]	34	1			T6	1		T14	1		T26	1
auto[UartRx]	values[10]	43	1			T6	2		T119	2		T120	2