Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2292	1			T6	1		T7	25		T8	1
auto[BaudRate115200]	2097	1			T4	3		T6	4		T7	17
auto[BaudRate230400]	2115	1			T4	9		T6	5		T7	10
auto[BaudRate128Kbps]	2132	1			T6	6		T7	9		T9	1
auto[BaudRate256Kbps]	2325	1			T1	2		T3	7		T6	3
auto[BaudRate1Mbps]	1891	1			T1	2		T2	1		T4	9
auto[BaudRate1p5Mbps]	1307	1			T1	1		T2	1		T4	6

---

Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1441	1			T128	9		T251	10		T334	30
freqs[25]	1226	1			T8	2		T10	18		T256	7
freqs[48]	552	1			T7	107		T112	10		T123	9
freqs[50]	734	1			T9	8		T32	2		T261	17
freqs[100]	1209	1			T250	9		T114	5		T19	7

---

Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	232	1			T251	3		T334	3		T177	1
auto[BaudRate9600]	freqs[25]	163	1			T8	1		T335	1		T312	1
auto[BaudRate9600]	freqs[48]	148	1			T7	25		T112	2		T123	2
auto[BaudRate9600]	freqs[50]	112	1			T9	1		T261	1		T175	2
auto[BaudRate9600]	freqs[100]	188	1			T250	2		T114	2		T19	1
auto[BaudRate115200]	freqs[24]	216	1			T128	1		T251	2		T334	3
auto[BaudRate115200]	freqs[25]	182	1			T8	1		T10	3		T292	1
auto[BaudRate115200]	freqs[48]	60	1			T7	17		T112	3		T123	1
auto[BaudRate115200]	freqs[50]	101	1			T261	3		T301	2		T267	1
auto[BaudRate115200]	freqs[100]	182	1			T250	4		T114	2		T19	1
auto[BaudRate230400]	freqs[24]	214	1			T128	1		T251	3		T334	3
auto[BaudRate230400]	freqs[25]	178	1			T10	3		T160	1		T312	1
auto[BaudRate230400]	freqs[48]	69	1			T7	10		T112	1		T123	1
auto[BaudRate230400]	freqs[50]	86	1			T9	1		T32	1		T261	2
auto[BaudRate230400]	freqs[100]	171	1			T250	1		T122	1		T257	2
auto[BaudRate128Kbps]	freqs[24]	187	1			T128	3		T334	9		T295	1
auto[BaudRate128Kbps]	freqs[25]	198	1			T10	3		T160	1		T312	1
auto[BaudRate128Kbps]	freqs[48]	58	1			T7	9		T112	1		T123	2
auto[BaudRate128Kbps]	freqs[50]	112	1			T9	1		T261	5		T301	2
auto[BaudRate128Kbps]	freqs[100]	159	1			T19	2		T122	2		T131	1
auto[BaudRate256Kbps]	freqs[24]	238	1			T128	2		T334	9		T177	1
auto[BaudRate256Kbps]	freqs[25]	179	1			T10	3		T256	1		T160	3
auto[BaudRate256Kbps]	freqs[48]	79	1			T7	18		T112	1		T293	3
auto[BaudRate256Kbps]	freqs[50]	111	1			T9	2		T261	2		T301	1
auto[BaudRate256Kbps]	freqs[100]	148	1			T19	1		T122	2		T257	3
auto[BaudRate1Mbps]	freqs[24]	231	1			T128	2		T251	2		T334	3
auto[BaudRate1Mbps]	freqs[25]	228	1			T10	6		T256	4		T292	1
auto[BaudRate1Mbps]	freqs[48]	75	1			T7	17		T112	2		T123	1
auto[BaudRate1Mbps]	freqs[50]	113	1			T9	1		T261	2		T301	1
auto[BaudRate1Mbps]	freqs[100]	182	1			T114	1		T19	1		T257	2
auto[BaudRate1p5Mbps]	freqs[25]	98	1			T256	2		T160	1		T312	2
auto[BaudRate1p5Mbps]	freqs[48]	63	1			T7	11		T123	2		T293	2
auto[BaudRate1p5Mbps]	freqs[50]	99	1			T9	2		T32	1		T261	2
auto[BaudRate1p5Mbps]	freqs[100]	179	1			T250	2		T19	1		T122	3

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded