Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.91	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	12	118	90.77

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	12	118	90.77	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	24972673	1			T1	99383		T3	36728		T4	3
all_levels[1]	187213	1			T1	1815		T3	1627		T6	94
all_levels[2]	2514	1			T6	3		T7	4		T9	1
all_levels[3]	1099	1			T6	2		T7	2		T9	1
all_levels[4]	771	1			T6	1		T7	1		T112	1
all_levels[5]	604	1			T7	1		T9	1		T34	2
all_levels[6]	427	1			T6	3		T14	2		T122	1
all_levels[7]	383	1			T6	1		T36	1		T14	4
all_levels[8]	319	1			T112	3		T36	1		T14	1
all_levels[9]	281	1			T34	2		T112	1		T36	1
all_levels[10]	232	1			T34	1		T36	2		T19	2
all_levels[11]	211	1			T9	1		T34	1		T112	2
all_levels[12]	192	1			T9	1		T34	2		T112	2
all_levels[13]	174	1			T6	1		T34	1		T122	1
all_levels[14]	151	1			T6	1		T9	3		T36	2
all_levels[15]	157	1			T6	1		T9	2		T33	1
all_levels[16]	131	1			T33	1		T123	2		T40	1
all_levels[17]	116	1			T9	2		T34	1		T123	1
all_levels[18]	93	1			T33	1		T14	1		T122	2
all_levels[19]	85	1			T6	1		T122	1		T123	1
all_levels[20]	72	1			T124	2		T125	1		T126	1
all_levels[21]	68	1			T9	1		T122	1		T127	2
all_levels[22]	65	1			T33	1		T36	1		T127	2
all_levels[23]	58	1			T123	1		T128	1		T13	1
all_levels[24]	62	1			T19	1		T40	1		T127	1
all_levels[25]	54	1			T40	1		T129	1		T130	1
all_levels[26]	46	1			T112	3		T19	1		T130	1
all_levels[27]	56	1			T9	1		T33	1		T19	1
all_levels[28]	30	1			T33	1		T14	1		T131	1
all_levels[29]	49	1			T9	1		T14	1		T125	1
all_levels[30]	42	1			T9	1		T122	1		T132	1
all_levels[31]	36	1			T9	1		T19	1		T130	1
all_levels[32]	32	1			T9	3		T33	1		T14	1
all_levels[33]	38	1			T123	1		T13	1		T133	1
all_levels[34]	26	1			T19	1		T134	1		T100	1
all_levels[35]	17	1			T128	1		T127	1		T135	1
all_levels[36]	24	1			T33	1		T112	1		T14	1
all_levels[37]	34	1			T14	1		T122	1		T13	1
all_levels[38]	24	1			T135	1		T136	1		T47	1
all_levels[39]	16	1			T122	1		T40	2		T31	1
all_levels[40]	20	1			T137	1		T138	1		T139	1
all_levels[41]	19	1			T12	1		T13	1		T140	2
all_levels[42]	20	1			T40	1		T133	1		T135	1
all_levels[43]	16	1			T9	3		T13	1		T141	2
all_levels[44]	12	1			T9	1		T34	1		T142	1
all_levels[45]	14	1			T119	1		T143	1		T144	4
all_levels[46]	9	1			T12	1		T107	1		T145	1
all_levels[47]	25	1			T14	1		T40	1		T126	1
all_levels[48]	6	1			T146	1		T147	1		T148	1
all_levels[49]	8	1			T149	1		T150	1		T151	1
all_levels[50]	12	1			T34	1		T14	1		T12	1
all_levels[51]	4	1			T40	1		T152	1		T153	1
all_levels[52]	8	1			T154	1		T155	1		T156	1
all_levels[53]	7	1			T157	1		T158	2		T159	1
all_levels[54]	10	1			T160	1		T161	1		T139	1
all_levels[55]	10	1			T162	1		T163	2		T164	1
all_levels[56]	7	1			T13	1		T127	1		T165	1
all_levels[57]	7	1			T7	1		T166	4		T167	1
all_levels[58]	10	1			T125	1		T168	1		T31	1
all_levels[59]	11	1			T134	1		T169	1		T170	1
all_levels[60]	12	1			T160	1		T171	2		T142	1
all_levels[61]	6	1			T172	1		T173	1		T174	1
all_levels[62]	6	1			T137	1		T171	1		T108	1
all_levels[63]	14	1			T36	1		T30	1		T175	1
all_levels[64]	119	1			T12	1		T13	1		T127	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25164147

1

T1

101198

T3

38355

T6

72696

auto[1]

4920

1

T4

3

T7

26

T9

3

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	12	118	90.77	12

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[28]]	[auto[1]]	0	1	1
[all_levels[35]]	[auto[1]]	0	1	1
[all_levels[39]]	[auto[1]]	0	1	1
[all_levels[48] , all_levels[49]]	[auto[1]]	--	--	2
[all_levels[51] , all_levels[52]]	[auto[1]]	--	--	2
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[61] , all_levels[62] , all_levels[63]]	[auto[1]]	--	--	3

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	24968254	1			T1	99383		T3	36728		T6	72588
all_levels[0]	auto[1]	4419	1			T4	3		T7	26		T9	1
all_levels[1]	auto[0]	187127	1			T1	1815		T3	1627		T6	94
all_levels[1]	auto[1]	86	1			T176	3		T39	3		T177	2
all_levels[2]	auto[0]	2485	1			T6	3		T7	4		T9	1
all_levels[2]	auto[1]	29	1			T113	1		T129	1		T116	2
all_levels[3]	auto[0]	1072	1			T6	2		T7	2		T9	1
all_levels[3]	auto[1]	27	1			T178	1		T179	1		T180	1
all_levels[4]	auto[0]	754	1			T6	1		T7	1		T112	1
all_levels[4]	auto[1]	17	1			T181	2		T143	2		T46	1
all_levels[5]	auto[0]	569	1			T7	1		T9	1		T34	1
all_levels[5]	auto[1]	35	1			T34	1		T182	2		T183	1
all_levels[6]	auto[0]	408	1			T6	3		T14	2		T122	1
all_levels[6]	auto[1]	19	1			T184	1		T140	1		T185	1
all_levels[7]	auto[0]	377	1			T6	1		T36	1		T14	4
all_levels[7]	auto[1]	6	1			T186	1		T187	1		T188	1
all_levels[8]	auto[0]	305	1			T112	3		T36	1		T14	1
all_levels[8]	auto[1]	14	1			T189	1		T183	2		T190	1
all_levels[9]	auto[0]	262	1			T34	2		T112	1		T36	1
all_levels[9]	auto[1]	19	1			T182	2		T191	2		T192	1
all_levels[10]	auto[0]	215	1			T34	1		T36	1		T19	2
all_levels[10]	auto[1]	17	1			T36	1		T184	1		T193	3
all_levels[11]	auto[0]	198	1			T9	1		T34	1		T112	2
all_levels[11]	auto[1]	13	1			T138	1		T158	2		T194	1
all_levels[12]	auto[0]	174	1			T9	1		T34	2		T112	1
all_levels[12]	auto[1]	18	1			T112	1		T126	1		T195	2
all_levels[13]	auto[0]	152	1			T6	1		T34	1		T122	1
all_levels[13]	auto[1]	22	1			T113	1		T184	1		T196	1
all_levels[14]	auto[0]	134	1			T6	1		T9	1		T36	1
all_levels[14]	auto[1]	17	1			T9	2		T36	1		T124	1
all_levels[15]	auto[0]	150	1			T6	1		T9	2		T33	1
all_levels[15]	auto[1]	7	1			T197	1		T198	1		T199	1
all_levels[16]	auto[0]	120	1			T33	1		T123	2		T40	1
all_levels[16]	auto[1]	11	1			T196	1		T200	1		T201	2
all_levels[17]	auto[0]	106	1			T9	2		T34	1		T123	1
all_levels[17]	auto[1]	10	1			T184	2		T202	1		T96	1
all_levels[18]	auto[0]	86	1			T33	1		T14	1		T122	2
all_levels[18]	auto[1]	7	1			T203	1		T204	1		T205	1
all_levels[19]	auto[0]	80	1			T6	1		T122	1		T123	1
all_levels[19]	auto[1]	5	1			T111	1		T206	2		T163	1
all_levels[20]	auto[0]	68	1			T124	1		T125	1		T126	1
all_levels[20]	auto[1]	4	1			T124	1		T207	1		T208	1
all_levels[21]	auto[0]	60	1			T9	1		T122	1		T127	1
all_levels[21]	auto[1]	8	1			T127	1		T209	2		T210	1
all_levels[22]	auto[0]	64	1			T33	1		T36	1		T127	1
all_levels[22]	auto[1]	1	1			T127	1		-	-		-	-
all_levels[23]	auto[0]	54	1			T123	1		T128	1		T13	1
all_levels[23]	auto[1]	4	1			T170	1		T211	1		T212	1
all_levels[24]	auto[0]	55	1			T19	1		T40	1		T127	1
all_levels[24]	auto[1]	7	1			T213	1		T198	1		T167	1
all_levels[25]	auto[0]	47	1			T40	1		T129	1		T130	1
all_levels[25]	auto[1]	7	1			T214	1		T192	1		T215	2
all_levels[26]	auto[0]	42	1			T112	2		T19	1		T130	1
all_levels[26]	auto[1]	4	1			T112	1		T134	1		T216	1
all_levels[27]	auto[0]	53	1			T9	1		T33	1		T19	1
all_levels[27]	auto[1]	3	1			T217	1		T218	2		-	-
all_levels[28]	auto[0]	30	1			T33	1		T14	1		T131	1
all_levels[29]	auto[0]	42	1			T9	1		T14	1		T125	1
all_levels[29]	auto[1]	7	1			T219	3		T220	3		T221	1
all_levels[30]	auto[0]	36	1			T9	1		T122	1		T132	1
all_levels[30]	auto[1]	6	1			T162	3		T222	1		T223	2
all_levels[31]	auto[0]	31	1			T9	1		T19	1		T130	1
all_levels[31]	auto[1]	5	1			T224	3		T152	1		T225	1
all_levels[32]	auto[0]	27	1			T9	3		T33	1		T14	1
all_levels[32]	auto[1]	5	1			T226	2		T227	2		T228	1
all_levels[33]	auto[0]	36	1			T123	1		T13	1		T133	1
all_levels[33]	auto[1]	2	1			T229	1		T230	1		-	-
all_levels[34]	auto[0]	24	1			T19	1		T134	1		T100	1
all_levels[34]	auto[1]	2	1			T231	1		T232	1		-	-
all_levels[35]	auto[0]	17	1			T128	1		T127	1		T135	1
all_levels[36]	auto[0]	22	1			T33	1		T112	1		T14	1
all_levels[36]	auto[1]	2	1			T214	1		T233	1		-	-
all_levels[37]	auto[0]	30	1			T14	1		T122	1		T13	1
all_levels[37]	auto[1]	4	1			T234	1		T175	1		T235	1
all_levels[38]	auto[0]	19	1			T135	1		T136	1		T47	1
all_levels[38]	auto[1]	5	1			T236	2		T192	1		T237	2
all_levels[39]	auto[0]	16	1			T122	1		T40	2		T31	1
all_levels[40]	auto[0]	15	1			T137	1		T138	1		T139	1
all_levels[40]	auto[1]	5	1			T238	3		T239	2		-	-
all_levels[41]	auto[0]	16	1			T12	1		T13	1		T140	1
all_levels[41]	auto[1]	3	1			T140	1		T240	1		T241	1
all_levels[42]	auto[0]	18	1			T40	1		T133	1		T135	1
all_levels[42]	auto[1]	2	1			T188	1		T242	1		-	-
all_levels[43]	auto[0]	15	1			T9	3		T13	1		T141	1
all_levels[43]	auto[1]	1	1			T141	1		-	-		-	-
all_levels[44]	auto[0]	11	1			T9	1		T34	1		T142	1
all_levels[44]	auto[1]	1	1			T211	1		-	-		-	-
all_levels[45]	auto[0]	12	1			T119	1		T143	1		T144	2
all_levels[45]	auto[1]	2	1			T144	2		-	-		-	-
all_levels[46]	auto[0]	8	1			T12	1		T107	1		T145	1
all_levels[46]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[47]	auto[0]	20	1			T14	1		T40	1		T126	1
all_levels[47]	auto[1]	5	1			T244	3		T218	1		T245	1
all_levels[48]	auto[0]	6	1			T146	1		T147	1		T148	1
all_levels[49]	auto[0]	8	1			T149	1		T150	1		T151	1
all_levels[50]	auto[0]	11	1			T34	1		T14	1		T12	1
all_levels[50]	auto[1]	1	1			T235	1		-	-		-	-
all_levels[51]	auto[0]	4	1			T40	1		T152	1		T153	1
all_levels[52]	auto[0]	8	1			T154	1		T155	1		T156	1
all_levels[53]	auto[0]	6	1			T157	1		T158	1		T159	1
all_levels[53]	auto[1]	1	1			T158	1		-	-		-	-
all_levels[54]	auto[0]	10	1			T160	1		T161	1		T139	1
all_levels[55]	auto[0]	8	1			T162	1		T163	1		T164	1
all_levels[55]	auto[1]	2	1			T163	1		T246	1		-	-
all_levels[56]	auto[0]	7	1			T13	1		T127	1		T165	1
all_levels[57]	auto[0]	4	1			T7	1		T166	1		T167	1
all_levels[57]	auto[1]	3	1			T166	3		-	-		-	-
all_levels[58]	auto[0]	9	1			T125	1		T168	1		T31	1
all_levels[58]	auto[1]	1	1			T247	1		-	-		-	-
all_levels[59]	auto[0]	9	1			T134	1		T169	1		T170	1
all_levels[59]	auto[1]	2	1			T241	2		-	-		-	-
all_levels[60]	auto[0]	10	1			T160	1		T171	2		T142	1
all_levels[60]	auto[1]	2	1			T248	2		-	-		-	-
all_levels[61]	auto[0]	6	1			T172	1		T173	1		T174	1
all_levels[62]	auto[0]	6	1			T137	1		T171	1		T108	1
all_levels[63]	auto[0]	14	1			T36	1		T30	1		T175	1
all_levels[64]	auto[0]	105	1			T12	1		T13	1		T127	1
all_levels[64]	auto[1]	14	1			T175	1		T162	1		T249	1