Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	97086	1			T1	65		T2	2		T3	16
all_pins[1]	97086	1			T1	65		T2	2		T3	16
all_pins[2]	97086	1			T1	65		T2	2		T3	16
all_pins[3]	97086	1			T1	65		T2	2		T3	16
all_pins[4]	97086	1			T1	65		T2	2		T3	16
all_pins[5]	97086	1			T1	65		T2	2		T3	16
all_pins[6]	97086	1			T1	65		T2	2		T3	16
all_pins[7]	97086	1			T1	65		T2	2		T3	16
all_pins[8]	97086	1			T1	65		T2	2		T3	16

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	831316	1			T1	580		T2	18		T3	140
values[0x1]	42458	1			T1	5		T3	4		T4	1
transitions[0x0=>0x1]	33550	1			T1	4		T3	4		T4	1
transitions[0x1=>0x0]	33324	1			T1	3		T3	3		T6	77

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	77514	1			T1	63		T2	2		T3	15
all_pins[0]	values[0x1]	19572	1			T1	2		T3	1		T4	1
all_pins[0]	transitions[0x0=>0x1]	18907	1			T1	2		T3	1		T4	1
all_pins[0]	transitions[0x1=>0x0]	1151	1			T6	1		T9	10		T33	2
all_pins[1]	values[0x0]	95270	1			T1	65		T2	2		T3	16
all_pins[1]	values[0x1]	1816	1			T6	3		T7	1		T9	10
all_pins[1]	transitions[0x0=>0x1]	1698	1			T6	3		T7	1		T9	9
all_pins[1]	transitions[0x1=>0x0]	2553	1			T1	1		T3	2		T6	7
all_pins[2]	values[0x0]	94415	1			T1	64		T2	2		T3	14
all_pins[2]	values[0x1]	2671	1			T1	1		T3	2		T6	7
all_pins[2]	transitions[0x0=>0x1]	2601	1			T1	1		T3	2		T6	7
all_pins[2]	transitions[0x1=>0x0]	252	1			T6	1		T7	2		T12	1
all_pins[3]	values[0x0]	96764	1			T1	65		T2	2		T3	16
all_pins[3]	values[0x1]	322	1			T6	1		T7	2		T12	1
all_pins[3]	transitions[0x0=>0x1]	271	1			T6	1		T12	1		T15	3
all_pins[3]	transitions[0x1=>0x0]	473	1			T7	1		T14	3		T15	5
all_pins[4]	values[0x0]	96562	1			T1	65		T2	2		T3	16
all_pins[4]	values[0x1]	524	1			T7	3		T14	3		T15	5
all_pins[4]	transitions[0x0=>0x1]	445	1			T7	2		T15	5		T117	16
all_pins[4]	transitions[0x1=>0x0]	171	1			T6	1		T7	5		T14	1
all_pins[5]	values[0x0]	96836	1			T1	65		T2	2		T3	16
all_pins[5]	values[0x1]	250	1			T6	1		T7	6		T14	4
all_pins[5]	transitions[0x0=>0x1]	193	1			T7	5		T14	2		T26	1
all_pins[5]	transitions[0x1=>0x0]	863	1			T6	4		T7	3		T9	2
all_pins[6]	values[0x0]	96166	1			T1	65		T2	2		T3	16
all_pins[6]	values[0x1]	920	1			T6	5		T7	4		T9	2
all_pins[6]	transitions[0x0=>0x1]	875	1			T6	5		T7	4		T9	2
all_pins[6]	transitions[0x1=>0x0]	310	1			T7	5		T14	2		T19	1
all_pins[7]	values[0x0]	96731	1			T1	65		T2	2		T3	16
all_pins[7]	values[0x1]	355	1			T7	5		T14	2		T19	1
all_pins[7]	transitions[0x0=>0x1]	203	1			T7	3		T14	2		T19	1
all_pins[7]	transitions[0x1=>0x0]	15876	1			T1	2		T3	1		T6	47
all_pins[8]	values[0x0]	81058	1			T1	63		T2	2		T3	15
all_pins[8]	values[0x1]	16028	1			T1	2		T3	1		T6	47
all_pins[8]	transitions[0x0=>0x1]	8357	1			T1	1		T3	1		T6	44
all_pins[8]	transitions[0x1=>0x0]	11675	1			T6	16		T7	27		T9	9