Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6203840	1			T1	79		T3	24		T6	4542
all_levels[1]	1583270	1			T1	94		T3	20		T6	2919
all_levels[2]	248344	1			T1	76		T3	19		T6	1291
all_levels[3]	391378	1			T1	101		T3	19		T6	1334
all_levels[4]	311673	1			T1	90		T3	22		T6	1580
all_levels[5]	180343	1			T1	83		T3	23		T6	991
all_levels[6]	162154	1			T1	86		T3	22		T6	1486
all_levels[7]	245500	1			T1	88		T3	18		T6	1079
all_levels[8]	297209	1			T1	90		T3	24		T6	1434
all_levels[9]	158325	1			T1	89		T3	23		T6	1589
all_levels[10]	188905	1			T1	84		T3	24		T6	1087
all_levels[11]	201534	1			T1	90		T3	23		T6	1341
all_levels[12]	245663	1			T1	89		T3	18		T6	1410
all_levels[13]	342935	1			T1	83		T3	22		T6	1142
all_levels[14]	275017	1			T1	86		T3	27		T6	1382
all_levels[15]	163989	1			T1	91		T3	22		T6	1160
all_levels[16]	320433	1			T1	78		T3	24		T6	924
all_levels[17]	147418	1			T1	90		T3	18		T6	1014
all_levels[18]	171805	1			T1	82		T3	20		T6	1324
all_levels[19]	244236	1			T1	91		T3	20		T6	1314
all_levels[20]	723416	1			T1	96		T3	20		T6	1345
all_levels[21]	327939	1			T1	94		T3	20		T6	1690
all_levels[22]	358936	1			T1	88		T3	26		T6	1894
all_levels[23]	152330	1			T1	86		T3	23		T6	1585
all_levels[24]	158649	1			T1	89		T3	21		T6	1797
all_levels[25]	297404	1			T1	84		T3	22		T6	1572
all_levels[26]	287953	1			T1	82		T3	21		T6	1842
all_levels[27]	202943	1			T1	79		T3	22		T6	2787
all_levels[28]	173467	1			T1	85		T3	18		T6	1368
all_levels[29]	207299	1			T1	90		T3	23		T6	1471
all_levels[30]	467719	1			T1	85		T3	20		T6	1310
all_levels[31]	497809	1			T1	2244		T3	419		T6	2693
all_levels[32]	9228814	1			T1	96257		T3	37269		T6	21000

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25164147

1

T1

101198

T3

38355

T6

72696

auto[1]

4502

1

T1

1

T3

1

T6

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6201203	1			T1	79		T3	24		T6	4542
all_levels[0]	auto[1]	2637	1			T7	15		T9	1		T11	6
all_levels[1]	auto[0]	1582976	1			T1	94		T3	20		T6	2919
all_levels[1]	auto[1]	294	1			T9	2		T33	1		T34	1
all_levels[2]	auto[0]	248309	1			T1	76		T3	19		T6	1291
all_levels[2]	auto[1]	35	1			T123	1		T234	1		T313	1
all_levels[3]	auto[0]	391291	1			T1	101		T3	19		T6	1334
all_levels[3]	auto[1]	87	1			T7	2		T36	2		T115	2
all_levels[4]	auto[0]	311640	1			T1	90		T3	22		T6	1580
all_levels[4]	auto[1]	33	1			T114	1		T265	2		T177	2
all_levels[5]	auto[0]	180312	1			T1	83		T3	23		T6	991
all_levels[5]	auto[1]	31	1			T337	2		T144	2		T146	1
all_levels[6]	auto[0]	162124	1			T1	86		T3	22		T6	1486
all_levels[6]	auto[1]	30	1			T34	1		T127	1		T116	2
all_levels[7]	auto[0]	245345	1			T1	88		T3	18		T6	1079
all_levels[7]	auto[1]	155	1			T189	1		T117	6		T118	1
all_levels[8]	auto[0]	297190	1			T1	90		T3	24		T6	1434
all_levels[8]	auto[1]	19	1			T127	1		T253	1		T338	1
all_levels[9]	auto[0]	158288	1			T1	89		T3	23		T6	1589
all_levels[9]	auto[1]	37	1			T34	2		T219	2		T116	1
all_levels[10]	auto[0]	188875	1			T1	84		T3	24		T6	1087
all_levels[10]	auto[1]	30	1			T113	2		T278	1		T253	1
all_levels[11]	auto[0]	201496	1			T1	90		T3	23		T6	1341
all_levels[11]	auto[1]	38	1			T323	1		T202	1		T284	1
all_levels[12]	auto[0]	245627	1			T1	89		T3	18		T6	1410
all_levels[12]	auto[1]	36	1			T124	1		T214	1		T108	1
all_levels[13]	auto[0]	342921	1			T1	83		T3	22		T6	1142
all_levels[13]	auto[1]	14	1			T179	1		T141	1		T339	1
all_levels[14]	auto[0]	275002	1			T1	86		T3	27		T6	1382
all_levels[14]	auto[1]	15	1			T9	1		T169	1		T306	1
all_levels[15]	auto[0]	163858	1			T1	91		T3	22		T6	1160
all_levels[15]	auto[1]	131	1			T117	3		T280	1		T180	1
all_levels[16]	auto[0]	320418	1			T1	78		T3	24		T6	924
all_levels[16]	auto[1]	15	1			T14	1		T340	1		T238	1
all_levels[17]	auto[0]	147399	1			T1	90		T3	18		T6	1014
all_levels[17]	auto[1]	19	1			T182	3		T134	1		T169	1
all_levels[18]	auto[0]	171786	1			T1	82		T3	20		T6	1324
all_levels[18]	auto[1]	19	1			T179	1		T31	1		T46	2
all_levels[19]	auto[0]	244198	1			T1	91		T3	20		T6	1314
all_levels[19]	auto[1]	38	1			T40	1		T128	1		T152	1
all_levels[20]	auto[0]	723401	1			T1	96		T3	20		T6	1345
all_levels[20]	auto[1]	15	1			T34	1		T31	1		T213	2
all_levels[21]	auto[0]	327917	1			T1	94		T3	20		T6	1690
all_levels[21]	auto[1]	22	1			T177	2		T169	1		T141	1
all_levels[22]	auto[0]	358922	1			T1	88		T3	26		T6	1894
all_levels[22]	auto[1]	14	1			T270	1		T168	1		T341	1
all_levels[23]	auto[0]	152311	1			T1	86		T3	23		T6	1585
all_levels[23]	auto[1]	19	1			T253	1		T116	2		T181	2
all_levels[24]	auto[0]	158624	1			T1	89		T3	21		T6	1797
all_levels[24]	auto[1]	25	1			T265	1		T12	1		T278	1
all_levels[25]	auto[0]	297380	1			T1	84		T3	22		T6	1572
all_levels[25]	auto[1]	24	1			T113	1		T342	1		T138	1
all_levels[26]	auto[0]	287908	1			T1	82		T3	21		T6	1842
all_levels[26]	auto[1]	45	1			T258	5		T184	1		T254	3
all_levels[27]	auto[0]	202930	1			T1	79		T3	22		T6	2787
all_levels[27]	auto[1]	13	1			T11	2		T39	2		T266	1
all_levels[28]	auto[0]	173438	1			T1	85		T3	18		T6	1368
all_levels[28]	auto[1]	29	1			T262	1		T234	1		T268	2
all_levels[29]	auto[0]	207283	1			T1	90		T3	23		T6	1471
all_levels[29]	auto[1]	16	1			T343	1		T344	1		T345	1
all_levels[30]	auto[0]	467702	1			T1	85		T3	20		T6	1310
all_levels[30]	auto[1]	17	1			T9	1		T283	1		T312	1
all_levels[31]	auto[0]	497796	1			T1	2244		T3	419		T6	2693
all_levels[31]	auto[1]	13	1			T291	1		T162	2		T346	1
all_levels[32]	auto[0]	9228277	1			T1	96256		T3	37268		T6	20999
all_levels[32]	auto[1]	537	1			T1	1		T3	1		T6	1