Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	798	1			T6	4		T7	15		T14	7
all_values[1]	798	1			T6	4		T7	15		T14	7
all_values[2]	798	1			T6	4		T7	15		T14	7
all_values[3]	798	1			T6	4		T7	15		T14	7
all_values[4]	798	1			T6	4		T7	15		T14	7
all_values[5]	798	1			T6	4		T7	15		T14	7
all_values[6]	798	1			T6	4		T7	15		T14	7
all_values[7]	798	1			T6	4		T7	15		T14	7
all_values[8]	798	1			T6	4		T7	15		T14	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3834

1

T6

13

T7

77

T14

28

auto[1]

3348

1

T6

23

T7

58

T14

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2391

1

T6

13

T7

46

T14

15

auto[1]

4791

1

T6

23

T7

89

T14

48

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4238

1

T6

22

T7

78

T14

30

auto[1]

2944

1

T6

14

T7

57

T14

33

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	233	1			T6	2		T7	4		T26	2
all_values[0]	auto[0]	auto[1]	auto[1]	222	1			T6	2		T7	4		T14	3
all_values[0]	auto[1]	auto[0]	auto[1]	177	1			T7	5		T26	2		T30	1
all_values[0]	auto[1]	auto[1]	auto[1]	166	1			T7	2		T14	4		T26	2
all_values[1]	auto[0]	auto[0]	auto[0]	244	1			T6	1		T7	5		T14	2
all_values[1]	auto[0]	auto[1]	auto[0]	234	1			T6	1		T7	4		T14	2
all_values[1]	auto[1]	auto[0]	auto[1]	184	1			T7	4		T14	2		T30	2
all_values[1]	auto[1]	auto[1]	auto[1]	136	1			T6	2		T7	2		T14	1
all_values[2]	auto[0]	auto[0]	auto[0]	153	1			T6	1		T7	3		T26	2
all_values[2]	auto[0]	auto[0]	auto[1]	83	1			T14	1		T26	1		T30	1
all_values[2]	auto[0]	auto[1]	auto[0]	126	1			T6	3		T7	3		T26	1
all_values[2]	auto[0]	auto[1]	auto[1]	83	1			T7	5		T30	1		T31	2
all_values[2]	auto[1]	auto[0]	auto[1]	191	1			T14	3		T26	1		T28	2
all_values[2]	auto[1]	auto[1]	auto[1]	162	1			T7	4		T14	3		T26	2
all_values[3]	auto[0]	auto[0]	auto[0]	169	1			T7	8		T26	2		T28	1
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T6	1		T7	2		T14	1
all_values[3]	auto[0]	auto[1]	auto[0]	122	1			T7	1		T14	4		T26	2
all_values[3]	auto[0]	auto[1]	auto[1]	79	1			T28	1		T31	1		T119	2
all_values[3]	auto[1]	auto[0]	auto[1]	184	1			T6	1		T7	4		T14	2
all_values[3]	auto[1]	auto[1]	auto[1]	163	1			T6	2		T31	3		T119	4
all_values[4]	auto[0]	auto[0]	auto[0]	187	1			T6	2		T7	2		T26	5
all_values[4]	auto[0]	auto[0]	auto[1]	56	1			T119	1		T120	2		T107	1
all_values[4]	auto[0]	auto[1]	auto[0]	184	1			T6	1		T7	8		T26	1
all_values[4]	auto[0]	auto[1]	auto[1]	74	1			T14	1		T31	4		T120	1
all_values[4]	auto[1]	auto[0]	auto[1]	160	1			T7	3		T14	4		T28	2
all_values[4]	auto[1]	auto[1]	auto[1]	137	1			T6	1		T7	2		T14	2
all_values[5]	auto[0]	auto[0]	auto[0]	168	1			T6	1		T14	1		T26	1
all_values[5]	auto[0]	auto[0]	auto[1]	87	1			T6	1		T7	2		T26	1
all_values[5]	auto[0]	auto[1]	auto[0]	133	1			T7	2		T30	1		T31	5
all_values[5]	auto[0]	auto[1]	auto[1]	81	1			T7	1		T14	2		T28	2
all_values[5]	auto[1]	auto[0]	auto[1]	187	1			T6	1		T7	6		T14	1
all_values[5]	auto[1]	auto[1]	auto[1]	142	1			T6	1		T7	4		T14	3
all_values[6]	auto[0]	auto[0]	auto[0]	166	1			T7	3		T14	1		T26	2
all_values[6]	auto[0]	auto[0]	auto[1]	89	1			T7	3		T28	1		T30	1
all_values[6]	auto[0]	auto[1]	auto[0]	148	1			T26	1		T30	2		T31	6
all_values[6]	auto[0]	auto[1]	auto[1]	81	1			T6	1		T14	3		T31	3
all_values[6]	auto[1]	auto[0]	auto[1]	165	1			T7	6		T14	2		T28	1
all_values[6]	auto[1]	auto[1]	auto[1]	149	1			T6	3		T7	3		T14	1
all_values[7]	auto[0]	auto[0]	auto[0]	206	1			T7	5		T14	3		T26	3
all_values[7]	auto[0]	auto[0]	auto[1]	66	1			T28	1		T31	2		T120	1
all_values[7]	auto[0]	auto[1]	auto[0]	151	1			T6	3		T7	2		T14	2
all_values[7]	auto[0]	auto[1]	auto[1]	72	1			T7	3		T14	1		T26	1
all_values[7]	auto[1]	auto[0]	auto[1]	175	1			T6	1		T7	3		T14	1
all_values[7]	auto[1]	auto[1]	auto[1]	128	1			T7	2		T26	1		T28	2
all_values[8]	auto[0]	auto[0]	auto[1]	238	1			T7	5		T14	2		T26	4
all_values[8]	auto[0]	auto[1]	auto[1]	222	1			T6	2		T7	3		T14	1
all_values[8]	auto[1]	auto[0]	auto[1]	185	1			T6	1		T7	4		T14	2
all_values[8]	auto[1]	auto[1]	auto[1]	153	1			T6	1		T7	3		T14	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal