Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.50


Total test records in report: 1314
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
T65 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1621810640 Aug 08 04:28:57 PM PDT 24 Aug 08 04:28:58 PM PDT 24 16453883 ps
T1259 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.317443121 Aug 08 04:28:53 PM PDT 24 Aug 08 04:28:55 PM PDT 24 248482172 ps
T1260 /workspace/coverage/cover_reg_top/29.uart_intr_test.1341748928 Aug 08 04:29:22 PM PDT 24 Aug 08 04:29:22 PM PDT 24 86200324 ps
T1261 /workspace/coverage/cover_reg_top/1.uart_intr_test.2588878406 Aug 08 04:28:53 PM PDT 24 Aug 08 04:28:54 PM PDT 24 41315049 ps
T1262 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3903749561 Aug 08 04:28:55 PM PDT 24 Aug 08 04:28:56 PM PDT 24 16705002 ps
T1263 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.878193107 Aug 08 04:28:55 PM PDT 24 Aug 08 04:28:56 PM PDT 24 72063626 ps
T1264 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1178833459 Aug 08 04:28:54 PM PDT 24 Aug 08 04:28:56 PM PDT 24 341183226 ps
T1265 /workspace/coverage/cover_reg_top/14.uart_intr_test.3435927246 Aug 08 04:29:05 PM PDT 24 Aug 08 04:29:06 PM PDT 24 13589695 ps
T1266 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1875658956 Aug 08 04:28:57 PM PDT 24 Aug 08 04:29:00 PM PDT 24 55869972 ps
T1267 /workspace/coverage/cover_reg_top/41.uart_intr_test.797161806 Aug 08 04:29:23 PM PDT 24 Aug 08 04:29:24 PM PDT 24 23430577 ps
T1268 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.4248043893 Aug 08 04:29:09 PM PDT 24 Aug 08 04:29:10 PM PDT 24 51915084 ps
T1269 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1639933488 Aug 08 04:29:04 PM PDT 24 Aug 08 04:29:05 PM PDT 24 43131515 ps
T1270 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.4154388885 Aug 08 04:29:06 PM PDT 24 Aug 08 04:29:08 PM PDT 24 18793803 ps
T1271 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1342567795 Aug 08 04:29:39 PM PDT 24 Aug 08 04:29:40 PM PDT 24 80945571 ps
T1272 /workspace/coverage/cover_reg_top/19.uart_tl_errors.3767060740 Aug 08 04:29:25 PM PDT 24 Aug 08 04:29:27 PM PDT 24 560039047 ps
T1273 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.293170840 Aug 08 04:28:56 PM PDT 24 Aug 08 04:28:57 PM PDT 24 41910453 ps
T1274 /workspace/coverage/cover_reg_top/18.uart_tl_errors.146419562 Aug 08 04:29:21 PM PDT 24 Aug 08 04:29:23 PM PDT 24 123870109 ps
T66 /workspace/coverage/cover_reg_top/8.uart_csr_rw.437642672 Aug 08 04:29:06 PM PDT 24 Aug 08 04:29:07 PM PDT 24 52190810 ps
T1275 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2858318394 Aug 08 04:28:59 PM PDT 24 Aug 08 04:29:00 PM PDT 24 222908806 ps
T92 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1466679298 Aug 08 04:28:55 PM PDT 24 Aug 08 04:28:56 PM PDT 24 46998753 ps
T1276 /workspace/coverage/cover_reg_top/38.uart_intr_test.2242935740 Aug 08 04:29:24 PM PDT 24 Aug 08 04:29:24 PM PDT 24 18463199 ps
T1277 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1975983074 Aug 08 04:29:08 PM PDT 24 Aug 08 04:29:09 PM PDT 24 21679909 ps
T1278 /workspace/coverage/cover_reg_top/6.uart_intr_test.1432138638 Aug 08 04:28:54 PM PDT 24 Aug 08 04:28:55 PM PDT 24 15455833 ps
T67 /workspace/coverage/cover_reg_top/19.uart_csr_rw.2219671467 Aug 08 04:29:24 PM PDT 24 Aug 08 04:29:24 PM PDT 24 30477441 ps
T68 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.69918678 Aug 08 04:28:57 PM PDT 24 Aug 08 04:28:59 PM PDT 24 987274299 ps
T1279 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1064564630 Aug 08 04:29:10 PM PDT 24 Aug 08 04:29:11 PM PDT 24 100557338 ps
T1280 /workspace/coverage/cover_reg_top/17.uart_intr_test.4080188615 Aug 08 04:29:06 PM PDT 24 Aug 08 04:29:07 PM PDT 24 52609180 ps
T1281 /workspace/coverage/cover_reg_top/15.uart_tl_errors.981558134 Aug 08 04:29:07 PM PDT 24 Aug 08 04:29:08 PM PDT 24 74830580 ps
T1282 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3888646034 Aug 08 04:29:09 PM PDT 24 Aug 08 04:29:10 PM PDT 24 82179284 ps
T1283 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1797321287 Aug 08 04:28:59 PM PDT 24 Aug 08 04:28:59 PM PDT 24 48620230 ps
T1284 /workspace/coverage/cover_reg_top/0.uart_csr_rw.136591634 Aug 08 04:29:02 PM PDT 24 Aug 08 04:29:03 PM PDT 24 14240632 ps
T1285 /workspace/coverage/cover_reg_top/17.uart_tl_errors.2423102558 Aug 08 04:29:08 PM PDT 24 Aug 08 04:29:10 PM PDT 24 135439609 ps
T1286 /workspace/coverage/cover_reg_top/24.uart_intr_test.3430349052 Aug 08 04:29:21 PM PDT 24 Aug 08 04:29:22 PM PDT 24 15917625 ps
T1287 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2576121367 Aug 08 04:29:27 PM PDT 24 Aug 08 04:29:28 PM PDT 24 24293962 ps
T1288 /workspace/coverage/cover_reg_top/5.uart_intr_test.3836230174 Aug 08 04:29:02 PM PDT 24 Aug 08 04:29:02 PM PDT 24 14854157 ps
T1289 /workspace/coverage/cover_reg_top/18.uart_intr_test.1463661920 Aug 08 04:29:22 PM PDT 24 Aug 08 04:29:23 PM PDT 24 13803110 ps
T1290 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.618395443 Aug 08 04:29:00 PM PDT 24 Aug 08 04:29:01 PM PDT 24 92290485 ps
T1291 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1955946419 Aug 08 04:28:56 PM PDT 24 Aug 08 04:28:57 PM PDT 24 60991935 ps
T1292 /workspace/coverage/cover_reg_top/12.uart_intr_test.3964839796 Aug 08 04:29:06 PM PDT 24 Aug 08 04:29:06 PM PDT 24 16730442 ps
T1293 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2781943481 Aug 08 04:28:57 PM PDT 24 Aug 08 04:28:57 PM PDT 24 13126778 ps
T1294 /workspace/coverage/cover_reg_top/3.uart_intr_test.1167797763 Aug 08 04:28:52 PM PDT 24 Aug 08 04:28:53 PM PDT 24 21954085 ps
T1295 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1916840230 Aug 08 04:28:58 PM PDT 24 Aug 08 04:29:00 PM PDT 24 521513274 ps
T69 /workspace/coverage/cover_reg_top/17.uart_csr_rw.1450294484 Aug 08 04:29:28 PM PDT 24 Aug 08 04:29:29 PM PDT 24 39545354 ps
T1296 /workspace/coverage/cover_reg_top/7.uart_csr_rw.1271214057 Aug 08 04:28:52 PM PDT 24 Aug 08 04:28:53 PM PDT 24 13573419 ps
T1297 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1213839642 Aug 08 04:29:02 PM PDT 24 Aug 08 04:29:03 PM PDT 24 61928520 ps
T70 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1577900497 Aug 08 04:28:54 PM PDT 24 Aug 08 04:28:55 PM PDT 24 108602204 ps
T1298 /workspace/coverage/cover_reg_top/1.uart_csr_rw.4133627683 Aug 08 04:29:00 PM PDT 24 Aug 08 04:29:01 PM PDT 24 18968391 ps
T1299 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.897305488 Aug 08 04:29:09 PM PDT 24 Aug 08 04:29:10 PM PDT 24 109253238 ps
T1300 /workspace/coverage/cover_reg_top/3.uart_csr_rw.481660232 Aug 08 04:28:57 PM PDT 24 Aug 08 04:28:58 PM PDT 24 14464608 ps
T1301 /workspace/coverage/cover_reg_top/15.uart_csr_rw.3045384480 Aug 08 04:29:05 PM PDT 24 Aug 08 04:29:06 PM PDT 24 45078553 ps
T1302 /workspace/coverage/cover_reg_top/33.uart_intr_test.4244690015 Aug 08 04:29:23 PM PDT 24 Aug 08 04:29:23 PM PDT 24 29130474 ps
T1303 /workspace/coverage/cover_reg_top/43.uart_intr_test.3116005244 Aug 08 04:29:21 PM PDT 24 Aug 08 04:29:21 PM PDT 24 30243051 ps
T1304 /workspace/coverage/cover_reg_top/11.uart_tl_errors.4281811708 Aug 08 04:29:10 PM PDT 24 Aug 08 04:29:12 PM PDT 24 71243876 ps
T1305 /workspace/coverage/cover_reg_top/32.uart_intr_test.257086694 Aug 08 04:29:23 PM PDT 24 Aug 08 04:29:24 PM PDT 24 43981681 ps
T1306 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3408875804 Aug 08 04:28:56 PM PDT 24 Aug 08 04:28:58 PM PDT 24 512945021 ps
T1307 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2241181697 Aug 08 04:28:57 PM PDT 24 Aug 08 04:28:59 PM PDT 24 346813241 ps
T1308 /workspace/coverage/cover_reg_top/35.uart_intr_test.1816371528 Aug 08 04:29:21 PM PDT 24 Aug 08 04:29:22 PM PDT 24 13624373 ps
T1309 /workspace/coverage/cover_reg_top/16.uart_tl_errors.1362443708 Aug 08 04:29:06 PM PDT 24 Aug 08 04:29:08 PM PDT 24 138458867 ps
T1310 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.360357598 Aug 08 04:29:32 PM PDT 24 Aug 08 04:29:33 PM PDT 24 34841141 ps
T88 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.686781842 Aug 08 04:28:56 PM PDT 24 Aug 08 04:28:57 PM PDT 24 295651543 ps
T1311 /workspace/coverage/cover_reg_top/39.uart_intr_test.1267875081 Aug 08 04:29:25 PM PDT 24 Aug 08 04:29:26 PM PDT 24 13663714 ps
T1312 /workspace/coverage/cover_reg_top/9.uart_tl_errors.3875657720 Aug 08 04:29:07 PM PDT 24 Aug 08 04:29:09 PM PDT 24 62017355 ps
T1313 /workspace/coverage/cover_reg_top/21.uart_intr_test.2696111831 Aug 08 04:29:37 PM PDT 24 Aug 08 04:29:37 PM PDT 24 13730600 ps
T1314 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.4231242658 Aug 08 04:29:08 PM PDT 24 Aug 08 04:29:09 PM PDT 24 70556279 ps

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3075356596
Short name T7
Test name
Test status
Simulation time 136871352025 ps
CPU time 587.41 seconds
Started Aug 08 04:38:43 PM PDT 24
Finished Aug 08 04:48:31 PM PDT 24
Peak memory 224600 kb
Host smart-18aac71f-1282-4210-a435-dead67906396
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075356596 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3075356596
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_stress_all.2948304847
Short name T254
Test name
Test status
Simulation time 311883295765 ps
CPU time 1170.31 seconds
Started Aug 08 04:32:23 PM PDT 24
Finished Aug 08 04:51:53 PM PDT 24
Peak memory 199804 kb
Host smart-5e8c9daf-3e6f-44df-a57d-86354c42558d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948304847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2948304847
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1839822604
Short name T6
Test name
Test status
Simulation time 29538239407 ps
CPU time 362.38 seconds
Started Aug 08 04:32:35 PM PDT 24
Finished Aug 08 04:38:38 PM PDT 24
Peak memory 216212 kb
Host smart-970ba54e-cff6-4030-bbfc-c802f28e3471
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839822604 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1839822604
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.2662174539
Short name T14
Test name
Test status
Simulation time 451754867700 ps
CPU time 725.07 seconds
Started Aug 08 04:38:44 PM PDT 24
Finished Aug 08 04:50:49 PM PDT 24
Peak memory 216120 kb
Host smart-7be27cc5-4847-4f84-b274-a0f5b2cce1ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662174539 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2662174539
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all.2162130997
Short name T40
Test name
Test status
Simulation time 415967509555 ps
CPU time 89.62 seconds
Started Aug 08 04:31:51 PM PDT 24
Finished Aug 08 04:33:21 PM PDT 24
Peak memory 199712 kb
Host smart-5a5e884a-2a95-4669-bd77-6acac8f874c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162130997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2162130997
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all.3660081154
Short name T16
Test name
Test status
Simulation time 351971754346 ps
CPU time 685.61 seconds
Started Aug 08 04:38:09 PM PDT 24
Finished Aug 08 04:49:35 PM PDT 24
Peak memory 199756 kb
Host smart-6797675b-adc1-4313-b2f5-7a559b874607
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660081154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3660081154
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2219134016
Short name T13
Test name
Test status
Simulation time 231860221283 ps
CPU time 377.71 seconds
Started Aug 08 04:39:33 PM PDT 24
Finished Aug 08 04:45:51 PM PDT 24
Peak memory 216428 kb
Host smart-3d992e84-bf78-462e-95cc-444741774cbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219134016 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2219134016
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2614637953
Short name T125
Test name
Test status
Simulation time 367488670606 ps
CPU time 46.9 seconds
Started Aug 08 04:37:51 PM PDT 24
Finished Aug 08 04:38:38 PM PDT 24
Peak memory 199824 kb
Host smart-460513d1-2127-4662-98be-0ba479aa00b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614637953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2614637953
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_sec_cm.512099007
Short name T23
Test name
Test status
Simulation time 707264430 ps
CPU time 0.79 seconds
Started Aug 08 04:31:54 PM PDT 24
Finished Aug 08 04:31:55 PM PDT 24
Peak memory 217996 kb
Host smart-b0def29d-3857-4f0e-ac8b-3bbf0a1b2c69
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512099007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.512099007
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/41.uart_stress_all.2918139962
Short name T197
Test name
Test status
Simulation time 440442440162 ps
CPU time 293.31 seconds
Started Aug 08 04:37:15 PM PDT 24
Finished Aug 08 04:42:08 PM PDT 24
Peak memory 208084 kb
Host smart-7ce978c3-c00c-48d5-9b92-6036662e965d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918139962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2918139962
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2224368361
Short name T115
Test name
Test status
Simulation time 274722003329 ps
CPU time 110.38 seconds
Started Aug 08 04:40:42 PM PDT 24
Finished Aug 08 04:42:33 PM PDT 24
Peak memory 199780 kb
Host smart-3ddde539-9b9c-4183-b4a0-4b80a5105631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224368361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2224368361
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all.2684392105
Short name T374
Test name
Test status
Simulation time 273033793860 ps
CPU time 346.01 seconds
Started Aug 08 04:35:48 PM PDT 24
Finished Aug 08 04:41:34 PM PDT 24
Peak memory 199748 kb
Host smart-647bc4b3-724d-443d-9e7b-731e4d88e00a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684392105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2684392105
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3331743221
Short name T42
Test name
Test status
Simulation time 44539617528 ps
CPU time 937.92 seconds
Started Aug 08 04:38:45 PM PDT 24
Finished Aug 08 04:54:23 PM PDT 24
Peak memory 216280 kb
Host smart-05e053a3-bded-4f4b-a62c-b62936dd95fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331743221 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3331743221
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3666661662
Short name T119
Test name
Test status
Simulation time 95425538886 ps
CPU time 793.84 seconds
Started Aug 08 04:38:44 PM PDT 24
Finished Aug 08 04:51:58 PM PDT 24
Peak memory 216304 kb
Host smart-bc900998-5162-4cf7-8de2-f71202dad281
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666661662 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3666661662
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1463251117
Short name T109
Test name
Test status
Simulation time 529959562340 ps
CPU time 489.63 seconds
Started Aug 08 04:39:06 PM PDT 24
Finished Aug 08 04:47:16 PM PDT 24
Peak memory 224576 kb
Host smart-53f054cd-1f40-4eb5-9d55-5d65613db3eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463251117 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1463251117
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.57215416
Short name T87
Test name
Test status
Simulation time 348638293 ps
CPU time 1.3 seconds
Started Aug 08 04:29:01 PM PDT 24
Finished Aug 08 04:29:02 PM PDT 24
Peak memory 199568 kb
Host smart-74aad2c3-4e78-4090-b933-edb9ab415f77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57215416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.57215416
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/default/17.uart_alert_test.25203217
Short name T350
Test name
Test status
Simulation time 22562162 ps
CPU time 0.58 seconds
Started Aug 08 04:34:02 PM PDT 24
Finished Aug 08 04:34:03 PM PDT 24
Peak memory 195436 kb
Host smart-a3a9f91c-02d8-4054-ba3c-677602066e5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25203217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.25203217
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.4128414757
Short name T150
Test name
Test status
Simulation time 379126629191 ps
CPU time 1073.31 seconds
Started Aug 08 04:31:54 PM PDT 24
Finished Aug 08 04:49:48 PM PDT 24
Peak memory 224452 kb
Host smart-f0fbf731-ce20-48da-ad03-d2df00110eb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128414757 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.4128414757
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.2469382400
Short name T19
Test name
Test status
Simulation time 83585021911 ps
CPU time 216.17 seconds
Started Aug 08 04:32:05 PM PDT 24
Finished Aug 08 04:35:42 PM PDT 24
Peak memory 199728 kb
Host smart-db9a7f89-aaba-418c-a61a-db6f1e6ba7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469382400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2469382400
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1476927955
Short name T251
Test name
Test status
Simulation time 280651449671 ps
CPU time 114.3 seconds
Started Aug 08 04:34:13 PM PDT 24
Finished Aug 08 04:36:08 PM PDT 24
Peak memory 199796 kb
Host smart-44d3074a-870c-40f6-ba6b-af0d5b216040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476927955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1476927955
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_stress_all.1045535540
Short name T283
Test name
Test status
Simulation time 289633672641 ps
CPU time 62.3 seconds
Started Aug 08 04:33:51 PM PDT 24
Finished Aug 08 04:34:53 PM PDT 24
Peak memory 199748 kb
Host smart-54c7dda0-a1cb-479c-aec4-c1355208c8a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045535540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1045535540
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all.863059241
Short name T171
Test name
Test status
Simulation time 213583193161 ps
CPU time 118.65 seconds
Started Aug 08 04:35:53 PM PDT 24
Finished Aug 08 04:37:52 PM PDT 24
Peak memory 199732 kb
Host smart-2ef660cb-c36e-48eb-a68d-d4a0fbbbecc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863059241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.863059241
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all.1622384070
Short name T127
Test name
Test status
Simulation time 97889280364 ps
CPU time 945.17 seconds
Started Aug 08 04:35:14 PM PDT 24
Finished Aug 08 04:51:00 PM PDT 24
Peak memory 208136 kb
Host smart-e02c1ce9-5fcf-47a1-bfd5-ff2ac78c66af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622384070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1622384070
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.4112554839
Short name T9
Test name
Test status
Simulation time 51080321172 ps
CPU time 49.46 seconds
Started Aug 08 04:38:44 PM PDT 24
Finished Aug 08 04:39:34 PM PDT 24
Peak memory 199824 kb
Host smart-6b2df734-b150-4a8c-a17f-5aa8d65efa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112554839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.4112554839
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1577900497
Short name T70
Test name
Test status
Simulation time 108602204 ps
CPU time 0.61 seconds
Started Aug 08 04:28:54 PM PDT 24
Finished Aug 08 04:28:55 PM PDT 24
Peak memory 195564 kb
Host smart-4ae94fbc-52c2-48fb-8cb0-4a7bf1020b02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577900497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1577900497
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2345587152
Short name T81
Test name
Test status
Simulation time 53933796 ps
CPU time 0.67 seconds
Started Aug 08 04:28:57 PM PDT 24
Finished Aug 08 04:28:58 PM PDT 24
Peak memory 197104 kb
Host smart-a69ea3d3-2dde-488d-a6b9-ae0565b05d6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345587152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2345587152
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.4232279177
Short name T333
Test name
Test status
Simulation time 450311027932 ps
CPU time 1146.54 seconds
Started Aug 08 04:38:32 PM PDT 24
Finished Aug 08 04:57:38 PM PDT 24
Peak memory 232632 kb
Host smart-aec32289-8429-4794-bdfe-eeaa5a669adb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232279177 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.4232279177
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.4187828224
Short name T289
Test name
Test status
Simulation time 41379007688 ps
CPU time 24.22 seconds
Started Aug 08 04:34:42 PM PDT 24
Finished Aug 08 04:35:06 PM PDT 24
Peak memory 199836 kb
Host smart-0e524110-9c69-4c76-aeac-ae35a2773d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187828224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.4187828224
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.447864326
Short name T146
Test name
Test status
Simulation time 398506794909 ps
CPU time 1371.29 seconds
Started Aug 08 04:38:31 PM PDT 24
Finished Aug 08 05:01:23 PM PDT 24
Peak memory 226272 kb
Host smart-3d7cecc2-edcb-4bbb-997e-83b5e5933b74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447864326 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.447864326
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2309717791
Short name T31
Test name
Test status
Simulation time 719897416995 ps
CPU time 1334.96 seconds
Started Aug 08 04:38:43 PM PDT 24
Finished Aug 08 05:00:58 PM PDT 24
Peak memory 229164 kb
Host smart-b8dcd7a1-1030-42a2-a530-22d30799fd62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309717791 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2309717791
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1597712320
Short name T124
Test name
Test status
Simulation time 177267908687 ps
CPU time 267.2 seconds
Started Aug 08 04:40:58 PM PDT 24
Finished Aug 08 04:45:26 PM PDT 24
Peak memory 199780 kb
Host smart-1d14633e-f0b9-4f82-8d7b-2bbb5d1a4824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597712320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1597712320
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1145119246
Short name T134
Test name
Test status
Simulation time 366658469236 ps
CPU time 37.06 seconds
Started Aug 08 04:39:33 PM PDT 24
Finished Aug 08 04:40:10 PM PDT 24
Peak memory 199836 kb
Host smart-50e00735-a87e-4e67-933d-0eba15165f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145119246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1145119246
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1354279965
Short name T175
Test name
Test status
Simulation time 44522505996 ps
CPU time 36.08 seconds
Started Aug 08 04:39:41 PM PDT 24
Finished Aug 08 04:40:17 PM PDT 24
Peak memory 199840 kb
Host smart-28d22630-12a8-475e-b4d1-e5f6a24da601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354279965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1354279965
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3802772322
Short name T243
Test name
Test status
Simulation time 75111284744 ps
CPU time 222.83 seconds
Started Aug 08 04:40:35 PM PDT 24
Finished Aug 08 04:44:18 PM PDT 24
Peak memory 199768 kb
Host smart-4d65442b-96c2-4ad4-a80c-7f3f3673ca51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802772322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3802772322
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2874427704
Short name T172
Test name
Test status
Simulation time 27067560454 ps
CPU time 18.32 seconds
Started Aug 08 04:39:06 PM PDT 24
Finished Aug 08 04:39:24 PM PDT 24
Peak memory 199732 kb
Host smart-f76b6a49-0f09-4198-83e9-2bf01a8a04f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874427704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2874427704
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3353930678
Short name T248
Test name
Test status
Simulation time 34022810407 ps
CPU time 13.92 seconds
Started Aug 08 04:38:53 PM PDT 24
Finished Aug 08 04:39:07 PM PDT 24
Peak memory 199672 kb
Host smart-dbaf41c3-3225-425d-b33a-3fd8a2cf3796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353930678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3353930678
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.996234730
Short name T973
Test name
Test status
Simulation time 153147288259 ps
CPU time 22.22 seconds
Started Aug 08 04:39:39 PM PDT 24
Finished Aug 08 04:40:01 PM PDT 24
Peak memory 199768 kb
Host smart-1cba668e-2daf-4d85-adbf-29148aaeb2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996234730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.996234730
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1346462230
Short name T122
Test name
Test status
Simulation time 20601317899 ps
CPU time 32.97 seconds
Started Aug 08 04:34:30 PM PDT 24
Finished Aug 08 04:35:03 PM PDT 24
Peak memory 199784 kb
Host smart-b0a307de-4e41-4415-b682-253d995bde2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346462230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1346462230
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.26754209
Short name T276
Test name
Test status
Simulation time 25506971170 ps
CPU time 399.72 seconds
Started Aug 08 04:35:24 PM PDT 24
Finished Aug 08 04:42:04 PM PDT 24
Peak memory 215964 kb
Host smart-b461a529-2638-45fa-a037-806f43005370
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26754209 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.26754209
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.598552319
Short name T111
Test name
Test status
Simulation time 520926308773 ps
CPU time 1287.71 seconds
Started Aug 08 04:33:03 PM PDT 24
Finished Aug 08 04:54:31 PM PDT 24
Peak memory 226840 kb
Host smart-ef255bd0-1fb8-466c-a95e-3ae57da8492d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598552319 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.598552319
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1119188072
Short name T190
Test name
Test status
Simulation time 111986060465 ps
CPU time 170.47 seconds
Started Aug 08 04:39:18 PM PDT 24
Finished Aug 08 04:42:09 PM PDT 24
Peak memory 199712 kb
Host smart-6de98372-6be4-4414-8dea-ec9a7c1c9f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119188072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1119188072
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.4006167314
Short name T540
Test name
Test status
Simulation time 16836763300 ps
CPU time 31.35 seconds
Started Aug 08 04:39:52 PM PDT 24
Finished Aug 08 04:40:23 PM PDT 24
Peak memory 199700 kb
Host smart-f2c05ea2-21aa-44e7-900a-5773179766fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006167314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.4006167314
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_stress_all.453056320
Short name T192
Test name
Test status
Simulation time 267057407077 ps
CPU time 377.15 seconds
Started Aug 08 04:38:22 PM PDT 24
Finished Aug 08 04:44:39 PM PDT 24
Peak memory 199820 kb
Host smart-84d2701a-1dea-4fcf-bd76-4c0c889af80c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453056320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.453056320
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.732233656
Short name T121
Test name
Test status
Simulation time 137583595 ps
CPU time 1.37 seconds
Started Aug 08 04:29:03 PM PDT 24
Finished Aug 08 04:29:05 PM PDT 24
Peak memory 199740 kb
Host smart-65636576-f4e5-46b3-a75e-858ca3355e92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732233656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.732233656
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1127325067
Short name T188
Test name
Test status
Simulation time 45004467280 ps
CPU time 83.83 seconds
Started Aug 08 04:39:19 PM PDT 24
Finished Aug 08 04:40:43 PM PDT 24
Peak memory 199784 kb
Host smart-bf2918a4-afe7-48f7-afb3-257af0dee23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127325067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1127325067
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.331941794
Short name T211
Test name
Test status
Simulation time 118982158349 ps
CPU time 92.62 seconds
Started Aug 08 04:39:35 PM PDT 24
Finished Aug 08 04:41:08 PM PDT 24
Peak memory 199744 kb
Host smart-c69d6340-696d-4ec5-98b7-66d599802ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331941794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.331941794
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.324871790
Short name T207
Test name
Test status
Simulation time 211526043854 ps
CPU time 309.24 seconds
Started Aug 08 04:39:36 PM PDT 24
Finished Aug 08 04:44:46 PM PDT 24
Peak memory 199716 kb
Host smart-a985268a-20bd-40d6-97b5-f253d1871aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324871790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.324871790
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1680163677
Short name T491
Test name
Test status
Simulation time 161044531989 ps
CPU time 232.88 seconds
Started Aug 08 04:33:51 PM PDT 24
Finished Aug 08 04:37:44 PM PDT 24
Peak memory 199732 kb
Host smart-56630658-bdf3-4073-8531-e406c9e7cf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680163677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1680163677
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1419427371
Short name T218
Test name
Test status
Simulation time 30620691032 ps
CPU time 26.54 seconds
Started Aug 08 04:39:39 PM PDT 24
Finished Aug 08 04:40:05 PM PDT 24
Peak memory 199688 kb
Host smart-c31e6711-afe2-4e8a-9d72-7914f1611695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419427371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1419427371
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3820588992
Short name T213
Test name
Test status
Simulation time 41544671076 ps
CPU time 23.74 seconds
Started Aug 08 04:39:45 PM PDT 24
Finished Aug 08 04:40:09 PM PDT 24
Peak memory 199752 kb
Host smart-325a70b2-98f5-4e38-81c4-10dceb2af83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820588992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3820588992
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2442479352
Short name T226
Test name
Test status
Simulation time 25541288578 ps
CPU time 14.65 seconds
Started Aug 08 04:34:02 PM PDT 24
Finished Aug 08 04:34:17 PM PDT 24
Peak memory 199800 kb
Host smart-183fe842-8ef9-472e-bffc-6b00d1f36c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442479352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2442479352
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3297807042
Short name T234
Test name
Test status
Simulation time 458455264570 ps
CPU time 81.76 seconds
Started Aug 08 04:39:49 PM PDT 24
Finished Aug 08 04:41:11 PM PDT 24
Peak memory 200104 kb
Host smart-fb0b91e3-ed43-4567-afce-8521ff87be73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297807042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3297807042
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2268487342
Short name T162
Test name
Test status
Simulation time 32905419160 ps
CPU time 27.14 seconds
Started Aug 08 04:38:33 PM PDT 24
Finished Aug 08 04:39:01 PM PDT 24
Peak memory 199696 kb
Host smart-e9e72f0f-8750-4374-81a3-67de2b7b5d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268487342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2268487342
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1517392854
Short name T241
Test name
Test status
Simulation time 70707009248 ps
CPU time 37.76 seconds
Started Aug 08 04:38:42 PM PDT 24
Finished Aug 08 04:39:20 PM PDT 24
Peak memory 199796 kb
Host smart-ebedacdf-b6e1-496b-bb84-c8ebb9d21140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517392854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1517392854
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_smoke.1530083490
Short name T423
Test name
Test status
Simulation time 5733291983 ps
CPU time 22.72 seconds
Started Aug 08 04:31:52 PM PDT 24
Finished Aug 08 04:32:15 PM PDT 24
Peak memory 199048 kb
Host smart-9a8915d2-0e27-4bf6-a308-8a578fd5d53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530083490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1530083490
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2784451208
Short name T256
Test name
Test status
Simulation time 55197212806 ps
CPU time 108.62 seconds
Started Aug 08 04:33:09 PM PDT 24
Finished Aug 08 04:34:58 PM PDT 24
Peak memory 199796 kb
Host smart-8e6a1105-b54c-4fdb-a129-faecb15c5be8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2784451208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2784451208
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.667234467
Short name T823
Test name
Test status
Simulation time 35807227747 ps
CPU time 27.83 seconds
Started Aug 08 04:39:05 PM PDT 24
Finished Aug 08 04:39:33 PM PDT 24
Peak memory 199816 kb
Host smart-ab4e483c-8679-438b-85fe-7166f3f32db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667234467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.667234467
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1919298854
Short name T128
Test name
Test status
Simulation time 80477159164 ps
CPU time 44.63 seconds
Started Aug 08 04:39:18 PM PDT 24
Finished Aug 08 04:40:03 PM PDT 24
Peak memory 199640 kb
Host smart-6ec3f18a-14fa-40b5-a97b-3d7ea99ad64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919298854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1919298854
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_smoke.2234928478
Short name T275
Test name
Test status
Simulation time 91934027 ps
CPU time 1.03 seconds
Started Aug 08 04:33:15 PM PDT 24
Finished Aug 08 04:33:16 PM PDT 24
Peak memory 199172 kb
Host smart-18f81d7e-cdd4-49ab-b4a7-77d891797026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234928478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2234928478
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.653997756
Short name T141
Test name
Test status
Simulation time 140880881005 ps
CPU time 65.52 seconds
Started Aug 08 04:39:18 PM PDT 24
Finished Aug 08 04:40:23 PM PDT 24
Peak memory 199748 kb
Host smart-6a2d5b40-a444-459c-863b-c9fe05de76bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653997756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.653997756
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2067457085
Short name T225
Test name
Test status
Simulation time 48044195325 ps
CPU time 76.53 seconds
Started Aug 08 04:39:18 PM PDT 24
Finished Aug 08 04:40:35 PM PDT 24
Peak memory 199756 kb
Host smart-ad6abf7f-e2ce-48b5-aafb-8657549b11a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067457085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2067457085
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.83645221
Short name T231
Test name
Test status
Simulation time 9936608032 ps
CPU time 15.34 seconds
Started Aug 08 04:39:30 PM PDT 24
Finished Aug 08 04:39:46 PM PDT 24
Peak memory 199708 kb
Host smart-ee378cfc-e1b2-47f0-a0bc-9994f68f8f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83645221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.83645221
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.4002007577
Short name T247
Test name
Test status
Simulation time 107253090101 ps
CPU time 45.36 seconds
Started Aug 08 04:33:50 PM PDT 24
Finished Aug 08 04:34:35 PM PDT 24
Peak memory 199832 kb
Host smart-6d4598c0-f363-4e34-a57e-5285fed88b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002007577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.4002007577
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1383184920
Short name T144
Test name
Test status
Simulation time 67153640447 ps
CPU time 36.8 seconds
Started Aug 08 04:34:14 PM PDT 24
Finished Aug 08 04:34:51 PM PDT 24
Peak memory 199840 kb
Host smart-fbdc05e3-53bf-4a94-9c87-206a5f40c08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383184920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1383184920
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.404349221
Short name T1043
Test name
Test status
Simulation time 23264738592 ps
CPU time 65.79 seconds
Started Aug 08 04:39:50 PM PDT 24
Finished Aug 08 04:40:56 PM PDT 24
Peak memory 199768 kb
Host smart-9a693f83-6af3-4288-89fe-1de5943b0312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404349221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.404349221
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.420112224
Short name T158
Test name
Test status
Simulation time 39427703623 ps
CPU time 17.13 seconds
Started Aug 08 04:40:00 PM PDT 24
Finished Aug 08 04:40:18 PM PDT 24
Peak memory 199728 kb
Host smart-56e7ef66-9681-4083-a1d2-385771bd3d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420112224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.420112224
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.4186149551
Short name T214
Test name
Test status
Simulation time 53048216580 ps
CPU time 19.92 seconds
Started Aug 08 04:40:12 PM PDT 24
Finished Aug 08 04:40:32 PM PDT 24
Peak memory 199700 kb
Host smart-94233335-5904-491d-b7d7-700d99f0a76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186149551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.4186149551
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.4180838623
Short name T239
Test name
Test status
Simulation time 143049656787 ps
CPU time 150.88 seconds
Started Aug 08 04:40:21 PM PDT 24
Finished Aug 08 04:42:52 PM PDT 24
Peak memory 199768 kb
Host smart-a7e497ed-84bc-4511-8c6a-918321e39404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180838623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.4180838623
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.363744031
Short name T229
Test name
Test status
Simulation time 26729402310 ps
CPU time 33.37 seconds
Started Aug 08 04:40:24 PM PDT 24
Finished Aug 08 04:40:58 PM PDT 24
Peak memory 199808 kb
Host smart-69a2a846-580c-44d7-989e-d3b4bc6bafde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363744031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.363744031
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2658316692
Short name T246
Test name
Test status
Simulation time 33268717707 ps
CPU time 32.09 seconds
Started Aug 08 04:41:02 PM PDT 24
Finished Aug 08 04:41:34 PM PDT 24
Peak memory 199912 kb
Host smart-d373f53e-717e-4104-b8dd-2317fc7d7c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658316692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2658316692
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.872046803
Short name T219
Test name
Test status
Simulation time 57535610337 ps
CPU time 219.66 seconds
Started Aug 08 04:32:05 PM PDT 24
Finished Aug 08 04:35:45 PM PDT 24
Peak memory 199812 kb
Host smart-a42286b3-0b5e-4230-bf1b-a610803376bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872046803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.872046803
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2024065288
Short name T166
Test name
Test status
Simulation time 135573257088 ps
CPU time 54.52 seconds
Started Aug 08 04:37:53 PM PDT 24
Finished Aug 08 04:38:48 PM PDT 24
Peak memory 199744 kb
Host smart-41839060-1e37-48e4-a410-ea1e701c55e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024065288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2024065288
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1798864159
Short name T235
Test name
Test status
Simulation time 37648432006 ps
CPU time 36.68 seconds
Started Aug 08 04:38:58 PM PDT 24
Finished Aug 08 04:39:35 PM PDT 24
Peak memory 199680 kb
Host smart-cba7b84a-e531-4d9b-8330-ef45e0794499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798864159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1798864159
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.502219547
Short name T1250
Test name
Test status
Simulation time 19067691 ps
CPU time 0.63 seconds
Started Aug 08 04:28:55 PM PDT 24
Finished Aug 08 04:28:56 PM PDT 24
Peak memory 195312 kb
Host smart-c17673ee-2516-4c5e-8a75-fb1c2d68157d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502219547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.502219547
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.317443121
Short name T1259
Test name
Test status
Simulation time 248482172 ps
CPU time 2.22 seconds
Started Aug 08 04:28:53 PM PDT 24
Finished Aug 08 04:28:55 PM PDT 24
Peak memory 197940 kb
Host smart-c28ad1ac-7423-4f10-9b41-6be4c135f8fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317443121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.317443121
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1378417636
Short name T1233
Test name
Test status
Simulation time 143790571 ps
CPU time 0.72 seconds
Started Aug 08 04:28:59 PM PDT 24
Finished Aug 08 04:28:59 PM PDT 24
Peak memory 198044 kb
Host smart-cae5c214-118c-4cff-9dd0-8fc0e44b02d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378417636 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1378417636
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.136591634
Short name T1284
Test name
Test status
Simulation time 14240632 ps
CPU time 0.61 seconds
Started Aug 08 04:29:02 PM PDT 24
Finished Aug 08 04:29:03 PM PDT 24
Peak memory 195616 kb
Host smart-4157c931-1782-4960-94f8-00a1833f55e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136591634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.136591634
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1257611683
Short name T1228
Test name
Test status
Simulation time 33240828 ps
CPU time 0.58 seconds
Started Aug 08 04:28:59 PM PDT 24
Finished Aug 08 04:29:00 PM PDT 24
Peak memory 194564 kb
Host smart-07b8ed00-cab4-4ee0-8a6c-261f7f85d964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257611683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1257611683
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3292635807
Short name T1238
Test name
Test status
Simulation time 399105934 ps
CPU time 1.14 seconds
Started Aug 08 04:28:53 PM PDT 24
Finished Aug 08 04:28:55 PM PDT 24
Peak memory 200200 kb
Host smart-65b7bffc-a1b1-4ea2-ae2c-cc81f7ecaee5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292635807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3292635807
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2195748717
Short name T93
Test name
Test status
Simulation time 705335699 ps
CPU time 0.93 seconds
Started Aug 08 04:28:58 PM PDT 24
Finished Aug 08 04:28:59 PM PDT 24
Peak memory 199180 kb
Host smart-16fee05c-7a41-458c-8a98-574bab153c31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195748717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2195748717
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1621810640
Short name T65
Test name
Test status
Simulation time 16453883 ps
CPU time 0.78 seconds
Started Aug 08 04:28:57 PM PDT 24
Finished Aug 08 04:28:58 PM PDT 24
Peak memory 197024 kb
Host smart-e737f625-90c2-4fcf-878f-d4653cff5899
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621810640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1621810640
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3408875804
Short name T1306
Test name
Test status
Simulation time 512945021 ps
CPU time 1.45 seconds
Started Aug 08 04:28:56 PM PDT 24
Finished Aug 08 04:28:58 PM PDT 24
Peak memory 197824 kb
Host smart-6801e4e7-0a77-4e61-975b-86f7536c7d6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408875804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3408875804
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2781943481
Short name T1293
Test name
Test status
Simulation time 13126778 ps
CPU time 0.59 seconds
Started Aug 08 04:28:57 PM PDT 24
Finished Aug 08 04:28:57 PM PDT 24
Peak memory 195592 kb
Host smart-607aa2c2-bea7-44e8-afb5-1a56360f1cb3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781943481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2781943481
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1797321287
Short name T1283
Test name
Test status
Simulation time 48620230 ps
CPU time 0.64 seconds
Started Aug 08 04:28:59 PM PDT 24
Finished Aug 08 04:28:59 PM PDT 24
Peak memory 197468 kb
Host smart-d020aaf1-ad74-4e35-8ac0-7f6283041960
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797321287 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1797321287
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.4133627683
Short name T1298
Test name
Test status
Simulation time 18968391 ps
CPU time 0.55 seconds
Started Aug 08 04:29:00 PM PDT 24
Finished Aug 08 04:29:01 PM PDT 24
Peak memory 195744 kb
Host smart-ec1dd343-7bbf-48e5-a79b-9b4f923242a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133627683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.4133627683
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2588878406
Short name T1261
Test name
Test status
Simulation time 41315049 ps
CPU time 0.59 seconds
Started Aug 08 04:28:53 PM PDT 24
Finished Aug 08 04:28:54 PM PDT 24
Peak memory 194564 kb
Host smart-2952e959-a285-4342-a5fb-87d7471e2be4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588878406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2588878406
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1203135286
Short name T79
Test name
Test status
Simulation time 28845330 ps
CPU time 0.82 seconds
Started Aug 08 04:28:53 PM PDT 24
Finished Aug 08 04:28:54 PM PDT 24
Peak memory 196328 kb
Host smart-f820bc6a-2cff-4f46-aaa8-8c164911536c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203135286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1203135286
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2651894036
Short name T1198
Test name
Test status
Simulation time 520715302 ps
CPU time 2.22 seconds
Started Aug 08 04:28:55 PM PDT 24
Finished Aug 08 04:28:58 PM PDT 24
Peak memory 200212 kb
Host smart-e58a6745-1bbd-483f-ab51-fd699ff7630f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651894036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2651894036
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.293170840
Short name T1273
Test name
Test status
Simulation time 41910453 ps
CPU time 0.96 seconds
Started Aug 08 04:28:56 PM PDT 24
Finished Aug 08 04:28:57 PM PDT 24
Peak memory 199296 kb
Host smart-89ff5ca5-e142-4b12-b784-7b93967f2c8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293170840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.293170840
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.897305488
Short name T1299
Test name
Test status
Simulation time 109253238 ps
CPU time 0.87 seconds
Started Aug 08 04:29:09 PM PDT 24
Finished Aug 08 04:29:10 PM PDT 24
Peak memory 200000 kb
Host smart-a15e484d-37e5-41b8-a975-d2d5fb2a3998
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897305488 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.897305488
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3411646786
Short name T1220
Test name
Test status
Simulation time 34026519 ps
CPU time 0.57 seconds
Started Aug 08 04:29:09 PM PDT 24
Finished Aug 08 04:29:09 PM PDT 24
Peak memory 195572 kb
Host smart-d3d7137c-1eea-4bcf-9325-ca67f9b9df8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411646786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3411646786
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.173263465
Short name T1194
Test name
Test status
Simulation time 49159176 ps
CPU time 0.59 seconds
Started Aug 08 04:29:06 PM PDT 24
Finished Aug 08 04:29:07 PM PDT 24
Peak memory 194572 kb
Host smart-dddb3b83-fd01-4ac7-8732-ff89ba750895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173263465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.173263465
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.55761520
Short name T78
Test name
Test status
Simulation time 59881515 ps
CPU time 0.73 seconds
Started Aug 08 04:29:10 PM PDT 24
Finished Aug 08 04:29:11 PM PDT 24
Peak memory 197140 kb
Host smart-8006e34e-ca01-4ba7-b6e2-0d138472632a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55761520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_
outstanding.55761520
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3269453507
Short name T1187
Test name
Test status
Simulation time 38586332 ps
CPU time 1.83 seconds
Started Aug 08 04:29:08 PM PDT 24
Finished Aug 08 04:29:10 PM PDT 24
Peak memory 200248 kb
Host smart-5c113835-7eeb-43a4-88d3-8e98ba954300
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269453507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3269453507
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.4231242658
Short name T1314
Test name
Test status
Simulation time 70556279 ps
CPU time 0.95 seconds
Started Aug 08 04:29:08 PM PDT 24
Finished Aug 08 04:29:09 PM PDT 24
Peak memory 199300 kb
Host smart-6d4edb6d-4827-4c84-a690-ef5159c2e5cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231242658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.4231242658
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.4154388885
Short name T1270
Test name
Test status
Simulation time 18793803 ps
CPU time 1.05 seconds
Started Aug 08 04:29:06 PM PDT 24
Finished Aug 08 04:29:08 PM PDT 24
Peak memory 200004 kb
Host smart-21fc1022-b4f0-4f55-ae8b-393e603ac614
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154388885 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.4154388885
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2359748899
Short name T1243
Test name
Test status
Simulation time 29717394 ps
CPU time 0.62 seconds
Started Aug 08 04:29:06 PM PDT 24
Finished Aug 08 04:29:07 PM PDT 24
Peak memory 195640 kb
Host smart-a50fbf7a-e035-47d0-9ad0-f79ee6923949
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359748899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2359748899
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.515283874
Short name T1191
Test name
Test status
Simulation time 12266864 ps
CPU time 0.58 seconds
Started Aug 08 04:29:07 PM PDT 24
Finished Aug 08 04:29:07 PM PDT 24
Peak memory 194604 kb
Host smart-2cdc3f78-c14a-477f-85af-f5c3e5cf6540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515283874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.515283874
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3216843475
Short name T1254
Test name
Test status
Simulation time 23856631 ps
CPU time 0.72 seconds
Started Aug 08 04:29:08 PM PDT 24
Finished Aug 08 04:29:08 PM PDT 24
Peak memory 194844 kb
Host smart-41731d0d-4f7e-4236-bca2-49aa511b284c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216843475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3216843475
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.4281811708
Short name T1304
Test name
Test status
Simulation time 71243876 ps
CPU time 1.16 seconds
Started Aug 08 04:29:10 PM PDT 24
Finished Aug 08 04:29:12 PM PDT 24
Peak memory 200292 kb
Host smart-0bb850b2-d2fb-4bae-9b4d-593517686b1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281811708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.4281811708
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3961068416
Short name T1202
Test name
Test status
Simulation time 47004038 ps
CPU time 0.81 seconds
Started Aug 08 04:29:06 PM PDT 24
Finished Aug 08 04:29:07 PM PDT 24
Peak memory 199952 kb
Host smart-2a2800af-9021-4c4d-b8bb-2166abf38dd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961068416 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3961068416
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3422678948
Short name T72
Test name
Test status
Simulation time 134026764 ps
CPU time 0.59 seconds
Started Aug 08 04:29:07 PM PDT 24
Finished Aug 08 04:29:07 PM PDT 24
Peak memory 195628 kb
Host smart-84ddc006-9a1a-4da2-a310-8d0314fecafa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422678948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3422678948
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3964839796
Short name T1292
Test name
Test status
Simulation time 16730442 ps
CPU time 0.56 seconds
Started Aug 08 04:29:06 PM PDT 24
Finished Aug 08 04:29:06 PM PDT 24
Peak memory 194596 kb
Host smart-8b6b925c-d84a-4ffd-8ddc-ec673228e499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964839796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3964839796
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1064564630
Short name T1279
Test name
Test status
Simulation time 100557338 ps
CPU time 0.78 seconds
Started Aug 08 04:29:10 PM PDT 24
Finished Aug 08 04:29:11 PM PDT 24
Peak memory 196060 kb
Host smart-d9ea933c-f9d3-4875-8429-4aa6104791d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064564630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1064564630
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1213839642
Short name T1297
Test name
Test status
Simulation time 61928520 ps
CPU time 0.87 seconds
Started Aug 08 04:29:02 PM PDT 24
Finished Aug 08 04:29:03 PM PDT 24
Peak memory 199872 kb
Host smart-be34b277-be90-4e98-891e-c1917f49a3cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213839642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1213839642
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3556859882
Short name T1207
Test name
Test status
Simulation time 40969376 ps
CPU time 0.91 seconds
Started Aug 08 04:29:10 PM PDT 24
Finished Aug 08 04:29:11 PM PDT 24
Peak memory 198740 kb
Host smart-ed41a57a-097a-4a28-80f0-e6d6751a7d97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556859882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3556859882
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2500441334
Short name T1247
Test name
Test status
Simulation time 13748591 ps
CPU time 0.63 seconds
Started Aug 08 04:29:08 PM PDT 24
Finished Aug 08 04:29:08 PM PDT 24
Peak memory 197792 kb
Host smart-3e7c7a02-7743-41a9-ae4a-b7f96617924a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500441334 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2500441334
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3147757021
Short name T1252
Test name
Test status
Simulation time 27270010 ps
CPU time 0.59 seconds
Started Aug 08 04:29:07 PM PDT 24
Finished Aug 08 04:29:08 PM PDT 24
Peak memory 195600 kb
Host smart-727ed3e6-24b1-46d3-99c9-24d57efe31b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147757021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3147757021
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2030516021
Short name T1201
Test name
Test status
Simulation time 29500325 ps
CPU time 0.57 seconds
Started Aug 08 04:29:08 PM PDT 24
Finished Aug 08 04:29:08 PM PDT 24
Peak memory 194584 kb
Host smart-b74b5d3a-455c-43a4-9d3d-c3103711b17e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030516021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2030516021
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3537898149
Short name T1225
Test name
Test status
Simulation time 52048199 ps
CPU time 0.73 seconds
Started Aug 08 04:29:06 PM PDT 24
Finished Aug 08 04:29:07 PM PDT 24
Peak memory 196216 kb
Host smart-b3901b8b-09bf-46cd-a62c-43a092b6e2fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537898149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3537898149
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3152042709
Short name T1230
Test name
Test status
Simulation time 824236428 ps
CPU time 2.17 seconds
Started Aug 08 04:29:10 PM PDT 24
Finished Aug 08 04:29:12 PM PDT 24
Peak memory 200248 kb
Host smart-4c0cef04-e2ae-45ba-89d5-bf1cb15c6326
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152042709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3152042709
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.4248043893
Short name T1268
Test name
Test status
Simulation time 51915084 ps
CPU time 0.92 seconds
Started Aug 08 04:29:09 PM PDT 24
Finished Aug 08 04:29:10 PM PDT 24
Peak memory 199184 kb
Host smart-64b9a26e-b568-49b0-a357-6b8d9eaa1d3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248043893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.4248043893
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.426712918
Short name T1227
Test name
Test status
Simulation time 100260622 ps
CPU time 0.87 seconds
Started Aug 08 04:29:07 PM PDT 24
Finished Aug 08 04:29:08 PM PDT 24
Peak memory 200052 kb
Host smart-d6e00a5f-e33d-4f94-8a1f-90a0e3caf4b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426712918 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.426712918
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.759713098
Short name T61
Test name
Test status
Simulation time 17082716 ps
CPU time 0.65 seconds
Started Aug 08 04:29:07 PM PDT 24
Finished Aug 08 04:29:08 PM PDT 24
Peak memory 195712 kb
Host smart-ef35839e-8cd1-45d4-af73-429dafc505ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759713098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.759713098
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3435927246
Short name T1265
Test name
Test status
Simulation time 13589695 ps
CPU time 0.57 seconds
Started Aug 08 04:29:05 PM PDT 24
Finished Aug 08 04:29:06 PM PDT 24
Peak memory 194492 kb
Host smart-f3bbf022-1a08-44e3-9a73-e0d09a191aa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435927246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3435927246
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4187768308
Short name T80
Test name
Test status
Simulation time 32982391 ps
CPU time 0.88 seconds
Started Aug 08 04:29:06 PM PDT 24
Finished Aug 08 04:29:08 PM PDT 24
Peak memory 196120 kb
Host smart-00c45459-a61e-4646-9aba-7c70b37ed367
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187768308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.4187768308
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1099417765
Short name T1214
Test name
Test status
Simulation time 34684984 ps
CPU time 1.76 seconds
Started Aug 08 04:29:03 PM PDT 24
Finished Aug 08 04:29:05 PM PDT 24
Peak memory 200108 kb
Host smart-d0cd13a5-3a7a-49b8-9578-7c1b524c46c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099417765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1099417765
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.834460111
Short name T91
Test name
Test status
Simulation time 117154153 ps
CPU time 1.26 seconds
Started Aug 08 04:29:08 PM PDT 24
Finished Aug 08 04:29:09 PM PDT 24
Peak memory 199592 kb
Host smart-24283313-ddde-4ef9-bc6c-fd15c4734f37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834460111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.834460111
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3481905446
Short name T1188
Test name
Test status
Simulation time 19102108 ps
CPU time 1.01 seconds
Started Aug 08 04:29:08 PM PDT 24
Finished Aug 08 04:29:09 PM PDT 24
Peak memory 200112 kb
Host smart-918339e6-7ef8-4c97-a99f-aa412a0a1b0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481905446 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3481905446
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3045384480
Short name T1301
Test name
Test status
Simulation time 45078553 ps
CPU time 0.62 seconds
Started Aug 08 04:29:05 PM PDT 24
Finished Aug 08 04:29:06 PM PDT 24
Peak memory 195808 kb
Host smart-7d2b512b-bd04-4724-ad75-d3d3a28109cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045384480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3045384480
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3313278985
Short name T1186
Test name
Test status
Simulation time 87264792 ps
CPU time 0.61 seconds
Started Aug 08 04:29:05 PM PDT 24
Finished Aug 08 04:29:06 PM PDT 24
Peak memory 194632 kb
Host smart-2343f62c-b51b-4e7c-871a-33631ecd6e7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313278985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3313278985
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.553372808
Short name T1219
Test name
Test status
Simulation time 28140587 ps
CPU time 0.7 seconds
Started Aug 08 04:29:08 PM PDT 24
Finished Aug 08 04:29:08 PM PDT 24
Peak memory 196080 kb
Host smart-c591d53a-7884-4e01-89d7-5be74c67dc0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553372808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.553372808
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.981558134
Short name T1281
Test name
Test status
Simulation time 74830580 ps
CPU time 1.15 seconds
Started Aug 08 04:29:07 PM PDT 24
Finished Aug 08 04:29:08 PM PDT 24
Peak memory 200052 kb
Host smart-84e9f07a-0080-4506-8441-02ea4c167383
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981558134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.981558134
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3017996470
Short name T1226
Test name
Test status
Simulation time 71398251 ps
CPU time 0.94 seconds
Started Aug 08 04:29:07 PM PDT 24
Finished Aug 08 04:29:08 PM PDT 24
Peak memory 199144 kb
Host smart-a48a6328-4355-4516-bbbb-f02000ae21a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017996470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3017996470
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1975983074
Short name T1277
Test name
Test status
Simulation time 21679909 ps
CPU time 1.04 seconds
Started Aug 08 04:29:08 PM PDT 24
Finished Aug 08 04:29:09 PM PDT 24
Peak memory 200060 kb
Host smart-2757d041-7cbc-43b4-8832-9bc559dfd199
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975983074 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1975983074
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.169229032
Short name T1224
Test name
Test status
Simulation time 31571700 ps
CPU time 0.63 seconds
Started Aug 08 04:29:06 PM PDT 24
Finished Aug 08 04:29:07 PM PDT 24
Peak memory 195736 kb
Host smart-a71121a8-0be0-4f62-b561-c3279d0dfe5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169229032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.169229032
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.689795596
Short name T1258
Test name
Test status
Simulation time 13778655 ps
CPU time 0.57 seconds
Started Aug 08 04:29:05 PM PDT 24
Finished Aug 08 04:29:05 PM PDT 24
Peak memory 194676 kb
Host smart-7cbd5225-0d50-4bfb-a2e0-3353c5a74296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689795596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.689795596
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1497990103
Short name T1218
Test name
Test status
Simulation time 79486193 ps
CPU time 0.64 seconds
Started Aug 08 04:29:09 PM PDT 24
Finished Aug 08 04:29:09 PM PDT 24
Peak memory 195840 kb
Host smart-b58f41a7-877d-4347-b059-248c75f6cb96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497990103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1497990103
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1362443708
Short name T1309
Test name
Test status
Simulation time 138458867 ps
CPU time 2.53 seconds
Started Aug 08 04:29:06 PM PDT 24
Finished Aug 08 04:29:08 PM PDT 24
Peak memory 200256 kb
Host smart-14eb366a-9a8d-402a-83cb-051d9c9fbad5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362443708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1362443708
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.56489074
Short name T1237
Test name
Test status
Simulation time 194598174 ps
CPU time 0.93 seconds
Started Aug 08 04:29:07 PM PDT 24
Finished Aug 08 04:29:08 PM PDT 24
Peak memory 199276 kb
Host smart-2d0b377c-eb97-43de-82a8-e02904d0828d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56489074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.56489074
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4145604081
Short name T1183
Test name
Test status
Simulation time 102979185 ps
CPU time 0.8 seconds
Started Aug 08 04:29:21 PM PDT 24
Finished Aug 08 04:29:21 PM PDT 24
Peak memory 199988 kb
Host smart-c5a6f476-691f-4f87-bbef-85ae662227ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145604081 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.4145604081
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1450294484
Short name T69
Test name
Test status
Simulation time 39545354 ps
CPU time 0.58 seconds
Started Aug 08 04:29:28 PM PDT 24
Finished Aug 08 04:29:29 PM PDT 24
Peak memory 195644 kb
Host smart-c29c25c7-9af6-49a9-a07a-4f650447ed33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450294484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1450294484
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.4080188615
Short name T1280
Test name
Test status
Simulation time 52609180 ps
CPU time 0.56 seconds
Started Aug 08 04:29:06 PM PDT 24
Finished Aug 08 04:29:07 PM PDT 24
Peak memory 194624 kb
Host smart-4f5142aa-14dc-488a-afd7-fd9c98a88481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080188615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.4080188615
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3554444971
Short name T1221
Test name
Test status
Simulation time 86720657 ps
CPU time 0.65 seconds
Started Aug 08 04:29:27 PM PDT 24
Finished Aug 08 04:29:28 PM PDT 24
Peak memory 196080 kb
Host smart-c86fd9da-a709-4a61-9278-3494fb8826f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554444971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3554444971
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2423102558
Short name T1285
Test name
Test status
Simulation time 135439609 ps
CPU time 1.88 seconds
Started Aug 08 04:29:08 PM PDT 24
Finished Aug 08 04:29:10 PM PDT 24
Peak memory 200248 kb
Host smart-b2349d2c-7d4d-49a9-9512-d4271b42f9f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423102558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2423102558
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1639933488
Short name T1269
Test name
Test status
Simulation time 43131515 ps
CPU time 0.99 seconds
Started Aug 08 04:29:04 PM PDT 24
Finished Aug 08 04:29:05 PM PDT 24
Peak memory 199040 kb
Host smart-60c0777c-43ab-417b-84d5-d73980f44a33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639933488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1639933488
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.360357598
Short name T1310
Test name
Test status
Simulation time 34841141 ps
CPU time 0.95 seconds
Started Aug 08 04:29:32 PM PDT 24
Finished Aug 08 04:29:33 PM PDT 24
Peak memory 200088 kb
Host smart-5ad85a33-f172-4cc1-99a9-3e98c237a392
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360357598 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.360357598
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.2877462061
Short name T73
Test name
Test status
Simulation time 16221118 ps
CPU time 0.61 seconds
Started Aug 08 04:29:34 PM PDT 24
Finished Aug 08 04:29:34 PM PDT 24
Peak memory 195680 kb
Host smart-a7a0dcc5-3be0-418b-96e7-9517e0cf60b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877462061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2877462061
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1463661920
Short name T1289
Test name
Test status
Simulation time 13803110 ps
CPU time 0.57 seconds
Started Aug 08 04:29:22 PM PDT 24
Finished Aug 08 04:29:23 PM PDT 24
Peak memory 194616 kb
Host smart-613d5bc4-df68-4c60-972a-2f219a112ae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463661920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1463661920
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2576121367
Short name T1287
Test name
Test status
Simulation time 24293962 ps
CPU time 0.68 seconds
Started Aug 08 04:29:27 PM PDT 24
Finished Aug 08 04:29:28 PM PDT 24
Peak memory 195696 kb
Host smart-36e05c6f-c5bc-4cc3-8896-b96368aff496
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576121367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2576121367
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.146419562
Short name T1274
Test name
Test status
Simulation time 123870109 ps
CPU time 1.39 seconds
Started Aug 08 04:29:21 PM PDT 24
Finished Aug 08 04:29:23 PM PDT 24
Peak memory 200336 kb
Host smart-e846c851-4f8c-41ea-80a7-811e5fe5be53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146419562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.146419562
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3312409966
Short name T1217
Test name
Test status
Simulation time 178592294 ps
CPU time 0.9 seconds
Started Aug 08 04:29:25 PM PDT 24
Finished Aug 08 04:29:26 PM PDT 24
Peak memory 199256 kb
Host smart-570a3c6c-7a83-429a-a3e0-db41f44129d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312409966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3312409966
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1342567795
Short name T1271
Test name
Test status
Simulation time 80945571 ps
CPU time 1.39 seconds
Started Aug 08 04:29:39 PM PDT 24
Finished Aug 08 04:29:40 PM PDT 24
Peak memory 200240 kb
Host smart-8b140aa3-5e6b-425f-86ec-34b3920529fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342567795 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1342567795
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2219671467
Short name T67
Test name
Test status
Simulation time 30477441 ps
CPU time 0.64 seconds
Started Aug 08 04:29:24 PM PDT 24
Finished Aug 08 04:29:24 PM PDT 24
Peak memory 195764 kb
Host smart-7e4f795d-fb36-4d05-9e66-bf02b49a6149
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219671467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2219671467
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.492194368
Short name T1189
Test name
Test status
Simulation time 30499827 ps
CPU time 0.53 seconds
Started Aug 08 04:29:25 PM PDT 24
Finished Aug 08 04:29:26 PM PDT 24
Peak memory 194584 kb
Host smart-b025a800-4918-4e84-9ad1-32a25de9420f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492194368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.492194368
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3681691801
Short name T74
Test name
Test status
Simulation time 61343740 ps
CPU time 0.64 seconds
Started Aug 08 04:29:21 PM PDT 24
Finished Aug 08 04:29:22 PM PDT 24
Peak memory 195756 kb
Host smart-2bdecf5b-ea8e-4695-aa97-bdb8bb87bb66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681691801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3681691801
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3767060740
Short name T1272
Test name
Test status
Simulation time 560039047 ps
CPU time 2.17 seconds
Started Aug 08 04:29:25 PM PDT 24
Finished Aug 08 04:29:27 PM PDT 24
Peak memory 200244 kb
Host smart-418bfa47-04b5-4eb0-9300-dd5d7424fab8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767060740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3767060740
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2352513986
Short name T83
Test name
Test status
Simulation time 178457581 ps
CPU time 0.91 seconds
Started Aug 08 04:29:23 PM PDT 24
Finished Aug 08 04:29:24 PM PDT 24
Peak memory 198904 kb
Host smart-d05e17e1-9e86-4de1-91be-e8abcc34f36a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352513986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2352513986
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3654854693
Short name T1185
Test name
Test status
Simulation time 264644586 ps
CPU time 0.68 seconds
Started Aug 08 04:28:53 PM PDT 24
Finished Aug 08 04:28:54 PM PDT 24
Peak memory 195596 kb
Host smart-7e202b0c-924c-4bba-b4ba-e3cac631b2be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654854693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3654854693
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1875658956
Short name T1266
Test name
Test status
Simulation time 55869972 ps
CPU time 2.17 seconds
Started Aug 08 04:28:57 PM PDT 24
Finished Aug 08 04:29:00 PM PDT 24
Peak memory 197776 kb
Host smart-c14ba4f0-f683-4f0c-9e54-1f7df2cedee6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875658956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1875658956
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3846255306
Short name T1234
Test name
Test status
Simulation time 1037575507 ps
CPU time 1.27 seconds
Started Aug 08 04:28:57 PM PDT 24
Finished Aug 08 04:28:58 PM PDT 24
Peak memory 195612 kb
Host smart-09763204-8253-43ea-ab57-55cda1b52870
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846255306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3846255306
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1955946419
Short name T1291
Test name
Test status
Simulation time 60991935 ps
CPU time 0.78 seconds
Started Aug 08 04:28:56 PM PDT 24
Finished Aug 08 04:28:57 PM PDT 24
Peak memory 200016 kb
Host smart-7c1d9a3c-0241-4c94-8e2c-6043244a5851
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955946419 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1955946419
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3627663894
Short name T71
Test name
Test status
Simulation time 25157796 ps
CPU time 0.57 seconds
Started Aug 08 04:28:55 PM PDT 24
Finished Aug 08 04:28:56 PM PDT 24
Peak memory 195580 kb
Host smart-169f6917-3f44-43de-aa8a-5fe40f48aa12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627663894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3627663894
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.968336365
Short name T1215
Test name
Test status
Simulation time 13642852 ps
CPU time 0.58 seconds
Started Aug 08 04:28:53 PM PDT 24
Finished Aug 08 04:28:54 PM PDT 24
Peak memory 194568 kb
Host smart-1bfd93e5-d720-47a2-9dd9-42bac65bb8a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968336365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.968336365
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2645980876
Short name T82
Test name
Test status
Simulation time 23581631 ps
CPU time 0.66 seconds
Started Aug 08 04:28:59 PM PDT 24
Finished Aug 08 04:29:00 PM PDT 24
Peak memory 196164 kb
Host smart-f30cd3e0-dd50-47ff-9b0f-954dba444a49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645980876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2645980876
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2858318394
Short name T1275
Test name
Test status
Simulation time 222908806 ps
CPU time 1.15 seconds
Started Aug 08 04:28:59 PM PDT 24
Finished Aug 08 04:29:00 PM PDT 24
Peak memory 200264 kb
Host smart-382e4e7f-f828-47fe-af0a-cb0b6a72fe4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858318394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2858318394
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3049037303
Short name T90
Test name
Test status
Simulation time 73083515 ps
CPU time 1.31 seconds
Started Aug 08 04:29:01 PM PDT 24
Finished Aug 08 04:29:03 PM PDT 24
Peak memory 199628 kb
Host smart-e9f7ffbd-15b8-4da5-ab9b-4d1166813921
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049037303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3049037303
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.551199335
Short name T1211
Test name
Test status
Simulation time 36430351 ps
CPU time 0.59 seconds
Started Aug 08 04:29:21 PM PDT 24
Finished Aug 08 04:29:22 PM PDT 24
Peak memory 194736 kb
Host smart-eab281f7-e51c-47bb-8748-ee5b45031668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551199335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.551199335
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2696111831
Short name T1313
Test name
Test status
Simulation time 13730600 ps
CPU time 0.57 seconds
Started Aug 08 04:29:37 PM PDT 24
Finished Aug 08 04:29:37 PM PDT 24
Peak memory 194580 kb
Host smart-8ea3b1b2-8ad2-4fa0-b367-6428f69c4dcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696111831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2696111831
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.645095823
Short name T1210
Test name
Test status
Simulation time 14672905 ps
CPU time 0.57 seconds
Started Aug 08 04:29:33 PM PDT 24
Finished Aug 08 04:29:34 PM PDT 24
Peak memory 194640 kb
Host smart-0ab202e2-6570-4256-8ebd-e2586b7c9f3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645095823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.645095823
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1340381007
Short name T1206
Test name
Test status
Simulation time 15338904 ps
CPU time 0.58 seconds
Started Aug 08 04:29:30 PM PDT 24
Finished Aug 08 04:29:31 PM PDT 24
Peak memory 194592 kb
Host smart-522d8aab-7593-4f1f-83d0-dce0e83396a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340381007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1340381007
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3430349052
Short name T1286
Test name
Test status
Simulation time 15917625 ps
CPU time 0.62 seconds
Started Aug 08 04:29:21 PM PDT 24
Finished Aug 08 04:29:22 PM PDT 24
Peak memory 194592 kb
Host smart-f17316fe-776d-467d-a8eb-48587f088786
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430349052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3430349052
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3619283416
Short name T1253
Test name
Test status
Simulation time 12636489 ps
CPU time 0.57 seconds
Started Aug 08 04:29:27 PM PDT 24
Finished Aug 08 04:29:28 PM PDT 24
Peak memory 194624 kb
Host smart-5060cb43-90d6-4182-96e0-17a4addcf96d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619283416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3619283416
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3660189957
Short name T1223
Test name
Test status
Simulation time 55436290 ps
CPU time 0.58 seconds
Started Aug 08 04:29:22 PM PDT 24
Finished Aug 08 04:29:23 PM PDT 24
Peak memory 194616 kb
Host smart-036bd547-989d-4139-b2b9-002c2ac829d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660189957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3660189957
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3565960109
Short name T1213
Test name
Test status
Simulation time 13054802 ps
CPU time 0.61 seconds
Started Aug 08 04:29:24 PM PDT 24
Finished Aug 08 04:29:25 PM PDT 24
Peak memory 194672 kb
Host smart-8b06dc30-f632-4ea0-a719-0ab5a98245d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565960109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3565960109
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2542748033
Short name T1205
Test name
Test status
Simulation time 19926087 ps
CPU time 0.56 seconds
Started Aug 08 04:29:26 PM PDT 24
Finished Aug 08 04:29:27 PM PDT 24
Peak memory 194616 kb
Host smart-71613764-97a7-483a-8da0-43cb6ccdcb76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542748033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2542748033
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1341748928
Short name T1260
Test name
Test status
Simulation time 86200324 ps
CPU time 0.59 seconds
Started Aug 08 04:29:22 PM PDT 24
Finished Aug 08 04:29:22 PM PDT 24
Peak memory 194588 kb
Host smart-1b2d5d5a-2699-4079-b1db-9061636c8819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341748928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1341748928
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3000879757
Short name T1200
Test name
Test status
Simulation time 20110793 ps
CPU time 0.66 seconds
Started Aug 08 04:28:54 PM PDT 24
Finished Aug 08 04:28:55 PM PDT 24
Peak memory 195720 kb
Host smart-b0e6bb50-0fcb-4e7d-8afd-456cca20ced9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000879757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3000879757
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1178833459
Short name T1264
Test name
Test status
Simulation time 341183226 ps
CPU time 2.42 seconds
Started Aug 08 04:28:54 PM PDT 24
Finished Aug 08 04:28:56 PM PDT 24
Peak memory 197868 kb
Host smart-1c7c22b1-67cc-4ff8-ab01-26831a761cb0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178833459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1178833459
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2400243269
Short name T1231
Test name
Test status
Simulation time 38169345 ps
CPU time 0.6 seconds
Started Aug 08 04:28:59 PM PDT 24
Finished Aug 08 04:29:00 PM PDT 24
Peak memory 195608 kb
Host smart-cc66e7ad-94d0-4d73-a642-d33dc9aa88bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400243269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2400243269
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2360254140
Short name T1195
Test name
Test status
Simulation time 27949392 ps
CPU time 0.62 seconds
Started Aug 08 04:28:54 PM PDT 24
Finished Aug 08 04:28:55 PM PDT 24
Peak memory 197352 kb
Host smart-e25a7c74-927e-42e3-bcdb-ce553bf88cfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360254140 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2360254140
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.481660232
Short name T1300
Test name
Test status
Simulation time 14464608 ps
CPU time 0.59 seconds
Started Aug 08 04:28:57 PM PDT 24
Finished Aug 08 04:28:58 PM PDT 24
Peak memory 195716 kb
Host smart-459459dc-0d80-4ea8-aa49-f0bfd7a3e5d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481660232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.481660232
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1167797763
Short name T1294
Test name
Test status
Simulation time 21954085 ps
CPU time 0.58 seconds
Started Aug 08 04:28:52 PM PDT 24
Finished Aug 08 04:28:53 PM PDT 24
Peak memory 194564 kb
Host smart-c1e658dd-1655-4787-b3e8-d5fd244511ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167797763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1167797763
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3380394594
Short name T77
Test name
Test status
Simulation time 25633163 ps
CPU time 0.75 seconds
Started Aug 08 04:28:55 PM PDT 24
Finished Aug 08 04:28:56 PM PDT 24
Peak memory 196724 kb
Host smart-39179639-cd9f-4d85-95bb-b95aaaac0a29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380394594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3380394594
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2936441335
Short name T1184
Test name
Test status
Simulation time 559050624 ps
CPU time 2.49 seconds
Started Aug 08 04:28:53 PM PDT 24
Finished Aug 08 04:28:56 PM PDT 24
Peak memory 200336 kb
Host smart-f56ad091-f0eb-4107-808f-45366d99215b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936441335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2936441335
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2154361099
Short name T84
Test name
Test status
Simulation time 251128046 ps
CPU time 0.95 seconds
Started Aug 08 04:28:55 PM PDT 24
Finished Aug 08 04:28:56 PM PDT 24
Peak memory 199020 kb
Host smart-b35a7e4c-ee55-4497-904e-1d5ec227c74d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154361099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2154361099
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2103527706
Short name T1216
Test name
Test status
Simulation time 75799301 ps
CPU time 0.54 seconds
Started Aug 08 04:29:34 PM PDT 24
Finished Aug 08 04:29:34 PM PDT 24
Peak memory 194556 kb
Host smart-92b98f3d-fe6a-482d-98ea-a2a19449a946
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103527706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2103527706
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.986222145
Short name T1212
Test name
Test status
Simulation time 15664095 ps
CPU time 0.58 seconds
Started Aug 08 04:29:20 PM PDT 24
Finished Aug 08 04:29:21 PM PDT 24
Peak memory 194644 kb
Host smart-b2494dc0-1f17-4c90-8003-09d6e7911ae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986222145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.986222145
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.257086694
Short name T1305
Test name
Test status
Simulation time 43981681 ps
CPU time 0.57 seconds
Started Aug 08 04:29:23 PM PDT 24
Finished Aug 08 04:29:24 PM PDT 24
Peak memory 194508 kb
Host smart-c556471b-f518-43fa-962f-3068a080c3ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257086694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.257086694
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.4244690015
Short name T1302
Test name
Test status
Simulation time 29130474 ps
CPU time 0.59 seconds
Started Aug 08 04:29:23 PM PDT 24
Finished Aug 08 04:29:23 PM PDT 24
Peak memory 194616 kb
Host smart-f3b50b20-14f1-4859-8df8-450333e73c7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244690015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.4244690015
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1603102395
Short name T1248
Test name
Test status
Simulation time 28513722 ps
CPU time 0.56 seconds
Started Aug 08 04:29:22 PM PDT 24
Finished Aug 08 04:29:22 PM PDT 24
Peak memory 194556 kb
Host smart-a2a5e013-8972-4f9b-880f-71203d5a36e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603102395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1603102395
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1816371528
Short name T1308
Test name
Test status
Simulation time 13624373 ps
CPU time 0.55 seconds
Started Aug 08 04:29:21 PM PDT 24
Finished Aug 08 04:29:22 PM PDT 24
Peak memory 194512 kb
Host smart-bebe9930-41a3-4b5e-826c-57e6746fefdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816371528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1816371528
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2438057839
Short name T1222
Test name
Test status
Simulation time 73219118 ps
CPU time 0.58 seconds
Started Aug 08 04:29:23 PM PDT 24
Finished Aug 08 04:29:24 PM PDT 24
Peak memory 194672 kb
Host smart-7033e91f-79f1-4477-a8eb-a1956196692f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438057839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2438057839
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1905208141
Short name T1242
Test name
Test status
Simulation time 21134442 ps
CPU time 0.55 seconds
Started Aug 08 04:29:28 PM PDT 24
Finished Aug 08 04:29:29 PM PDT 24
Peak memory 194492 kb
Host smart-e2fb9b3d-f095-4f38-83eb-7de7eb21e603
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905208141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1905208141
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2242935740
Short name T1276
Test name
Test status
Simulation time 18463199 ps
CPU time 0.57 seconds
Started Aug 08 04:29:24 PM PDT 24
Finished Aug 08 04:29:24 PM PDT 24
Peak memory 194600 kb
Host smart-0f4e686d-a853-4a13-84b8-a4b102b0667c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242935740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2242935740
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1267875081
Short name T1311
Test name
Test status
Simulation time 13663714 ps
CPU time 0.6 seconds
Started Aug 08 04:29:25 PM PDT 24
Finished Aug 08 04:29:26 PM PDT 24
Peak memory 194576 kb
Host smart-c87d31b1-297a-4a17-b1c2-21d30560162d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267875081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1267875081
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2546970722
Short name T1251
Test name
Test status
Simulation time 20684519 ps
CPU time 0.64 seconds
Started Aug 08 04:28:57 PM PDT 24
Finished Aug 08 04:28:57 PM PDT 24
Peak memory 194968 kb
Host smart-1ef56f63-45c0-4422-9f7d-e39b64059a6d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546970722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2546970722
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.69918678
Short name T68
Test name
Test status
Simulation time 987274299 ps
CPU time 2.36 seconds
Started Aug 08 04:28:57 PM PDT 24
Finished Aug 08 04:28:59 PM PDT 24
Peak memory 197980 kb
Host smart-b37e56a5-ab08-4eb0-a652-2c0b9704f05a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69918678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.69918678
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3227978955
Short name T63
Test name
Test status
Simulation time 16780296 ps
CPU time 0.7 seconds
Started Aug 08 04:28:58 PM PDT 24
Finished Aug 08 04:28:59 PM PDT 24
Peak memory 195596 kb
Host smart-1c9b5329-846f-425e-b439-e67a3ded0358
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227978955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3227978955
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.878193107
Short name T1263
Test name
Test status
Simulation time 72063626 ps
CPU time 0.77 seconds
Started Aug 08 04:28:55 PM PDT 24
Finished Aug 08 04:28:56 PM PDT 24
Peak memory 199724 kb
Host smart-21b36f13-459a-429b-b39a-948640b86a5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878193107 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.878193107
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.52178918
Short name T64
Test name
Test status
Simulation time 59116842 ps
CPU time 0.58 seconds
Started Aug 08 04:29:02 PM PDT 24
Finished Aug 08 04:29:03 PM PDT 24
Peak memory 195736 kb
Host smart-2f9ea7b1-af9e-40dc-852b-47cdc00a2874
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52178918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.52178918
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.780955314
Short name T1249
Test name
Test status
Simulation time 24180656 ps
CPU time 0.58 seconds
Started Aug 08 04:28:57 PM PDT 24
Finished Aug 08 04:28:58 PM PDT 24
Peak memory 194528 kb
Host smart-0167a381-680a-467e-a654-f12e75c4a11b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780955314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.780955314
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4119443967
Short name T1256
Test name
Test status
Simulation time 34859769 ps
CPU time 0.75 seconds
Started Aug 08 04:28:54 PM PDT 24
Finished Aug 08 04:28:55 PM PDT 24
Peak memory 197432 kb
Host smart-4c94ca99-532c-4e07-bea4-88e7ce9dd276
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119443967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.4119443967
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.992584052
Short name T1199
Test name
Test status
Simulation time 57872496 ps
CPU time 1.43 seconds
Started Aug 08 04:28:54 PM PDT 24
Finished Aug 08 04:28:56 PM PDT 24
Peak memory 200252 kb
Host smart-f0f349b9-5298-4435-aecd-079de5b4c6e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992584052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.992584052
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1697933286
Short name T89
Test name
Test status
Simulation time 36435655 ps
CPU time 0.92 seconds
Started Aug 08 04:28:55 PM PDT 24
Finished Aug 08 04:28:56 PM PDT 24
Peak memory 199000 kb
Host smart-5966c4dc-8900-4e12-a0c8-dd319526c45c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697933286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1697933286
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2770862306
Short name T1193
Test name
Test status
Simulation time 34519916 ps
CPU time 0.52 seconds
Started Aug 08 04:29:32 PM PDT 24
Finished Aug 08 04:29:33 PM PDT 24
Peak memory 194556 kb
Host smart-81e7b990-c549-40ee-8476-9550a4420ad7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770862306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2770862306
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.797161806
Short name T1267
Test name
Test status
Simulation time 23430577 ps
CPU time 0.59 seconds
Started Aug 08 04:29:23 PM PDT 24
Finished Aug 08 04:29:24 PM PDT 24
Peak memory 194620 kb
Host smart-815ad9b9-9d1a-4dcf-99b5-6b056d7dbde8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797161806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.797161806
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3978080356
Short name T1229
Test name
Test status
Simulation time 18231294 ps
CPU time 0.57 seconds
Started Aug 08 04:29:25 PM PDT 24
Finished Aug 08 04:29:26 PM PDT 24
Peak memory 194508 kb
Host smart-1c65aa23-1401-48fd-b865-d4fb672c5083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978080356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3978080356
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3116005244
Short name T1303
Test name
Test status
Simulation time 30243051 ps
CPU time 0.58 seconds
Started Aug 08 04:29:21 PM PDT 24
Finished Aug 08 04:29:21 PM PDT 24
Peak memory 194608 kb
Host smart-b9546385-4b90-425f-b229-ab2805166770
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116005244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3116005244
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3545298794
Short name T1257
Test name
Test status
Simulation time 39914101 ps
CPU time 0.57 seconds
Started Aug 08 04:29:23 PM PDT 24
Finished Aug 08 04:29:24 PM PDT 24
Peak memory 194556 kb
Host smart-f9858ddd-3753-45e8-a001-a1eb1fec38ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545298794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3545298794
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3567625085
Short name T1203
Test name
Test status
Simulation time 12411651 ps
CPU time 0.56 seconds
Started Aug 08 04:29:30 PM PDT 24
Finished Aug 08 04:29:31 PM PDT 24
Peak memory 194516 kb
Host smart-a2a810c3-790e-4ea0-83d0-51265e852649
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567625085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3567625085
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3717235267
Short name T1192
Test name
Test status
Simulation time 85257890 ps
CPU time 0.57 seconds
Started Aug 08 04:29:23 PM PDT 24
Finished Aug 08 04:29:24 PM PDT 24
Peak memory 194668 kb
Host smart-deb1f8ac-f7f6-4bbd-aee3-fe667a711584
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717235267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3717235267
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3658162951
Short name T1208
Test name
Test status
Simulation time 17089415 ps
CPU time 0.58 seconds
Started Aug 08 04:29:22 PM PDT 24
Finished Aug 08 04:29:23 PM PDT 24
Peak memory 194592 kb
Host smart-e00f6f93-dad7-4544-9d81-ec5cae98e94b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658162951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3658162951
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.509186497
Short name T1209
Test name
Test status
Simulation time 25670483 ps
CPU time 0.56 seconds
Started Aug 08 04:29:28 PM PDT 24
Finished Aug 08 04:29:29 PM PDT 24
Peak memory 194572 kb
Host smart-4777cdb2-70ee-4180-acb1-6eb33cbf0d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509186497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.509186497
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.4221030367
Short name T1241
Test name
Test status
Simulation time 21904694 ps
CPU time 0.54 seconds
Started Aug 08 04:29:28 PM PDT 24
Finished Aug 08 04:29:28 PM PDT 24
Peak memory 194644 kb
Host smart-26eb388a-77d1-411c-8248-d15da60e8c12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221030367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.4221030367
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.618395443
Short name T1290
Test name
Test status
Simulation time 92290485 ps
CPU time 1.22 seconds
Started Aug 08 04:29:00 PM PDT 24
Finished Aug 08 04:29:01 PM PDT 24
Peak memory 200248 kb
Host smart-2e97a9f2-c6c3-4101-bf24-46300339efc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618395443 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.618395443
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3903749561
Short name T1262
Test name
Test status
Simulation time 16705002 ps
CPU time 0.58 seconds
Started Aug 08 04:28:55 PM PDT 24
Finished Aug 08 04:28:56 PM PDT 24
Peak memory 195628 kb
Host smart-ad5cb55e-065a-49a3-b43e-563501e33730
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903749561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3903749561
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3836230174
Short name T1288
Test name
Test status
Simulation time 14854157 ps
CPU time 0.57 seconds
Started Aug 08 04:29:02 PM PDT 24
Finished Aug 08 04:29:02 PM PDT 24
Peak memory 194636 kb
Host smart-a3670416-ba15-4859-ac80-1566303dfdad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836230174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3836230174
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2662155979
Short name T1236
Test name
Test status
Simulation time 17569365 ps
CPU time 0.68 seconds
Started Aug 08 04:28:52 PM PDT 24
Finished Aug 08 04:28:53 PM PDT 24
Peak memory 197256 kb
Host smart-9de9a974-e20d-4792-bb1e-d4a08829f85d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662155979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2662155979
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.4291741405
Short name T1196
Test name
Test status
Simulation time 240695799 ps
CPU time 2.18 seconds
Started Aug 08 04:29:04 PM PDT 24
Finished Aug 08 04:29:06 PM PDT 24
Peak memory 200320 kb
Host smart-8a639db2-7d85-447c-961e-99ac3e242d91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291741405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.4291741405
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2515393133
Short name T1239
Test name
Test status
Simulation time 21680729 ps
CPU time 0.65 seconds
Started Aug 08 04:28:56 PM PDT 24
Finished Aug 08 04:28:57 PM PDT 24
Peak memory 197708 kb
Host smart-af5c989c-b197-4a56-86ca-0d14c9df2bd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515393133 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2515393133
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2818884273
Short name T62
Test name
Test status
Simulation time 139237342 ps
CPU time 0.6 seconds
Started Aug 08 04:28:56 PM PDT 24
Finished Aug 08 04:28:56 PM PDT 24
Peak memory 195676 kb
Host smart-6f0049b5-a65a-4e40-a81b-8511ebc72434
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818884273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2818884273
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1432138638
Short name T1278
Test name
Test status
Simulation time 15455833 ps
CPU time 0.58 seconds
Started Aug 08 04:28:54 PM PDT 24
Finished Aug 08 04:28:55 PM PDT 24
Peak memory 194636 kb
Host smart-491ed941-87df-48a9-8af0-0978613b871c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432138638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1432138638
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1733535022
Short name T75
Test name
Test status
Simulation time 38326340 ps
CPU time 0.64 seconds
Started Aug 08 04:29:00 PM PDT 24
Finished Aug 08 04:29:01 PM PDT 24
Peak memory 195964 kb
Host smart-c58f74db-c8cd-4f0d-b428-ac7131e271b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733535022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1733535022
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1916840230
Short name T1295
Test name
Test status
Simulation time 521513274 ps
CPU time 1.88 seconds
Started Aug 08 04:28:58 PM PDT 24
Finished Aug 08 04:29:00 PM PDT 24
Peak memory 200240 kb
Host smart-3d290ddb-c562-4883-9747-d803aee8f04b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916840230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1916840230
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.58660945
Short name T85
Test name
Test status
Simulation time 364863268 ps
CPU time 1.35 seconds
Started Aug 08 04:29:03 PM PDT 24
Finished Aug 08 04:29:04 PM PDT 24
Peak memory 199580 kb
Host smart-deba3667-3804-47d4-95b8-c4e2286c456a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58660945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.58660945
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.367848237
Short name T1190
Test name
Test status
Simulation time 23097426 ps
CPU time 0.74 seconds
Started Aug 08 04:28:54 PM PDT 24
Finished Aug 08 04:28:55 PM PDT 24
Peak memory 198860 kb
Host smart-40df4ed6-0414-4f2e-9fc6-5215650a0553
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367848237 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.367848237
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1271214057
Short name T1296
Test name
Test status
Simulation time 13573419 ps
CPU time 0.59 seconds
Started Aug 08 04:28:52 PM PDT 24
Finished Aug 08 04:28:53 PM PDT 24
Peak memory 195740 kb
Host smart-6f91f756-1f1f-445d-bfdd-22ea041a3a47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271214057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1271214057
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3365162110
Short name T1244
Test name
Test status
Simulation time 12049283 ps
CPU time 0.57 seconds
Started Aug 08 04:29:05 PM PDT 24
Finished Aug 08 04:29:05 PM PDT 24
Peak memory 194532 kb
Host smart-45e7876c-4cca-4393-b246-b201b8dc2384
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365162110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3365162110
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3561270172
Short name T76
Test name
Test status
Simulation time 17637723 ps
CPU time 0.67 seconds
Started Aug 08 04:28:59 PM PDT 24
Finished Aug 08 04:29:00 PM PDT 24
Peak memory 196052 kb
Host smart-a4f200e0-4e96-44f3-855b-b9055e372862
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561270172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3561270172
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2241181697
Short name T1307
Test name
Test status
Simulation time 346813241 ps
CPU time 1.75 seconds
Started Aug 08 04:28:57 PM PDT 24
Finished Aug 08 04:28:59 PM PDT 24
Peak memory 200300 kb
Host smart-31325614-d078-4138-bcd6-52374c4d852f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241181697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2241181697
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1466679298
Short name T92
Test name
Test status
Simulation time 46998753 ps
CPU time 0.91 seconds
Started Aug 08 04:28:55 PM PDT 24
Finished Aug 08 04:28:56 PM PDT 24
Peak memory 199000 kb
Host smart-d847fc47-708b-4a55-b959-dea8b51be682
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466679298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1466679298
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2547398781
Short name T1232
Test name
Test status
Simulation time 87897643 ps
CPU time 0.68 seconds
Started Aug 08 04:29:03 PM PDT 24
Finished Aug 08 04:29:04 PM PDT 24
Peak memory 198144 kb
Host smart-6f06d69a-028b-4d2c-aeb0-34160b8702f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547398781 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2547398781
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.437642672
Short name T66
Test name
Test status
Simulation time 52190810 ps
CPU time 0.62 seconds
Started Aug 08 04:29:06 PM PDT 24
Finished Aug 08 04:29:07 PM PDT 24
Peak memory 195672 kb
Host smart-ad60db01-6292-409b-82bb-cb468c3c5f62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437642672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.437642672
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.216632858
Short name T1240
Test name
Test status
Simulation time 55014588 ps
CPU time 0.59 seconds
Started Aug 08 04:28:57 PM PDT 24
Finished Aug 08 04:28:58 PM PDT 24
Peak memory 194596 kb
Host smart-053f0a28-ef8f-4452-8283-9ec300148622
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216632858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.216632858
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.231422874
Short name T1235
Test name
Test status
Simulation time 25998585 ps
CPU time 0.66 seconds
Started Aug 08 04:29:04 PM PDT 24
Finished Aug 08 04:29:05 PM PDT 24
Peak memory 194972 kb
Host smart-4e412526-4044-425f-907d-f8c171ed40e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231422874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_
outstanding.231422874
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3187781478
Short name T1197
Test name
Test status
Simulation time 789311676 ps
CPU time 1.61 seconds
Started Aug 08 04:28:57 PM PDT 24
Finished Aug 08 04:28:59 PM PDT 24
Peak memory 200208 kb
Host smart-b7391499-1105-4e48-818f-6d20f2117ca5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187781478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3187781478
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.686781842
Short name T88
Test name
Test status
Simulation time 295651543 ps
CPU time 1.37 seconds
Started Aug 08 04:28:56 PM PDT 24
Finished Aug 08 04:28:57 PM PDT 24
Peak memory 199740 kb
Host smart-0ea4be77-be8d-44c8-b4fd-c7b366783fe3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686781842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.686781842
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3888646034
Short name T1282
Test name
Test status
Simulation time 82179284 ps
CPU time 1.04 seconds
Started Aug 08 04:29:09 PM PDT 24
Finished Aug 08 04:29:10 PM PDT 24
Peak memory 200240 kb
Host smart-2ad8810f-08d7-4149-92da-9fabd3176a54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888646034 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3888646034
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2175526211
Short name T1246
Test name
Test status
Simulation time 12130770 ps
CPU time 0.61 seconds
Started Aug 08 04:29:07 PM PDT 24
Finished Aug 08 04:29:08 PM PDT 24
Peak memory 195660 kb
Host smart-ad15bdeb-0a3b-4641-af7e-837e74f214e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175526211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2175526211
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2023005000
Short name T1245
Test name
Test status
Simulation time 13881113 ps
CPU time 0.61 seconds
Started Aug 08 04:29:05 PM PDT 24
Finished Aug 08 04:29:06 PM PDT 24
Peak memory 194600 kb
Host smart-2e9a9277-30a2-425b-b4b9-4b1a10968fc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023005000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2023005000
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3221454017
Short name T1255
Test name
Test status
Simulation time 117220695 ps
CPU time 0.71 seconds
Started Aug 08 04:29:05 PM PDT 24
Finished Aug 08 04:29:05 PM PDT 24
Peak memory 197196 kb
Host smart-4d5bb735-9e3d-469c-a343-7df10688a535
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221454017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3221454017
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3875657720
Short name T1312
Test name
Test status
Simulation time 62017355 ps
CPU time 1.41 seconds
Started Aug 08 04:29:07 PM PDT 24
Finished Aug 08 04:29:09 PM PDT 24
Peak memory 200312 kb
Host smart-094d30b6-ed35-414c-ac01-01cdfb976bf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875657720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3875657720
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1668900702
Short name T1204
Test name
Test status
Simulation time 89369456 ps
CPU time 1.02 seconds
Started Aug 08 04:29:07 PM PDT 24
Finished Aug 08 04:29:08 PM PDT 24
Peak memory 199088 kb
Host smart-aac5fbca-42e1-4d71-982a-f7ec50debacc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668900702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1668900702
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.3557976032
Short name T420
Test name
Test status
Simulation time 30443514 ps
CPU time 0.54 seconds
Started Aug 08 04:31:50 PM PDT 24
Finished Aug 08 04:31:51 PM PDT 24
Peak memory 194092 kb
Host smart-a44bc740-0bb2-4cf6-9c54-38841de5c166
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557976032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3557976032
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.459320946
Short name T882
Test name
Test status
Simulation time 323191907147 ps
CPU time 130.4 seconds
Started Aug 08 04:31:52 PM PDT 24
Finished Aug 08 04:34:03 PM PDT 24
Peak memory 199756 kb
Host smart-3ea596ff-1b33-4633-a7d8-408f74a8b890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459320946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.459320946
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1949517711
Short name T1117
Test name
Test status
Simulation time 89616881627 ps
CPU time 131.44 seconds
Started Aug 08 04:31:50 PM PDT 24
Finished Aug 08 04:34:01 PM PDT 24
Peak memory 199796 kb
Host smart-ebf613bc-f82e-4ad4-b6b0-acec881bb10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949517711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1949517711
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1964098976
Short name T653
Test name
Test status
Simulation time 7617328658 ps
CPU time 13.31 seconds
Started Aug 08 04:31:49 PM PDT 24
Finished Aug 08 04:32:02 PM PDT 24
Peak memory 199820 kb
Host smart-3bfa06b2-95d8-407d-99d1-f5da673b40ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964098976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1964098976
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.3251718034
Short name T487
Test name
Test status
Simulation time 38236286908 ps
CPU time 11 seconds
Started Aug 08 04:31:54 PM PDT 24
Finished Aug 08 04:32:05 PM PDT 24
Peak memory 199700 kb
Host smart-1ea2f1a5-a725-4716-be36-57e0ff33e0b4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251718034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3251718034
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.628712646
Short name T427
Test name
Test status
Simulation time 44867211937 ps
CPU time 212.05 seconds
Started Aug 08 04:31:54 PM PDT 24
Finished Aug 08 04:35:26 PM PDT 24
Peak memory 199736 kb
Host smart-c1b42daa-65df-4562-91e5-5fa23c814875
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=628712646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.628712646
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.4166935945
Short name T473
Test name
Test status
Simulation time 5567435284 ps
CPU time 7.62 seconds
Started Aug 08 04:31:54 PM PDT 24
Finished Aug 08 04:32:02 PM PDT 24
Peak memory 198932 kb
Host smart-98f8cadc-2af9-4402-8a49-62f7b4989e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166935945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.4166935945
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.3170648186
Short name T311
Test name
Test status
Simulation time 123368101539 ps
CPU time 35.03 seconds
Started Aug 08 04:31:54 PM PDT 24
Finished Aug 08 04:32:29 PM PDT 24
Peak memory 199104 kb
Host smart-9a5c492f-41a8-4e97-838c-6696eaff188c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170648186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3170648186
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3273828273
Short name T876
Test name
Test status
Simulation time 13521676346 ps
CPU time 175.96 seconds
Started Aug 08 04:31:54 PM PDT 24
Finished Aug 08 04:34:50 PM PDT 24
Peak memory 199692 kb
Host smart-7b5f73fb-e468-46f5-881d-cb9425622a35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3273828273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3273828273
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2626646185
Short name T771
Test name
Test status
Simulation time 4902671272 ps
CPU time 22.15 seconds
Started Aug 08 04:31:50 PM PDT 24
Finished Aug 08 04:32:12 PM PDT 24
Peak memory 198200 kb
Host smart-69871164-5a11-4337-a595-6db5dde19e89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2626646185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2626646185
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3866211330
Short name T417
Test name
Test status
Simulation time 28879092132 ps
CPU time 42 seconds
Started Aug 08 04:31:51 PM PDT 24
Finished Aug 08 04:32:33 PM PDT 24
Peak memory 199736 kb
Host smart-6d08c454-94da-49f3-9ee8-62dbdd68699a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866211330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3866211330
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1167413369
Short name T679
Test name
Test status
Simulation time 4881924324 ps
CPU time 1.09 seconds
Started Aug 08 04:31:55 PM PDT 24
Finished Aug 08 04:31:56 PM PDT 24
Peak memory 195876 kb
Host smart-5cf29d91-e62d-49f9-9208-5e1d6443832f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167413369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1167413369
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.344276755
Short name T633
Test name
Test status
Simulation time 156957296307 ps
CPU time 622.76 seconds
Started Aug 08 04:31:53 PM PDT 24
Finished Aug 08 04:42:16 PM PDT 24
Peak memory 216236 kb
Host smart-274c59b7-3acc-423e-b38e-02f0d7f1b983
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344276755 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.344276755
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.3325075236
Short name T968
Test name
Test status
Simulation time 1089783702 ps
CPU time 2.3 seconds
Started Aug 08 04:31:52 PM PDT 24
Finished Aug 08 04:31:54 PM PDT 24
Peak memory 198232 kb
Host smart-1c80eba9-2374-4afd-9e13-c37ca4f52c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325075236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3325075236
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3243164009
Short name T1033
Test name
Test status
Simulation time 18196637507 ps
CPU time 28.89 seconds
Started Aug 08 04:31:50 PM PDT 24
Finished Aug 08 04:32:19 PM PDT 24
Peak memory 199776 kb
Host smart-ef351bd1-1254-462a-ba2e-85d1811984f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243164009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3243164009
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1929346343
Short name T927
Test name
Test status
Simulation time 42677129 ps
CPU time 0.56 seconds
Started Aug 08 04:32:06 PM PDT 24
Finished Aug 08 04:32:07 PM PDT 24
Peak memory 195164 kb
Host smart-0d21f2f0-b399-434f-b170-ded9fbb2b732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929346343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1929346343
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.229049295
Short name T1142
Test name
Test status
Simulation time 118625483263 ps
CPU time 107.97 seconds
Started Aug 08 04:31:54 PM PDT 24
Finished Aug 08 04:33:42 PM PDT 24
Peak memory 199784 kb
Host smart-73a0b2eb-05bf-4d16-a8b9-9f75d015a405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229049295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.229049295
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2814742268
Short name T873
Test name
Test status
Simulation time 84477040698 ps
CPU time 15.37 seconds
Started Aug 08 04:31:49 PM PDT 24
Finished Aug 08 04:32:05 PM PDT 24
Peak memory 199656 kb
Host smart-3990f084-9233-483f-b5a6-ab34c32cfedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814742268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2814742268
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3754438642
Short name T498
Test name
Test status
Simulation time 45753870741 ps
CPU time 122.21 seconds
Started Aug 08 04:31:51 PM PDT 24
Finished Aug 08 04:33:53 PM PDT 24
Peak memory 199788 kb
Host smart-0f7c7b71-0aad-4dd1-bc14-006811d534d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754438642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3754438642
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.3272894044
Short name T666
Test name
Test status
Simulation time 83173353286 ps
CPU time 64.98 seconds
Started Aug 08 04:31:50 PM PDT 24
Finished Aug 08 04:32:55 PM PDT 24
Peak memory 199780 kb
Host smart-95a0a48f-8be8-49e3-acb3-034d57f776b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272894044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3272894044
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1123228111
Short name T494
Test name
Test status
Simulation time 101916912865 ps
CPU time 314.49 seconds
Started Aug 08 04:31:56 PM PDT 24
Finished Aug 08 04:37:10 PM PDT 24
Peak memory 199748 kb
Host smart-f8ccc62f-671e-46eb-95ca-1a2ba7459aa8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1123228111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1123228111
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.827340811
Short name T853
Test name
Test status
Simulation time 2719882193 ps
CPU time 4.88 seconds
Started Aug 08 04:31:51 PM PDT 24
Finished Aug 08 04:31:56 PM PDT 24
Peak memory 197444 kb
Host smart-f0adab2e-447d-45c0-a555-6f24a09dbb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827340811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.827340811
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.3041868500
Short name T323
Test name
Test status
Simulation time 66343729833 ps
CPU time 97.52 seconds
Started Aug 08 04:31:49 PM PDT 24
Finished Aug 08 04:33:27 PM PDT 24
Peak memory 199876 kb
Host smart-f426f913-001f-4450-b26b-4ef6267b8ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041868500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3041868500
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2871867520
Short name T683
Test name
Test status
Simulation time 16457993261 ps
CPU time 994.73 seconds
Started Aug 08 04:31:55 PM PDT 24
Finished Aug 08 04:48:30 PM PDT 24
Peak memory 199740 kb
Host smart-92e14c29-5899-45c8-aaa7-c2f5145ccd97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2871867520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2871867520
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.1255132492
Short name T726
Test name
Test status
Simulation time 4614649235 ps
CPU time 19.24 seconds
Started Aug 08 04:31:52 PM PDT 24
Finished Aug 08 04:32:11 PM PDT 24
Peak memory 199184 kb
Host smart-4774515d-96a5-455b-ba5c-c2ffe293bd74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1255132492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1255132492
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3469811363
Short name T137
Test name
Test status
Simulation time 44235052625 ps
CPU time 73 seconds
Started Aug 08 04:31:50 PM PDT 24
Finished Aug 08 04:33:04 PM PDT 24
Peak memory 199764 kb
Host smart-568d9092-a5a3-4353-993b-e09207f5104c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469811363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3469811363
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3631737234
Short name T541
Test name
Test status
Simulation time 71983920498 ps
CPU time 104.33 seconds
Started Aug 08 04:31:52 PM PDT 24
Finished Aug 08 04:33:36 PM PDT 24
Peak memory 195640 kb
Host smart-7e7bf0c6-f83c-499a-af55-cbb81a791e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631737234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3631737234
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3449295498
Short name T25
Test name
Test status
Simulation time 126810525 ps
CPU time 0.9 seconds
Started Aug 08 04:31:50 PM PDT 24
Finished Aug 08 04:31:51 PM PDT 24
Peak memory 218192 kb
Host smart-e83eb270-6477-4218-9156-8a60b9401afa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449295498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3449295498
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2365224550
Short name T431
Test name
Test status
Simulation time 5350410734 ps
CPU time 12.3 seconds
Started Aug 08 04:31:51 PM PDT 24
Finished Aug 08 04:32:03 PM PDT 24
Peak memory 199668 kb
Host smart-048bbbf2-776d-4cbe-a2fe-138584469be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365224550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2365224550
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.350520157
Short name T702
Test name
Test status
Simulation time 76882192969 ps
CPU time 254.18 seconds
Started Aug 08 04:31:54 PM PDT 24
Finished Aug 08 04:36:08 PM PDT 24
Peak memory 199680 kb
Host smart-c712b1a8-ce45-44df-87b9-309739d50930
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350520157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.350520157
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3956745957
Short name T830
Test name
Test status
Simulation time 1379358580 ps
CPU time 3.25 seconds
Started Aug 08 04:31:52 PM PDT 24
Finished Aug 08 04:31:55 PM PDT 24
Peak memory 199632 kb
Host smart-7771e73e-ef5b-4ac2-9238-90246f10fb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956745957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3956745957
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1797192155
Short name T1072
Test name
Test status
Simulation time 11733132727 ps
CPU time 4.97 seconds
Started Aug 08 04:31:51 PM PDT 24
Finished Aug 08 04:31:56 PM PDT 24
Peak memory 199756 kb
Host smart-f24f8171-4297-4fc3-ad1e-d66b6e57929b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797192155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1797192155
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.960741796
Short name T697
Test name
Test status
Simulation time 13611470 ps
CPU time 0.58 seconds
Started Aug 08 04:33:03 PM PDT 24
Finished Aug 08 04:33:03 PM PDT 24
Peak memory 195144 kb
Host smart-c3597550-1895-4538-8037-c894c7841b52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960741796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.960741796
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1760557410
Short name T260
Test name
Test status
Simulation time 59853871600 ps
CPU time 118.96 seconds
Started Aug 08 04:33:03 PM PDT 24
Finished Aug 08 04:35:03 PM PDT 24
Peak memory 200108 kb
Host smart-891f2592-0dd2-43a9-ac78-6e266dc108e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760557410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1760557410
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3030499184
Short name T132
Test name
Test status
Simulation time 15992510886 ps
CPU time 21.9 seconds
Started Aug 08 04:33:04 PM PDT 24
Finished Aug 08 04:33:26 PM PDT 24
Peak memory 198948 kb
Host smart-5c254fba-1dba-484a-b26f-70ed2499edb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030499184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3030499184
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2170249331
Short name T1152
Test name
Test status
Simulation time 29606080225 ps
CPU time 30.77 seconds
Started Aug 08 04:33:03 PM PDT 24
Finished Aug 08 04:33:34 PM PDT 24
Peak memory 199716 kb
Host smart-e8cf1a3f-9b07-48af-a24a-f667fe4952f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170249331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2170249331
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.4273360756
Short name T15
Test name
Test status
Simulation time 32794194314 ps
CPU time 28.57 seconds
Started Aug 08 04:33:05 PM PDT 24
Finished Aug 08 04:33:33 PM PDT 24
Peak memory 198220 kb
Host smart-146d59c8-b31f-4ac1-b14c-0e1f3ae7f3c4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273360756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.4273360756
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_loopback.3596842693
Short name T1014
Test name
Test status
Simulation time 5817311130 ps
CPU time 11.21 seconds
Started Aug 08 04:33:02 PM PDT 24
Finished Aug 08 04:33:14 PM PDT 24
Peak memory 198336 kb
Host smart-c063f488-8c6d-4eec-a75a-093e91a1abea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596842693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3596842693
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_perf.442004133
Short name T580
Test name
Test status
Simulation time 15752776005 ps
CPU time 108.35 seconds
Started Aug 08 04:33:02 PM PDT 24
Finished Aug 08 04:34:50 PM PDT 24
Peak memory 199856 kb
Host smart-20452307-3de9-440b-b5b8-277ecd1f3171
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=442004133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.442004133
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1398313942
Short name T485
Test name
Test status
Simulation time 5776002514 ps
CPU time 41.43 seconds
Started Aug 08 04:33:09 PM PDT 24
Finished Aug 08 04:33:51 PM PDT 24
Peak memory 198620 kb
Host smart-014e5a05-ea8d-405c-94d9-6e07a17f8e25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1398313942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1398313942
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2776485292
Short name T1170
Test name
Test status
Simulation time 143763847811 ps
CPU time 77.56 seconds
Started Aug 08 04:33:04 PM PDT 24
Finished Aug 08 04:34:21 PM PDT 24
Peak memory 199592 kb
Host smart-b7d88e3a-d8da-47dd-a3c3-1362af26349c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776485292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2776485292
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2103963199
Short name T45
Test name
Test status
Simulation time 3066306847 ps
CPU time 5.57 seconds
Started Aug 08 04:33:04 PM PDT 24
Finished Aug 08 04:33:10 PM PDT 24
Peak memory 196272 kb
Host smart-c874689a-6805-4a98-9d3e-0de4a6e013d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103963199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2103963199
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3934816344
Short name T957
Test name
Test status
Simulation time 309428560 ps
CPU time 0.97 seconds
Started Aug 08 04:33:09 PM PDT 24
Finished Aug 08 04:33:10 PM PDT 24
Peak memory 198412 kb
Host smart-956b483e-25b1-41e4-a57d-01692d97eac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934816344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3934816344
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.3163250089
Short name T449
Test name
Test status
Simulation time 57546853904 ps
CPU time 55.55 seconds
Started Aug 08 04:33:04 PM PDT 24
Finished Aug 08 04:33:59 PM PDT 24
Peak memory 199720 kb
Host smart-0ab30362-0c76-409b-aa7d-be8f53f17630
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163250089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3163250089
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1354398371
Short name T623
Test name
Test status
Simulation time 7078007035 ps
CPU time 19.22 seconds
Started Aug 08 04:33:03 PM PDT 24
Finished Aug 08 04:33:22 PM PDT 24
Peak memory 199676 kb
Host smart-80344bca-a51f-4945-af95-fc7d5bc9d240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354398371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1354398371
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.219818079
Short name T717
Test name
Test status
Simulation time 84375719847 ps
CPU time 43.18 seconds
Started Aug 08 04:33:10 PM PDT 24
Finished Aug 08 04:33:53 PM PDT 24
Peak memory 199756 kb
Host smart-b9371cd0-dfe2-43ad-afbf-ade38bb0a221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219818079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.219818079
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.926932638
Short name T861
Test name
Test status
Simulation time 35967922965 ps
CPU time 26.81 seconds
Started Aug 08 04:39:07 PM PDT 24
Finished Aug 08 04:39:34 PM PDT 24
Peak memory 199752 kb
Host smart-26056ba9-5bbc-40a0-98f0-0d0446cc7a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926932638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.926932638
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3959979519
Short name T778
Test name
Test status
Simulation time 129237785517 ps
CPU time 41.18 seconds
Started Aug 08 04:39:05 PM PDT 24
Finished Aug 08 04:39:46 PM PDT 24
Peak memory 199768 kb
Host smart-406dc1f0-07cb-479f-91e1-578cc69146cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959979519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3959979519
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.113046262
Short name T34
Test name
Test status
Simulation time 18538810776 ps
CPU time 25.48 seconds
Started Aug 08 04:39:13 PM PDT 24
Finished Aug 08 04:39:39 PM PDT 24
Peak memory 199828 kb
Host smart-d598b021-46c3-4ee2-87bf-7b41c04a0dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113046262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.113046262
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.682833804
Short name T227
Test name
Test status
Simulation time 36465405548 ps
CPU time 32.96 seconds
Started Aug 08 04:39:05 PM PDT 24
Finished Aug 08 04:39:38 PM PDT 24
Peak memory 199792 kb
Host smart-5b720ed9-036b-493f-a21c-2fd6e134c4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682833804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.682833804
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1471564154
Short name T1048
Test name
Test status
Simulation time 56187312041 ps
CPU time 13.2 seconds
Started Aug 08 04:39:04 PM PDT 24
Finished Aug 08 04:39:17 PM PDT 24
Peak memory 199760 kb
Host smart-6cd8de34-2a64-4c37-a1c2-840083f4d4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471564154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1471564154
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.493289817
Short name T705
Test name
Test status
Simulation time 11114920902 ps
CPU time 22.65 seconds
Started Aug 08 04:39:06 PM PDT 24
Finished Aug 08 04:39:28 PM PDT 24
Peak memory 199796 kb
Host smart-4f94d777-f75d-4449-b57e-984f7d37fd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493289817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.493289817
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1083663893
Short name T244
Test name
Test status
Simulation time 71892883852 ps
CPU time 30.82 seconds
Started Aug 08 04:39:05 PM PDT 24
Finished Aug 08 04:39:36 PM PDT 24
Peak memory 199624 kb
Host smart-991e3c15-a1ff-4794-a275-1cc016517189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083663893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1083663893
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3771246798
Short name T860
Test name
Test status
Simulation time 38867869473 ps
CPU time 56.08 seconds
Started Aug 08 04:39:07 PM PDT 24
Finished Aug 08 04:40:03 PM PDT 24
Peak memory 200164 kb
Host smart-a97a8b84-29b8-49b3-bf37-b58232752853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771246798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3771246798
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3928798640
Short name T975
Test name
Test status
Simulation time 22306714 ps
CPU time 0.55 seconds
Started Aug 08 04:33:16 PM PDT 24
Finished Aug 08 04:33:16 PM PDT 24
Peak memory 194604 kb
Host smart-7c2d5063-d976-443e-bbae-6d42f0d92c47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928798640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3928798640
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2175920390
Short name T514
Test name
Test status
Simulation time 57727835230 ps
CPU time 23.76 seconds
Started Aug 08 04:33:04 PM PDT 24
Finished Aug 08 04:33:28 PM PDT 24
Peak memory 199824 kb
Host smart-ba69c10f-d2e5-4ded-8e88-aea2401f359e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175920390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2175920390
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2147959998
Short name T33
Test name
Test status
Simulation time 20185691738 ps
CPU time 31.76 seconds
Started Aug 08 04:33:14 PM PDT 24
Finished Aug 08 04:33:46 PM PDT 24
Peak memory 199764 kb
Host smart-917a496b-a288-4ad6-84d8-9a3210c564d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147959998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2147959998
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.4124899871
Short name T596
Test name
Test status
Simulation time 140703420382 ps
CPU time 396.14 seconds
Started Aug 08 04:33:14 PM PDT 24
Finished Aug 08 04:39:50 PM PDT 24
Peak memory 199716 kb
Host smart-4932f597-bb0a-40f5-931a-e3ce6c8077a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124899871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.4124899871
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3525400595
Short name T463
Test name
Test status
Simulation time 2294460504 ps
CPU time 8.93 seconds
Started Aug 08 04:33:14 PM PDT 24
Finished Aug 08 04:33:23 PM PDT 24
Peak memory 199796 kb
Host smart-c9430f72-aba6-404e-980f-ead401969ad9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525400595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3525400595
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2100768933
Short name T366
Test name
Test status
Simulation time 212625035374 ps
CPU time 288.68 seconds
Started Aug 08 04:33:16 PM PDT 24
Finished Aug 08 04:38:05 PM PDT 24
Peak memory 199724 kb
Host smart-60cc07a4-9e1b-4fb5-9511-7cc3bb79627e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2100768933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2100768933
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2953631576
Short name T1075
Test name
Test status
Simulation time 4532146472 ps
CPU time 2.12 seconds
Started Aug 08 04:33:18 PM PDT 24
Finished Aug 08 04:33:21 PM PDT 24
Peak memory 198780 kb
Host smart-50eb9cff-6d1a-4b45-b8f3-976a67678a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953631576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2953631576
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1419169607
Short name T1022
Test name
Test status
Simulation time 14744300718 ps
CPU time 23.77 seconds
Started Aug 08 04:33:15 PM PDT 24
Finished Aug 08 04:33:39 PM PDT 24
Peak memory 198036 kb
Host smart-830c768b-e931-4dae-a684-2f479cc1099b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419169607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1419169607
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3001211864
Short name T1089
Test name
Test status
Simulation time 20383980070 ps
CPU time 193.48 seconds
Started Aug 08 04:33:14 PM PDT 24
Finished Aug 08 04:36:28 PM PDT 24
Peak memory 199788 kb
Host smart-3ae6c7ee-bae0-4975-b724-65ed1be0ed3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3001211864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3001211864
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3123053694
Short name T733
Test name
Test status
Simulation time 4026715509 ps
CPU time 10.31 seconds
Started Aug 08 04:33:15 PM PDT 24
Finished Aug 08 04:33:25 PM PDT 24
Peak memory 197828 kb
Host smart-0349e8a7-6a5d-4133-8e29-81a6fd22ae74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3123053694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3123053694
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2120006029
Short name T1096
Test name
Test status
Simulation time 90966965638 ps
CPU time 12.56 seconds
Started Aug 08 04:33:14 PM PDT 24
Finished Aug 08 04:33:27 PM PDT 24
Peak memory 199768 kb
Host smart-b8b8c532-74ee-4dac-86bf-264dcf28f615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120006029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2120006029
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3940577934
Short name T445
Test name
Test status
Simulation time 3153486661 ps
CPU time 2 seconds
Started Aug 08 04:33:16 PM PDT 24
Finished Aug 08 04:33:18 PM PDT 24
Peak memory 195740 kb
Host smart-744229d9-2657-4cfc-ac79-08ec093db335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940577934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3940577934
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1588029668
Short name T753
Test name
Test status
Simulation time 507087215 ps
CPU time 3.24 seconds
Started Aug 08 04:33:04 PM PDT 24
Finished Aug 08 04:33:07 PM PDT 24
Peak memory 198512 kb
Host smart-3919b734-2d5c-4878-b55c-9da7853dfdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588029668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1588029668
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3187995231
Short name T428
Test name
Test status
Simulation time 353872115389 ps
CPU time 1152.12 seconds
Started Aug 08 04:33:15 PM PDT 24
Finished Aug 08 04:52:27 PM PDT 24
Peak memory 199768 kb
Host smart-a6653c9b-82e4-4e74-8f84-36024c3b2b8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187995231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3187995231
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.979244758
Short name T965
Test name
Test status
Simulation time 103374221315 ps
CPU time 408.6 seconds
Started Aug 08 04:33:16 PM PDT 24
Finished Aug 08 04:40:04 PM PDT 24
Peak memory 215852 kb
Host smart-9ddc35f2-fd3c-4b8d-8850-18b14a8362bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979244758 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.979244758
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2488893393
Short name T521
Test name
Test status
Simulation time 1514071041 ps
CPU time 2.84 seconds
Started Aug 08 04:33:15 PM PDT 24
Finished Aug 08 04:33:18 PM PDT 24
Peak memory 198336 kb
Host smart-b5069966-4f38-4233-9eee-cbd27de42433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488893393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2488893393
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.4112098389
Short name T963
Test name
Test status
Simulation time 36380808215 ps
CPU time 51.1 seconds
Started Aug 08 04:33:05 PM PDT 24
Finished Aug 08 04:33:56 PM PDT 24
Peak memory 199760 kb
Host smart-c1fd4325-be07-4c78-95e0-b4a9ee17fb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112098389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.4112098389
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1963220723
Short name T467
Test name
Test status
Simulation time 9845240227 ps
CPU time 19.17 seconds
Started Aug 08 04:39:06 PM PDT 24
Finished Aug 08 04:39:25 PM PDT 24
Peak memory 199756 kb
Host smart-abecbe0f-3af2-44a6-941d-8f4f080e259e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963220723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1963220723
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.642496861
Short name T346
Test name
Test status
Simulation time 83208018258 ps
CPU time 129.77 seconds
Started Aug 08 04:39:18 PM PDT 24
Finished Aug 08 04:41:28 PM PDT 24
Peak memory 199756 kb
Host smart-c5a4c0f7-a6e5-4194-95d9-6678b1481422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642496861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.642496861
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2980904980
Short name T889
Test name
Test status
Simulation time 24319338897 ps
CPU time 46.78 seconds
Started Aug 08 04:39:17 PM PDT 24
Finished Aug 08 04:40:04 PM PDT 24
Peak memory 199728 kb
Host smart-a4649d00-d80d-421a-bbf2-e96674d7649c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980904980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2980904980
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1193362335
Short name T479
Test name
Test status
Simulation time 183876923235 ps
CPU time 23.27 seconds
Started Aug 08 04:39:18 PM PDT 24
Finished Aug 08 04:39:41 PM PDT 24
Peak memory 199776 kb
Host smart-00b952fe-3620-4bd0-a322-2cec6ab2cc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193362335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1193362335
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.443151196
Short name T839
Test name
Test status
Simulation time 206017760400 ps
CPU time 55.29 seconds
Started Aug 08 04:39:17 PM PDT 24
Finished Aug 08 04:40:12 PM PDT 24
Peak memory 199760 kb
Host smart-3ca37ec9-445d-42c1-8132-8dd8893da6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443151196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.443151196
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2401591382
Short name T696
Test name
Test status
Simulation time 32849450753 ps
CPU time 52.02 seconds
Started Aug 08 04:39:20 PM PDT 24
Finished Aug 08 04:40:12 PM PDT 24
Peak memory 199748 kb
Host smart-f6e0884e-fc61-4832-ac57-ec18399aa98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401591382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2401591382
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3598559652
Short name T1070
Test name
Test status
Simulation time 130174470541 ps
CPU time 65.02 seconds
Started Aug 08 04:39:19 PM PDT 24
Finished Aug 08 04:40:24 PM PDT 24
Peak memory 199792 kb
Host smart-b826dd09-8d65-4d42-9b26-b58afb029a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598559652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3598559652
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2397771764
Short name T784
Test name
Test status
Simulation time 79758734030 ps
CPU time 37.55 seconds
Started Aug 08 04:39:20 PM PDT 24
Finished Aug 08 04:39:58 PM PDT 24
Peak memory 200104 kb
Host smart-58e021f0-df46-47f0-b36f-f34e9353201b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397771764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2397771764
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2365407140
Short name T866
Test name
Test status
Simulation time 120522629 ps
CPU time 0.54 seconds
Started Aug 08 04:33:31 PM PDT 24
Finished Aug 08 04:33:32 PM PDT 24
Peak memory 195200 kb
Host smart-de3ee95d-5cbd-4e4b-897b-8a560fedc74a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365407140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2365407140
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1503731865
Short name T606
Test name
Test status
Simulation time 152892204344 ps
CPU time 66.8 seconds
Started Aug 08 04:33:16 PM PDT 24
Finished Aug 08 04:34:23 PM PDT 24
Peak memory 199688 kb
Host smart-f624e964-f871-48d7-85e1-0e3e52d42a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503731865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1503731865
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1712497869
Short name T744
Test name
Test status
Simulation time 16684534075 ps
CPU time 27.55 seconds
Started Aug 08 04:33:16 PM PDT 24
Finished Aug 08 04:33:44 PM PDT 24
Peak memory 199840 kb
Host smart-ef83288d-71bd-489b-a82b-f23ffa845534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712497869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1712497869
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.9011182
Short name T497
Test name
Test status
Simulation time 106639981057 ps
CPU time 198.33 seconds
Started Aug 08 04:33:15 PM PDT 24
Finished Aug 08 04:36:33 PM PDT 24
Peak memory 199760 kb
Host smart-42f2a79b-4f87-44a0-a6ad-6fb2c56eb866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9011182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.9011182
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.4184055148
Short name T1153
Test name
Test status
Simulation time 251368868310 ps
CPU time 407.07 seconds
Started Aug 08 04:33:15 PM PDT 24
Finished Aug 08 04:40:02 PM PDT 24
Peak memory 197340 kb
Host smart-57b846f9-59a0-43e9-91ff-ea61c9e78771
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184055148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.4184055148
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1468535299
Short name T871
Test name
Test status
Simulation time 207865501230 ps
CPU time 237.83 seconds
Started Aug 08 04:33:27 PM PDT 24
Finished Aug 08 04:37:25 PM PDT 24
Peak memory 199664 kb
Host smart-6c309770-0f7b-40ed-9163-619d129f59a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1468535299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1468535299
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1276260916
Short name T1110
Test name
Test status
Simulation time 72890883 ps
CPU time 0.7 seconds
Started Aug 08 04:33:29 PM PDT 24
Finished Aug 08 04:33:30 PM PDT 24
Peak memory 195784 kb
Host smart-e92403ba-c93f-44a4-bf56-092b1a048b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276260916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1276260916
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2678296315
Short name T617
Test name
Test status
Simulation time 108385289189 ps
CPU time 46.45 seconds
Started Aug 08 04:33:15 PM PDT 24
Finished Aug 08 04:34:01 PM PDT 24
Peak memory 198980 kb
Host smart-40beced6-aef5-4cb6-b12c-7affa0d0e5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678296315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2678296315
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2590700560
Short name T648
Test name
Test status
Simulation time 4166975352 ps
CPU time 243.51 seconds
Started Aug 08 04:33:30 PM PDT 24
Finished Aug 08 04:37:34 PM PDT 24
Peak memory 199836 kb
Host smart-2087641f-3cee-4715-8358-e28ddd6898cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2590700560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2590700560
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.945894658
Short name T810
Test name
Test status
Simulation time 3432788521 ps
CPU time 3.77 seconds
Started Aug 08 04:33:18 PM PDT 24
Finished Aug 08 04:33:22 PM PDT 24
Peak memory 197936 kb
Host smart-82e071a5-8ef8-47da-8bc2-79e1da487fe8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=945894658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.945894658
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.24357401
Short name T147
Test name
Test status
Simulation time 75498391420 ps
CPU time 28.42 seconds
Started Aug 08 04:33:31 PM PDT 24
Finished Aug 08 04:33:59 PM PDT 24
Peak memory 199792 kb
Host smart-ec2ff42c-f722-43cc-93a0-3637b70c060e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24357401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.24357401
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1072368217
Short name T292
Test name
Test status
Simulation time 4200432905 ps
CPU time 2.42 seconds
Started Aug 08 04:33:15 PM PDT 24
Finished Aug 08 04:33:18 PM PDT 24
Peak memory 196372 kb
Host smart-bc1db491-7d22-4378-8b0d-4a0ff9b7947c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072368217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1072368217
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_stress_all.3338406697
Short name T899
Test name
Test status
Simulation time 72012090107 ps
CPU time 105.62 seconds
Started Aug 08 04:33:31 PM PDT 24
Finished Aug 08 04:35:16 PM PDT 24
Peak memory 199784 kb
Host smart-ffc6cb9d-e53d-4879-85c5-c170dca88045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338406697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3338406697
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2882605446
Short name T53
Test name
Test status
Simulation time 552152152983 ps
CPU time 543.6 seconds
Started Aug 08 04:33:30 PM PDT 24
Finished Aug 08 04:42:33 PM PDT 24
Peak memory 224616 kb
Host smart-f84a1c76-0d9f-490b-b12c-0b4dded41224
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882605446 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2882605446
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2061619187
Short name T773
Test name
Test status
Simulation time 596801487 ps
CPU time 1.48 seconds
Started Aug 08 04:33:26 PM PDT 24
Finished Aug 08 04:33:27 PM PDT 24
Peak memory 198424 kb
Host smart-233de563-7554-4319-a8fa-bdbad315fbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061619187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2061619187
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1348220358
Short name T933
Test name
Test status
Simulation time 53926209335 ps
CPU time 23.85 seconds
Started Aug 08 04:33:16 PM PDT 24
Finished Aug 08 04:33:40 PM PDT 24
Peak memory 199808 kb
Host smart-59a09c3b-b4bd-4d09-8368-854bd7985344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348220358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1348220358
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3632148047
Short name T1034
Test name
Test status
Simulation time 47832943280 ps
CPU time 79.32 seconds
Started Aug 08 04:39:17 PM PDT 24
Finished Aug 08 04:40:37 PM PDT 24
Peak memory 199516 kb
Host smart-533bf2e2-2e8b-4ef6-9aa3-7b8c4cede15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632148047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3632148047
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.737063637
Short name T265
Test name
Test status
Simulation time 16893134926 ps
CPU time 14.49 seconds
Started Aug 08 04:39:19 PM PDT 24
Finished Aug 08 04:39:33 PM PDT 24
Peak memory 199756 kb
Host smart-22646d32-7422-4ade-aeef-206ac00ffd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737063637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.737063637
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.154756005
Short name T183
Test name
Test status
Simulation time 55119491643 ps
CPU time 88.21 seconds
Started Aug 08 04:39:18 PM PDT 24
Finished Aug 08 04:40:46 PM PDT 24
Peak memory 199692 kb
Host smart-05f9d95f-4ea5-4d2b-b148-2d0400e72c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154756005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.154756005
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2813070639
Short name T712
Test name
Test status
Simulation time 16935858129 ps
CPU time 34.88 seconds
Started Aug 08 04:39:18 PM PDT 24
Finished Aug 08 04:39:53 PM PDT 24
Peak memory 199832 kb
Host smart-749689da-844a-49c0-8979-87d52af583ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813070639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2813070639
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1756286119
Short name T152
Test name
Test status
Simulation time 50112210117 ps
CPU time 43.43 seconds
Started Aug 08 04:39:37 PM PDT 24
Finished Aug 08 04:40:20 PM PDT 24
Peak memory 199800 kb
Host smart-9eb7c45f-1514-4759-8d11-a59113d75b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756286119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1756286119
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2100873845
Short name T1055
Test name
Test status
Simulation time 48857219064 ps
CPU time 74.6 seconds
Started Aug 08 04:39:30 PM PDT 24
Finished Aug 08 04:40:45 PM PDT 24
Peak memory 199736 kb
Host smart-d8738805-a1c4-46ff-859d-a29be55ecbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100873845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2100873845
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2479633413
Short name T980
Test name
Test status
Simulation time 58583911454 ps
CPU time 70.33 seconds
Started Aug 08 04:39:33 PM PDT 24
Finished Aug 08 04:40:43 PM PDT 24
Peak memory 199780 kb
Host smart-420fcea7-c92e-49b8-b890-c55984ac5621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479633413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2479633413
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1229362393
Short name T667
Test name
Test status
Simulation time 65632489 ps
CPU time 0.54 seconds
Started Aug 08 04:33:39 PM PDT 24
Finished Aug 08 04:33:40 PM PDT 24
Peak memory 195244 kb
Host smart-91163137-d423-4700-bfce-2168bbe9ed6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229362393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1229362393
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1453475814
Short name T100
Test name
Test status
Simulation time 240718151039 ps
CPU time 37.82 seconds
Started Aug 08 04:33:28 PM PDT 24
Finished Aug 08 04:34:06 PM PDT 24
Peak memory 199816 kb
Host smart-7515986d-e741-47c9-8291-662d65bef58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453475814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1453475814
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.307436580
Short name T340
Test name
Test status
Simulation time 164869466493 ps
CPU time 53.96 seconds
Started Aug 08 04:33:28 PM PDT 24
Finished Aug 08 04:34:22 PM PDT 24
Peak memory 199720 kb
Host smart-4c2e885b-9942-4c0f-8237-de531d131d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307436580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.307436580
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2616567871
Short name T734
Test name
Test status
Simulation time 100158252115 ps
CPU time 81.04 seconds
Started Aug 08 04:33:27 PM PDT 24
Finished Aug 08 04:34:48 PM PDT 24
Peak memory 199772 kb
Host smart-83c67ace-50e0-45cf-96c6-fe745e84b311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616567871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2616567871
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3337828789
Short name T118
Test name
Test status
Simulation time 87393989765 ps
CPU time 36.48 seconds
Started Aug 08 04:33:27 PM PDT 24
Finished Aug 08 04:34:03 PM PDT 24
Peak memory 199768 kb
Host smart-d0a185cf-64a4-4592-89e3-3d93c41dce51
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337828789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3337828789
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1147138319
Short name T526
Test name
Test status
Simulation time 90775569308 ps
CPU time 184.04 seconds
Started Aug 08 04:33:27 PM PDT 24
Finished Aug 08 04:36:31 PM PDT 24
Peak memory 199836 kb
Host smart-a5d6b6fa-624c-4bca-8774-1e540cc984ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1147138319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1147138319
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.2447254739
Short name T362
Test name
Test status
Simulation time 4833766938 ps
CPU time 20.79 seconds
Started Aug 08 04:33:27 PM PDT 24
Finished Aug 08 04:33:47 PM PDT 24
Peak memory 199840 kb
Host smart-062f96b0-8d8e-4950-afb1-ca653a50ac49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447254739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2447254739
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1691130528
Short name T535
Test name
Test status
Simulation time 37081044735 ps
CPU time 74.46 seconds
Started Aug 08 04:33:28 PM PDT 24
Finished Aug 08 04:34:42 PM PDT 24
Peak memory 208016 kb
Host smart-ef9df407-db0e-4120-8773-2a90bd9c318a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691130528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1691130528
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3776599547
Short name T1058
Test name
Test status
Simulation time 7999482968 ps
CPU time 125.16 seconds
Started Aug 08 04:33:27 PM PDT 24
Finished Aug 08 04:35:32 PM PDT 24
Peak memory 199720 kb
Host smart-da05d725-0bb1-459c-bb3f-703ccad22f41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3776599547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3776599547
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.4171205713
Short name T764
Test name
Test status
Simulation time 2555665983 ps
CPU time 4.91 seconds
Started Aug 08 04:33:30 PM PDT 24
Finished Aug 08 04:33:35 PM PDT 24
Peak memory 198784 kb
Host smart-92473108-34f5-4dda-9920-4061129bb0ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4171205713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.4171205713
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.4037220520
Short name T917
Test name
Test status
Simulation time 24862773306 ps
CPU time 41.87 seconds
Started Aug 08 04:33:30 PM PDT 24
Finished Aug 08 04:34:12 PM PDT 24
Peak memory 199676 kb
Host smart-2f270665-e774-42f2-80b3-92b81ab4bc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037220520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.4037220520
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2197532589
Short name T678
Test name
Test status
Simulation time 46939519892 ps
CPU time 15.18 seconds
Started Aug 08 04:33:31 PM PDT 24
Finished Aug 08 04:33:46 PM PDT 24
Peak memory 196072 kb
Host smart-b01b055c-53bc-460d-81d9-f62b41aedc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197532589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2197532589
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1387619348
Short name T297
Test name
Test status
Simulation time 928955068 ps
CPU time 3.39 seconds
Started Aug 08 04:33:30 PM PDT 24
Finished Aug 08 04:33:34 PM PDT 24
Peak memory 198112 kb
Host smart-c786ac2f-ddc8-4f01-9e69-ca1278682038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387619348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1387619348
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.2208944815
Short name T478
Test name
Test status
Simulation time 278797773240 ps
CPU time 459.39 seconds
Started Aug 08 04:33:43 PM PDT 24
Finished Aug 08 04:41:23 PM PDT 24
Peak memory 208148 kb
Host smart-778f927f-3c67-4900-b973-f2a74e251830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208944815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2208944815
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3839213863
Short name T58
Test name
Test status
Simulation time 203987586870 ps
CPU time 979.63 seconds
Started Aug 08 04:33:26 PM PDT 24
Finished Aug 08 04:49:46 PM PDT 24
Peak memory 216004 kb
Host smart-8ca6059f-43ad-4c05-88a3-2a7e98c9a315
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839213863 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3839213863
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2256356296
Short name T655
Test name
Test status
Simulation time 2201239597 ps
CPU time 2.09 seconds
Started Aug 08 04:33:31 PM PDT 24
Finished Aug 08 04:33:33 PM PDT 24
Peak memory 199452 kb
Host smart-5239b983-9b43-496a-a96d-aa87121cd02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256356296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2256356296
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.4039490364
Short name T1140
Test name
Test status
Simulation time 29553069264 ps
CPU time 36.13 seconds
Started Aug 08 04:33:28 PM PDT 24
Finished Aug 08 04:34:04 PM PDT 24
Peak memory 199700 kb
Host smart-944a2f2a-e4ed-43ab-809c-526b0363a2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039490364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.4039490364
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3005517983
Short name T804
Test name
Test status
Simulation time 228822647903 ps
CPU time 248.8 seconds
Started Aug 08 04:39:30 PM PDT 24
Finished Aug 08 04:43:39 PM PDT 24
Peak memory 199760 kb
Host smart-696277e4-9259-40a8-ad1d-7ad2f5b703df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005517983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3005517983
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.142905072
Short name T281
Test name
Test status
Simulation time 129273408274 ps
CPU time 191.89 seconds
Started Aug 08 04:39:35 PM PDT 24
Finished Aug 08 04:42:47 PM PDT 24
Peak memory 199720 kb
Host smart-090492ed-e78d-41b2-bb68-1f32d977fceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142905072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.142905072
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.375588473
Short name T780
Test name
Test status
Simulation time 8275694218 ps
CPU time 9.96 seconds
Started Aug 08 04:39:30 PM PDT 24
Finished Aug 08 04:39:40 PM PDT 24
Peak memory 199780 kb
Host smart-0f16e775-80d0-4b61-b3cd-c05b3a8baccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375588473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.375588473
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1398053329
Short name T595
Test name
Test status
Simulation time 91909758227 ps
CPU time 61.05 seconds
Started Aug 08 04:39:32 PM PDT 24
Finished Aug 08 04:40:33 PM PDT 24
Peak memory 199804 kb
Host smart-7cccb1da-8b12-47b5-a4fc-e91ad41665f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398053329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1398053329
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2383886034
Short name T263
Test name
Test status
Simulation time 138268128240 ps
CPU time 31.8 seconds
Started Aug 08 04:39:30 PM PDT 24
Finished Aug 08 04:40:02 PM PDT 24
Peak memory 199744 kb
Host smart-cbccee3e-d0c2-4d5d-9f10-3f52830f174e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383886034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2383886034
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.35594655
Short name T194
Test name
Test status
Simulation time 39970399180 ps
CPU time 178.77 seconds
Started Aug 08 04:39:32 PM PDT 24
Finished Aug 08 04:42:31 PM PDT 24
Peak memory 199792 kb
Host smart-f8a7db6b-31a3-4a89-ab0e-21367fca1c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35594655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.35594655
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2797474156
Short name T1077
Test name
Test status
Simulation time 69785358547 ps
CPU time 22.02 seconds
Started Aug 08 04:39:36 PM PDT 24
Finished Aug 08 04:39:58 PM PDT 24
Peak memory 199752 kb
Host smart-0ca1849e-ef5a-4d01-972b-9617fdc3a973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797474156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2797474156
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.202814258
Short name T489
Test name
Test status
Simulation time 31638338856 ps
CPU time 13 seconds
Started Aug 08 04:39:31 PM PDT 24
Finished Aug 08 04:39:44 PM PDT 24
Peak memory 199532 kb
Host smart-aa282883-073c-407c-8f3b-ac8755d6ea3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202814258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.202814258
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2001922408
Short name T750
Test name
Test status
Simulation time 38844278439 ps
CPU time 47.95 seconds
Started Aug 08 04:39:33 PM PDT 24
Finished Aug 08 04:40:21 PM PDT 24
Peak memory 199744 kb
Host smart-a00d0f9c-93ec-4b2b-8986-54b6cbc4824b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001922408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2001922408
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1005940148
Short name T1029
Test name
Test status
Simulation time 100335314 ps
CPU time 0.57 seconds
Started Aug 08 04:33:40 PM PDT 24
Finished Aug 08 04:33:41 PM PDT 24
Peak memory 195428 kb
Host smart-c932ab4e-8ed2-40c3-a5a4-2beae8dd509e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005940148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1005940148
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.123759293
Short name T934
Test name
Test status
Simulation time 165962934945 ps
CPU time 240.99 seconds
Started Aug 08 04:33:39 PM PDT 24
Finished Aug 08 04:37:40 PM PDT 24
Peak memory 199768 kb
Host smart-0d5ecc27-f496-4bbe-a3b7-920beb9a8413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123759293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.123759293
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1933150745
Short name T1180
Test name
Test status
Simulation time 118589208028 ps
CPU time 222.78 seconds
Started Aug 08 04:33:40 PM PDT 24
Finished Aug 08 04:37:22 PM PDT 24
Peak memory 199716 kb
Host smart-f10114c5-d508-4f04-bd15-65a6223af70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933150745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1933150745
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1480601324
Short name T1009
Test name
Test status
Simulation time 138278626690 ps
CPU time 50.3 seconds
Started Aug 08 04:33:44 PM PDT 24
Finished Aug 08 04:34:35 PM PDT 24
Peak memory 199656 kb
Host smart-2b0f5118-9868-4e77-9b17-594bc3417df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480601324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1480601324
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3993016506
Short name T1083
Test name
Test status
Simulation time 561508085822 ps
CPU time 209.92 seconds
Started Aug 08 04:33:39 PM PDT 24
Finished Aug 08 04:37:09 PM PDT 24
Peak memory 198924 kb
Host smart-69d0558f-c0bc-4eaa-af26-5375f9ca6816
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993016506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3993016506
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2726058201
Short name T765
Test name
Test status
Simulation time 108917382520 ps
CPU time 507.07 seconds
Started Aug 08 04:33:44 PM PDT 24
Finished Aug 08 04:42:11 PM PDT 24
Peak memory 199744 kb
Host smart-3da5b812-c727-4614-a273-72ba634b0882
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2726058201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2726058201
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.1414200285
Short name T974
Test name
Test status
Simulation time 4656244755 ps
CPU time 10.23 seconds
Started Aug 08 04:33:38 PM PDT 24
Finished Aug 08 04:33:48 PM PDT 24
Peak memory 199096 kb
Host smart-ea337a9e-894d-4343-ba90-addd99c98731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414200285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1414200285
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1659635769
Short name T884
Test name
Test status
Simulation time 70632913061 ps
CPU time 55.51 seconds
Started Aug 08 04:33:44 PM PDT 24
Finished Aug 08 04:34:40 PM PDT 24
Peak memory 198744 kb
Host smart-518d5ad0-60b7-44cc-9373-5b0d06cc5f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659635769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1659635769
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.33654079
Short name T856
Test name
Test status
Simulation time 9400876278 ps
CPU time 265.63 seconds
Started Aug 08 04:33:38 PM PDT 24
Finished Aug 08 04:38:04 PM PDT 24
Peak memory 199792 kb
Host smart-b2f20ad4-e351-491a-842f-203d30cae04f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33654079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.33654079
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1140617703
Short name T569
Test name
Test status
Simulation time 3247504670 ps
CPU time 1.85 seconds
Started Aug 08 04:33:39 PM PDT 24
Finished Aug 08 04:33:41 PM PDT 24
Peak memory 198128 kb
Host smart-958bd91d-78a3-4b12-8a70-8e51eb8ca00f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1140617703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1140617703
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2698543264
Short name T706
Test name
Test status
Simulation time 258924633764 ps
CPU time 195.04 seconds
Started Aug 08 04:33:45 PM PDT 24
Finished Aug 08 04:37:00 PM PDT 24
Peak memory 199736 kb
Host smart-a2c016e7-1c32-4394-ae79-214583de44bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698543264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2698543264
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3402652059
Short name T1134
Test name
Test status
Simulation time 1550303376 ps
CPU time 1.42 seconds
Started Aug 08 04:33:39 PM PDT 24
Finished Aug 08 04:33:41 PM PDT 24
Peak memory 195288 kb
Host smart-411cd75b-8c45-4e43-8f33-d395bcd20ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402652059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3402652059
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1630863923
Short name T777
Test name
Test status
Simulation time 899353830 ps
CPU time 2.02 seconds
Started Aug 08 04:33:38 PM PDT 24
Finished Aug 08 04:33:40 PM PDT 24
Peak memory 199392 kb
Host smart-a542c238-c2ee-4121-9ec6-e2d788c803f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630863923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1630863923
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.3628336726
Short name T157
Test name
Test status
Simulation time 256164744716 ps
CPU time 182.72 seconds
Started Aug 08 04:33:38 PM PDT 24
Finished Aug 08 04:36:41 PM PDT 24
Peak memory 199832 kb
Host smart-5ff91b83-de66-4461-86bb-38110c624675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628336726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3628336726
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.4254220687
Short name T1019
Test name
Test status
Simulation time 139115082060 ps
CPU time 556.45 seconds
Started Aug 08 04:33:43 PM PDT 24
Finished Aug 08 04:43:00 PM PDT 24
Peak memory 216284 kb
Host smart-28a09350-5cad-4485-a3d9-fca6fbf4ef50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254220687 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.4254220687
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3802483955
Short name T986
Test name
Test status
Simulation time 684613508 ps
CPU time 1.63 seconds
Started Aug 08 04:33:40 PM PDT 24
Finished Aug 08 04:33:42 PM PDT 24
Peak memory 198432 kb
Host smart-26b8fa4d-eed2-40b8-a9ed-51d34354e073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802483955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3802483955
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3132819761
Short name T313
Test name
Test status
Simulation time 16705495506 ps
CPU time 13.37 seconds
Started Aug 08 04:33:38 PM PDT 24
Finished Aug 08 04:33:52 PM PDT 24
Peak memory 199644 kb
Host smart-ff466811-2400-483b-a9ef-c9e9a9a85bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132819761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3132819761
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1572620031
Short name T185
Test name
Test status
Simulation time 214413165737 ps
CPU time 132.34 seconds
Started Aug 08 04:39:33 PM PDT 24
Finished Aug 08 04:41:45 PM PDT 24
Peak memory 199696 kb
Host smart-fe893c78-c137-4508-b9c8-9b99ec1ea69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572620031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1572620031
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3507513811
Short name T464
Test name
Test status
Simulation time 71543483761 ps
CPU time 156.35 seconds
Started Aug 08 04:39:36 PM PDT 24
Finished Aug 08 04:42:12 PM PDT 24
Peak memory 199780 kb
Host smart-bb8693ee-14db-4aee-93e9-c3cffc1960c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507513811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3507513811
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3999133192
Short name T51
Test name
Test status
Simulation time 13162366315 ps
CPU time 20.97 seconds
Started Aug 08 04:39:35 PM PDT 24
Finished Aug 08 04:39:56 PM PDT 24
Peak memory 199404 kb
Host smart-0eb2146b-535a-4c8c-8fa7-5a0e0091d6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999133192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3999133192
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3770881832
Short name T393
Test name
Test status
Simulation time 64072101885 ps
CPU time 101.11 seconds
Started Aug 08 04:39:37 PM PDT 24
Finished Aug 08 04:41:18 PM PDT 24
Peak memory 199812 kb
Host smart-f4e3a0d9-fdda-441a-a688-3889ba4e9c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770881832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3770881832
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2478661492
Short name T1177
Test name
Test status
Simulation time 123682614144 ps
CPU time 152.95 seconds
Started Aug 08 04:39:30 PM PDT 24
Finished Aug 08 04:42:03 PM PDT 24
Peak memory 199700 kb
Host smart-707ffc4c-9138-4b87-9937-38a4742d1341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478661492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2478661492
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2949428392
Short name T1181
Test name
Test status
Simulation time 236656764251 ps
CPU time 49.74 seconds
Started Aug 08 04:39:30 PM PDT 24
Finished Aug 08 04:40:20 PM PDT 24
Peak memory 199872 kb
Host smart-5fdf41a1-03bd-4cbe-bd63-144b38f46fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949428392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2949428392
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2807522321
Short name T1044
Test name
Test status
Simulation time 148618059660 ps
CPU time 84.68 seconds
Started Aug 08 04:39:32 PM PDT 24
Finished Aug 08 04:40:56 PM PDT 24
Peak memory 199728 kb
Host smart-5427065a-6b82-4aee-b292-dfaf005ab592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807522321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2807522321
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3600146768
Short name T441
Test name
Test status
Simulation time 37143978 ps
CPU time 0.56 seconds
Started Aug 08 04:33:49 PM PDT 24
Finished Aug 08 04:33:50 PM PDT 24
Peak memory 195500 kb
Host smart-fc3502b0-8158-49a7-a667-8281c16a3ae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600146768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3600146768
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.3330620340
Short name T303
Test name
Test status
Simulation time 7387452717 ps
CPU time 12.29 seconds
Started Aug 08 04:33:50 PM PDT 24
Finished Aug 08 04:34:03 PM PDT 24
Peak memory 199780 kb
Host smart-9fd54020-c440-4eb5-b2ec-9a3d51490809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330620340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3330620340
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_intr.2200792985
Short name T798
Test name
Test status
Simulation time 21457646431 ps
CPU time 34.4 seconds
Started Aug 08 04:33:48 PM PDT 24
Finished Aug 08 04:34:23 PM PDT 24
Peak memory 199788 kb
Host smart-9af4811a-3591-47ed-8fef-7473f4f58505
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200792985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2200792985
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1179957802
Short name T3
Test name
Test status
Simulation time 173112227906 ps
CPU time 172.6 seconds
Started Aug 08 04:33:49 PM PDT 24
Finished Aug 08 04:36:41 PM PDT 24
Peak memory 199788 kb
Host smart-15baac74-d744-4565-872e-ec44da971b52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1179957802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1179957802
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1620360096
Short name T820
Test name
Test status
Simulation time 5603518503 ps
CPU time 5.94 seconds
Started Aug 08 04:33:49 PM PDT 24
Finished Aug 08 04:33:55 PM PDT 24
Peak memory 197740 kb
Host smart-326ebe99-c7fb-4bd6-827a-8ab1373c0629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620360096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1620360096
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3044724863
Short name T1112
Test name
Test status
Simulation time 45185501612 ps
CPU time 73.34 seconds
Started Aug 08 04:33:51 PM PDT 24
Finished Aug 08 04:35:04 PM PDT 24
Peak memory 199948 kb
Host smart-a68e9882-b0dd-4703-af3d-950918fed46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044724863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3044724863
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3661512022
Short name T867
Test name
Test status
Simulation time 13830317406 ps
CPU time 73.79 seconds
Started Aug 08 04:33:49 PM PDT 24
Finished Aug 08 04:35:03 PM PDT 24
Peak memory 199752 kb
Host smart-ee2f9086-8266-48dd-97c9-a8292cdc003e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3661512022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3661512022
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2547069321
Short name T1143
Test name
Test status
Simulation time 1182569911 ps
CPU time 1 seconds
Started Aug 08 04:33:50 PM PDT 24
Finished Aug 08 04:33:51 PM PDT 24
Peak memory 195352 kb
Host smart-c33adf46-b2d8-4276-bbb6-d383f6560c1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2547069321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2547069321
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.74564100
Short name T590
Test name
Test status
Simulation time 66168613374 ps
CPU time 108.59 seconds
Started Aug 08 04:33:49 PM PDT 24
Finished Aug 08 04:35:38 PM PDT 24
Peak memory 199760 kb
Host smart-ec86055e-8c83-40ce-849d-368c5418ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74564100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.74564100
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3496048070
Short name T450
Test name
Test status
Simulation time 4777840609 ps
CPU time 4.03 seconds
Started Aug 08 04:33:49 PM PDT 24
Finished Aug 08 04:33:54 PM PDT 24
Peak memory 196596 kb
Host smart-3ddc8d22-ee84-458c-9bd8-897a04ee2d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496048070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3496048070
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3773692829
Short name T729
Test name
Test status
Simulation time 6159924996 ps
CPU time 11.82 seconds
Started Aug 08 04:33:38 PM PDT 24
Finished Aug 08 04:33:50 PM PDT 24
Peak memory 199712 kb
Host smart-44cb4e01-0718-497b-a2cc-9f9fd9fc943c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773692829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3773692829
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3808741459
Short name T26
Test name
Test status
Simulation time 17957422106 ps
CPU time 254.13 seconds
Started Aug 08 04:33:48 PM PDT 24
Finished Aug 08 04:38:03 PM PDT 24
Peak memory 216348 kb
Host smart-34860215-2a31-4e95-a619-3fa3d2cdd6ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808741459 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3808741459
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3090660689
Short name T37
Test name
Test status
Simulation time 319950077 ps
CPU time 1.24 seconds
Started Aug 08 04:33:49 PM PDT 24
Finished Aug 08 04:33:50 PM PDT 24
Peak memory 197924 kb
Host smart-d0452029-a800-48be-82f4-7113d75c1b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090660689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3090660689
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3606441697
Short name T872
Test name
Test status
Simulation time 30241542129 ps
CPU time 46.39 seconds
Started Aug 08 04:33:37 PM PDT 24
Finished Aug 08 04:34:24 PM PDT 24
Peak memory 199656 kb
Host smart-453eeddc-b073-4bb3-bcfe-c280fbc00a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606441697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3606441697
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2489869804
Short name T812
Test name
Test status
Simulation time 14674928720 ps
CPU time 12.34 seconds
Started Aug 08 04:39:49 PM PDT 24
Finished Aug 08 04:40:01 PM PDT 24
Peak memory 199748 kb
Host smart-3ef18718-51a1-4900-8bbe-9e08537f3c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489869804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2489869804
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1217562279
Short name T840
Test name
Test status
Simulation time 173783638326 ps
CPU time 26.16 seconds
Started Aug 08 04:39:40 PM PDT 24
Finished Aug 08 04:40:06 PM PDT 24
Peak memory 199408 kb
Host smart-3ed249b9-01d6-4916-bccd-0ed357182675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217562279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1217562279
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1487809670
Short name T985
Test name
Test status
Simulation time 113630151840 ps
CPU time 26.53 seconds
Started Aug 08 04:39:49 PM PDT 24
Finished Aug 08 04:40:16 PM PDT 24
Peak memory 199836 kb
Host smart-7789e936-8538-492b-867f-408dc1f821c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487809670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1487809670
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.4198392262
Short name T605
Test name
Test status
Simulation time 30563840913 ps
CPU time 15.13 seconds
Started Aug 08 04:39:40 PM PDT 24
Finished Aug 08 04:39:55 PM PDT 24
Peak memory 199820 kb
Host smart-0c919200-468f-4d9a-aa7a-7392c204f0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198392262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.4198392262
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1096632929
Short name T721
Test name
Test status
Simulation time 43907217294 ps
CPU time 18.4 seconds
Started Aug 08 04:39:40 PM PDT 24
Finished Aug 08 04:39:58 PM PDT 24
Peak memory 199736 kb
Host smart-a45d40cb-8759-490b-bbd5-31effcae2579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096632929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1096632929
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2498295469
Short name T509
Test name
Test status
Simulation time 89627325469 ps
CPU time 67.64 seconds
Started Aug 08 04:39:56 PM PDT 24
Finished Aug 08 04:41:04 PM PDT 24
Peak memory 199792 kb
Host smart-a058c90a-98cd-4476-8ea1-75bd461fed52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498295469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2498295469
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2466504503
Short name T216
Test name
Test status
Simulation time 75180250587 ps
CPU time 50.45 seconds
Started Aug 08 04:39:39 PM PDT 24
Finished Aug 08 04:40:29 PM PDT 24
Peak memory 199740 kb
Host smart-4fa2a5d1-1137-40d4-a717-aad8643c0a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466504503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2466504503
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1270358220
Short name T1164
Test name
Test status
Simulation time 30162104401 ps
CPU time 19.76 seconds
Started Aug 08 04:39:50 PM PDT 24
Finished Aug 08 04:40:10 PM PDT 24
Peak memory 199756 kb
Host smart-7b034f91-b083-4449-afef-590f222ec8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270358220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1270358220
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1600659703
Short name T1071
Test name
Test status
Simulation time 98889008815 ps
CPU time 171.28 seconds
Started Aug 08 04:39:39 PM PDT 24
Finished Aug 08 04:42:30 PM PDT 24
Peak memory 199776 kb
Host smart-b4c5a294-0210-4cb6-a782-c6d77a9cf96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600659703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1600659703
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2402461918
Short name T538
Test name
Test status
Simulation time 11217943289 ps
CPU time 22.52 seconds
Started Aug 08 04:39:44 PM PDT 24
Finished Aug 08 04:40:06 PM PDT 24
Peak memory 199736 kb
Host smart-5a6180eb-94e5-41fc-9db5-43b594c9eaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402461918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2402461918
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1626048020
Short name T953
Test name
Test status
Simulation time 15089911 ps
CPU time 0.57 seconds
Started Aug 08 04:34:02 PM PDT 24
Finished Aug 08 04:34:03 PM PDT 24
Peak memory 195268 kb
Host smart-139810ee-ac14-4b06-b72a-20d30b7a0625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626048020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1626048020
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2824125547
Short name T567
Test name
Test status
Simulation time 116484696955 ps
CPU time 187.74 seconds
Started Aug 08 04:33:51 PM PDT 24
Finished Aug 08 04:36:59 PM PDT 24
Peak memory 199796 kb
Host smart-30e15232-b9fd-47b7-b0d5-252ca7901d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824125547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2824125547
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1378000271
Short name T155
Test name
Test status
Simulation time 35672435747 ps
CPU time 17.59 seconds
Started Aug 08 04:33:52 PM PDT 24
Finished Aug 08 04:34:09 PM PDT 24
Peak memory 199820 kb
Host smart-9fabb98c-dee3-4975-9ff3-a7fb77b3034e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378000271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1378000271
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.867658490
Short name T795
Test name
Test status
Simulation time 33170186725 ps
CPU time 27.86 seconds
Started Aug 08 04:33:49 PM PDT 24
Finished Aug 08 04:34:17 PM PDT 24
Peak memory 199748 kb
Host smart-721ee388-b860-4be8-ae3f-92c45d5fe2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867658490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.867658490
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1872233517
Short name T581
Test name
Test status
Simulation time 59990440601 ps
CPU time 99.32 seconds
Started Aug 08 04:33:50 PM PDT 24
Finished Aug 08 04:35:30 PM PDT 24
Peak memory 199776 kb
Host smart-8e839b47-b37c-496f-ad20-f282f28fe73a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872233517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1872233517
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1010282243
Short name T1005
Test name
Test status
Simulation time 133394660954 ps
CPU time 876.85 seconds
Started Aug 08 04:34:01 PM PDT 24
Finished Aug 08 04:48:38 PM PDT 24
Peak memory 199740 kb
Host smart-c5d66239-e016-439e-8a00-1e404c922e04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1010282243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1010282243
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2606116178
Short name T360
Test name
Test status
Simulation time 3318910533 ps
CPU time 9.63 seconds
Started Aug 08 04:34:01 PM PDT 24
Finished Aug 08 04:34:11 PM PDT 24
Peak memory 199544 kb
Host smart-2ae3fdaa-fb7f-4fa3-89bb-6216e2419fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606116178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2606116178
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2886333908
Short name T682
Test name
Test status
Simulation time 88204787506 ps
CPU time 171.28 seconds
Started Aug 08 04:33:51 PM PDT 24
Finished Aug 08 04:36:42 PM PDT 24
Peak memory 199596 kb
Host smart-07ef6b59-a529-405d-82bc-21b1970cb710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886333908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2886333908
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.4182233888
Short name T1100
Test name
Test status
Simulation time 17802453461 ps
CPU time 136.87 seconds
Started Aug 08 04:34:03 PM PDT 24
Finished Aug 08 04:36:20 PM PDT 24
Peak memory 199868 kb
Host smart-beb1527e-ae8a-4c6f-b053-410bf78ccd52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182233888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.4182233888
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1155046020
Short name T392
Test name
Test status
Simulation time 1586104188 ps
CPU time 6.39 seconds
Started Aug 08 04:33:49 PM PDT 24
Finished Aug 08 04:33:56 PM PDT 24
Peak memory 199160 kb
Host smart-89a2e0db-88c4-4f60-a8ec-8d92ace05902
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1155046020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1155046020
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3843981130
Short name T269
Test name
Test status
Simulation time 186160768831 ps
CPU time 721.04 seconds
Started Aug 08 04:33:51 PM PDT 24
Finished Aug 08 04:45:52 PM PDT 24
Peak memory 199796 kb
Host smart-c27b6d11-c9bf-44ea-a636-413196203fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843981130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3843981130
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1035893700
Short name T405
Test name
Test status
Simulation time 3352200646 ps
CPU time 5.49 seconds
Started Aug 08 04:33:48 PM PDT 24
Finished Aug 08 04:33:54 PM PDT 24
Peak memory 196324 kb
Host smart-7313c9b2-4bdf-4b8e-8e85-cc3fbc4cbf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035893700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1035893700
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.527823266
Short name T1015
Test name
Test status
Simulation time 870724396 ps
CPU time 2.24 seconds
Started Aug 08 04:33:49 PM PDT 24
Finished Aug 08 04:33:51 PM PDT 24
Peak memory 198204 kb
Host smart-bb74e80d-3946-4640-9e4a-12d282a8f8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527823266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.527823266
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.1118047620
Short name T156
Test name
Test status
Simulation time 306858210814 ps
CPU time 162.43 seconds
Started Aug 08 04:34:01 PM PDT 24
Finished Aug 08 04:36:44 PM PDT 24
Peak memory 216120 kb
Host smart-a53afbb4-bc94-42fd-a6fa-7d8345564365
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118047620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1118047620
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2077771311
Short name T59
Test name
Test status
Simulation time 69267150226 ps
CPU time 345.72 seconds
Started Aug 08 04:34:02 PM PDT 24
Finished Aug 08 04:39:48 PM PDT 24
Peak memory 216420 kb
Host smart-caeb1ac4-293c-46d0-b386-851f5dd3148a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077771311 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2077771311
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.4075358890
Short name T271
Test name
Test status
Simulation time 1071308240 ps
CPU time 3.85 seconds
Started Aug 08 04:34:03 PM PDT 24
Finished Aug 08 04:34:07 PM PDT 24
Peak memory 199488 kb
Host smart-fc6ed1ab-69fe-4e9d-95e3-f05eb566631a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075358890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.4075358890
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2698251814
Short name T815
Test name
Test status
Simulation time 53876639112 ps
CPU time 79.31 seconds
Started Aug 08 04:33:48 PM PDT 24
Finished Aug 08 04:35:08 PM PDT 24
Peak memory 199732 kb
Host smart-8c2d6ba4-a9b4-49bb-894b-4a723c1b4ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698251814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2698251814
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.4194624391
Short name T901
Test name
Test status
Simulation time 75663641605 ps
CPU time 119.42 seconds
Started Aug 08 04:39:48 PM PDT 24
Finished Aug 08 04:41:47 PM PDT 24
Peak memory 199700 kb
Host smart-bde96225-533f-4451-9ccc-56c70be858cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194624391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.4194624391
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.4277206425
Short name T206
Test name
Test status
Simulation time 14521934892 ps
CPU time 28.34 seconds
Started Aug 08 04:39:40 PM PDT 24
Finished Aug 08 04:40:08 PM PDT 24
Peak memory 199776 kb
Host smart-56d8ef83-9e8d-46bf-96fe-a5fd5e5f4b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277206425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.4277206425
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2809360989
Short name T96
Test name
Test status
Simulation time 63960135359 ps
CPU time 66.7 seconds
Started Aug 08 04:39:41 PM PDT 24
Finished Aug 08 04:40:48 PM PDT 24
Peak memory 199740 kb
Host smart-1c540cfc-b16e-46d1-99cd-01c903282d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809360989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2809360989
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2154337764
Short name T217
Test name
Test status
Simulation time 6994580611 ps
CPU time 16.44 seconds
Started Aug 08 04:39:52 PM PDT 24
Finished Aug 08 04:40:08 PM PDT 24
Peak memory 199828 kb
Host smart-2881d966-45ee-43c2-9389-5c6a2072a064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154337764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2154337764
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1095089894
Short name T439
Test name
Test status
Simulation time 24344872619 ps
CPU time 39.29 seconds
Started Aug 08 04:40:51 PM PDT 24
Finished Aug 08 04:41:31 PM PDT 24
Peak memory 198956 kb
Host smart-08a60a1f-572d-4249-80e9-0ca8e55f89b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095089894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1095089894
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1670678467
Short name T991
Test name
Test status
Simulation time 25696816277 ps
CPU time 17.9 seconds
Started Aug 08 04:40:06 PM PDT 24
Finished Aug 08 04:40:24 PM PDT 24
Peak memory 199836 kb
Host smart-a4320183-c827-4ecc-9f66-5871847ac9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670678467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1670678467
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3073534185
Short name T1159
Test name
Test status
Simulation time 223353807341 ps
CPU time 230.74 seconds
Started Aug 08 04:34:02 PM PDT 24
Finished Aug 08 04:37:53 PM PDT 24
Peak memory 199728 kb
Host smart-2e6fabbd-1271-4988-9066-fe8cdb3a80dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073534185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3073534185
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1677818765
Short name T772
Test name
Test status
Simulation time 58362954569 ps
CPU time 92.49 seconds
Started Aug 08 04:34:01 PM PDT 24
Finished Aug 08 04:35:33 PM PDT 24
Peak memory 199812 kb
Host smart-cf0ddd42-9ee4-4bbc-926e-76ba47530f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677818765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1677818765
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_intr.189086320
Short name T929
Test name
Test status
Simulation time 69076529996 ps
CPU time 26.09 seconds
Started Aug 08 04:34:01 PM PDT 24
Finished Aug 08 04:34:27 PM PDT 24
Peak memory 199808 kb
Host smart-2bd37777-a25b-4911-823b-496fb458a1bf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189086320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.189086320
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.594085271
Short name T1092
Test name
Test status
Simulation time 72427953188 ps
CPU time 551.6 seconds
Started Aug 08 04:34:01 PM PDT 24
Finished Aug 08 04:43:13 PM PDT 24
Peak memory 199772 kb
Host smart-38cca0b4-0a02-41ad-9f1a-fc7b1ee94363
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=594085271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.594085271
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.177522935
Short name T10
Test name
Test status
Simulation time 3491529304 ps
CPU time 2.21 seconds
Started Aug 08 04:34:02 PM PDT 24
Finished Aug 08 04:34:04 PM PDT 24
Peak memory 196548 kb
Host smart-feb8c10b-7839-47a3-8d73-a16087efe4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177522935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.177522935
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2001281656
Short name T724
Test name
Test status
Simulation time 122494693291 ps
CPU time 124.94 seconds
Started Aug 08 04:34:01 PM PDT 24
Finished Aug 08 04:36:06 PM PDT 24
Peak memory 208000 kb
Host smart-d63e1c93-ef7c-4f94-a3ae-06cda11e0d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001281656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2001281656
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.1712427974
Short name T400
Test name
Test status
Simulation time 7210054385 ps
CPU time 417.22 seconds
Started Aug 08 04:34:01 PM PDT 24
Finished Aug 08 04:40:59 PM PDT 24
Peak memory 199876 kb
Host smart-c18bae59-f562-43fa-a6fc-881d118fc68e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1712427974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1712427974
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.1578275385
Short name T711
Test name
Test status
Simulation time 1899095404 ps
CPU time 7.88 seconds
Started Aug 08 04:34:03 PM PDT 24
Finished Aug 08 04:34:10 PM PDT 24
Peak memory 197780 kb
Host smart-f86a9b46-f9e1-4005-8fb5-f2de0fba266b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1578275385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1578275385
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3364793435
Short name T161
Test name
Test status
Simulation time 19681186852 ps
CPU time 23.46 seconds
Started Aug 08 04:34:02 PM PDT 24
Finished Aug 08 04:34:26 PM PDT 24
Peak memory 199844 kb
Host smart-b1ba2b59-af42-4436-b6c0-a187f1200ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364793435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3364793435
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1741933654
Short name T542
Test name
Test status
Simulation time 43920594740 ps
CPU time 11.74 seconds
Started Aug 08 04:34:01 PM PDT 24
Finished Aug 08 04:34:13 PM PDT 24
Peak memory 195940 kb
Host smart-3ecbbad3-f4cf-434e-821a-ef25c161ab1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741933654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1741933654
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2383187656
Short name T751
Test name
Test status
Simulation time 655295346 ps
CPU time 1.98 seconds
Started Aug 08 04:34:02 PM PDT 24
Finished Aug 08 04:34:04 PM PDT 24
Peak memory 198704 kb
Host smart-de86d1ea-93b1-4b6d-86bd-9f056adbc048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383187656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2383187656
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.723682829
Short name T1003
Test name
Test status
Simulation time 134959950361 ps
CPU time 238.94 seconds
Started Aug 08 04:34:03 PM PDT 24
Finished Aug 08 04:38:02 PM PDT 24
Peak memory 199800 kb
Host smart-89cf9fa0-c0c0-481d-be3b-760bd86366e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723682829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.723682829
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.4289291657
Short name T56
Test name
Test status
Simulation time 80372801785 ps
CPU time 178 seconds
Started Aug 08 04:34:03 PM PDT 24
Finished Aug 08 04:37:01 PM PDT 24
Peak memory 215452 kb
Host smart-093053c7-5cd8-436d-a149-a24719fd478c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289291657 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.4289291657
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.3304666587
Short name T1156
Test name
Test status
Simulation time 1721255454 ps
CPU time 3.01 seconds
Started Aug 08 04:34:02 PM PDT 24
Finished Aug 08 04:34:05 PM PDT 24
Peak memory 198452 kb
Host smart-a79d7cee-4d63-4a57-a0e8-a09634f6d70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304666587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3304666587
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.587666374
Short name T261
Test name
Test status
Simulation time 72813193279 ps
CPU time 60.89 seconds
Started Aug 08 04:34:02 PM PDT 24
Finished Aug 08 04:35:03 PM PDT 24
Peak memory 199824 kb
Host smart-aa3cecfd-29ee-49b3-b78f-934414faec68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587666374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.587666374
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2204090793
Short name T236
Test name
Test status
Simulation time 23299973914 ps
CPU time 39.22 seconds
Started Aug 08 04:40:08 PM PDT 24
Finished Aug 08 04:40:47 PM PDT 24
Peak memory 199800 kb
Host smart-bbeb54e4-0708-4f95-b63d-f0ca917fd024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204090793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2204090793
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3794482623
Short name T801
Test name
Test status
Simulation time 109315326124 ps
CPU time 381.03 seconds
Started Aug 08 04:39:50 PM PDT 24
Finished Aug 08 04:46:11 PM PDT 24
Peak memory 199756 kb
Host smart-f28d46ee-02ba-49c2-ad5f-2cd855ce185a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794482623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3794482623
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1890424342
Short name T278
Test name
Test status
Simulation time 122128862584 ps
CPU time 197.83 seconds
Started Aug 08 04:39:50 PM PDT 24
Finished Aug 08 04:43:08 PM PDT 24
Peak memory 199464 kb
Host smart-8ef0698d-8f9d-44b1-a507-6419c29d894d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890424342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1890424342
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1441781552
Short name T39
Test name
Test status
Simulation time 100114535652 ps
CPU time 144.8 seconds
Started Aug 08 04:41:00 PM PDT 24
Finished Aug 08 04:43:25 PM PDT 24
Peak memory 199468 kb
Host smart-05b3c11f-319a-4153-b68a-da2239774b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441781552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1441781552
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.377859010
Short name T453
Test name
Test status
Simulation time 16893283500 ps
CPU time 29.21 seconds
Started Aug 08 04:39:50 PM PDT 24
Finished Aug 08 04:40:19 PM PDT 24
Peak memory 199752 kb
Host smart-d0e37a5c-9835-4e93-b619-17b470cec6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377859010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.377859010
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3631169976
Short name T189
Test name
Test status
Simulation time 119686185397 ps
CPU time 95.31 seconds
Started Aug 08 04:40:07 PM PDT 24
Finished Aug 08 04:41:42 PM PDT 24
Peak memory 199756 kb
Host smart-bdbd5d9a-b77e-4187-a5bf-72dd37c296e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631169976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3631169976
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2461340101
Short name T341
Test name
Test status
Simulation time 14412472662 ps
CPU time 11.43 seconds
Started Aug 08 04:39:50 PM PDT 24
Finished Aug 08 04:40:01 PM PDT 24
Peak memory 199644 kb
Host smart-69ef10a8-639f-4909-a08c-8d2bd6a138bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461340101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2461340101
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3548652814
Short name T913
Test name
Test status
Simulation time 65888660900 ps
CPU time 22.05 seconds
Started Aug 08 04:40:59 PM PDT 24
Finished Aug 08 04:41:21 PM PDT 24
Peak memory 199396 kb
Host smart-aa8761fe-c84f-4414-a64a-2341dd416d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548652814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3548652814
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3522249865
Short name T1049
Test name
Test status
Simulation time 25641164393 ps
CPU time 17.37 seconds
Started Aug 08 04:39:50 PM PDT 24
Finished Aug 08 04:40:07 PM PDT 24
Peak memory 199712 kb
Host smart-f2d069a1-d06b-43cd-8140-ea47b6b0c30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522249865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3522249865
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2617258858
Short name T824
Test name
Test status
Simulation time 17185195 ps
CPU time 0.58 seconds
Started Aug 08 04:34:12 PM PDT 24
Finished Aug 08 04:34:13 PM PDT 24
Peak memory 195232 kb
Host smart-48ef2089-1d62-4c66-89b9-710f2ae6e96b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617258858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2617258858
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3544645782
Short name T1118
Test name
Test status
Simulation time 180061204242 ps
CPU time 134.91 seconds
Started Aug 08 04:34:02 PM PDT 24
Finished Aug 08 04:36:17 PM PDT 24
Peak memory 199848 kb
Host smart-96020bea-881e-48c6-8775-6c250fe83397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544645782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3544645782
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2967418720
Short name T499
Test name
Test status
Simulation time 118451731916 ps
CPU time 43.5 seconds
Started Aug 08 04:34:04 PM PDT 24
Finished Aug 08 04:34:47 PM PDT 24
Peak memory 199720 kb
Host smart-d0286e72-cdee-4dac-82aa-7e8137b358f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967418720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2967418720
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_intr.2625837597
Short name T1099
Test name
Test status
Simulation time 70818167652 ps
CPU time 70.64 seconds
Started Aug 08 04:34:17 PM PDT 24
Finished Aug 08 04:35:28 PM PDT 24
Peak memory 199800 kb
Host smart-da5ecf7b-0f79-4d7f-a039-5d2ee27403e5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625837597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2625837597
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1596055458
Short name T657
Test name
Test status
Simulation time 113721262722 ps
CPU time 633.82 seconds
Started Aug 08 04:34:12 PM PDT 24
Finished Aug 08 04:44:46 PM PDT 24
Peak memory 199784 kb
Host smart-c7757bb1-4ef5-436d-bca3-a1b75f31486a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1596055458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1596055458
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1423670524
Short name T686
Test name
Test status
Simulation time 6024946805 ps
CPU time 10.6 seconds
Started Aug 08 04:34:15 PM PDT 24
Finished Aug 08 04:34:26 PM PDT 24
Peak memory 199620 kb
Host smart-4f835b9e-6b43-4170-92b4-42aa90945366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423670524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1423670524
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3819117390
Short name T544
Test name
Test status
Simulation time 37645235169 ps
CPU time 31.9 seconds
Started Aug 08 04:34:14 PM PDT 24
Finished Aug 08 04:34:46 PM PDT 24
Peak memory 199872 kb
Host smart-4ddd0f21-2a3a-4600-9ce3-aa9b2283b618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819117390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3819117390
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1953043274
Short name T1057
Test name
Test status
Simulation time 6742962519 ps
CPU time 250.17 seconds
Started Aug 08 04:34:12 PM PDT 24
Finished Aug 08 04:38:23 PM PDT 24
Peak memory 199720 kb
Host smart-8fc00bf5-b780-4b90-a0b4-92f734e5e8d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1953043274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1953043274
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1302278782
Short name T1155
Test name
Test status
Simulation time 4502635170 ps
CPU time 39.47 seconds
Started Aug 08 04:34:14 PM PDT 24
Finished Aug 08 04:34:54 PM PDT 24
Peak memory 199308 kb
Host smart-ddc706a4-1e99-423b-a13d-a7babb01924d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1302278782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1302278782
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1568470280
Short name T1046
Test name
Test status
Simulation time 4555817666 ps
CPU time 2.21 seconds
Started Aug 08 04:34:14 PM PDT 24
Finished Aug 08 04:34:17 PM PDT 24
Peak memory 196092 kb
Host smart-64b3d50a-de0a-484f-b817-22072f41f40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568470280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1568470280
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2604423268
Short name T308
Test name
Test status
Simulation time 6206379613 ps
CPU time 20.42 seconds
Started Aug 08 04:34:04 PM PDT 24
Finished Aug 08 04:34:25 PM PDT 24
Peak memory 199556 kb
Host smart-22a45e7e-e16d-4c6d-a28a-b05b3ec3fcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604423268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2604423268
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.608122572
Short name T827
Test name
Test status
Simulation time 123238300561 ps
CPU time 338.4 seconds
Started Aug 08 04:34:15 PM PDT 24
Finished Aug 08 04:39:53 PM PDT 24
Peak memory 199772 kb
Host smart-461e33db-46f9-4c0b-86c0-5259c32e2a97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608122572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.608122572
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2178912315
Short name T1136
Test name
Test status
Simulation time 73001104405 ps
CPU time 759.24 seconds
Started Aug 08 04:34:13 PM PDT 24
Finished Aug 08 04:46:52 PM PDT 24
Peak memory 224608 kb
Host smart-756e0a9e-aedf-42cd-b181-4375289c9904
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178912315 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2178912315
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1351592335
Short name T1104
Test name
Test status
Simulation time 1204968840 ps
CPU time 2.2 seconds
Started Aug 08 04:34:17 PM PDT 24
Finished Aug 08 04:34:20 PM PDT 24
Peak memory 199076 kb
Host smart-e7734d4b-e8f8-489c-8581-0c77edb43394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351592335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1351592335
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2184597138
Short name T656
Test name
Test status
Simulation time 34753363244 ps
CPU time 49.92 seconds
Started Aug 08 04:34:02 PM PDT 24
Finished Aug 08 04:34:52 PM PDT 24
Peak memory 199776 kb
Host smart-8fbdb67b-dc88-40a2-8378-e7174c1f583f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184597138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2184597138
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1824188720
Short name T205
Test name
Test status
Simulation time 35181123951 ps
CPU time 17.01 seconds
Started Aug 08 04:40:04 PM PDT 24
Finished Aug 08 04:40:21 PM PDT 24
Peak memory 199776 kb
Host smart-cdf5a60b-fe5c-4cf9-96ce-1d4c40ff9df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824188720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1824188720
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.905289078
Short name T240
Test name
Test status
Simulation time 79295966268 ps
CPU time 80.05 seconds
Started Aug 08 04:39:50 PM PDT 24
Finished Aug 08 04:41:10 PM PDT 24
Peak memory 199772 kb
Host smart-a0c2beb1-c5fa-47ba-bd94-687bed31236a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905289078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.905289078
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3641131655
Short name T1095
Test name
Test status
Simulation time 76414924268 ps
CPU time 34.46 seconds
Started Aug 08 04:39:49 PM PDT 24
Finished Aug 08 04:40:23 PM PDT 24
Peak memory 199848 kb
Host smart-e955fcec-416e-4861-819d-2d0b147a0ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641131655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3641131655
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.764712355
Short name T343
Test name
Test status
Simulation time 10216334999 ps
CPU time 26.97 seconds
Started Aug 08 04:39:59 PM PDT 24
Finished Aug 08 04:40:26 PM PDT 24
Peak memory 199728 kb
Host smart-fe93219c-8943-45b9-b856-7da42fd12721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764712355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.764712355
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3293181171
Short name T11
Test name
Test status
Simulation time 275106537404 ps
CPU time 54.04 seconds
Started Aug 08 04:40:02 PM PDT 24
Finished Aug 08 04:40:56 PM PDT 24
Peak memory 199788 kb
Host smart-a97c78a4-0c14-4420-8850-f1da83f334f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293181171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3293181171
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2036282805
Short name T1178
Test name
Test status
Simulation time 7071399892 ps
CPU time 13.17 seconds
Started Aug 08 04:40:11 PM PDT 24
Finished Aug 08 04:40:24 PM PDT 24
Peak memory 199692 kb
Host smart-3b90ebc5-28b3-40cb-91aa-d98ecee471cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036282805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2036282805
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3027650130
Short name T149
Test name
Test status
Simulation time 47856869677 ps
CPU time 9.53 seconds
Started Aug 08 04:40:11 PM PDT 24
Finished Aug 08 04:40:21 PM PDT 24
Peak memory 199780 kb
Host smart-681164af-e5eb-44d3-a96f-b264f26d1576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027650130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3027650130
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2442852955
Short name T624
Test name
Test status
Simulation time 13975779 ps
CPU time 0.58 seconds
Started Aug 08 04:34:30 PM PDT 24
Finished Aug 08 04:34:30 PM PDT 24
Peak memory 195200 kb
Host smart-19676d8a-04e9-4eef-85ab-1fe8688762ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442852955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2442852955
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.749882429
Short name T413
Test name
Test status
Simulation time 153421446468 ps
CPU time 34.17 seconds
Started Aug 08 04:34:13 PM PDT 24
Finished Aug 08 04:34:47 PM PDT 24
Peak memory 199720 kb
Host smart-718a784a-a316-4813-b26e-eaaa495d9adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749882429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.749882429
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.856212468
Short name T608
Test name
Test status
Simulation time 16300220433 ps
CPU time 24.25 seconds
Started Aug 08 04:34:14 PM PDT 24
Finished Aug 08 04:34:38 PM PDT 24
Peak memory 199184 kb
Host smart-ad84cdac-cd26-4dbc-9dcd-89617e60bc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856212468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.856212468
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.405533452
Short name T626
Test name
Test status
Simulation time 253074361786 ps
CPU time 35.95 seconds
Started Aug 08 04:34:14 PM PDT 24
Finished Aug 08 04:34:50 PM PDT 24
Peak memory 199768 kb
Host smart-8cdd1193-2e5f-4091-9720-163c0b299478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405533452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.405533452
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.2839954938
Short name T1108
Test name
Test status
Simulation time 50106608505 ps
CPU time 80.51 seconds
Started Aug 08 04:34:13 PM PDT 24
Finished Aug 08 04:35:33 PM PDT 24
Peak memory 199204 kb
Host smart-b4468129-e6be-4429-a8b8-e9a4b3c37630
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839954938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2839954938
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3993212
Short name T937
Test name
Test status
Simulation time 57983644075 ps
CPU time 261.37 seconds
Started Aug 08 04:34:30 PM PDT 24
Finished Aug 08 04:38:51 PM PDT 24
Peak memory 199716 kb
Host smart-12614014-92e0-47f5-9c05-b5a4b8a76109
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3993212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3993212
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.878932900
Short name T524
Test name
Test status
Simulation time 5645921557 ps
CPU time 3.92 seconds
Started Aug 08 04:34:14 PM PDT 24
Finished Aug 08 04:34:18 PM PDT 24
Peak memory 198948 kb
Host smart-ddbb4adc-39f6-49b1-a7e2-4bc97e1bb695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878932900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.878932900
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2318505140
Short name T469
Test name
Test status
Simulation time 261364724036 ps
CPU time 35.99 seconds
Started Aug 08 04:34:13 PM PDT 24
Finished Aug 08 04:34:49 PM PDT 24
Peak memory 199836 kb
Host smart-55986248-2de4-4d47-a8de-5720cca3a353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318505140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2318505140
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.2085113327
Short name T902
Test name
Test status
Simulation time 15907515031 ps
CPU time 107.9 seconds
Started Aug 08 04:34:15 PM PDT 24
Finished Aug 08 04:36:03 PM PDT 24
Peak memory 199784 kb
Host smart-62cb5e8d-9fe1-4baa-8f20-e0c52f1cf5cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2085113327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2085113327
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.4043415938
Short name T1135
Test name
Test status
Simulation time 2122972737 ps
CPU time 12.37 seconds
Started Aug 08 04:34:16 PM PDT 24
Finished Aug 08 04:34:28 PM PDT 24
Peak memory 197816 kb
Host smart-06692f7d-a4be-427a-a165-7f73d03fda14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4043415938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.4043415938
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2235134213
Short name T433
Test name
Test status
Simulation time 196960691220 ps
CPU time 286.14 seconds
Started Aug 08 04:34:15 PM PDT 24
Finished Aug 08 04:39:01 PM PDT 24
Peak memory 199832 kb
Host smart-c43ef12f-7ebc-48fc-a54b-5c3237c9bfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235134213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2235134213
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.654956599
Short name T687
Test name
Test status
Simulation time 4422227697 ps
CPU time 2.4 seconds
Started Aug 08 04:34:13 PM PDT 24
Finished Aug 08 04:34:16 PM PDT 24
Peak memory 196660 kb
Host smart-2c50c0a0-7ee1-4c4a-abf8-50ebf440d187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654956599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.654956599
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3289573536
Short name T926
Test name
Test status
Simulation time 5385247909 ps
CPU time 29.42 seconds
Started Aug 08 04:34:14 PM PDT 24
Finished Aug 08 04:34:43 PM PDT 24
Peak memory 199488 kb
Host smart-4da7c858-818d-48fc-bcf6-379c096824d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289573536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3289573536
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.4234364527
Short name T483
Test name
Test status
Simulation time 126678927390 ps
CPU time 54.92 seconds
Started Aug 08 04:34:27 PM PDT 24
Finished Aug 08 04:35:22 PM PDT 24
Peak memory 199852 kb
Host smart-7aae1cb2-d6be-4e0e-a3dd-2bb88fea9dca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234364527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.4234364527
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1754101543
Short name T935
Test name
Test status
Simulation time 123567493019 ps
CPU time 353.52 seconds
Started Aug 08 04:34:27 PM PDT 24
Finished Aug 08 04:40:21 PM PDT 24
Peak memory 216272 kb
Host smart-ff4622ad-442b-44e5-b76f-d7c4e8b7ca59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754101543 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1754101543
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3394659014
Short name T668
Test name
Test status
Simulation time 7248785212 ps
CPU time 8.48 seconds
Started Aug 08 04:34:14 PM PDT 24
Finished Aug 08 04:34:23 PM PDT 24
Peak memory 199824 kb
Host smart-1ab3491a-d424-418d-b056-64381cd963ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394659014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3394659014
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.28862819
Short name T504
Test name
Test status
Simulation time 25677772724 ps
CPU time 10.13 seconds
Started Aug 08 04:34:18 PM PDT 24
Finished Aug 08 04:34:28 PM PDT 24
Peak memory 196596 kb
Host smart-28e49bd0-e679-4402-948b-ce587f9d0795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28862819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.28862819
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.375467624
Short name T268
Test name
Test status
Simulation time 99057606962 ps
CPU time 68.39 seconds
Started Aug 08 04:40:03 PM PDT 24
Finished Aug 08 04:41:11 PM PDT 24
Peak memory 199732 kb
Host smart-b339e318-0a2b-406d-aa6b-208084cbe5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375467624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.375467624
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3622734974
Short name T558
Test name
Test status
Simulation time 175340122695 ps
CPU time 56.29 seconds
Started Aug 08 04:40:01 PM PDT 24
Finished Aug 08 04:40:58 PM PDT 24
Peak memory 199864 kb
Host smart-0536e6c9-8aab-4702-9ca3-309479670172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622734974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3622734974
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3017449423
Short name T643
Test name
Test status
Simulation time 102113784781 ps
CPU time 145.36 seconds
Started Aug 08 04:40:02 PM PDT 24
Finished Aug 08 04:42:27 PM PDT 24
Peak memory 200104 kb
Host smart-91ad0e1e-b171-49ab-a49c-e29de51d8369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017449423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3017449423
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1346518985
Short name T1107
Test name
Test status
Simulation time 93397719297 ps
CPU time 32.67 seconds
Started Aug 08 04:40:11 PM PDT 24
Finished Aug 08 04:40:44 PM PDT 24
Peak memory 199752 kb
Host smart-0b2efa03-61ea-4dfb-b1ee-3409168bcf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346518985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1346518985
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2450085786
Short name T1027
Test name
Test status
Simulation time 176666495740 ps
CPU time 66.73 seconds
Started Aug 08 04:40:36 PM PDT 24
Finished Aug 08 04:41:43 PM PDT 24
Peak memory 199692 kb
Host smart-f95d46e5-9bac-4d07-a4eb-f1f036b82c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450085786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2450085786
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1591084731
Short name T781
Test name
Test status
Simulation time 65390648573 ps
CPU time 21.32 seconds
Started Aug 08 04:40:00 PM PDT 24
Finished Aug 08 04:40:22 PM PDT 24
Peak memory 199792 kb
Host smart-6bf9c5cc-9254-443e-a3ff-6fcbcf13b371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591084731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1591084731
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3745756954
Short name T376
Test name
Test status
Simulation time 31140599800 ps
CPU time 13.79 seconds
Started Aug 08 04:40:01 PM PDT 24
Finished Aug 08 04:40:15 PM PDT 24
Peak memory 199812 kb
Host smart-b22f6cf5-e779-409b-bd38-dce71b21a1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745756954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3745756954
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3111140852
Short name T561
Test name
Test status
Simulation time 56026120449 ps
CPU time 99.83 seconds
Started Aug 08 04:40:01 PM PDT 24
Finished Aug 08 04:41:41 PM PDT 24
Peak memory 199708 kb
Host smart-ecfd44ad-c9d2-43a3-9e22-7c66928fcc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111140852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3111140852
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.652783910
Short name T981
Test name
Test status
Simulation time 44080794261 ps
CPU time 19.67 seconds
Started Aug 08 04:40:00 PM PDT 24
Finished Aug 08 04:40:20 PM PDT 24
Peak memory 199716 kb
Host smart-38ffb99f-8617-4894-81c8-215a399552a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652783910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.652783910
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1005021779
Short name T210
Test name
Test status
Simulation time 76931352501 ps
CPU time 122.1 seconds
Started Aug 08 04:40:00 PM PDT 24
Finished Aug 08 04:42:02 PM PDT 24
Peak memory 199768 kb
Host smart-1588da7e-6fdd-4b56-a961-c5fa92918719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005021779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1005021779
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2645886800
Short name T943
Test name
Test status
Simulation time 30153648 ps
CPU time 0.54 seconds
Started Aug 08 04:32:07 PM PDT 24
Finished Aug 08 04:32:07 PM PDT 24
Peak memory 194460 kb
Host smart-f6f4731e-e119-4f1a-becc-db93e0f3660e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645886800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2645886800
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.310750832
Short name T808
Test name
Test status
Simulation time 145214596051 ps
CPU time 622.17 seconds
Started Aug 08 04:32:06 PM PDT 24
Finished Aug 08 04:42:28 PM PDT 24
Peak memory 199804 kb
Host smart-d65d3afa-dcb1-4d44-a51b-d1bc1c92bf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310750832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.310750832
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2625392996
Short name T925
Test name
Test status
Simulation time 68342504641 ps
CPU time 27.24 seconds
Started Aug 08 04:32:07 PM PDT 24
Finished Aug 08 04:32:34 PM PDT 24
Peak memory 199724 kb
Host smart-de1af61b-4cbd-4244-954f-f0de6f12cc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625392996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2625392996
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1560853506
Short name T584
Test name
Test status
Simulation time 214718108939 ps
CPU time 328.01 seconds
Started Aug 08 04:32:06 PM PDT 24
Finished Aug 08 04:37:34 PM PDT 24
Peak memory 199876 kb
Host smart-823fcdca-cc3a-4793-ac64-52d0608aebb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560853506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1560853506
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1723829328
Short name T1030
Test name
Test status
Simulation time 48957751346 ps
CPU time 8.07 seconds
Started Aug 08 04:32:06 PM PDT 24
Finished Aug 08 04:32:15 PM PDT 24
Peak memory 200012 kb
Host smart-4b116af2-9c10-4261-ac9f-db8792fd88ed
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723829328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1723829328
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.4117807680
Short name T757
Test name
Test status
Simulation time 91152551136 ps
CPU time 558.25 seconds
Started Aug 08 04:32:06 PM PDT 24
Finished Aug 08 04:41:24 PM PDT 24
Peak memory 199656 kb
Host smart-e680d6d1-8676-4879-a039-89577c9d508b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4117807680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.4117807680
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.908985368
Short name T354
Test name
Test status
Simulation time 8925350933 ps
CPU time 22.41 seconds
Started Aug 08 04:32:04 PM PDT 24
Finished Aug 08 04:32:27 PM PDT 24
Peak memory 199824 kb
Host smart-c951a47a-3fc5-46ae-8717-64b44c6f0e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908985368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.908985368
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3135269713
Short name T505
Test name
Test status
Simulation time 141232186691 ps
CPU time 39.03 seconds
Started Aug 08 04:32:08 PM PDT 24
Finished Aug 08 04:32:47 PM PDT 24
Peak memory 199840 kb
Host smart-a7018ad5-01a8-4cb0-968b-7e65041cbd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135269713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3135269713
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.2161494686
Short name T296
Test name
Test status
Simulation time 17209993488 ps
CPU time 225.72 seconds
Started Aug 08 04:32:06 PM PDT 24
Finished Aug 08 04:35:52 PM PDT 24
Peak memory 199752 kb
Host smart-3a2ea17d-79ed-408e-baba-02801a576a16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2161494686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2161494686
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1214172005
Short name T20
Test name
Test status
Simulation time 1994146395 ps
CPU time 11.84 seconds
Started Aug 08 04:32:08 PM PDT 24
Finished Aug 08 04:32:20 PM PDT 24
Peak memory 198520 kb
Host smart-7da2aa29-9b35-40d4-936c-66c25f1d44e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214172005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1214172005
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.923958466
Short name T631
Test name
Test status
Simulation time 38251548660 ps
CPU time 10.23 seconds
Started Aug 08 04:32:06 PM PDT 24
Finished Aug 08 04:32:16 PM PDT 24
Peak memory 195648 kb
Host smart-396db2ea-c863-4593-bcb5-e30801653a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923958466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.923958466
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2159598110
Short name T95
Test name
Test status
Simulation time 64194450 ps
CPU time 0.84 seconds
Started Aug 08 04:32:08 PM PDT 24
Finished Aug 08 04:32:09 PM PDT 24
Peak memory 218212 kb
Host smart-b8f6ca96-a2aa-4b46-bd79-d39e868fd054
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159598110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2159598110
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1320432481
Short name T414
Test name
Test status
Simulation time 280649266 ps
CPU time 0.92 seconds
Started Aug 08 04:32:07 PM PDT 24
Finished Aug 08 04:32:08 PM PDT 24
Peak memory 199716 kb
Host smart-be5e951e-b2fb-4d78-ae02-f9690b523348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320432481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1320432481
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.547451218
Short name T1158
Test name
Test status
Simulation time 236252174231 ps
CPU time 793.17 seconds
Started Aug 08 04:32:08 PM PDT 24
Finished Aug 08 04:45:22 PM PDT 24
Peak memory 199792 kb
Host smart-820f9d38-f12f-4673-9d72-16431a2e7f38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547451218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.547451218
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.4178215240
Short name T437
Test name
Test status
Simulation time 287515895450 ps
CPU time 310.35 seconds
Started Aug 08 04:32:06 PM PDT 24
Finished Aug 08 04:37:16 PM PDT 24
Peak memory 216336 kb
Host smart-30a65427-5dbf-42af-9fce-dcd9dd6dcc3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178215240 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.4178215240
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.414533288
Short name T372
Test name
Test status
Simulation time 846950028 ps
CPU time 3.4 seconds
Started Aug 08 04:32:07 PM PDT 24
Finished Aug 08 04:32:11 PM PDT 24
Peak memory 199020 kb
Host smart-0a3325f6-260a-41b3-86aa-c64d0ca65c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414533288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.414533288
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2871431000
Short name T939
Test name
Test status
Simulation time 34917639044 ps
CPU time 32.32 seconds
Started Aug 08 04:32:06 PM PDT 24
Finished Aug 08 04:32:38 PM PDT 24
Peak memory 199720 kb
Host smart-5ea8cfa2-1832-4d71-a1d6-e477f62f6da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871431000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2871431000
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1973984522
Short name T1172
Test name
Test status
Simulation time 32498389 ps
CPU time 0.54 seconds
Started Aug 08 04:34:27 PM PDT 24
Finished Aug 08 04:34:28 PM PDT 24
Peak memory 194668 kb
Host smart-b5b1aa13-84a2-4f2a-a0e6-cd05b08af21b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973984522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1973984522
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.4283975524
Short name T615
Test name
Test status
Simulation time 91104626195 ps
CPU time 39.44 seconds
Started Aug 08 04:34:29 PM PDT 24
Finished Aug 08 04:35:09 PM PDT 24
Peak memory 199716 kb
Host smart-3297edf0-a10d-4779-8d75-d20fdf0c4844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283975524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.4283975524
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3234227050
Short name T460
Test name
Test status
Simulation time 41916887183 ps
CPU time 32.83 seconds
Started Aug 08 04:34:29 PM PDT 24
Finished Aug 08 04:35:02 PM PDT 24
Peak memory 199752 kb
Host smart-c8a347ec-3f74-4747-a088-8f506eae9051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234227050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3234227050
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.843662183
Short name T874
Test name
Test status
Simulation time 13734594061 ps
CPU time 11.79 seconds
Started Aug 08 04:34:29 PM PDT 24
Finished Aug 08 04:34:41 PM PDT 24
Peak memory 199784 kb
Host smart-80b6ee77-0145-4238-8733-65226dad55a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843662183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.843662183
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.1935906739
Short name T641
Test name
Test status
Simulation time 159597457054 ps
CPU time 225.73 seconds
Started Aug 08 04:34:27 PM PDT 24
Finished Aug 08 04:38:13 PM PDT 24
Peak memory 196036 kb
Host smart-e4f37f48-0f33-48b8-a026-54c5eeed4faf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935906739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1935906739
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1950979354
Short name T102
Test name
Test status
Simulation time 63169009324 ps
CPU time 98.57 seconds
Started Aug 08 04:34:29 PM PDT 24
Finished Aug 08 04:36:08 PM PDT 24
Peak memory 199788 kb
Host smart-df40d002-71d2-4d9d-93fd-89bcd6687d13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1950979354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1950979354
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.419234259
Short name T1040
Test name
Test status
Simulation time 1576464321 ps
CPU time 2.33 seconds
Started Aug 08 04:34:28 PM PDT 24
Finished Aug 08 04:34:31 PM PDT 24
Peak memory 199544 kb
Host smart-de4f3e38-3987-4334-adca-3c325e626150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419234259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.419234259
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.864093572
Short name T1032
Test name
Test status
Simulation time 150316101384 ps
CPU time 137.32 seconds
Started Aug 08 04:34:28 PM PDT 24
Finished Aug 08 04:36:46 PM PDT 24
Peak memory 199864 kb
Host smart-b14dfdda-613e-464b-861a-7e39e451f921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864093572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.864093572
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.1860063913
Short name T782
Test name
Test status
Simulation time 14503401893 ps
CPU time 451.55 seconds
Started Aug 08 04:34:34 PM PDT 24
Finished Aug 08 04:42:05 PM PDT 24
Peak memory 199732 kb
Host smart-752795bd-4af1-4278-8ff9-0d3ce96f93c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1860063913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1860063913
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3547258019
Short name T409
Test name
Test status
Simulation time 7536567126 ps
CPU time 19.43 seconds
Started Aug 08 04:34:28 PM PDT 24
Finished Aug 08 04:34:47 PM PDT 24
Peak memory 199444 kb
Host smart-1971dfe5-39d8-4c9a-a862-9215ec8958a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3547258019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3547258019
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.93716748
Short name T300
Test name
Test status
Simulation time 4822565644 ps
CPU time 2.54 seconds
Started Aug 08 04:34:27 PM PDT 24
Finished Aug 08 04:34:30 PM PDT 24
Peak memory 196312 kb
Host smart-f7e22165-7869-489d-ab91-d444761d1fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93716748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.93716748
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2184627310
Short name T327
Test name
Test status
Simulation time 317020399 ps
CPU time 1.15 seconds
Started Aug 08 04:34:28 PM PDT 24
Finished Aug 08 04:34:29 PM PDT 24
Peak memory 198464 kb
Host smart-beb04fe9-0cda-4402-8bcb-831198046c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184627310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2184627310
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.3315013455
Short name T1182
Test name
Test status
Simulation time 70765932076 ps
CPU time 104.14 seconds
Started Aug 08 04:34:29 PM PDT 24
Finished Aug 08 04:36:14 PM PDT 24
Peak memory 199796 kb
Host smart-aa199171-5948-4665-89fc-951bcba01c7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315013455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3315013455
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1973605777
Short name T107
Test name
Test status
Simulation time 63113380604 ps
CPU time 246.11 seconds
Started Aug 08 04:34:29 PM PDT 24
Finished Aug 08 04:38:36 PM PDT 24
Peak memory 215692 kb
Host smart-e4e03aa2-d542-40cd-8a55-d7277ff4053c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973605777 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1973605777
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3061084477
Short name T1035
Test name
Test status
Simulation time 260551611 ps
CPU time 1.35 seconds
Started Aug 08 04:34:27 PM PDT 24
Finished Aug 08 04:34:29 PM PDT 24
Peak memory 198364 kb
Host smart-d233961f-90f9-40dc-a58e-40daaa239747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061084477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3061084477
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1215748490
Short name T547
Test name
Test status
Simulation time 66527331077 ps
CPU time 56.15 seconds
Started Aug 08 04:34:31 PM PDT 24
Finished Aug 08 04:35:27 PM PDT 24
Peak memory 199892 kb
Host smart-db84e468-f8e1-4f5e-adde-e4f84e16d9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215748490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1215748490
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.2659243804
Short name T663
Test name
Test status
Simulation time 37906096281 ps
CPU time 17.82 seconds
Started Aug 08 04:40:50 PM PDT 24
Finished Aug 08 04:41:08 PM PDT 24
Peak memory 199752 kb
Host smart-a0aa8da5-d61d-4417-b313-97493c4214d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659243804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2659243804
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.232539602
Short name T495
Test name
Test status
Simulation time 253010762471 ps
CPU time 306.23 seconds
Started Aug 08 04:40:12 PM PDT 24
Finished Aug 08 04:45:18 PM PDT 24
Peak memory 199788 kb
Host smart-8484e5f2-4d1d-425c-94e2-04e84d9b9d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232539602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.232539602
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1863762893
Short name T909
Test name
Test status
Simulation time 23440624291 ps
CPU time 20.97 seconds
Started Aug 08 04:40:14 PM PDT 24
Finished Aug 08 04:40:35 PM PDT 24
Peak memory 199696 kb
Host smart-23fb5ce3-7180-47a4-ac10-0a91f5c62fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863762893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1863762893
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.4030313250
Short name T665
Test name
Test status
Simulation time 174204841815 ps
CPU time 39.72 seconds
Started Aug 08 04:40:39 PM PDT 24
Finished Aug 08 04:41:19 PM PDT 24
Peak memory 199780 kb
Host smart-9bfe18ae-caad-47a0-ba3e-983a41303f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030313250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.4030313250
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.649745715
Short name T36
Test name
Test status
Simulation time 96808829915 ps
CPU time 103.62 seconds
Started Aug 08 04:40:39 PM PDT 24
Finished Aug 08 04:42:23 PM PDT 24
Peak memory 199756 kb
Host smart-f2881bc7-0185-4493-adf0-b33d59dbdfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649745715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.649745715
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1308480663
Short name T660
Test name
Test status
Simulation time 20051367490 ps
CPU time 6.67 seconds
Started Aug 08 04:40:12 PM PDT 24
Finished Aug 08 04:40:19 PM PDT 24
Peak memory 199668 kb
Host smart-40186c9e-e91e-404f-961e-05cfba372199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308480663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1308480663
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3354560778
Short name T760
Test name
Test status
Simulation time 132844202085 ps
CPU time 179.66 seconds
Started Aug 08 04:41:00 PM PDT 24
Finished Aug 08 04:44:00 PM PDT 24
Peak memory 199752 kb
Host smart-6859e0dc-ed79-4244-8afd-ebfd40b44320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354560778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3354560778
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1437292471
Short name T345
Test name
Test status
Simulation time 43482813909 ps
CPU time 35.08 seconds
Started Aug 08 04:40:13 PM PDT 24
Finished Aug 08 04:40:49 PM PDT 24
Peak memory 199832 kb
Host smart-40c5bbed-464c-419a-83cb-53c0aba43765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437292471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1437292471
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2476373890
Short name T501
Test name
Test status
Simulation time 47012759268 ps
CPU time 24.92 seconds
Started Aug 08 04:41:03 PM PDT 24
Finished Aug 08 04:41:28 PM PDT 24
Peak memory 199740 kb
Host smart-dc4ce3b9-659c-42c0-ba11-afa42826b13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476373890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2476373890
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1076184209
Short name T222
Test name
Test status
Simulation time 37946611638 ps
CPU time 54.6 seconds
Started Aug 08 04:40:39 PM PDT 24
Finished Aug 08 04:41:34 PM PDT 24
Peak memory 199812 kb
Host smart-d1f87070-a3c1-431e-8a00-f6945c84d79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076184209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1076184209
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2862553186
Short name T481
Test name
Test status
Simulation time 13889759 ps
CPU time 0.58 seconds
Started Aug 08 04:34:42 PM PDT 24
Finished Aug 08 04:34:42 PM PDT 24
Peak memory 195216 kb
Host smart-94da286f-7a56-4669-ae04-5cb5b67c19a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862553186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2862553186
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.1345780582
Short name T987
Test name
Test status
Simulation time 199459976215 ps
CPU time 382.22 seconds
Started Aug 08 04:34:27 PM PDT 24
Finished Aug 08 04:40:50 PM PDT 24
Peak memory 199832 kb
Host smart-0d43bcbc-d6ff-4b8e-9fbd-faebd50c3008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345780582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1345780582
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2563360323
Short name T950
Test name
Test status
Simulation time 150450321587 ps
CPU time 63.71 seconds
Started Aug 08 04:34:29 PM PDT 24
Finished Aug 08 04:35:33 PM PDT 24
Peak memory 199476 kb
Host smart-b7393d95-101f-4935-adb7-49c231f7989b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563360323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2563360323
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1334274376
Short name T258
Test name
Test status
Simulation time 76006159372 ps
CPU time 372.03 seconds
Started Aug 08 04:34:29 PM PDT 24
Finished Aug 08 04:40:41 PM PDT 24
Peak memory 199756 kb
Host smart-1960d9a4-b094-45f9-96a6-19303d2585de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334274376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1334274376
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.954787133
Short name T1047
Test name
Test status
Simulation time 1899863614 ps
CPU time 3.67 seconds
Started Aug 08 04:34:29 PM PDT 24
Finished Aug 08 04:34:33 PM PDT 24
Peak memory 198620 kb
Host smart-ba0e00e0-afb7-421c-8f0a-0185aa8d5786
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954787133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.954787133
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.819864359
Short name T992
Test name
Test status
Simulation time 107959014886 ps
CPU time 314.49 seconds
Started Aug 08 04:34:41 PM PDT 24
Finished Aug 08 04:39:56 PM PDT 24
Peak memory 199872 kb
Host smart-9bdc8e36-375a-40c8-9896-c43979c28bcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=819864359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.819864359
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1002696584
Short name T349
Test name
Test status
Simulation time 804352533 ps
CPU time 1.69 seconds
Started Aug 08 04:34:42 PM PDT 24
Finished Aug 08 04:34:44 PM PDT 24
Peak memory 195436 kb
Host smart-db548be4-9cac-4a76-a97f-6a9e9bf406f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002696584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1002696584
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1849639460
Short name T285
Test name
Test status
Simulation time 146469710688 ps
CPU time 85.04 seconds
Started Aug 08 04:34:28 PM PDT 24
Finished Aug 08 04:35:53 PM PDT 24
Peak memory 199940 kb
Host smart-399aa959-35a2-4f2c-8af5-061ee7fbc992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849639460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1849639460
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2197426159
Short name T294
Test name
Test status
Simulation time 15869691116 ps
CPU time 190.75 seconds
Started Aug 08 04:34:40 PM PDT 24
Finished Aug 08 04:37:51 PM PDT 24
Peak memory 199708 kb
Host smart-e259922d-8b7d-492f-bb03-e94dfef7d956
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2197426159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2197426159
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1853108434
Short name T905
Test name
Test status
Simulation time 7536458420 ps
CPU time 16.08 seconds
Started Aug 08 04:34:30 PM PDT 24
Finished Aug 08 04:34:46 PM PDT 24
Peak memory 198952 kb
Host smart-7d628302-9ff9-46cd-ac7d-27159b0cd870
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853108434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1853108434
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.894875391
Short name T941
Test name
Test status
Simulation time 3201153419 ps
CPU time 5.99 seconds
Started Aug 08 04:34:27 PM PDT 24
Finished Aug 08 04:34:33 PM PDT 24
Peak memory 195732 kb
Host smart-0e7c4439-8b3d-4b0c-814c-4e189cec07ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894875391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.894875391
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3553763258
Short name T361
Test name
Test status
Simulation time 285850078 ps
CPU time 1.38 seconds
Started Aug 08 04:34:28 PM PDT 24
Finished Aug 08 04:34:30 PM PDT 24
Peak memory 198344 kb
Host smart-8a51b907-11e0-4a29-b311-5d22267adee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553763258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3553763258
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2548559857
Short name T877
Test name
Test status
Simulation time 175737071436 ps
CPU time 261.65 seconds
Started Aug 08 04:34:42 PM PDT 24
Finished Aug 08 04:39:03 PM PDT 24
Peak memory 199728 kb
Host smart-1d0ac217-95e8-4e1c-adb8-d75892a6cb38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548559857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2548559857
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.4294903485
Short name T864
Test name
Test status
Simulation time 152889398036 ps
CPU time 628.55 seconds
Started Aug 08 04:34:43 PM PDT 24
Finished Aug 08 04:45:12 PM PDT 24
Peak memory 216312 kb
Host smart-eaadc7b0-4b2b-486e-9f30-ec71e7ef78f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294903485 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.4294903485
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1855285146
Short name T923
Test name
Test status
Simulation time 2522788681 ps
CPU time 2.47 seconds
Started Aug 08 04:34:45 PM PDT 24
Finished Aug 08 04:34:48 PM PDT 24
Peak memory 198300 kb
Host smart-ff8bdfd7-4797-4908-be31-39156dffffea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855285146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1855285146
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1572934887
Short name T291
Test name
Test status
Simulation time 67227112317 ps
CPU time 30.97 seconds
Started Aug 08 04:34:28 PM PDT 24
Finished Aug 08 04:34:59 PM PDT 24
Peak memory 199844 kb
Host smart-7259be24-4358-483e-a28d-3a7c27caadda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572934887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1572934887
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2635174749
Short name T113
Test name
Test status
Simulation time 60184628516 ps
CPU time 114.07 seconds
Started Aug 08 04:40:21 PM PDT 24
Finished Aug 08 04:42:15 PM PDT 24
Peak memory 199772 kb
Host smart-35fccb76-dfbe-412f-9fd6-982da1538ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635174749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2635174749
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2148176594
Short name T1161
Test name
Test status
Simulation time 62762189078 ps
CPU time 16.07 seconds
Started Aug 08 04:41:03 PM PDT 24
Finished Aug 08 04:41:19 PM PDT 24
Peak memory 199796 kb
Host smart-efe01780-0948-4a96-92de-8741fc4b9a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148176594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2148176594
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.4162611390
Short name T1016
Test name
Test status
Simulation time 16508810295 ps
CPU time 19.25 seconds
Started Aug 08 04:40:13 PM PDT 24
Finished Aug 08 04:40:32 PM PDT 24
Peak memory 199812 kb
Host smart-031b05d6-487f-4361-a6fa-3179aa20f7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162611390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.4162611390
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.1521022148
Short name T1097
Test name
Test status
Simulation time 39722221994 ps
CPU time 33.16 seconds
Started Aug 08 04:40:10 PM PDT 24
Finished Aug 08 04:40:44 PM PDT 24
Peak memory 199772 kb
Host smart-36a553df-f9e2-42dd-aba2-607352df0a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521022148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1521022148
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.715157557
Short name T233
Test name
Test status
Simulation time 17493287455 ps
CPU time 28.83 seconds
Started Aug 08 04:40:11 PM PDT 24
Finished Aug 08 04:40:40 PM PDT 24
Peak memory 199748 kb
Host smart-22fc5d34-7539-43ad-958c-20e1f656d243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715157557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.715157557
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3747701989
Short name T551
Test name
Test status
Simulation time 30691225201 ps
CPU time 45.19 seconds
Started Aug 08 04:40:12 PM PDT 24
Finished Aug 08 04:40:58 PM PDT 24
Peak memory 199748 kb
Host smart-98c4cb5d-d0a9-4c69-932f-afd9926bcd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747701989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3747701989
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.4233534294
Short name T201
Test name
Test status
Simulation time 27263087149 ps
CPU time 54.27 seconds
Started Aug 08 04:40:13 PM PDT 24
Finished Aug 08 04:41:07 PM PDT 24
Peak memory 199748 kb
Host smart-cda6eec4-0cdf-48b1-931f-2739de69b520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233534294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.4233534294
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.52471622
Short name T176
Test name
Test status
Simulation time 261173514870 ps
CPU time 29.48 seconds
Started Aug 08 04:40:12 PM PDT 24
Finished Aug 08 04:40:42 PM PDT 24
Peak memory 199740 kb
Host smart-f03b0a47-b421-4a78-9384-fae24f9a38c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52471622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.52471622
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1382765933
Short name T944
Test name
Test status
Simulation time 114199091862 ps
CPU time 95.93 seconds
Started Aug 08 04:40:11 PM PDT 24
Finished Aug 08 04:41:47 PM PDT 24
Peak memory 199692 kb
Host smart-2a36bbe5-f3f3-4fc3-b656-237ef9d5a8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382765933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1382765933
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.923990710
Short name T1173
Test name
Test status
Simulation time 11131238 ps
CPU time 0.58 seconds
Started Aug 08 04:34:43 PM PDT 24
Finished Aug 08 04:34:44 PM PDT 24
Peak memory 195412 kb
Host smart-71cd2b4d-9068-4da9-9401-682929d7c722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923990710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.923990710
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1882555625
Short name T326
Test name
Test status
Simulation time 220436715139 ps
CPU time 515.56 seconds
Started Aug 08 04:34:41 PM PDT 24
Finished Aug 08 04:43:17 PM PDT 24
Peak memory 199780 kb
Host smart-065a820c-695f-45df-973c-c05db3291ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882555625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1882555625
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2638575458
Short name T1147
Test name
Test status
Simulation time 115386074981 ps
CPU time 215.96 seconds
Started Aug 08 04:34:43 PM PDT 24
Finished Aug 08 04:38:19 PM PDT 24
Peak memory 199688 kb
Host smart-71741c34-2cbe-4105-84be-d70fdd70f585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638575458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2638575458
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2030447476
Short name T342
Test name
Test status
Simulation time 26179138918 ps
CPU time 42.23 seconds
Started Aug 08 04:34:45 PM PDT 24
Finished Aug 08 04:35:27 PM PDT 24
Peak memory 199768 kb
Host smart-62439c93-b904-4706-8215-4275e3d7bc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030447476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2030447476
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2491414347
Short name T317
Test name
Test status
Simulation time 49920865282 ps
CPU time 92.04 seconds
Started Aug 08 04:34:41 PM PDT 24
Finished Aug 08 04:36:14 PM PDT 24
Peak memory 199756 kb
Host smart-d8cfffe3-b51b-4fb0-a0f2-1b3a6ff07f23
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491414347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2491414347
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3772242907
Short name T1025
Test name
Test status
Simulation time 67924349361 ps
CPU time 332.96 seconds
Started Aug 08 04:34:43 PM PDT 24
Finished Aug 08 04:40:16 PM PDT 24
Peak memory 199748 kb
Host smart-274c157c-7b46-4eed-8af5-5a1b2581f91d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3772242907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3772242907
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2186022782
Short name T788
Test name
Test status
Simulation time 1913793632 ps
CPU time 3.3 seconds
Started Aug 08 04:34:42 PM PDT 24
Finished Aug 08 04:34:45 PM PDT 24
Peak memory 198348 kb
Host smart-de1853f9-313b-49ed-af49-cc0d53521726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186022782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2186022782
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.573268261
Short name T659
Test name
Test status
Simulation time 43896307906 ps
CPU time 43.46 seconds
Started Aug 08 04:34:47 PM PDT 24
Finished Aug 08 04:35:30 PM PDT 24
Peak memory 199464 kb
Host smart-821701b1-212e-41bc-ad07-d85e0ddbad7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573268261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.573268261
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.697291092
Short name T786
Test name
Test status
Simulation time 17923279599 ps
CPU time 74.77 seconds
Started Aug 08 04:34:42 PM PDT 24
Finished Aug 08 04:35:57 PM PDT 24
Peak memory 199792 kb
Host smart-16125354-c0cd-4ef5-be5b-953af5ca8edf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697291092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.697291092
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.275120256
Short name T1065
Test name
Test status
Simulation time 1431298407 ps
CPU time 0.8 seconds
Started Aug 08 04:34:43 PM PDT 24
Finished Aug 08 04:34:43 PM PDT 24
Peak memory 195400 kb
Host smart-13f915bf-4131-415d-aa4d-b00bed573cb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=275120256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.275120256
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1062897696
Short name T12
Test name
Test status
Simulation time 161759905627 ps
CPU time 105.33 seconds
Started Aug 08 04:34:45 PM PDT 24
Finished Aug 08 04:36:30 PM PDT 24
Peak memory 199720 kb
Host smart-079d5292-9f15-4405-be77-02fec23bd102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062897696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1062897696
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3570720691
Short name T755
Test name
Test status
Simulation time 3322463586 ps
CPU time 1.73 seconds
Started Aug 08 04:34:41 PM PDT 24
Finished Aug 08 04:34:43 PM PDT 24
Peak memory 195988 kb
Host smart-6dab8045-fc3a-4385-a505-770a26c09a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570720691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3570720691
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1367813911
Short name T658
Test name
Test status
Simulation time 6226261816 ps
CPU time 4.28 seconds
Started Aug 08 04:34:45 PM PDT 24
Finished Aug 08 04:34:49 PM PDT 24
Peak memory 199776 kb
Host smart-d922bbdc-a1a6-4dfb-8074-e1edbda572b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367813911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1367813911
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.2065215525
Short name T844
Test name
Test status
Simulation time 291525609416 ps
CPU time 294.17 seconds
Started Aug 08 04:34:40 PM PDT 24
Finished Aug 08 04:39:35 PM PDT 24
Peak memory 199764 kb
Host smart-50db8d26-2970-43ac-8d8d-acd0dee041d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065215525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2065215525
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.855495387
Short name T57
Test name
Test status
Simulation time 56544926686 ps
CPU time 333.3 seconds
Started Aug 08 04:34:47 PM PDT 24
Finished Aug 08 04:40:21 PM PDT 24
Peak memory 216272 kb
Host smart-08dadf79-d211-4ccf-a9e5-8321cbd4add8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855495387 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.855495387
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3839800046
Short name T639
Test name
Test status
Simulation time 1134256779 ps
CPU time 1.34 seconds
Started Aug 08 04:34:44 PM PDT 24
Finished Aug 08 04:34:45 PM PDT 24
Peak memory 198788 kb
Host smart-6128909e-3131-4681-a5d0-250c7949d940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839800046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3839800046
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.782878024
Short name T593
Test name
Test status
Simulation time 92622088759 ps
CPU time 41.56 seconds
Started Aug 08 04:34:47 PM PDT 24
Finished Aug 08 04:35:29 PM PDT 24
Peak memory 199776 kb
Host smart-ee0a06cf-09c4-4728-bbc2-b1f8adf44a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782878024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.782878024
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.2131844106
Short name T187
Test name
Test status
Simulation time 108703754723 ps
CPU time 64.33 seconds
Started Aug 08 04:40:19 PM PDT 24
Finished Aug 08 04:41:24 PM PDT 24
Peak memory 199756 kb
Host smart-f49e7fd1-a491-46fa-b745-826e055897ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131844106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2131844106
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2075571480
Short name T662
Test name
Test status
Simulation time 93939223365 ps
CPU time 127.32 seconds
Started Aug 08 04:40:14 PM PDT 24
Finished Aug 08 04:42:21 PM PDT 24
Peak memory 199696 kb
Host smart-b425d557-541a-4898-bac1-6a1029ecbae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075571480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2075571480
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.1327414935
Short name T408
Test name
Test status
Simulation time 51908702338 ps
CPU time 66.72 seconds
Started Aug 08 04:40:19 PM PDT 24
Finished Aug 08 04:41:26 PM PDT 24
Peak memory 199772 kb
Host smart-b5a9f538-59b9-4340-acef-ea2252e6d0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327414935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1327414935
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1289881317
Short name T817
Test name
Test status
Simulation time 108966857320 ps
CPU time 19.65 seconds
Started Aug 08 04:40:21 PM PDT 24
Finished Aug 08 04:40:41 PM PDT 24
Peak memory 199764 kb
Host smart-b7fb199c-e96c-441d-b959-921ec1c2eb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289881317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1289881317
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.810242809
Short name T977
Test name
Test status
Simulation time 21171349936 ps
CPU time 38.28 seconds
Started Aug 08 04:40:24 PM PDT 24
Finished Aug 08 04:41:02 PM PDT 24
Peak memory 199756 kb
Host smart-404913ca-261b-43de-8c57-8fe1aca8bf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810242809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.810242809
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3725927228
Short name T140
Test name
Test status
Simulation time 120067156807 ps
CPU time 43.91 seconds
Started Aug 08 04:40:23 PM PDT 24
Finished Aug 08 04:41:07 PM PDT 24
Peak memory 199672 kb
Host smart-44ba348b-817c-473f-a373-fa1fe0ae76b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725927228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3725927228
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2483588037
Short name T1026
Test name
Test status
Simulation time 78546908663 ps
CPU time 252.53 seconds
Started Aug 08 04:40:20 PM PDT 24
Finished Aug 08 04:44:33 PM PDT 24
Peak memory 199720 kb
Host smart-bf4c1ea8-fb78-4ab6-9c77-e12007a68cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483588037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2483588037
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2856174147
Short name T627
Test name
Test status
Simulation time 115230567769 ps
CPU time 52.09 seconds
Started Aug 08 04:40:22 PM PDT 24
Finished Aug 08 04:41:14 PM PDT 24
Peak memory 199796 kb
Host smart-649bde9e-f86c-44c6-b972-c53c4bfb8a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856174147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2856174147
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1048243685
Short name T1132
Test name
Test status
Simulation time 105351154506 ps
CPU time 50.56 seconds
Started Aug 08 04:40:23 PM PDT 24
Finished Aug 08 04:41:14 PM PDT 24
Peak memory 199800 kb
Host smart-498f961e-ca65-4fcd-b2f3-a1c54137f936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048243685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1048243685
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1697620595
Short name T369
Test name
Test status
Simulation time 30627409 ps
CPU time 0.56 seconds
Started Aug 08 04:34:52 PM PDT 24
Finished Aug 08 04:34:53 PM PDT 24
Peak memory 195168 kb
Host smart-6dfb8c20-9d00-490d-8730-1994c20d25ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697620595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1697620595
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1401823725
Short name T790
Test name
Test status
Simulation time 89126325192 ps
CPU time 34.16 seconds
Started Aug 08 04:34:47 PM PDT 24
Finished Aug 08 04:35:21 PM PDT 24
Peak memory 199772 kb
Host smart-8ce819d9-d63c-4267-92c8-cdb95e2c9722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401823725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1401823725
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.66028146
Short name T1051
Test name
Test status
Simulation time 29253785329 ps
CPU time 54.72 seconds
Started Aug 08 04:34:44 PM PDT 24
Finished Aug 08 04:35:38 PM PDT 24
Peak memory 199716 kb
Host smart-ca453ee0-e716-4dcb-8099-3b6db27e8f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66028146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.66028146
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2527394719
Short name T836
Test name
Test status
Simulation time 142178246056 ps
CPU time 46.83 seconds
Started Aug 08 04:34:51 PM PDT 24
Finished Aug 08 04:35:38 PM PDT 24
Peak memory 199724 kb
Host smart-f9e6ab3d-3197-469d-8e47-fca1a0fa223a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527394719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2527394719
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2961256779
Short name T331
Test name
Test status
Simulation time 7663103822 ps
CPU time 10.23 seconds
Started Aug 08 04:34:51 PM PDT 24
Finished Aug 08 04:35:01 PM PDT 24
Peak memory 196496 kb
Host smart-548d3060-2eab-4222-933f-e76f1ed7c09d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961256779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2961256779
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.946020266
Short name T490
Test name
Test status
Simulation time 55593570196 ps
CPU time 224.65 seconds
Started Aug 08 04:34:53 PM PDT 24
Finished Aug 08 04:38:38 PM PDT 24
Peak memory 199756 kb
Host smart-bfb14193-2b62-40d8-b4c9-be2944510dff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=946020266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.946020266
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1140373905
Short name T571
Test name
Test status
Simulation time 2020211359 ps
CPU time 2.35 seconds
Started Aug 08 04:34:52 PM PDT 24
Finished Aug 08 04:34:54 PM PDT 24
Peak memory 195292 kb
Host smart-f98bcd6d-5327-4851-ba13-f2f85135e540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140373905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1140373905
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.2343884951
Short name T370
Test name
Test status
Simulation time 13608820619 ps
CPU time 20.75 seconds
Started Aug 08 04:34:53 PM PDT 24
Finished Aug 08 04:35:14 PM PDT 24
Peak memory 199860 kb
Host smart-fa0a0de7-89cd-4588-8af0-96b4256b1ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343884951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2343884951
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.301313288
Short name T938
Test name
Test status
Simulation time 12529162929 ps
CPU time 367.09 seconds
Started Aug 08 04:34:51 PM PDT 24
Finished Aug 08 04:40:58 PM PDT 24
Peak memory 199784 kb
Host smart-254d083d-f71c-45b6-b2bd-ed7a86937707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=301313288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.301313288
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1476673149
Short name T1050
Test name
Test status
Simulation time 7025849063 ps
CPU time 30.33 seconds
Started Aug 08 04:34:51 PM PDT 24
Finished Aug 08 04:35:21 PM PDT 24
Peak memory 198692 kb
Host smart-028269dd-c655-4d39-8622-556b4fd0e7a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1476673149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1476673149
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1118106532
Short name T1006
Test name
Test status
Simulation time 95348988141 ps
CPU time 73.66 seconds
Started Aug 08 04:34:51 PM PDT 24
Finished Aug 08 04:36:05 PM PDT 24
Peak memory 199744 kb
Host smart-455d17f5-0ec9-42a2-a796-9a57b762d60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118106532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1118106532
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2801316950
Short name T383
Test name
Test status
Simulation time 646177360 ps
CPU time 1.77 seconds
Started Aug 08 04:34:52 PM PDT 24
Finished Aug 08 04:34:54 PM PDT 24
Peak memory 195248 kb
Host smart-332af801-c21a-46a6-822d-09bf59b86a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801316950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2801316950
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.2000076681
Short name T353
Test name
Test status
Simulation time 502932308 ps
CPU time 1.31 seconds
Started Aug 08 04:34:44 PM PDT 24
Finished Aug 08 04:34:45 PM PDT 24
Peak memory 198060 kb
Host smart-de7bec3a-e4bb-49bb-beaa-5525d16b3fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000076681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2000076681
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1494455135
Short name T492
Test name
Test status
Simulation time 36586708712 ps
CPU time 83.87 seconds
Started Aug 08 04:34:57 PM PDT 24
Finished Aug 08 04:36:21 PM PDT 24
Peak memory 199756 kb
Host smart-10d220a7-dce3-48a3-9640-ccc5dec4b986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494455135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1494455135
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2240761242
Short name T151
Test name
Test status
Simulation time 516262172949 ps
CPU time 661.41 seconds
Started Aug 08 04:34:51 PM PDT 24
Finished Aug 08 04:45:53 PM PDT 24
Peak memory 230512 kb
Host smart-ce3f97aa-6547-4909-b05d-46be431ad4b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240761242 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2240761242
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1116208605
Short name T809
Test name
Test status
Simulation time 594105600 ps
CPU time 1.42 seconds
Started Aug 08 04:35:03 PM PDT 24
Finished Aug 08 04:35:04 PM PDT 24
Peak memory 199732 kb
Host smart-78a68dab-e533-47b8-aedd-f4d0a9b85219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116208605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1116208605
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.2727669028
Short name T680
Test name
Test status
Simulation time 107487475625 ps
CPU time 44.32 seconds
Started Aug 08 04:34:44 PM PDT 24
Finished Aug 08 04:35:28 PM PDT 24
Peak memory 199764 kb
Host smart-8f01055b-9cdb-40a8-b531-e6c23fa7aec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727669028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2727669028
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3187856900
Short name T1144
Test name
Test status
Simulation time 18948046118 ps
CPU time 32.82 seconds
Started Aug 08 04:40:21 PM PDT 24
Finished Aug 08 04:40:54 PM PDT 24
Peak memory 199760 kb
Host smart-97b30c33-c7d4-42a0-995d-70cfcae4c816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187856900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3187856900
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2820334520
Short name T1080
Test name
Test status
Simulation time 97492786290 ps
CPU time 23.4 seconds
Started Aug 08 04:40:31 PM PDT 24
Finished Aug 08 04:40:54 PM PDT 24
Peak memory 199868 kb
Host smart-a15ed6d7-9268-4d46-95f0-24c24541c4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820334520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2820334520
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3251756840
Short name T858
Test name
Test status
Simulation time 24756907483 ps
CPU time 41.89 seconds
Started Aug 08 04:40:22 PM PDT 24
Finished Aug 08 04:41:04 PM PDT 24
Peak memory 199792 kb
Host smart-3160fa74-cac0-43cf-8e6b-c6f38bce5783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251756840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3251756840
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1779197397
Short name T736
Test name
Test status
Simulation time 23135882204 ps
CPU time 63.82 seconds
Started Aug 08 04:40:23 PM PDT 24
Finished Aug 08 04:41:27 PM PDT 24
Peak memory 199896 kb
Host smart-fe8d81be-6c92-47ab-bd56-f4c479f1cfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779197397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1779197397
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2633301521
Short name T288
Test name
Test status
Simulation time 7999751862 ps
CPU time 13.86 seconds
Started Aug 08 04:40:24 PM PDT 24
Finished Aug 08 04:40:38 PM PDT 24
Peak memory 199760 kb
Host smart-4b221e3b-a6d5-449a-b1dc-9551dd1aa110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633301521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2633301521
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1832380752
Short name T970
Test name
Test status
Simulation time 63463171128 ps
CPU time 13.59 seconds
Started Aug 08 04:40:35 PM PDT 24
Finished Aug 08 04:40:48 PM PDT 24
Peak memory 199736 kb
Host smart-bf0eb09f-aed7-4ba4-ac9e-a43e258d73ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832380752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1832380752
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.498491941
Short name T46
Test name
Test status
Simulation time 26164063798 ps
CPU time 45.2 seconds
Started Aug 08 04:40:35 PM PDT 24
Finished Aug 08 04:41:21 PM PDT 24
Peak memory 199828 kb
Host smart-0dc56dec-595b-46c7-97ff-b60f2ece431b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498491941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.498491941
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3568390897
Short name T1012
Test name
Test status
Simulation time 27713315 ps
CPU time 0.56 seconds
Started Aug 08 04:35:03 PM PDT 24
Finished Aug 08 04:35:04 PM PDT 24
Peak memory 194668 kb
Host smart-5517eba0-4f72-40ef-a7c1-8c297a731222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568390897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3568390897
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2836732371
Short name T307
Test name
Test status
Simulation time 48069001114 ps
CPU time 38.41 seconds
Started Aug 08 04:34:53 PM PDT 24
Finished Aug 08 04:35:31 PM PDT 24
Peak memory 199820 kb
Host smart-f51d1faa-9301-45d6-bb8b-67b477c10acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836732371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2836732371
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2742780972
Short name T942
Test name
Test status
Simulation time 110244138876 ps
CPU time 34.62 seconds
Started Aug 08 04:34:51 PM PDT 24
Finished Aug 08 04:35:26 PM PDT 24
Peak memory 199732 kb
Host smart-5537cf08-832c-4b1a-be39-616de1e48445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742780972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2742780972
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.4213691429
Short name T739
Test name
Test status
Simulation time 14335862051 ps
CPU time 22.96 seconds
Started Aug 08 04:34:54 PM PDT 24
Finished Aug 08 04:35:17 PM PDT 24
Peak memory 199808 kb
Host smart-e60ae011-c681-4e14-82bc-e184b7ef54df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213691429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.4213691429
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.2226506309
Short name T336
Test name
Test status
Simulation time 62003024558 ps
CPU time 26.17 seconds
Started Aug 08 04:35:04 PM PDT 24
Finished Aug 08 04:35:30 PM PDT 24
Peak memory 198908 kb
Host smart-e3d95ec0-b970-4f88-b243-d52fe3af1515
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226506309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2226506309
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.172838117
Short name T738
Test name
Test status
Simulation time 216518336724 ps
CPU time 395.02 seconds
Started Aug 08 04:34:52 PM PDT 24
Finished Aug 08 04:41:27 PM PDT 24
Peak memory 199724 kb
Host smart-5e5f89bd-6a02-412c-8744-b671f48e1575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=172838117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.172838117
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3457743406
Short name T892
Test name
Test status
Simulation time 2329036540 ps
CPU time 3.78 seconds
Started Aug 08 04:35:03 PM PDT 24
Finished Aug 08 04:35:07 PM PDT 24
Peak memory 196028 kb
Host smart-751c7134-950b-492f-b67b-b3ebf3c9d982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457743406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3457743406
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.3950985095
Short name T401
Test name
Test status
Simulation time 15899208185 ps
CPU time 6.48 seconds
Started Aug 08 04:34:53 PM PDT 24
Finished Aug 08 04:34:59 PM PDT 24
Peak memory 198156 kb
Host smart-126c68ac-d237-4741-94d0-6f059541eb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950985095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3950985095
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2858029460
Short name T455
Test name
Test status
Simulation time 22890449376 ps
CPU time 282.21 seconds
Started Aug 08 04:35:03 PM PDT 24
Finished Aug 08 04:39:45 PM PDT 24
Peak memory 199732 kb
Host smart-4b939825-6a4b-49c9-aa85-013f9c142bc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2858029460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2858029460
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3189393249
Short name T18
Test name
Test status
Simulation time 5576529270 ps
CPU time 24.09 seconds
Started Aug 08 04:34:55 PM PDT 24
Finished Aug 08 04:35:19 PM PDT 24
Peak memory 199036 kb
Host smart-9ecb2673-9878-43fa-92d5-4e4551d5f13a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3189393249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3189393249
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1050375700
Short name T559
Test name
Test status
Simulation time 22591199966 ps
CPU time 48.05 seconds
Started Aug 08 04:34:55 PM PDT 24
Finished Aug 08 04:35:43 PM PDT 24
Peak memory 199804 kb
Host smart-dd69f925-563a-4d70-b7fd-ab47620cd575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050375700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1050375700
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2193887653
Short name T574
Test name
Test status
Simulation time 48470651376 ps
CPU time 17.16 seconds
Started Aug 08 04:34:55 PM PDT 24
Finished Aug 08 04:35:12 PM PDT 24
Peak memory 195784 kb
Host smart-7e398b55-d169-4fef-aaa3-9012c83eed09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193887653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2193887653
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1093999915
Short name T920
Test name
Test status
Simulation time 266469574 ps
CPU time 1.34 seconds
Started Aug 08 04:34:51 PM PDT 24
Finished Aug 08 04:34:53 PM PDT 24
Peak memory 198620 kb
Host smart-a81d03bc-83b8-4e2c-ad61-6e06d6f795d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093999915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1093999915
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.1660164888
Short name T845
Test name
Test status
Simulation time 202519313842 ps
CPU time 170.33 seconds
Started Aug 08 04:35:03 PM PDT 24
Finished Aug 08 04:37:54 PM PDT 24
Peak memory 199792 kb
Host smart-6abd956a-1b65-4878-9c29-6b66dd7628b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660164888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1660164888
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3020449773
Short name T110
Test name
Test status
Simulation time 26511364411 ps
CPU time 357.48 seconds
Started Aug 08 04:34:54 PM PDT 24
Finished Aug 08 04:40:52 PM PDT 24
Peak memory 216460 kb
Host smart-b7a85ee1-69b5-4776-b246-a762ca4c38f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020449773 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3020449773
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2418411794
Short name T274
Test name
Test status
Simulation time 2340798600 ps
CPU time 2.34 seconds
Started Aug 08 04:34:53 PM PDT 24
Finished Aug 08 04:34:55 PM PDT 24
Peak memory 199780 kb
Host smart-7b01d796-1ed6-49fc-a7cc-8a478fba63f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418411794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2418411794
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.727481065
Short name T870
Test name
Test status
Simulation time 138684276293 ps
CPU time 63.01 seconds
Started Aug 08 04:34:52 PM PDT 24
Finished Aug 08 04:35:55 PM PDT 24
Peak memory 199744 kb
Host smart-72bdba77-3b0a-4923-9079-412ce15a81ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727481065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.727481065
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.587148225
Short name T1045
Test name
Test status
Simulation time 14297967775 ps
CPU time 10.84 seconds
Started Aug 08 04:40:34 PM PDT 24
Finished Aug 08 04:40:45 PM PDT 24
Peak memory 199820 kb
Host smart-8eb5a313-db97-47a9-9371-d05cc07ebc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587148225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.587148225
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2125505694
Short name T493
Test name
Test status
Simulation time 76233854700 ps
CPU time 104.22 seconds
Started Aug 08 04:40:32 PM PDT 24
Finished Aug 08 04:42:16 PM PDT 24
Peak memory 199696 kb
Host smart-ef29a1ce-218d-4baf-b133-d7dc9083353d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125505694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2125505694
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2969043893
Short name T859
Test name
Test status
Simulation time 138889887016 ps
CPU time 66.25 seconds
Started Aug 08 04:40:33 PM PDT 24
Finished Aug 08 04:41:39 PM PDT 24
Peak memory 199852 kb
Host smart-a352d534-9339-4f73-87b3-06036f0d670e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969043893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2969043893
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2947071347
Short name T516
Test name
Test status
Simulation time 55679652030 ps
CPU time 23.78 seconds
Started Aug 08 04:40:57 PM PDT 24
Finished Aug 08 04:41:21 PM PDT 24
Peak memory 199788 kb
Host smart-e96c49dc-2b38-452e-9015-3853b640d917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947071347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2947071347
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1824977385
Short name T138
Test name
Test status
Simulation time 40497192497 ps
CPU time 77.81 seconds
Started Aug 08 04:41:40 PM PDT 24
Finished Aug 08 04:42:58 PM PDT 24
Peak memory 199752 kb
Host smart-602aaaa0-9055-47a0-b5f3-dd7d3654aece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824977385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1824977385
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3007346509
Short name T1052
Test name
Test status
Simulation time 91706857876 ps
CPU time 133.19 seconds
Started Aug 08 04:40:59 PM PDT 24
Finished Aug 08 04:43:13 PM PDT 24
Peak memory 199676 kb
Host smart-debd0fd8-971d-4a32-8e9c-9608b5bee5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007346509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3007346509
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.4252502339
Short name T451
Test name
Test status
Simulation time 12380885142 ps
CPU time 19.88 seconds
Started Aug 08 04:41:01 PM PDT 24
Finished Aug 08 04:41:21 PM PDT 24
Peak memory 199700 kb
Host smart-2ad0699f-583c-422e-890c-464ffd26b8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252502339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.4252502339
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.702895819
Short name T603
Test name
Test status
Simulation time 27203161201 ps
CPU time 47.09 seconds
Started Aug 08 04:41:30 PM PDT 24
Finished Aug 08 04:42:17 PM PDT 24
Peak memory 199816 kb
Host smart-417f8783-6e82-4a5f-b3a7-0441b8a50f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702895819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.702895819
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1896195962
Short name T184
Test name
Test status
Simulation time 9829391098 ps
CPU time 13.88 seconds
Started Aug 08 04:40:31 PM PDT 24
Finished Aug 08 04:40:45 PM PDT 24
Peak memory 199720 kb
Host smart-045390d8-0490-427d-aa78-82636ef810ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896195962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1896195962
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2322447106
Short name T756
Test name
Test status
Simulation time 74156481176 ps
CPU time 116.91 seconds
Started Aug 08 04:40:58 PM PDT 24
Finished Aug 08 04:42:56 PM PDT 24
Peak memory 199852 kb
Host smart-7ef2d0d8-609f-40e9-ab24-1debfc37823a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322447106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2322447106
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3876220717
Short name T599
Test name
Test status
Simulation time 12710292 ps
CPU time 0.55 seconds
Started Aug 08 04:35:10 PM PDT 24
Finished Aug 08 04:35:10 PM PDT 24
Peak memory 195448 kb
Host smart-5f66cfbd-8a19-4109-8b73-bba022b6f7b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876220717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3876220717
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.669840329
Short name T131
Test name
Test status
Simulation time 63642860449 ps
CPU time 100.38 seconds
Started Aug 08 04:35:03 PM PDT 24
Finished Aug 08 04:36:44 PM PDT 24
Peak memory 199684 kb
Host smart-d125ac8d-d27e-48e6-9095-b8abb72a81bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669840329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.669840329
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.286288732
Short name T598
Test name
Test status
Simulation time 98119551630 ps
CPU time 42.49 seconds
Started Aug 08 04:35:03 PM PDT 24
Finished Aug 08 04:35:46 PM PDT 24
Peak memory 199816 kb
Host smart-819b2412-3ba5-4555-941b-74ad5d72c45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286288732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.286288732
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3096321499
Short name T181
Test name
Test status
Simulation time 96078689407 ps
CPU time 129.63 seconds
Started Aug 08 04:35:03 PM PDT 24
Finished Aug 08 04:37:12 PM PDT 24
Peak memory 199760 kb
Host smart-1ab6b904-1442-4561-9485-2f7105067500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096321499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3096321499
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3097948496
Short name T799
Test name
Test status
Simulation time 43096277202 ps
CPU time 34.97 seconds
Started Aug 08 04:35:05 PM PDT 24
Finished Aug 08 04:35:40 PM PDT 24
Peak memory 199728 kb
Host smart-e8d7d01f-a383-4393-a4b3-30ce1278c83d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097948496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3097948496
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.978888411
Short name T1111
Test name
Test status
Simulation time 66565931044 ps
CPU time 264.51 seconds
Started Aug 08 04:35:10 PM PDT 24
Finished Aug 08 04:39:35 PM PDT 24
Peak memory 199756 kb
Host smart-8474ba37-c5bf-419a-8e0b-69802927a72c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=978888411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.978888411
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.882780452
Short name T1011
Test name
Test status
Simulation time 1959899216 ps
CPU time 3.19 seconds
Started Aug 08 04:35:09 PM PDT 24
Finished Aug 08 04:35:12 PM PDT 24
Peak memory 195316 kb
Host smart-79f23c53-088e-4a57-b6d8-9d37b01990b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882780452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.882780452
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2633139955
Short name T395
Test name
Test status
Simulation time 17761628158 ps
CPU time 33.56 seconds
Started Aug 08 04:35:03 PM PDT 24
Finished Aug 08 04:35:36 PM PDT 24
Peak memory 199868 kb
Host smart-306b8f8b-0ff2-48f5-aee5-833202f0207a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633139955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2633139955
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.2633041019
Short name T805
Test name
Test status
Simulation time 11363657450 ps
CPU time 135.53 seconds
Started Aug 08 04:35:06 PM PDT 24
Finished Aug 08 04:37:22 PM PDT 24
Peak memory 199800 kb
Host smart-86e3ee88-5b76-4f1b-9dfe-61fd93d43732
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2633041019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2633041019
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1911341561
Short name T415
Test name
Test status
Simulation time 1487769052 ps
CPU time 3.44 seconds
Started Aug 08 04:35:03 PM PDT 24
Finished Aug 08 04:35:07 PM PDT 24
Peak memory 198124 kb
Host smart-aa77c9ce-9f0e-470a-93e2-a0c186a8081e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911341561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1911341561
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2553647831
Short name T761
Test name
Test status
Simulation time 191802954466 ps
CPU time 33.53 seconds
Started Aug 08 04:35:09 PM PDT 24
Finished Aug 08 04:35:42 PM PDT 24
Peak memory 199768 kb
Host smart-e7265122-6e23-4695-b57c-256df7643fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553647831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2553647831
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.4225661421
Short name T647
Test name
Test status
Simulation time 3351945741 ps
CPU time 5.4 seconds
Started Aug 08 04:35:05 PM PDT 24
Finished Aug 08 04:35:10 PM PDT 24
Peak memory 196316 kb
Host smart-61dd7cde-b431-44f2-a0be-566bcd5c61c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225661421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.4225661421
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2170835796
Short name T912
Test name
Test status
Simulation time 5470127466 ps
CPU time 18.7 seconds
Started Aug 08 04:35:03 PM PDT 24
Finished Aug 08 04:35:22 PM PDT 24
Peak memory 199488 kb
Host smart-9b8b5f7a-ddf7-4f1e-98cb-21be7333bba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170835796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2170835796
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.217705606
Short name T277
Test name
Test status
Simulation time 57033741307 ps
CPU time 143.13 seconds
Started Aug 08 04:35:10 PM PDT 24
Finished Aug 08 04:37:33 PM PDT 24
Peak memory 216140 kb
Host smart-b1d31fc4-ee04-4087-8fc2-316d6297dbe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217705606 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.217705606
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2125922123
Short name T1109
Test name
Test status
Simulation time 593500216 ps
CPU time 1.98 seconds
Started Aug 08 04:35:03 PM PDT 24
Finished Aug 08 04:35:05 PM PDT 24
Peak memory 198992 kb
Host smart-9dead8ab-d166-4bec-b0a6-8194f5fd4e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125922123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2125922123
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1702963550
Short name T1128
Test name
Test status
Simulation time 258837924094 ps
CPU time 40.45 seconds
Started Aug 08 04:35:03 PM PDT 24
Finished Aug 08 04:35:44 PM PDT 24
Peak memory 199808 kb
Host smart-90ef39eb-80d6-498d-8852-3703fc0bcadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702963550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1702963550
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2405535134
Short name T960
Test name
Test status
Simulation time 31853758335 ps
CPU time 72.87 seconds
Started Aug 08 04:40:57 PM PDT 24
Finished Aug 08 04:42:10 PM PDT 24
Peak memory 199748 kb
Host smart-5c9890ef-e1c4-4d7c-b7dd-2dd8d384518d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405535134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2405535134
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.209740676
Short name T270
Test name
Test status
Simulation time 20235483496 ps
CPU time 9.86 seconds
Started Aug 08 04:40:34 PM PDT 24
Finished Aug 08 04:40:44 PM PDT 24
Peak memory 199720 kb
Host smart-80561478-e72f-41ad-96f3-0bc3d80e7649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209740676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.209740676
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2058891440
Short name T878
Test name
Test status
Simulation time 36866534656 ps
CPU time 55.48 seconds
Started Aug 08 04:40:35 PM PDT 24
Finished Aug 08 04:41:31 PM PDT 24
Peak memory 199748 kb
Host smart-4b8a3053-612c-4ef3-a06a-de693335e589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058891440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2058891440
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2733027649
Short name T180
Test name
Test status
Simulation time 15604704903 ps
CPU time 13.57 seconds
Started Aug 08 04:40:42 PM PDT 24
Finished Aug 08 04:40:56 PM PDT 24
Peak memory 199588 kb
Host smart-3418daaf-f917-4ec7-9204-0e13fcccb2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733027649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2733027649
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.938972856
Short name T1053
Test name
Test status
Simulation time 65682242981 ps
CPU time 25.93 seconds
Started Aug 08 04:40:42 PM PDT 24
Finished Aug 08 04:41:08 PM PDT 24
Peak memory 199716 kb
Host smart-1d738765-38a3-46a8-9644-f5ece5218cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938972856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.938972856
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1328003294
Short name T737
Test name
Test status
Simulation time 40739072534 ps
CPU time 10.88 seconds
Started Aug 08 04:40:48 PM PDT 24
Finished Aug 08 04:40:59 PM PDT 24
Peak memory 198032 kb
Host smart-3a23c85b-31cb-4380-944d-b1f03899eb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328003294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1328003294
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2117701711
Short name T988
Test name
Test status
Simulation time 42096119421 ps
CPU time 43.49 seconds
Started Aug 08 04:40:41 PM PDT 24
Finished Aug 08 04:41:25 PM PDT 24
Peak memory 199752 kb
Host smart-6fcdccd8-9904-4064-b698-48dded054990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117701711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2117701711
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3621034922
Short name T199
Test name
Test status
Simulation time 84435801774 ps
CPU time 135 seconds
Started Aug 08 04:40:41 PM PDT 24
Finished Aug 08 04:42:56 PM PDT 24
Peak memory 199752 kb
Host smart-46ccbd7a-c7dc-4ffd-b2a2-e4ff9638eac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621034922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3621034922
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.390028893
Short name T708
Test name
Test status
Simulation time 140693994993 ps
CPU time 124.57 seconds
Started Aug 08 04:40:44 PM PDT 24
Finished Aug 08 04:42:49 PM PDT 24
Peak memory 200108 kb
Host smart-dd3df354-d50b-4477-a069-d7b48e274310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390028893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.390028893
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.4204437353
Short name T731
Test name
Test status
Simulation time 24557394 ps
CPU time 0.58 seconds
Started Aug 08 04:35:13 PM PDT 24
Finished Aug 08 04:35:13 PM PDT 24
Peak memory 195232 kb
Host smart-5afa9ce9-3d43-4adc-97cd-00ff4f73caca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204437353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.4204437353
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.4190747980
Short name T886
Test name
Test status
Simulation time 115787546310 ps
CPU time 69.21 seconds
Started Aug 08 04:35:07 PM PDT 24
Finished Aug 08 04:36:16 PM PDT 24
Peak memory 199656 kb
Host smart-3df3324e-936b-47c1-907f-3c0994bdfd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190747980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.4190747980
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.605289601
Short name T133
Test name
Test status
Simulation time 36993621787 ps
CPU time 60.33 seconds
Started Aug 08 04:35:12 PM PDT 24
Finished Aug 08 04:36:12 PM PDT 24
Peak memory 199728 kb
Host smart-649a0357-966b-4660-b045-170a21566645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605289601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.605289601
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2929626049
Short name T209
Test name
Test status
Simulation time 5597417555 ps
CPU time 10.06 seconds
Started Aug 08 04:35:13 PM PDT 24
Finished Aug 08 04:35:23 PM PDT 24
Peak memory 199748 kb
Host smart-170a46a3-80df-480d-9c65-46417cc3f7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929626049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2929626049
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.4005464812
Short name T380
Test name
Test status
Simulation time 45790502308 ps
CPU time 65.04 seconds
Started Aug 08 04:35:12 PM PDT 24
Finished Aug 08 04:36:17 PM PDT 24
Peak memory 199788 kb
Host smart-6add15ce-50bf-462d-8394-9d8fa365cb06
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005464812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.4005464812
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2457657533
Short name T255
Test name
Test status
Simulation time 119169858063 ps
CPU time 599.67 seconds
Started Aug 08 04:35:17 PM PDT 24
Finished Aug 08 04:45:16 PM PDT 24
Peak memory 199780 kb
Host smart-0c990be8-8b05-496c-b051-4cbdf3cf29fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2457657533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2457657533
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3597690822
Short name T458
Test name
Test status
Simulation time 9429335514 ps
CPU time 15.7 seconds
Started Aug 08 04:35:12 PM PDT 24
Finished Aug 08 04:35:28 PM PDT 24
Peak memory 198376 kb
Host smart-aae2432d-367c-4fd9-b4fa-51638ff0f77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597690822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3597690822
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.2309396117
Short name T1037
Test name
Test status
Simulation time 61252656143 ps
CPU time 13.17 seconds
Started Aug 08 04:35:20 PM PDT 24
Finished Aug 08 04:35:34 PM PDT 24
Peak memory 198380 kb
Host smart-5924d5a1-7b43-4b28-9737-4bae74aa5dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309396117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2309396117
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3371161074
Short name T421
Test name
Test status
Simulation time 33095594748 ps
CPU time 848.69 seconds
Started Aug 08 04:35:17 PM PDT 24
Finished Aug 08 04:49:26 PM PDT 24
Peak memory 199792 kb
Host smart-784c6392-819c-461b-8359-2df937e36525
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3371161074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3371161074
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2958498572
Short name T583
Test name
Test status
Simulation time 2603978225 ps
CPU time 18.27 seconds
Started Aug 08 04:35:21 PM PDT 24
Finished Aug 08 04:35:40 PM PDT 24
Peak memory 198320 kb
Host smart-77d8b85f-9126-42be-ab71-c7da31ab2ce1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2958498572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2958498572
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.501301033
Short name T486
Test name
Test status
Simulation time 92858764457 ps
CPU time 81.7 seconds
Started Aug 08 04:35:16 PM PDT 24
Finished Aug 08 04:36:38 PM PDT 24
Peak memory 199700 kb
Host smart-68626a8b-2401-43bb-9a31-d79adf7627d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501301033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.501301033
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3814980456
Short name T989
Test name
Test status
Simulation time 4290205184 ps
CPU time 1.03 seconds
Started Aug 08 04:35:16 PM PDT 24
Finished Aug 08 04:35:18 PM PDT 24
Peak memory 196304 kb
Host smart-26cc8316-5e0b-41ef-bbcc-b4e231148915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814980456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3814980456
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3878962298
Short name T713
Test name
Test status
Simulation time 6071874030 ps
CPU time 27.85 seconds
Started Aug 08 04:35:11 PM PDT 24
Finished Aug 08 04:35:39 PM PDT 24
Peak memory 199588 kb
Host smart-4319400c-03af-4a36-9f3a-f0c04e6dc56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878962298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3878962298
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3495802802
Short name T621
Test name
Test status
Simulation time 152107852488 ps
CPU time 114.39 seconds
Started Aug 08 04:35:15 PM PDT 24
Finished Aug 08 04:37:09 PM PDT 24
Peak memory 199784 kb
Host smart-0f93731f-4018-469b-a491-52216e9c64f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495802802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3495802802
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2026434158
Short name T1148
Test name
Test status
Simulation time 138262090992 ps
CPU time 719.45 seconds
Started Aug 08 04:35:29 PM PDT 24
Finished Aug 08 04:47:28 PM PDT 24
Peak memory 210428 kb
Host smart-4cfbc544-ceb8-4c6a-b308-22e35b0b5fc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026434158 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2026434158
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3295290306
Short name T459
Test name
Test status
Simulation time 2041526033 ps
CPU time 2.67 seconds
Started Aug 08 04:35:14 PM PDT 24
Finished Aug 08 04:35:17 PM PDT 24
Peak memory 199712 kb
Host smart-8fbbd60d-6d1d-4342-a33e-eb15d5c8ffe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295290306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3295290306
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3929672037
Short name T956
Test name
Test status
Simulation time 49206424586 ps
CPU time 68.96 seconds
Started Aug 08 04:35:04 PM PDT 24
Finished Aug 08 04:36:14 PM PDT 24
Peak memory 199736 kb
Host smart-ed54a91e-4dd0-4759-90be-82a62b12b6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929672037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3929672037
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2330897040
Short name T177
Test name
Test status
Simulation time 26128109264 ps
CPU time 10.75 seconds
Started Aug 08 04:40:42 PM PDT 24
Finished Aug 08 04:40:53 PM PDT 24
Peak memory 199736 kb
Host smart-5a584f54-468d-4ee9-99f4-811665d4e314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330897040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2330897040
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1386710224
Short name T351
Test name
Test status
Simulation time 32469789966 ps
CPU time 44.4 seconds
Started Aug 08 04:40:44 PM PDT 24
Finished Aug 08 04:41:29 PM PDT 24
Peak memory 199836 kb
Host smart-4e47bcb8-c3fb-4f71-a7bd-309b7fab415a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386710224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1386710224
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3996960334
Short name T202
Test name
Test status
Simulation time 145054287694 ps
CPU time 226.65 seconds
Started Aug 08 04:41:11 PM PDT 24
Finished Aug 08 04:44:58 PM PDT 24
Peak memory 199816 kb
Host smart-32210210-6875-4bfc-8069-a0a92ec72a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996960334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3996960334
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1055763565
Short name T1042
Test name
Test status
Simulation time 55739194363 ps
CPU time 21.54 seconds
Started Aug 08 04:40:46 PM PDT 24
Finished Aug 08 04:41:07 PM PDT 24
Peak memory 199692 kb
Host smart-970127af-c5bf-487d-94ee-16e0446472f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055763565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1055763565
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1259653490
Short name T186
Test name
Test status
Simulation time 6344312603 ps
CPU time 11.21 seconds
Started Aug 08 04:40:42 PM PDT 24
Finished Aug 08 04:40:53 PM PDT 24
Peak memory 199324 kb
Host smart-6ebc2a61-198c-4e94-96aa-a6f321957585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259653490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1259653490
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.367899948
Short name T167
Test name
Test status
Simulation time 177069664634 ps
CPU time 87.54 seconds
Started Aug 08 04:40:48 PM PDT 24
Finished Aug 08 04:42:16 PM PDT 24
Peak memory 199720 kb
Host smart-3ab6b8e3-b528-46b1-ae03-8f47c3e31a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367899948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.367899948
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3214053368
Short name T191
Test name
Test status
Simulation time 112214589972 ps
CPU time 137.55 seconds
Started Aug 08 04:40:53 PM PDT 24
Finished Aug 08 04:43:10 PM PDT 24
Peak memory 199820 kb
Host smart-4f4b62e0-551f-40e9-b301-3aa5f5033038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214053368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3214053368
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1417852549
Short name T169
Test name
Test status
Simulation time 151844891918 ps
CPU time 114.55 seconds
Started Aug 08 04:40:47 PM PDT 24
Finished Aug 08 04:42:42 PM PDT 24
Peak memory 199800 kb
Host smart-7e2208d2-cb4c-4fa8-b383-0a61331e1e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417852549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1417852549
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.46330765
Short name T512
Test name
Test status
Simulation time 65755206893 ps
CPU time 22.54 seconds
Started Aug 08 04:40:46 PM PDT 24
Finished Aug 08 04:41:08 PM PDT 24
Peak memory 199572 kb
Host smart-948543c2-f906-4b8a-9479-a228f7817bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46330765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.46330765
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3058848717
Short name T585
Test name
Test status
Simulation time 41698590701 ps
CPU time 11.76 seconds
Started Aug 08 04:40:44 PM PDT 24
Finished Aug 08 04:40:56 PM PDT 24
Peak memory 200164 kb
Host smart-64ea42b5-f601-4f0e-ac6c-0a5ff9c2bc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058848717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3058848717
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.971939997
Short name T22
Test name
Test status
Simulation time 10822404 ps
CPU time 0.63 seconds
Started Aug 08 04:35:25 PM PDT 24
Finished Aug 08 04:35:25 PM PDT 24
Peak memory 195552 kb
Host smart-1d94dfb4-0731-4a28-9a7e-aa7b1e29af37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971939997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.971939997
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.4143550833
Short name T904
Test name
Test status
Simulation time 48857541660 ps
CPU time 40.43 seconds
Started Aug 08 04:35:13 PM PDT 24
Finished Aug 08 04:35:53 PM PDT 24
Peak memory 199856 kb
Host smart-449e728f-476e-460c-97f4-4ad645067465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143550833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.4143550833
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1938954720
Short name T1138
Test name
Test status
Simulation time 177915532858 ps
CPU time 261.57 seconds
Started Aug 08 04:35:12 PM PDT 24
Finished Aug 08 04:39:34 PM PDT 24
Peak memory 199796 kb
Host smart-e417f960-8e6a-479e-b012-d3cc9aa91e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938954720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1938954720
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.42274395
Short name T715
Test name
Test status
Simulation time 60067098442 ps
CPU time 47.68 seconds
Started Aug 08 04:35:12 PM PDT 24
Finished Aug 08 04:36:00 PM PDT 24
Peak memory 199648 kb
Host smart-745eb6b9-e9fa-42cf-885b-d3e590087330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42274395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.42274395
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.2719252225
Short name T295
Test name
Test status
Simulation time 240716727796 ps
CPU time 102.94 seconds
Started Aug 08 04:35:21 PM PDT 24
Finished Aug 08 04:37:04 PM PDT 24
Peak memory 199732 kb
Host smart-85b07153-9e2f-4c2e-808a-679a8f6f7bdf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719252225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2719252225
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3187937379
Short name T758
Test name
Test status
Simulation time 149907626615 ps
CPU time 403.15 seconds
Started Aug 08 04:35:25 PM PDT 24
Finished Aug 08 04:42:08 PM PDT 24
Peak memory 199800 kb
Host smart-30248857-a709-417c-8f5a-f4f098c753fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3187937379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3187937379
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3001390763
Short name T334
Test name
Test status
Simulation time 6787046137 ps
CPU time 5.65 seconds
Started Aug 08 04:35:25 PM PDT 24
Finished Aug 08 04:35:31 PM PDT 24
Peak memory 199828 kb
Host smart-f3c084fb-5e76-490e-a959-658666668481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001390763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3001390763
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.3532581971
Short name T456
Test name
Test status
Simulation time 26755717797 ps
CPU time 67.85 seconds
Started Aug 08 04:35:13 PM PDT 24
Finished Aug 08 04:36:21 PM PDT 24
Peak memory 198172 kb
Host smart-d42294a9-a17f-4a70-b5d9-4c626d3fcb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532581971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3532581971
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2706656302
Short name T319
Test name
Test status
Simulation time 8469238235 ps
CPU time 361.67 seconds
Started Aug 08 04:35:27 PM PDT 24
Finished Aug 08 04:41:29 PM PDT 24
Peak memory 199736 kb
Host smart-822776d6-e8fe-40df-9db1-0c20d55e2cbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2706656302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2706656302
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.4112838428
Short name T1001
Test name
Test status
Simulation time 1819248871 ps
CPU time 2.16 seconds
Started Aug 08 04:35:21 PM PDT 24
Finished Aug 08 04:35:23 PM PDT 24
Peak memory 197828 kb
Host smart-ca3b52c9-1d68-4a65-91a2-711100a6b058
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4112838428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.4112838428
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1132580178
Short name T438
Test name
Test status
Simulation time 142602414377 ps
CPU time 50.34 seconds
Started Aug 08 04:35:15 PM PDT 24
Finished Aug 08 04:36:06 PM PDT 24
Peak memory 199708 kb
Host smart-31935d23-9c00-4e8b-93f0-1536437606d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132580178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1132580178
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3794772684
Short name T1090
Test name
Test status
Simulation time 44384625116 ps
CPU time 58.56 seconds
Started Aug 08 04:35:12 PM PDT 24
Finished Aug 08 04:36:10 PM PDT 24
Peak memory 196004 kb
Host smart-adb421ba-47df-46e3-87ca-4d8d1ad1c85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794772684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3794772684
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3119392008
Short name T454
Test name
Test status
Simulation time 464918570 ps
CPU time 1.53 seconds
Started Aug 08 04:35:21 PM PDT 24
Finished Aug 08 04:35:23 PM PDT 24
Peak memory 197980 kb
Host smart-d50f0145-9c7d-4b4d-9e8b-820dd623bdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119392008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3119392008
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1973710952
Short name T883
Test name
Test status
Simulation time 81885675633 ps
CPU time 159.26 seconds
Started Aug 08 04:35:24 PM PDT 24
Finished Aug 08 04:38:04 PM PDT 24
Peak memory 199776 kb
Host smart-2bebc8f8-8492-4e6c-bec7-17db8ad4d136
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973710952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1973710952
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.4155576455
Short name T476
Test name
Test status
Simulation time 13764266822 ps
CPU time 18.49 seconds
Started Aug 08 04:35:14 PM PDT 24
Finished Aug 08 04:35:33 PM PDT 24
Peak memory 199712 kb
Host smart-510535db-4f89-4f52-9bd8-f3cc45ef63b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155576455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.4155576455
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3255303473
Short name T328
Test name
Test status
Simulation time 329768903287 ps
CPU time 32.37 seconds
Started Aug 08 04:35:17 PM PDT 24
Finished Aug 08 04:35:50 PM PDT 24
Peak memory 199732 kb
Host smart-2bb73db7-bbf7-4a79-9880-b96a47552b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255303473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3255303473
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.642228892
Short name T200
Test name
Test status
Simulation time 38852114078 ps
CPU time 20.25 seconds
Started Aug 08 04:42:59 PM PDT 24
Finished Aug 08 04:43:19 PM PDT 24
Peak memory 197592 kb
Host smart-377af438-4b6d-4dce-a09c-5e88e7937474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642228892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.642228892
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2532226633
Short name T422
Test name
Test status
Simulation time 9872698474 ps
CPU time 18.18 seconds
Started Aug 08 04:40:47 PM PDT 24
Finished Aug 08 04:41:06 PM PDT 24
Peak memory 199616 kb
Host smart-729a301c-0f85-42a8-91db-8ba6edcdf195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532226633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2532226633
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3048261584
Short name T727
Test name
Test status
Simulation time 48488025827 ps
CPU time 53.33 seconds
Started Aug 08 04:40:48 PM PDT 24
Finished Aug 08 04:41:41 PM PDT 24
Peak memory 199700 kb
Host smart-7cbcfcf0-45ec-4a60-a4c6-c75e8dfb2dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048261584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3048261584
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.425502943
Short name T1078
Test name
Test status
Simulation time 136460849065 ps
CPU time 121.88 seconds
Started Aug 08 04:40:41 PM PDT 24
Finished Aug 08 04:42:43 PM PDT 24
Peak memory 199820 kb
Host smart-ef41b8c7-249e-4eff-97c2-74541eaf230c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425502943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.425502943
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.97501925
Short name T575
Test name
Test status
Simulation time 38694389057 ps
CPU time 15.59 seconds
Started Aug 08 04:40:41 PM PDT 24
Finished Aug 08 04:40:57 PM PDT 24
Peak memory 199076 kb
Host smart-1824ff88-2854-4ca0-aa63-7c1b10105b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97501925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.97501925
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1876171749
Short name T237
Test name
Test status
Simulation time 61235560872 ps
CPU time 57.85 seconds
Started Aug 08 04:40:52 PM PDT 24
Finished Aug 08 04:41:50 PM PDT 24
Peak memory 199828 kb
Host smart-eee592dd-18b7-4030-95c0-dccfbf0ad611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876171749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1876171749
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.633755983
Short name T182
Test name
Test status
Simulation time 95630349380 ps
CPU time 20.67 seconds
Started Aug 08 04:40:52 PM PDT 24
Finished Aug 08 04:41:13 PM PDT 24
Peak memory 199788 kb
Host smart-87f292a2-5e6d-427a-9e51-72290f1a2e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633755983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.633755983
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2370369522
Short name T518
Test name
Test status
Simulation time 109566681005 ps
CPU time 133.83 seconds
Started Aug 08 04:41:18 PM PDT 24
Finished Aug 08 04:43:32 PM PDT 24
Peak memory 199664 kb
Host smart-4213f095-f4a6-4577-a343-c24589471d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370369522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2370369522
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.4244209161
Short name T337
Test name
Test status
Simulation time 120917959340 ps
CPU time 193.8 seconds
Started Aug 08 04:41:00 PM PDT 24
Finished Aug 08 04:44:14 PM PDT 24
Peak memory 199808 kb
Host smart-834c7214-cf92-42ef-928f-bd9b22780873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244209161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.4244209161
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1665987174
Short name T104
Test name
Test status
Simulation time 13645985 ps
CPU time 0.55 seconds
Started Aug 08 04:35:34 PM PDT 24
Finished Aug 08 04:35:35 PM PDT 24
Peak memory 195212 kb
Host smart-fcd62a1a-1a80-482f-b5d6-5629eb56cccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665987174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1665987174
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.4015133596
Short name T139
Test name
Test status
Simulation time 39932100045 ps
CPU time 35.4 seconds
Started Aug 08 04:35:25 PM PDT 24
Finished Aug 08 04:36:01 PM PDT 24
Peak memory 199776 kb
Host smart-31001356-6145-45fa-bef7-f90887134471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015133596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.4015133596
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3661735204
Short name T510
Test name
Test status
Simulation time 166286815061 ps
CPU time 357.29 seconds
Started Aug 08 04:35:24 PM PDT 24
Finished Aug 08 04:41:21 PM PDT 24
Peak memory 199836 kb
Host smart-af091fb0-e5ca-4d9c-8284-bd925625ec15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661735204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3661735204
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2948912929
Short name T851
Test name
Test status
Simulation time 108413065826 ps
CPU time 58.47 seconds
Started Aug 08 04:35:21 PM PDT 24
Finished Aug 08 04:36:20 PM PDT 24
Peak memory 199716 kb
Host smart-ab0c0a52-daea-4591-a216-6ce26003665b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948912929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2948912929
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.4034819676
Short name T763
Test name
Test status
Simulation time 127004410257 ps
CPU time 714.01 seconds
Started Aug 08 04:35:35 PM PDT 24
Finished Aug 08 04:47:30 PM PDT 24
Peak memory 199676 kb
Host smart-80f9d6a5-e581-4e10-9ca5-4116498eb9f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4034819676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.4034819676
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3536886265
Short name T537
Test name
Test status
Simulation time 6921080862 ps
CPU time 4.69 seconds
Started Aug 08 04:35:42 PM PDT 24
Finished Aug 08 04:35:47 PM PDT 24
Peak memory 198816 kb
Host smart-b4a24e8b-e975-46c5-9110-c0aa22d6ad9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536886265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3536886265
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.288553130
Short name T403
Test name
Test status
Simulation time 16387532222 ps
CPU time 229.45 seconds
Started Aug 08 04:35:36 PM PDT 24
Finished Aug 08 04:39:26 PM PDT 24
Peak memory 199868 kb
Host smart-beb62f35-b9e4-4282-ad6a-7b8eba1e052c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=288553130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.288553130
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.63082796
Short name T411
Test name
Test status
Simulation time 1480869576 ps
CPU time 5.51 seconds
Started Aug 08 04:35:24 PM PDT 24
Finished Aug 08 04:35:30 PM PDT 24
Peak memory 197892 kb
Host smart-cb1d2746-2852-4563-bd1e-600787b48e09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=63082796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.63082796
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1294331033
Short name T279
Test name
Test status
Simulation time 165281879117 ps
CPU time 251.22 seconds
Started Aug 08 04:35:36 PM PDT 24
Finished Aug 08 04:39:47 PM PDT 24
Peak memory 199700 kb
Host smart-6f59e400-e064-40ff-b159-f86c179962f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294331033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1294331033
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1638116362
Short name T500
Test name
Test status
Simulation time 3454644843 ps
CPU time 6.45 seconds
Started Aug 08 04:35:35 PM PDT 24
Finished Aug 08 04:35:41 PM PDT 24
Peak memory 196084 kb
Host smart-25511cf9-15aa-4d73-814a-7f05904c777d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638116362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1638116362
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2659295042
Short name T302
Test name
Test status
Simulation time 470661506 ps
CPU time 3.37 seconds
Started Aug 08 04:35:25 PM PDT 24
Finished Aug 08 04:35:29 PM PDT 24
Peak memory 198224 kb
Host smart-7e117a30-0257-4340-919d-99a0862136c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659295042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2659295042
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.1382195726
Short name T280
Test name
Test status
Simulation time 135957038645 ps
CPU time 184.07 seconds
Started Aug 08 04:35:35 PM PDT 24
Finished Aug 08 04:38:39 PM PDT 24
Peak memory 199752 kb
Host smart-4af54876-cfe2-455c-8e20-61b1a7dde463
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382195726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1382195726
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2792022904
Short name T672
Test name
Test status
Simulation time 198296919926 ps
CPU time 432.16 seconds
Started Aug 08 04:35:36 PM PDT 24
Finished Aug 08 04:42:48 PM PDT 24
Peak memory 216500 kb
Host smart-b6f93164-f7e6-42a0-937a-bd68c0d63dda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792022904 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2792022904
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.406571901
Short name T746
Test name
Test status
Simulation time 1311860593 ps
CPU time 1.41 seconds
Started Aug 08 04:35:34 PM PDT 24
Finished Aug 08 04:35:36 PM PDT 24
Peak memory 199628 kb
Host smart-52bd3ad4-433a-42d4-83cf-8a9376a07182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406571901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.406571901
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3827312132
Short name T632
Test name
Test status
Simulation time 193676327730 ps
CPU time 94.78 seconds
Started Aug 08 04:35:24 PM PDT 24
Finished Aug 08 04:36:59 PM PDT 24
Peak memory 199712 kb
Host smart-04930d47-f557-4dd8-9e28-be0d68d62308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827312132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3827312132
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3205132256
Short name T532
Test name
Test status
Simulation time 146260886135 ps
CPU time 159.98 seconds
Started Aug 08 04:40:50 PM PDT 24
Finished Aug 08 04:43:31 PM PDT 24
Peak memory 199760 kb
Host smart-987df1a6-0d28-4351-8216-4c1bf7c056e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205132256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3205132256
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1420514519
Short name T699
Test name
Test status
Simulation time 27944981560 ps
CPU time 10.06 seconds
Started Aug 08 04:40:51 PM PDT 24
Finished Aug 08 04:41:01 PM PDT 24
Peak memory 199780 kb
Host smart-2c19cec9-f36a-4e5a-b4f1-4dbd5e9e9558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420514519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1420514519
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.964265690
Short name T126
Test name
Test status
Simulation time 148032152958 ps
CPU time 49.73 seconds
Started Aug 08 04:41:19 PM PDT 24
Finished Aug 08 04:42:09 PM PDT 24
Peak memory 199812 kb
Host smart-fef06b8a-86f8-4d5f-93c4-b8927413bdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964265690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.964265690
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2801408493
Short name T284
Test name
Test status
Simulation time 8184112046 ps
CPU time 15.75 seconds
Started Aug 08 04:40:53 PM PDT 24
Finished Aug 08 04:41:09 PM PDT 24
Peak memory 199820 kb
Host smart-6178c1ec-4821-453f-87e8-e6871a27900f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801408493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2801408493
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3619628465
Short name T1116
Test name
Test status
Simulation time 58854114827 ps
CPU time 81.93 seconds
Started Aug 08 04:41:00 PM PDT 24
Finished Aug 08 04:42:22 PM PDT 24
Peak memory 199808 kb
Host smart-3634ed58-e4b3-42f9-a3c6-e2a746859f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619628465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3619628465
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1103677909
Short name T224
Test name
Test status
Simulation time 8660521694 ps
CPU time 13.05 seconds
Started Aug 08 04:40:52 PM PDT 24
Finished Aug 08 04:41:05 PM PDT 24
Peak memory 199796 kb
Host smart-ef57cc56-f000-49f7-8dc3-36cbb2137920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103677909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1103677909
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3903884133
Short name T1127
Test name
Test status
Simulation time 158587300985 ps
CPU time 140.24 seconds
Started Aug 08 04:40:55 PM PDT 24
Finished Aug 08 04:43:15 PM PDT 24
Peak memory 199780 kb
Host smart-f793cf3d-cb27-4c00-8da0-e946d0a339ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903884133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3903884133
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2657976137
Short name T195
Test name
Test status
Simulation time 20269685223 ps
CPU time 33.55 seconds
Started Aug 08 04:40:53 PM PDT 24
Finished Aug 08 04:41:26 PM PDT 24
Peak memory 199848 kb
Host smart-a13f2490-ed61-42ba-86f8-f2e2c3eba5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657976137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2657976137
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.955752284
Short name T850
Test name
Test status
Simulation time 109243200274 ps
CPU time 153.22 seconds
Started Aug 08 04:40:50 PM PDT 24
Finished Aug 08 04:43:23 PM PDT 24
Peak memory 199752 kb
Host smart-71136797-2bd8-4353-a4a7-8d14523e29c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955752284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.955752284
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3340947623
Short name T466
Test name
Test status
Simulation time 12319991060 ps
CPU time 11.38 seconds
Started Aug 08 04:41:49 PM PDT 24
Finished Aug 08 04:42:00 PM PDT 24
Peak memory 199788 kb
Host smart-51d27314-7984-4770-a629-08cbb0dee326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340947623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3340947623
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.515031287
Short name T429
Test name
Test status
Simulation time 11715879 ps
CPU time 0.56 seconds
Started Aug 08 04:35:47 PM PDT 24
Finished Aug 08 04:35:48 PM PDT 24
Peak memory 195184 kb
Host smart-a9f98646-2919-491b-9eaa-9423f30b53db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515031287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.515031287
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.831856699
Short name T948
Test name
Test status
Simulation time 75839087489 ps
CPU time 102.61 seconds
Started Aug 08 04:35:35 PM PDT 24
Finished Aug 08 04:37:18 PM PDT 24
Peak memory 199748 kb
Host smart-13f26941-ad17-4a65-a331-2b7986ff1c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831856699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.831856699
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2429839199
Short name T1167
Test name
Test status
Simulation time 144730113096 ps
CPU time 69.78 seconds
Started Aug 08 04:35:36 PM PDT 24
Finished Aug 08 04:36:46 PM PDT 24
Peak memory 199796 kb
Host smart-2dcb6e62-31a5-45a8-8e2d-2436770470ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429839199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2429839199
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2738303357
Short name T204
Test name
Test status
Simulation time 24719046456 ps
CPU time 40.51 seconds
Started Aug 08 04:35:34 PM PDT 24
Finished Aug 08 04:36:15 PM PDT 24
Peak memory 199780 kb
Host smart-d863516b-f6ea-4f6f-a161-0396230c49ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738303357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2738303357
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.3505698292
Short name T48
Test name
Test status
Simulation time 453154365589 ps
CPU time 362.24 seconds
Started Aug 08 04:35:34 PM PDT 24
Finished Aug 08 04:41:36 PM PDT 24
Peak memory 198692 kb
Host smart-d6b5ad9b-0a60-4e4f-8197-f923066cb9cf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505698292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3505698292
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2832160871
Short name T35
Test name
Test status
Simulation time 117242676242 ps
CPU time 151.18 seconds
Started Aug 08 04:35:37 PM PDT 24
Finished Aug 08 04:38:08 PM PDT 24
Peak memory 199816 kb
Host smart-47619686-c326-4ba0-8e11-f49c5c8bddc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2832160871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2832160871
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1630506455
Short name T378
Test name
Test status
Simulation time 2172028319 ps
CPU time 4.02 seconds
Started Aug 08 04:35:39 PM PDT 24
Finished Aug 08 04:35:43 PM PDT 24
Peak memory 198804 kb
Host smart-07c01604-c27c-49b4-917b-915290d5cfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630506455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1630506455
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2701127685
Short name T914
Test name
Test status
Simulation time 49194881914 ps
CPU time 8.27 seconds
Started Aug 08 04:35:36 PM PDT 24
Finished Aug 08 04:35:44 PM PDT 24
Peak memory 195460 kb
Host smart-cff30814-b533-4955-9b06-dbda876dd6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701127685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2701127685
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.772578403
Short name T828
Test name
Test status
Simulation time 10788202917 ps
CPU time 133.67 seconds
Started Aug 08 04:35:40 PM PDT 24
Finished Aug 08 04:37:53 PM PDT 24
Peak memory 199724 kb
Host smart-6b906fd3-3a59-488e-9152-c4cdfea38bd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=772578403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.772578403
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1403975039
Short name T728
Test name
Test status
Simulation time 4013153284 ps
CPU time 28.64 seconds
Started Aug 08 04:35:40 PM PDT 24
Finished Aug 08 04:36:09 PM PDT 24
Peak memory 199208 kb
Host smart-f9434259-f3e7-4091-9d23-0e093c61179f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1403975039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1403975039
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3847912876
Short name T779
Test name
Test status
Simulation time 129752607036 ps
CPU time 67.81 seconds
Started Aug 08 04:35:34 PM PDT 24
Finished Aug 08 04:36:42 PM PDT 24
Peak memory 199696 kb
Host smart-af22f1b4-4791-4691-99d5-87ea316e6729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847912876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3847912876
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.307589297
Short name T367
Test name
Test status
Simulation time 579876184 ps
CPU time 1.05 seconds
Started Aug 08 04:35:42 PM PDT 24
Finished Aug 08 04:35:43 PM PDT 24
Peak memory 195336 kb
Host smart-5b0cb8f4-be9b-4c72-aacf-8f6bd697f553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307589297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.307589297
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1063905994
Short name T305
Test name
Test status
Simulation time 6211191945 ps
CPU time 19.89 seconds
Started Aug 08 04:35:36 PM PDT 24
Finished Aug 08 04:35:56 PM PDT 24
Peak memory 199744 kb
Host smart-6efb9de6-63b2-4e13-bc0e-6affa307e415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063905994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1063905994
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3747716435
Short name T249
Test name
Test status
Simulation time 428952341673 ps
CPU time 77.34 seconds
Started Aug 08 04:35:50 PM PDT 24
Finished Aug 08 04:37:08 PM PDT 24
Peak memory 215644 kb
Host smart-6a884c70-76bc-4588-83ad-7587c5b5dd55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747716435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3747716435
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.138060178
Short name T164
Test name
Test status
Simulation time 44234740533 ps
CPU time 481.18 seconds
Started Aug 08 04:35:38 PM PDT 24
Finished Aug 08 04:43:39 PM PDT 24
Peak memory 216300 kb
Host smart-f42e762f-1f40-491e-a1f1-7f49e107b73f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138060178 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.138060178
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2795821151
Short name T634
Test name
Test status
Simulation time 6453326089 ps
CPU time 8.68 seconds
Started Aug 08 04:35:35 PM PDT 24
Finished Aug 08 04:35:44 PM PDT 24
Peak memory 199572 kb
Host smart-0712b157-1223-4ad6-9659-6552da053a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795821151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2795821151
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2307066548
Short name T318
Test name
Test status
Simulation time 43121791292 ps
CPU time 63.15 seconds
Started Aug 08 04:35:37 PM PDT 24
Finished Aug 08 04:36:40 PM PDT 24
Peak memory 199828 kb
Host smart-b0625ee9-9105-48b1-b42b-2baddefc1ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307066548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2307066548
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.866470416
Short name T688
Test name
Test status
Simulation time 15691989085 ps
CPU time 30.53 seconds
Started Aug 08 04:41:51 PM PDT 24
Finished Aug 08 04:42:22 PM PDT 24
Peak memory 199800 kb
Host smart-babfa689-b0a0-4ba6-af6c-9a95ab2d27b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866470416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.866470416
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.494839817
Short name T1171
Test name
Test status
Simulation time 19420278415 ps
CPU time 32.23 seconds
Started Aug 08 04:41:49 PM PDT 24
Finished Aug 08 04:42:21 PM PDT 24
Peak memory 199796 kb
Host smart-233db044-6d3a-44eb-9402-f2c33f99c51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494839817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.494839817
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2943961915
Short name T198
Test name
Test status
Simulation time 36772986631 ps
CPU time 27.44 seconds
Started Aug 08 04:40:50 PM PDT 24
Finished Aug 08 04:41:18 PM PDT 24
Peak memory 199756 kb
Host smart-d3e55108-9a1a-4a46-959b-55b3233861b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943961915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2943961915
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1436424026
Short name T230
Test name
Test status
Simulation time 14552666816 ps
CPU time 21.95 seconds
Started Aug 08 04:41:50 PM PDT 24
Finished Aug 08 04:42:12 PM PDT 24
Peak memory 199812 kb
Host smart-2ff26feb-3ac4-4e2a-af2c-e1b031aaad79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436424026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1436424026
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1708783521
Short name T723
Test name
Test status
Simulation time 60862078080 ps
CPU time 84.91 seconds
Started Aug 08 04:40:49 PM PDT 24
Finished Aug 08 04:42:14 PM PDT 24
Peak memory 199712 kb
Host smart-e936b819-0d5f-4d40-b2dd-9cd9fe64ef54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708783521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1708783521
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.3573474123
Short name T865
Test name
Test status
Simulation time 60302840352 ps
CPU time 101.34 seconds
Started Aug 08 04:40:53 PM PDT 24
Finished Aug 08 04:42:34 PM PDT 24
Peak memory 199848 kb
Host smart-cf36088e-784f-40fe-8c88-ca9858feeb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573474123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3573474123
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.280697301
Short name T1098
Test name
Test status
Simulation time 18187470337 ps
CPU time 14.79 seconds
Started Aug 08 04:41:04 PM PDT 24
Finished Aug 08 04:41:19 PM PDT 24
Peak memory 199740 kb
Host smart-6809ec72-2a1e-4e9f-a27b-3dd2de0cf158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280697301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.280697301
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3856730155
Short name T1174
Test name
Test status
Simulation time 44905950712 ps
CPU time 11.33 seconds
Started Aug 08 04:41:04 PM PDT 24
Finished Aug 08 04:41:16 PM PDT 24
Peak memory 199712 kb
Host smart-813c4cc3-9898-45aa-860f-3deb3255e17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856730155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3856730155
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.1385571992
Short name T170
Test name
Test status
Simulation time 5108279777 ps
CPU time 4.81 seconds
Started Aug 08 04:41:03 PM PDT 24
Finished Aug 08 04:41:08 PM PDT 24
Peak memory 199584 kb
Host smart-9a996e55-725c-42ef-8e49-b199ad968bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385571992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1385571992
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.632737401
Short name T997
Test name
Test status
Simulation time 38863555 ps
CPU time 0.57 seconds
Started Aug 08 04:32:24 PM PDT 24
Finished Aug 08 04:32:25 PM PDT 24
Peak memory 195124 kb
Host smart-b73f850e-aa95-4c47-bbe3-3d92b1815df1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632737401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.632737401
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2109271979
Short name T123
Test name
Test status
Simulation time 82732027297 ps
CPU time 69.42 seconds
Started Aug 08 04:32:07 PM PDT 24
Finished Aug 08 04:33:17 PM PDT 24
Peak memory 199720 kb
Host smart-c0d637e7-8af2-429a-bdde-53fc810333b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109271979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2109271979
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2978756800
Short name T879
Test name
Test status
Simulation time 218691209515 ps
CPU time 23.46 seconds
Started Aug 08 04:32:07 PM PDT 24
Finished Aug 08 04:32:31 PM PDT 24
Peak memory 199148 kb
Host smart-f8a8d1b5-ee17-41a8-a85d-26d5150a84d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978756800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2978756800
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_intr.3438436755
Short name T609
Test name
Test status
Simulation time 65452954680 ps
CPU time 142.12 seconds
Started Aug 08 04:32:05 PM PDT 24
Finished Aug 08 04:34:27 PM PDT 24
Peak memory 199748 kb
Host smart-cd3de06e-c3f5-4eff-a9bc-aa1a50855fa5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438436755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3438436755
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3419456386
Short name T452
Test name
Test status
Simulation time 83026190601 ps
CPU time 186.25 seconds
Started Aug 08 04:32:23 PM PDT 24
Finished Aug 08 04:35:30 PM PDT 24
Peak memory 199784 kb
Host smart-98f303a0-fea1-46b5-b8c8-11c9e3975405
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3419456386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3419456386
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.165689963
Short name T969
Test name
Test status
Simulation time 5854510026 ps
CPU time 8.26 seconds
Started Aug 08 04:32:22 PM PDT 24
Finished Aug 08 04:32:31 PM PDT 24
Peak memory 199628 kb
Host smart-af12975e-27ad-4bfa-81d6-fb53f8908246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165689963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.165689963
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.2909529726
Short name T462
Test name
Test status
Simulation time 29869666813 ps
CPU time 49.41 seconds
Started Aug 08 04:32:26 PM PDT 24
Finished Aug 08 04:33:15 PM PDT 24
Peak memory 199880 kb
Host smart-624e2e6f-3da8-4771-bb50-12d956b26ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909529726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2909529726
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1634394069
Short name T636
Test name
Test status
Simulation time 20988693738 ps
CPU time 85.07 seconds
Started Aug 08 04:32:25 PM PDT 24
Finished Aug 08 04:33:50 PM PDT 24
Peak memory 199760 kb
Host smart-fe1187c4-b38d-412a-9eb1-2e25baf307d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1634394069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1634394069
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3229282334
Short name T1106
Test name
Test status
Simulation time 5459572983 ps
CPU time 42.4 seconds
Started Aug 08 04:32:06 PM PDT 24
Finished Aug 08 04:32:49 PM PDT 24
Peak memory 197964 kb
Host smart-3c76e61c-d4d3-4e89-80c5-d5430b59e31d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3229282334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3229282334
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2876448339
Short name T1062
Test name
Test status
Simulation time 138189351987 ps
CPU time 73.86 seconds
Started Aug 08 04:32:23 PM PDT 24
Finished Aug 08 04:33:37 PM PDT 24
Peak memory 199756 kb
Host smart-0d5c939d-ef1c-4e33-840a-0f10c7eac1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876448339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2876448339
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1969907507
Short name T868
Test name
Test status
Simulation time 17447655863 ps
CPU time 7.13 seconds
Started Aug 08 04:32:22 PM PDT 24
Finished Aug 08 04:32:29 PM PDT 24
Peak memory 195912 kb
Host smart-b9244966-2fbf-43c0-805a-4f4247254cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969907507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1969907507
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.606032376
Short name T24
Test name
Test status
Simulation time 214377837 ps
CPU time 0.78 seconds
Started Aug 08 04:32:23 PM PDT 24
Finished Aug 08 04:32:24 PM PDT 24
Peak memory 218104 kb
Host smart-794e16ec-a56c-49c1-b958-83eee1a65478
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606032376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.606032376
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.901385413
Short name T287
Test name
Test status
Simulation time 5710229604 ps
CPU time 16.84 seconds
Started Aug 08 04:32:05 PM PDT 24
Finished Aug 08 04:32:22 PM PDT 24
Peak memory 199052 kb
Host smart-ccb75343-7cbc-4438-b6a3-4efc64419650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901385413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.901385413
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.293608130
Short name T822
Test name
Test status
Simulation time 193081977845 ps
CPU time 330.59 seconds
Started Aug 08 04:32:22 PM PDT 24
Finished Aug 08 04:37:53 PM PDT 24
Peak memory 216148 kb
Host smart-38cb3660-04b0-4b0e-8e89-4ed1176611b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293608130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.293608130
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.3729668387
Short name T691
Test name
Test status
Simulation time 56044924439 ps
CPU time 664.96 seconds
Started Aug 08 04:32:22 PM PDT 24
Finished Aug 08 04:43:27 PM PDT 24
Peak memory 216268 kb
Host smart-00397c0f-5ec3-4811-b30a-45bb55b07205
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729668387 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3729668387
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1549205939
Short name T1157
Test name
Test status
Simulation time 927458265 ps
CPU time 1.48 seconds
Started Aug 08 04:32:22 PM PDT 24
Finished Aug 08 04:32:23 PM PDT 24
Peak memory 198112 kb
Host smart-acfabf98-b850-49d1-a65d-edbb86004f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549205939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1549205939
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2016560229
Short name T312
Test name
Test status
Simulation time 42960367537 ps
CPU time 20.38 seconds
Started Aug 08 04:32:06 PM PDT 24
Finished Aug 08 04:32:26 PM PDT 24
Peak memory 199744 kb
Host smart-79d89d91-7c4f-483e-9133-c7ed4330817b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016560229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2016560229
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2751088710
Short name T993
Test name
Test status
Simulation time 30515559 ps
CPU time 0.55 seconds
Started Aug 08 04:35:45 PM PDT 24
Finished Aug 08 04:35:46 PM PDT 24
Peak memory 195208 kb
Host smart-8cd05e43-e2b6-47eb-a93e-b9c9c07a4a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751088710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2751088710
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3156741491
Short name T267
Test name
Test status
Simulation time 64385335826 ps
CPU time 51.85 seconds
Started Aug 08 04:36:03 PM PDT 24
Finished Aug 08 04:36:55 PM PDT 24
Peak memory 199844 kb
Host smart-182d3a6c-631b-4137-ad6d-89b8cbd650f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156741491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3156741491
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1993895485
Short name T928
Test name
Test status
Simulation time 34759141703 ps
CPU time 38.48 seconds
Started Aug 08 04:35:49 PM PDT 24
Finished Aug 08 04:36:27 PM PDT 24
Peak memory 199728 kb
Host smart-8a441da5-7426-4ab8-8e1e-c1d6ad45f910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993895485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1993895485
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.6800012
Short name T163
Test name
Test status
Simulation time 14285734086 ps
CPU time 20.88 seconds
Started Aug 08 04:35:48 PM PDT 24
Finished Aug 08 04:36:09 PM PDT 24
Peak memory 199768 kb
Host smart-947edd92-ada4-4020-98e4-ff2816dc2896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6800012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.6800012
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3386600580
Short name T1122
Test name
Test status
Simulation time 22451306340 ps
CPU time 19.99 seconds
Started Aug 08 04:35:47 PM PDT 24
Finished Aug 08 04:36:07 PM PDT 24
Peak memory 199768 kb
Host smart-2585caf2-6b4b-4211-9ed9-ad01485d1588
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386600580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3386600580
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3569385761
Short name T675
Test name
Test status
Simulation time 67146878625 ps
CPU time 271.29 seconds
Started Aug 08 04:35:49 PM PDT 24
Finished Aug 08 04:40:20 PM PDT 24
Peak memory 199708 kb
Host smart-6214f6bd-bebc-4702-80b9-3a95acbd2294
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3569385761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3569385761
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1218950320
Short name T918
Test name
Test status
Simulation time 11565621287 ps
CPU time 19.42 seconds
Started Aug 08 04:35:47 PM PDT 24
Finished Aug 08 04:36:06 PM PDT 24
Peak memory 198932 kb
Host smart-f4bcd3c3-e418-480c-ad58-f01a46416e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218950320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1218950320
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.441321070
Short name T1038
Test name
Test status
Simulation time 447982453124 ps
CPU time 57.01 seconds
Started Aug 08 04:35:45 PM PDT 24
Finished Aug 08 04:36:43 PM PDT 24
Peak memory 199828 kb
Host smart-133f4499-164a-4fe5-8483-b0dc50cf7096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441321070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.441321070
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2172260830
Short name T694
Test name
Test status
Simulation time 8964389534 ps
CPU time 256.77 seconds
Started Aug 08 04:35:54 PM PDT 24
Finished Aug 08 04:40:11 PM PDT 24
Peak memory 199744 kb
Host smart-921306d2-c102-469e-9cd0-d8cf8d7785d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2172260830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2172260830
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3814000711
Short name T880
Test name
Test status
Simulation time 7587444028 ps
CPU time 35.68 seconds
Started Aug 08 04:35:47 PM PDT 24
Finished Aug 08 04:36:23 PM PDT 24
Peak memory 199020 kb
Host smart-1044461d-a0cd-4da1-9c08-b14471b633e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814000711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3814000711
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.850114276
Short name T553
Test name
Test status
Simulation time 106827329794 ps
CPU time 45.43 seconds
Started Aug 08 04:35:48 PM PDT 24
Finished Aug 08 04:36:34 PM PDT 24
Peak memory 200096 kb
Host smart-50fd1162-d5dd-46a2-a847-2429a00a0a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850114276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.850114276
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.223479234
Short name T700
Test name
Test status
Simulation time 6888128118 ps
CPU time 1.43 seconds
Started Aug 08 04:35:46 PM PDT 24
Finished Aug 08 04:35:48 PM PDT 24
Peak memory 196076 kb
Host smart-878374a5-c89a-4e47-8de4-298b99f995b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223479234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.223479234
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3264623314
Short name T309
Test name
Test status
Simulation time 6076232459 ps
CPU time 28.19 seconds
Started Aug 08 04:35:47 PM PDT 24
Finished Aug 08 04:36:15 PM PDT 24
Peak memory 199392 kb
Host smart-2fe6feb7-23a3-474c-8675-9c3e8541e6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264623314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3264623314
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1419143920
Short name T1119
Test name
Test status
Simulation time 22825830115 ps
CPU time 275.4 seconds
Started Aug 08 04:35:47 PM PDT 24
Finished Aug 08 04:40:22 PM PDT 24
Peak memory 208144 kb
Host smart-d1a35644-e257-4cc4-a77c-59b97d4ec21a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419143920 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1419143920
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.4117647466
Short name T322
Test name
Test status
Simulation time 1182852679 ps
CPU time 4 seconds
Started Aug 08 04:36:05 PM PDT 24
Finished Aug 08 04:36:09 PM PDT 24
Peak memory 200100 kb
Host smart-1edbae12-3796-4f4c-b05a-c3f06de11854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117647466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.4117647466
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3626825524
Short name T677
Test name
Test status
Simulation time 153630603497 ps
CPU time 191.21 seconds
Started Aug 08 04:35:48 PM PDT 24
Finished Aug 08 04:38:59 PM PDT 24
Peak memory 199792 kb
Host smart-a19b8603-87f7-49a2-ab9e-a2ab1441b4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626825524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3626825524
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3242187491
Short name T1017
Test name
Test status
Simulation time 13920521 ps
CPU time 0.56 seconds
Started Aug 08 04:36:12 PM PDT 24
Finished Aug 08 04:36:12 PM PDT 24
Peak memory 195460 kb
Host smart-3bd12ffd-a9a3-433f-9581-ed98a3a9aa93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242187491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3242187491
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3588632261
Short name T38
Test name
Test status
Simulation time 161618933511 ps
CPU time 100.49 seconds
Started Aug 08 04:35:54 PM PDT 24
Finished Aug 08 04:37:35 PM PDT 24
Peak memory 199720 kb
Host smart-d209faf7-0bde-48a9-9652-f2500f77fc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588632261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3588632261
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.847156288
Short name T976
Test name
Test status
Simulation time 29227913988 ps
CPU time 46.04 seconds
Started Aug 08 04:35:55 PM PDT 24
Finished Aug 08 04:36:41 PM PDT 24
Peak memory 199776 kb
Host smart-a4f2bc13-70a5-4e69-a67f-66dca45e596e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847156288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.847156288
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3294323643
Short name T1137
Test name
Test status
Simulation time 192258845095 ps
CPU time 125.46 seconds
Started Aug 08 04:35:58 PM PDT 24
Finished Aug 08 04:38:04 PM PDT 24
Peak memory 199760 kb
Host smart-6f917806-8895-408d-9c60-ec832e8e7a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294323643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3294323643
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3730638018
Short name T117
Test name
Test status
Simulation time 55207622592 ps
CPU time 47.23 seconds
Started Aug 08 04:36:08 PM PDT 24
Finished Aug 08 04:36:55 PM PDT 24
Peak memory 199800 kb
Host smart-d30ac233-553e-4964-8038-28eb47ece3e6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730638018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3730638018
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3199589845
Short name T652
Test name
Test status
Simulation time 77277645691 ps
CPU time 580.77 seconds
Started Aug 08 04:36:05 PM PDT 24
Finished Aug 08 04:45:46 PM PDT 24
Peak memory 199780 kb
Host smart-0d5cdd11-9c1f-4d4b-97d9-d2457b7d1b33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3199589845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3199589845
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1907153874
Short name T356
Test name
Test status
Simulation time 9237578393 ps
CPU time 27.67 seconds
Started Aug 08 04:35:55 PM PDT 24
Finished Aug 08 04:36:23 PM PDT 24
Peak memory 199728 kb
Host smart-2d0a9e88-39e1-45c5-ad7a-3e62c42d6dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907153874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1907153874
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.1993338246
Short name T299
Test name
Test status
Simulation time 164122461889 ps
CPU time 309.57 seconds
Started Aug 08 04:35:55 PM PDT 24
Finished Aug 08 04:41:05 PM PDT 24
Peak memory 199892 kb
Host smart-217c25cc-99d5-4902-857f-fa7ba3f59191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993338246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1993338246
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.2129427002
Short name T692
Test name
Test status
Simulation time 19358655028 ps
CPU time 226.57 seconds
Started Aug 08 04:35:58 PM PDT 24
Finished Aug 08 04:39:45 PM PDT 24
Peak memory 199836 kb
Host smart-09f57cd0-2f62-4bf6-ad4c-d514dd9ac2ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2129427002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2129427002
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1523884199
Short name T887
Test name
Test status
Simulation time 5652760151 ps
CPU time 15.07 seconds
Started Aug 08 04:36:00 PM PDT 24
Finished Aug 08 04:36:15 PM PDT 24
Peak memory 197956 kb
Host smart-2b31bbee-0c13-4823-8daf-1ea11c2e87ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1523884199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1523884199
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1856267948
Short name T613
Test name
Test status
Simulation time 113191593843 ps
CPU time 382.08 seconds
Started Aug 08 04:36:07 PM PDT 24
Finished Aug 08 04:42:29 PM PDT 24
Peak memory 199744 kb
Host smart-ec6ceda8-74f7-4dec-ac95-7ed84c857a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856267948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1856267948
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2087655688
Short name T435
Test name
Test status
Simulation time 1748363450 ps
CPU time 3.15 seconds
Started Aug 08 04:35:54 PM PDT 24
Finished Aug 08 04:35:57 PM PDT 24
Peak memory 195328 kb
Host smart-bfec8380-7376-4ebe-b81f-dd7fdcf51bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087655688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2087655688
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1613947385
Short name T759
Test name
Test status
Simulation time 846103310 ps
CPU time 3.03 seconds
Started Aug 08 04:35:48 PM PDT 24
Finished Aug 08 04:35:51 PM PDT 24
Peak memory 198396 kb
Host smart-be2585a9-a61d-466f-8e82-7b49631d8625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613947385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1613947385
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2212114431
Short name T814
Test name
Test status
Simulation time 169374326240 ps
CPU time 444.62 seconds
Started Aug 08 04:36:04 PM PDT 24
Finished Aug 08 04:43:29 PM PDT 24
Peak memory 216260 kb
Host smart-178ed5c3-78c9-40c9-9c4c-d6971fc20bb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212114431 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2212114431
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.349172355
Short name T743
Test name
Test status
Simulation time 553272550 ps
CPU time 2.44 seconds
Started Aug 08 04:35:59 PM PDT 24
Finished Aug 08 04:36:01 PM PDT 24
Peak memory 199708 kb
Host smart-33f22e08-5c8e-4641-b4bf-bfa6bcb3904b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349172355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.349172355
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1099365639
Short name T384
Test name
Test status
Simulation time 4578931791 ps
CPU time 8.05 seconds
Started Aug 08 04:35:46 PM PDT 24
Finished Aug 08 04:35:54 PM PDT 24
Peak memory 199160 kb
Host smart-47b406fc-4426-4f46-a966-7cea2505d9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099365639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1099365639
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1313136437
Short name T900
Test name
Test status
Simulation time 13730730 ps
CPU time 0.59 seconds
Started Aug 08 04:36:07 PM PDT 24
Finished Aug 08 04:36:07 PM PDT 24
Peak memory 195160 kb
Host smart-7dd432dc-085a-44da-955f-cfc08265f5c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313136437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1313136437
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.658613522
Short name T543
Test name
Test status
Simulation time 156182608103 ps
CPU time 210.85 seconds
Started Aug 08 04:35:57 PM PDT 24
Finished Aug 08 04:39:28 PM PDT 24
Peak memory 199752 kb
Host smart-5131aec4-dcb9-4ef5-9aa2-2c222c017229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658613522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.658613522
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2335396360
Short name T159
Test name
Test status
Simulation time 83412793945 ps
CPU time 35.91 seconds
Started Aug 08 04:36:05 PM PDT 24
Finished Aug 08 04:36:41 PM PDT 24
Peak memory 199820 kb
Host smart-bab965aa-fc7a-4087-81c3-3ee5215355c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335396360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2335396360
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2661166246
Short name T826
Test name
Test status
Simulation time 57397784717 ps
CPU time 93.41 seconds
Started Aug 08 04:36:27 PM PDT 24
Finished Aug 08 04:38:00 PM PDT 24
Peak memory 199792 kb
Host smart-ebf0ee97-f29a-42cf-95d6-5d9517dbbcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661166246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2661166246
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3061797451
Short name T695
Test name
Test status
Simulation time 9872018267 ps
CPU time 3.17 seconds
Started Aug 08 04:36:05 PM PDT 24
Finished Aug 08 04:36:08 PM PDT 24
Peak memory 196520 kb
Host smart-2de23650-a2c5-48f9-9fb9-6b82e895be6c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061797451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3061797451
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3507078536
Short name T324
Test name
Test status
Simulation time 77346772978 ps
CPU time 171.27 seconds
Started Aug 08 04:36:05 PM PDT 24
Finished Aug 08 04:38:57 PM PDT 24
Peak memory 199688 kb
Host smart-340deb17-b698-4cd2-b7e9-467883b396bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3507078536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3507078536
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3027050146
Short name T424
Test name
Test status
Simulation time 1413687703 ps
CPU time 2.79 seconds
Started Aug 08 04:36:09 PM PDT 24
Finished Aug 08 04:36:12 PM PDT 24
Peak memory 195264 kb
Host smart-224a380e-a2f3-4b0f-b73a-7fb69c830187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027050146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3027050146
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.2863911623
Short name T800
Test name
Test status
Simulation time 52257582484 ps
CPU time 44.74 seconds
Started Aug 08 04:36:05 PM PDT 24
Finished Aug 08 04:36:50 PM PDT 24
Peak memory 199968 kb
Host smart-16f2a929-3e4f-4ffd-ba35-9f3a40decf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863911623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2863911623
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.3629298879
Short name T803
Test name
Test status
Simulation time 14381578740 ps
CPU time 268.24 seconds
Started Aug 08 04:36:05 PM PDT 24
Finished Aug 08 04:40:33 PM PDT 24
Peak memory 199780 kb
Host smart-0225342f-138a-4307-80dc-284a0561ee81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3629298879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3629298879
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.896176779
Short name T390
Test name
Test status
Simulation time 1711383473 ps
CPU time 1.97 seconds
Started Aug 08 04:36:07 PM PDT 24
Finished Aug 08 04:36:09 PM PDT 24
Peak memory 197796 kb
Host smart-dc433953-2894-475a-866b-e6475f64bab3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896176779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.896176779
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1198249362
Short name T264
Test name
Test status
Simulation time 79408006378 ps
CPU time 136.06 seconds
Started Aug 08 04:36:07 PM PDT 24
Finished Aug 08 04:38:23 PM PDT 24
Peak memory 199660 kb
Host smart-d5cf9f30-5619-4bec-adfb-b8e503f6b092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198249362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1198249362
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1054419129
Short name T470
Test name
Test status
Simulation time 32151504881 ps
CPU time 44.4 seconds
Started Aug 08 04:36:08 PM PDT 24
Finished Aug 08 04:36:52 PM PDT 24
Peak memory 196116 kb
Host smart-52948b5c-ca69-45e1-9fe5-422c590dcc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054419129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1054419129
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.2875228605
Short name T862
Test name
Test status
Simulation time 855601658 ps
CPU time 2.44 seconds
Started Aug 08 04:35:56 PM PDT 24
Finished Aug 08 04:35:58 PM PDT 24
Peak memory 198128 kb
Host smart-2bca078d-b8b6-49c7-adcc-6afb0bf14f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875228605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2875228605
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.665994403
Short name T488
Test name
Test status
Simulation time 136718927447 ps
CPU time 269.57 seconds
Started Aug 08 04:36:06 PM PDT 24
Finished Aug 08 04:40:35 PM PDT 24
Peak memory 215500 kb
Host smart-7c13d8fb-d815-4702-b0d3-b8c78a5d6264
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665994403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.665994403
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3374553276
Short name T1084
Test name
Test status
Simulation time 15970923904 ps
CPU time 248.5 seconds
Started Aug 08 04:36:16 PM PDT 24
Finished Aug 08 04:40:24 PM PDT 24
Peak memory 215440 kb
Host smart-430b3bba-4ad8-4d05-a190-f7c82c80ce7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374553276 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3374553276
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2135408729
Short name T396
Test name
Test status
Simulation time 2725644279 ps
CPU time 2.33 seconds
Started Aug 08 04:36:05 PM PDT 24
Finished Aug 08 04:36:08 PM PDT 24
Peak memory 198716 kb
Host smart-08e4afec-2ff7-40d6-aefd-513d64789015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135408729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2135408729
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.829450877
Short name T813
Test name
Test status
Simulation time 82572605776 ps
CPU time 41.04 seconds
Started Aug 08 04:35:59 PM PDT 24
Finished Aug 08 04:36:40 PM PDT 24
Peak memory 199772 kb
Host smart-192a98c4-9649-45c2-9145-634768ca1efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829450877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.829450877
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.345784613
Short name T741
Test name
Test status
Simulation time 13717599 ps
CPU time 0.58 seconds
Started Aug 08 04:36:18 PM PDT 24
Finished Aug 08 04:36:19 PM PDT 24
Peak memory 195428 kb
Host smart-f45a73a1-9f97-4be9-a93c-c3ddac044820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345784613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.345784613
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.3143338838
Short name T638
Test name
Test status
Simulation time 135012231389 ps
CPU time 104.17 seconds
Started Aug 08 04:36:13 PM PDT 24
Finished Aug 08 04:37:58 PM PDT 24
Peak memory 199768 kb
Host smart-53be3c0f-e6ef-4b55-ae72-da380d763fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143338838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3143338838
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2182046989
Short name T1145
Test name
Test status
Simulation time 4962918300 ps
CPU time 9.1 seconds
Started Aug 08 04:36:14 PM PDT 24
Finished Aug 08 04:36:23 PM PDT 24
Peak memory 199856 kb
Host smart-c58a9d5d-4414-49ef-a5bf-d59f9f8c469d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182046989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2182046989
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1728171494
Short name T503
Test name
Test status
Simulation time 145456617131 ps
CPU time 108.85 seconds
Started Aug 08 04:36:19 PM PDT 24
Finished Aug 08 04:38:08 PM PDT 24
Peak memory 199224 kb
Host smart-160b8b1e-f2e7-4f49-b4c1-7492ddda62f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728171494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1728171494
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3670553748
Short name T502
Test name
Test status
Simulation time 5819048505 ps
CPU time 2.94 seconds
Started Aug 08 04:36:18 PM PDT 24
Finished Aug 08 04:36:21 PM PDT 24
Peak memory 196608 kb
Host smart-1449055e-756c-4bab-937b-ad62daed54e6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670553748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3670553748
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1401844872
Short name T325
Test name
Test status
Simulation time 94542491955 ps
CPU time 486.19 seconds
Started Aug 08 04:36:16 PM PDT 24
Finished Aug 08 04:44:22 PM PDT 24
Peak memory 199764 kb
Host smart-b981e1a9-2afa-4444-9ca5-cb91f4a4f6a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401844872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1401844872
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.674801677
Short name T888
Test name
Test status
Simulation time 8457078553 ps
CPU time 5.03 seconds
Started Aug 08 04:36:24 PM PDT 24
Finished Aug 08 04:36:29 PM PDT 24
Peak memory 198504 kb
Host smart-cc02762f-99da-4899-aa39-cfdf439764b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674801677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.674801677
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.3201378453
Short name T908
Test name
Test status
Simulation time 9258385798 ps
CPU time 16.03 seconds
Started Aug 08 04:36:14 PM PDT 24
Finished Aug 08 04:36:30 PM PDT 24
Peak memory 197144 kb
Host smart-55e6faa4-ee03-4a5e-ba82-011d6d07ccb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201378453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3201378453
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2564686292
Short name T1085
Test name
Test status
Simulation time 7266733755 ps
CPU time 74.74 seconds
Started Aug 08 04:36:14 PM PDT 24
Finished Aug 08 04:37:28 PM PDT 24
Peak memory 199636 kb
Host smart-f52771b3-f22a-479e-a769-8e4f2b1ab203
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2564686292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2564686292
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.4110264115
Short name T1131
Test name
Test status
Simulation time 1615534168 ps
CPU time 2.9 seconds
Started Aug 08 04:36:18 PM PDT 24
Finished Aug 08 04:36:21 PM PDT 24
Peak memory 197600 kb
Host smart-8712aa17-31f6-4f53-a0e8-d51e19690d10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4110264115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.4110264115
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.178076547
Short name T555
Test name
Test status
Simulation time 18865819307 ps
CPU time 7.74 seconds
Started Aug 08 04:36:15 PM PDT 24
Finished Aug 08 04:36:23 PM PDT 24
Peak memory 199784 kb
Host smart-6f7d2f99-ed30-445a-8534-e1e9835009b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178076547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.178076547
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.878279847
Short name T530
Test name
Test status
Simulation time 40624513255 ps
CPU time 13.23 seconds
Started Aug 08 04:36:15 PM PDT 24
Finished Aug 08 04:36:28 PM PDT 24
Peak memory 195800 kb
Host smart-456afb8f-b741-40f3-90a3-bf15a4d755b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878279847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.878279847
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.754919412
Short name T572
Test name
Test status
Simulation time 297021667 ps
CPU time 1.21 seconds
Started Aug 08 04:36:07 PM PDT 24
Finished Aug 08 04:36:08 PM PDT 24
Peak memory 198224 kb
Host smart-2d8602a5-ae8d-4829-ab17-896e71f726e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754919412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.754919412
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.1483464577
Short name T1059
Test name
Test status
Simulation time 120633220782 ps
CPU time 807.24 seconds
Started Aug 08 04:36:14 PM PDT 24
Finished Aug 08 04:49:41 PM PDT 24
Peak memory 199688 kb
Host smart-1b854ad5-30e9-4c25-b5c4-d771d4138c5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483464577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1483464577
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.558646450
Short name T52
Test name
Test status
Simulation time 127035467319 ps
CPU time 338.65 seconds
Started Aug 08 04:36:13 PM PDT 24
Finished Aug 08 04:41:51 PM PDT 24
Peak memory 216364 kb
Host smart-b697ef5d-6b99-4145-a078-3bb2c2b748a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558646450 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.558646450
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2199159926
Short name T1113
Test name
Test status
Simulation time 639681099 ps
CPU time 2.11 seconds
Started Aug 08 04:36:15 PM PDT 24
Finished Aug 08 04:36:17 PM PDT 24
Peak memory 198004 kb
Host smart-abb0a60f-bffa-494c-9165-9b8f6f61beb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199159926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2199159926
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2316318036
Short name T262
Test name
Test status
Simulation time 62974144263 ps
CPU time 41.69 seconds
Started Aug 08 04:36:05 PM PDT 24
Finished Aug 08 04:36:47 PM PDT 24
Peak memory 199760 kb
Host smart-45b0af91-dae3-4d43-91ab-b7e9c333ddb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316318036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2316318036
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2977165383
Short name T1121
Test name
Test status
Simulation time 39998292 ps
CPU time 0.54 seconds
Started Aug 08 04:36:23 PM PDT 24
Finished Aug 08 04:36:24 PM PDT 24
Peak memory 195244 kb
Host smart-e97c88e8-f5fa-4469-962b-e2bd946c1611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977165383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2977165383
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.325634006
Short name T257
Test name
Test status
Simulation time 24391829502 ps
CPU time 33.8 seconds
Started Aug 08 04:36:17 PM PDT 24
Finished Aug 08 04:36:51 PM PDT 24
Peak memory 199824 kb
Host smart-bba338df-e12b-42ac-8b1a-de62b87bbd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325634006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.325634006
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.969379328
Short name T135
Test name
Test status
Simulation time 47741311302 ps
CPU time 70.99 seconds
Started Aug 08 04:36:23 PM PDT 24
Finished Aug 08 04:37:35 PM PDT 24
Peak memory 199716 kb
Host smart-44e134f2-beb8-40be-ad50-2747c5ccfa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969379328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.969379328
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.642181470
Short name T253
Test name
Test status
Simulation time 51872701732 ps
CPU time 210.98 seconds
Started Aug 08 04:36:15 PM PDT 24
Finished Aug 08 04:39:46 PM PDT 24
Peak memory 199792 kb
Host smart-8d2bbc1c-5c27-4bdf-bb98-14814e374f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642181470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.642181470
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3996860349
Short name T531
Test name
Test status
Simulation time 9769157511 ps
CPU time 5.48 seconds
Started Aug 08 04:36:14 PM PDT 24
Finished Aug 08 04:36:20 PM PDT 24
Peak memory 199136 kb
Host smart-82014e5f-522b-44fa-8ecc-c751efef07c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996860349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3996860349
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3557308783
Short name T1024
Test name
Test status
Simulation time 303011353047 ps
CPU time 378.98 seconds
Started Aug 08 04:36:23 PM PDT 24
Finished Aug 08 04:42:42 PM PDT 24
Peak memory 199784 kb
Host smart-28641aed-cf71-434f-bfb0-9d6e64a10987
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3557308783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3557308783
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3664077106
Short name T528
Test name
Test status
Simulation time 5926834445 ps
CPU time 7.27 seconds
Started Aug 08 04:36:26 PM PDT 24
Finished Aug 08 04:36:34 PM PDT 24
Peak memory 198640 kb
Host smart-ea8f0e46-07c2-42fc-9cfc-8ce5074c47d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664077106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3664077106
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3591956332
Short name T931
Test name
Test status
Simulation time 90659186722 ps
CPU time 20.69 seconds
Started Aug 08 04:36:13 PM PDT 24
Finished Aug 08 04:36:34 PM PDT 24
Peak memory 199924 kb
Host smart-3469e1f9-e591-454d-9c4d-c0ad7b3ced89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591956332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3591956332
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.817431639
Short name T402
Test name
Test status
Simulation time 19967138222 ps
CPU time 520.76 seconds
Started Aug 08 04:36:25 PM PDT 24
Finished Aug 08 04:45:06 PM PDT 24
Peak memory 199772 kb
Host smart-348246b5-fef7-4b9d-ab13-e17c0c136bc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=817431639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.817431639
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2217626573
Short name T446
Test name
Test status
Simulation time 6747684373 ps
CPU time 55.85 seconds
Started Aug 08 04:36:14 PM PDT 24
Finished Aug 08 04:37:10 PM PDT 24
Peak memory 197944 kb
Host smart-8745fcb8-ef48-4552-8219-7cd2076836e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2217626573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2217626573
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1357647579
Short name T915
Test name
Test status
Simulation time 25125402557 ps
CPU time 42.67 seconds
Started Aug 08 04:36:18 PM PDT 24
Finished Aug 08 04:37:00 PM PDT 24
Peak memory 199768 kb
Host smart-9993eceb-1e9e-4576-b63f-f34c95771c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357647579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1357647579
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.611730285
Short name T272
Test name
Test status
Simulation time 2104349209 ps
CPU time 2.74 seconds
Started Aug 08 04:36:16 PM PDT 24
Finished Aug 08 04:36:19 PM PDT 24
Peak memory 195324 kb
Host smart-6bc3ab72-a26e-4161-ba65-7b1e0627602c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611730285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.611730285
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.570844835
Short name T32
Test name
Test status
Simulation time 298180798 ps
CPU time 1.61 seconds
Started Aug 08 04:36:16 PM PDT 24
Finished Aug 08 04:36:17 PM PDT 24
Peak memory 198108 kb
Host smart-f4abdccb-3400-4ff7-8fa1-4982caf78fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570844835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.570844835
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1825827083
Short name T99
Test name
Test status
Simulation time 261298493322 ps
CPU time 541.89 seconds
Started Aug 08 04:36:24 PM PDT 24
Finished Aug 08 04:45:26 PM PDT 24
Peak memory 199796 kb
Host smart-2feb5f70-5e5d-4291-99be-c468b3cbf657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825827083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1825827083
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3325466209
Short name T614
Test name
Test status
Simulation time 108253811187 ps
CPU time 872.82 seconds
Started Aug 08 04:36:27 PM PDT 24
Finished Aug 08 04:51:00 PM PDT 24
Peak memory 216324 kb
Host smart-48738915-7326-4067-8e3c-e9aa081a89e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325466209 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3325466209
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1732878485
Short name T475
Test name
Test status
Simulation time 1868508522 ps
CPU time 1.34 seconds
Started Aug 08 04:36:18 PM PDT 24
Finished Aug 08 04:36:19 PM PDT 24
Peak memory 196708 kb
Host smart-0a628f16-b8bc-4ff6-95cf-5dba266534b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732878485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1732878485
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1545294311
Short name T1151
Test name
Test status
Simulation time 14051854630 ps
CPU time 17.5 seconds
Started Aug 08 04:36:14 PM PDT 24
Finished Aug 08 04:36:32 PM PDT 24
Peak memory 198752 kb
Host smart-91a949b2-7f89-4464-a128-5ed270ce5f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545294311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1545294311
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2692021767
Short name T86
Test name
Test status
Simulation time 36972668 ps
CPU time 0.52 seconds
Started Aug 08 04:36:34 PM PDT 24
Finished Aug 08 04:36:35 PM PDT 24
Peak memory 194240 kb
Host smart-714e4789-2678-4d4e-8956-2bf4cd51d134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692021767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2692021767
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1209091897
Short name T793
Test name
Test status
Simulation time 28926572836 ps
CPU time 19.04 seconds
Started Aug 08 04:37:37 PM PDT 24
Finished Aug 08 04:37:56 PM PDT 24
Peak memory 198372 kb
Host smart-c4b4f08d-45e3-4584-a554-c27c78b22df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209091897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1209091897
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3019276581
Short name T1141
Test name
Test status
Simulation time 26782566360 ps
CPU time 37.82 seconds
Started Aug 08 04:37:51 PM PDT 24
Finished Aug 08 04:38:29 PM PDT 24
Peak memory 199604 kb
Host smart-67b8f7cb-daf3-4ebe-b387-007340dd3770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019276581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3019276581
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3315302811
Short name T242
Test name
Test status
Simulation time 72550001501 ps
CPU time 19.79 seconds
Started Aug 08 04:36:23 PM PDT 24
Finished Aug 08 04:36:43 PM PDT 24
Peak memory 199808 kb
Host smart-3fdb6861-6dce-48b1-82d1-e150f1a5ec98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315302811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3315302811
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2496707349
Short name T1061
Test name
Test status
Simulation time 3976522623 ps
CPU time 6.25 seconds
Started Aug 08 04:36:24 PM PDT 24
Finished Aug 08 04:36:31 PM PDT 24
Peak memory 196364 kb
Host smart-55b73d6d-a8bc-4104-bf97-b6c613ac4ea3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496707349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2496707349
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.296124694
Short name T381
Test name
Test status
Simulation time 120227795654 ps
CPU time 217.24 seconds
Started Aug 08 04:37:37 PM PDT 24
Finished Aug 08 04:41:14 PM PDT 24
Peak memory 198936 kb
Host smart-f2498b4d-279d-4d62-9219-e03a1ce49852
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=296124694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.296124694
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2921494503
Short name T358
Test name
Test status
Simulation time 1300378041 ps
CPU time 2.77 seconds
Started Aug 08 04:37:37 PM PDT 24
Finished Aug 08 04:37:40 PM PDT 24
Peak memory 195768 kb
Host smart-17f2d5d6-cd3a-4c02-a118-7bcd38f281f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921494503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2921494503
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.3805666455
Short name T1041
Test name
Test status
Simulation time 117071135783 ps
CPU time 94.66 seconds
Started Aug 08 04:36:27 PM PDT 24
Finished Aug 08 04:38:02 PM PDT 24
Peak memory 198644 kb
Host smart-88107321-dc42-47ef-9882-3237f4afdbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805666455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3805666455
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2015741788
Short name T1013
Test name
Test status
Simulation time 9785399607 ps
CPU time 295.31 seconds
Started Aug 08 04:36:27 PM PDT 24
Finished Aug 08 04:41:22 PM PDT 24
Peak memory 198592 kb
Host smart-bbe71be1-8175-4442-adea-9a2a05f44618
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2015741788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2015741788
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2649155009
Short name T49
Test name
Test status
Simulation time 7160849704 ps
CPU time 10.94 seconds
Started Aug 08 04:36:24 PM PDT 24
Finished Aug 08 04:36:35 PM PDT 24
Peak memory 198124 kb
Host smart-a11bbeb2-b3e4-452d-b304-89e43087e314
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2649155009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2649155009
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1463092698
Short name T570
Test name
Test status
Simulation time 61971053733 ps
CPU time 31.03 seconds
Started Aug 08 04:37:51 PM PDT 24
Finished Aug 08 04:38:22 PM PDT 24
Peak memory 199596 kb
Host smart-899bd390-f772-47fe-87bb-ac54feee20f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463092698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1463092698
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2647218497
Short name T875
Test name
Test status
Simulation time 43943729862 ps
CPU time 37.35 seconds
Started Aug 08 04:36:24 PM PDT 24
Finished Aug 08 04:37:01 PM PDT 24
Peak memory 195836 kb
Host smart-61edadc6-74d8-49a2-8531-916bf3ba9d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647218497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2647218497
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2725270802
Short name T990
Test name
Test status
Simulation time 5714125585 ps
CPU time 18.89 seconds
Started Aug 08 04:37:37 PM PDT 24
Finished Aug 08 04:37:56 PM PDT 24
Peak memory 198024 kb
Host smart-9debfb92-651c-4971-ae65-ff3318f7362b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725270802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2725270802
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2098634047
Short name T212
Test name
Test status
Simulation time 400102222251 ps
CPU time 410.13 seconds
Started Aug 08 04:37:37 PM PDT 24
Finished Aug 08 04:44:27 PM PDT 24
Peak memory 197968 kb
Host smart-cd886793-6c24-4a7e-9b4a-55243a64c023
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098634047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2098634047
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2164326087
Short name T546
Test name
Test status
Simulation time 36853652161 ps
CPU time 381.33 seconds
Started Aug 08 04:36:24 PM PDT 24
Finished Aug 08 04:42:45 PM PDT 24
Peak memory 216300 kb
Host smart-a457eea1-540f-4c2f-956f-99c1ecfa6a58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164326087 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2164326087
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.4270123545
Short name T847
Test name
Test status
Simulation time 6629108538 ps
CPU time 47.3 seconds
Started Aug 08 04:37:37 PM PDT 24
Finished Aug 08 04:38:24 PM PDT 24
Peak memory 197548 kb
Host smart-896a713a-5f46-4c2d-89bf-1d1282f50979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270123545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.4270123545
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2639006241
Short name T1073
Test name
Test status
Simulation time 114450010164 ps
CPU time 41.92 seconds
Started Aug 08 04:36:27 PM PDT 24
Finished Aug 08 04:37:09 PM PDT 24
Peak memory 198588 kb
Host smart-311b0f72-f37d-434b-ab06-0e82c7dba402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639006241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2639006241
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.96670198
Short name T357
Test name
Test status
Simulation time 45747662 ps
CPU time 0.56 seconds
Started Aug 08 04:36:32 PM PDT 24
Finished Aug 08 04:36:33 PM PDT 24
Peak memory 195168 kb
Host smart-0bed1e2a-3259-46d9-87e1-8cc04eb6e087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96670198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.96670198
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3127611107
Short name T410
Test name
Test status
Simulation time 29125162735 ps
CPU time 13.22 seconds
Started Aug 08 04:36:40 PM PDT 24
Finished Aug 08 04:36:53 PM PDT 24
Peak memory 199764 kb
Host smart-e13abbc8-40ac-46be-9a34-01e45d987e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127611107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3127611107
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2254906778
Short name T315
Test name
Test status
Simulation time 91899104365 ps
CPU time 62.99 seconds
Started Aug 08 04:36:34 PM PDT 24
Finished Aug 08 04:37:37 PM PDT 24
Peak memory 199868 kb
Host smart-5d7c18d0-446e-42c4-9a2b-a7a0c2814db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254906778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2254906778
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1533734037
Short name T693
Test name
Test status
Simulation time 107628450867 ps
CPU time 152.07 seconds
Started Aug 08 04:37:51 PM PDT 24
Finished Aug 08 04:40:23 PM PDT 24
Peak memory 199632 kb
Host smart-3e9e1e52-79b8-444f-b3e0-1c80a52066bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533734037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1533734037
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3215632280
Short name T1091
Test name
Test status
Simulation time 71772177016 ps
CPU time 138.27 seconds
Started Aug 08 04:37:52 PM PDT 24
Finished Aug 08 04:40:10 PM PDT 24
Peak memory 199720 kb
Host smart-c3f476b1-3cb9-4bce-a3be-1adac08f4782
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215632280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3215632280
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.44362494
Short name T1039
Test name
Test status
Simulation time 65803247163 ps
CPU time 437.74 seconds
Started Aug 08 04:36:36 PM PDT 24
Finished Aug 08 04:43:54 PM PDT 24
Peak memory 199652 kb
Host smart-0dc64ba7-40a5-4398-8cce-d2ad4dc71d3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=44362494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.44362494
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1575181198
Short name T477
Test name
Test status
Simulation time 1126479584 ps
CPU time 2.55 seconds
Started Aug 08 04:36:35 PM PDT 24
Finished Aug 08 04:36:38 PM PDT 24
Peak memory 195292 kb
Host smart-aaca163b-7a63-4c10-a818-8d9b90a0408c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575181198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1575181198
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1833147316
Short name T1010
Test name
Test status
Simulation time 223576442855 ps
CPU time 40.56 seconds
Started Aug 08 04:36:40 PM PDT 24
Finished Aug 08 04:37:21 PM PDT 24
Peak memory 208140 kb
Host smart-14c7b9b6-6da3-405c-bb04-b3fdbff69844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833147316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1833147316
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3231582611
Short name T704
Test name
Test status
Simulation time 13303434324 ps
CPU time 621.84 seconds
Started Aug 08 04:36:40 PM PDT 24
Finished Aug 08 04:47:02 PM PDT 24
Peak memory 199816 kb
Host smart-124aafce-7a83-4272-b843-03f3ac54006d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3231582611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3231582611
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.613080435
Short name T98
Test name
Test status
Simulation time 6706352502 ps
CPU time 26.9 seconds
Started Aug 08 04:36:36 PM PDT 24
Finished Aug 08 04:37:03 PM PDT 24
Peak memory 198772 kb
Host smart-a84b9667-bbf1-4f8e-b229-74d799cf675d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=613080435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.613080435
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.469753568
Short name T972
Test name
Test status
Simulation time 64994156092 ps
CPU time 35.38 seconds
Started Aug 08 04:36:34 PM PDT 24
Finished Aug 08 04:37:10 PM PDT 24
Peak memory 199796 kb
Host smart-4fbc54d2-b7a4-4b4c-b73a-235c7c3b975e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469753568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.469753568
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1118488510
Short name T607
Test name
Test status
Simulation time 3170880057 ps
CPU time 2.07 seconds
Started Aug 08 04:36:35 PM PDT 24
Finished Aug 08 04:36:37 PM PDT 24
Peak memory 195820 kb
Host smart-c79770db-dfc7-4d08-9d58-77225a77ee61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118488510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1118488510
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2898094419
Short name T1069
Test name
Test status
Simulation time 6089912612 ps
CPU time 7.23 seconds
Started Aug 08 04:36:34 PM PDT 24
Finished Aug 08 04:36:41 PM PDT 24
Peak memory 199052 kb
Host smart-14e7ad0c-0484-4ac4-b3cd-0523ec40c79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898094419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2898094419
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.3787013649
Short name T203
Test name
Test status
Simulation time 218809777545 ps
CPU time 314.81 seconds
Started Aug 08 04:36:35 PM PDT 24
Finished Aug 08 04:41:50 PM PDT 24
Peak memory 208084 kb
Host smart-08d77e3e-d578-46f3-a89a-bf4baa295fad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787013649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3787013649
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1280436166
Short name T508
Test name
Test status
Simulation time 122136272900 ps
CPU time 748.61 seconds
Started Aug 08 04:36:34 PM PDT 24
Finished Aug 08 04:49:03 PM PDT 24
Peak memory 210844 kb
Host smart-4b7f8852-ee68-4c27-900f-f31fcc2493e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280436166 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1280436166
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2787976733
Short name T1101
Test name
Test status
Simulation time 1405185479 ps
CPU time 2.42 seconds
Started Aug 08 04:36:34 PM PDT 24
Finished Aug 08 04:36:37 PM PDT 24
Peak memory 198652 kb
Host smart-b034af9d-30da-4457-805b-2dd90ca8e980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787976733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2787976733
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.780783515
Short name T468
Test name
Test status
Simulation time 115842423776 ps
CPU time 60.16 seconds
Started Aug 08 04:36:34 PM PDT 24
Finished Aug 08 04:37:34 PM PDT 24
Peak memory 199828 kb
Host smart-0592c414-e566-46ff-9304-8d31a5f33007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780783515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.780783515
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.2163960278
Short name T21
Test name
Test status
Simulation time 40210560 ps
CPU time 0.59 seconds
Started Aug 08 04:36:58 PM PDT 24
Finished Aug 08 04:36:59 PM PDT 24
Peak memory 195552 kb
Host smart-82634ebf-4e00-4c8d-a5fa-1c76cd68294d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163960278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2163960278
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.1494273118
Short name T1149
Test name
Test status
Simulation time 18383432829 ps
CPU time 12.86 seconds
Started Aug 08 04:36:44 PM PDT 24
Finished Aug 08 04:36:57 PM PDT 24
Peak memory 198608 kb
Host smart-637f095b-6cb7-4626-b6ae-96c1c79855d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494273118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1494273118
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.799022081
Short name T397
Test name
Test status
Simulation time 41333004706 ps
CPU time 79.58 seconds
Started Aug 08 04:36:46 PM PDT 24
Finished Aug 08 04:38:06 PM PDT 24
Peak memory 199840 kb
Host smart-3d5d0eaa-e21e-429e-a2d2-2efe064678c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799022081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.799022081
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2409646743
Short name T178
Test name
Test status
Simulation time 19473903522 ps
CPU time 31.68 seconds
Started Aug 08 04:36:45 PM PDT 24
Finished Aug 08 04:37:16 PM PDT 24
Peak memory 199680 kb
Host smart-868cf8e5-7ac5-4888-8170-691f263e4ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409646743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2409646743
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1159161043
Short name T894
Test name
Test status
Simulation time 63440499455 ps
CPU time 92.79 seconds
Started Aug 08 04:36:46 PM PDT 24
Finished Aug 08 04:38:19 PM PDT 24
Peak memory 199792 kb
Host smart-dfed0cd8-015f-4196-99d7-986ecc90661e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159161043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1159161043
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3828667309
Short name T650
Test name
Test status
Simulation time 82480950586 ps
CPU time 477.44 seconds
Started Aug 08 04:36:44 PM PDT 24
Finished Aug 08 04:44:42 PM PDT 24
Peak memory 199700 kb
Host smart-483d02c7-f714-493e-9456-bd9c6ea6029e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828667309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3828667309
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2915012646
Short name T443
Test name
Test status
Simulation time 3199296762 ps
CPU time 4.42 seconds
Started Aug 08 04:36:44 PM PDT 24
Finished Aug 08 04:36:49 PM PDT 24
Peak memory 199048 kb
Host smart-6f141ed2-a27d-4a8c-a0fd-813b1b62448c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915012646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2915012646
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1120702766
Short name T669
Test name
Test status
Simulation time 116730837140 ps
CPU time 333.31 seconds
Started Aug 08 04:37:51 PM PDT 24
Finished Aug 08 04:43:25 PM PDT 24
Peak memory 207972 kb
Host smart-5b29d4e9-a6bc-4a92-943a-3fce084c57b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120702766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1120702766
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2641159053
Short name T620
Test name
Test status
Simulation time 13729598983 ps
CPU time 720.99 seconds
Started Aug 08 04:36:45 PM PDT 24
Finished Aug 08 04:48:46 PM PDT 24
Peak memory 199804 kb
Host smart-163a0b5c-ecc9-4488-8b70-89d1558fce74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2641159053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2641159053
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.7418148
Short name T17
Test name
Test status
Simulation time 4507998734 ps
CPU time 33.54 seconds
Started Aug 08 04:36:44 PM PDT 24
Finished Aug 08 04:37:17 PM PDT 24
Peak memory 199756 kb
Host smart-de67c84a-b360-4b6f-b3b5-77c5a4cd022f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=7418148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.7418148
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2754748347
Short name T625
Test name
Test status
Simulation time 34553095231 ps
CPU time 60.05 seconds
Started Aug 08 04:36:46 PM PDT 24
Finished Aug 08 04:37:46 PM PDT 24
Peak memory 199732 kb
Host smart-f3d890c0-96fb-45f8-872f-1d6d15b0032a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754748347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2754748347
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.4174416415
Short name T818
Test name
Test status
Simulation time 2711042394 ps
CPU time 2.32 seconds
Started Aug 08 04:36:46 PM PDT 24
Finished Aug 08 04:36:49 PM PDT 24
Peak memory 196340 kb
Host smart-aece9699-cf7e-403e-98bc-938870a8ce20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174416415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.4174416415
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2300269718
Short name T1163
Test name
Test status
Simulation time 931758350 ps
CPU time 2.89 seconds
Started Aug 08 04:36:47 PM PDT 24
Finished Aug 08 04:36:50 PM PDT 24
Peak memory 197996 kb
Host smart-1d974d3d-7edd-4d43-8193-6159b0d913f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300269718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2300269718
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3862957544
Short name T789
Test name
Test status
Simulation time 222730187686 ps
CPU time 632.77 seconds
Started Aug 08 04:36:58 PM PDT 24
Finished Aug 08 04:47:31 PM PDT 24
Peak memory 199776 kb
Host smart-139e9f3e-02a7-4c0a-9245-7afb8aacc089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862957544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3862957544
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1487564887
Short name T28
Test name
Test status
Simulation time 18853965506 ps
CPU time 252.27 seconds
Started Aug 08 04:36:58 PM PDT 24
Finished Aug 08 04:41:11 PM PDT 24
Peak memory 215516 kb
Host smart-d408f1e2-5d97-44ce-aebe-0a06d6c8de9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487564887 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1487564887
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3284146786
Short name T1002
Test name
Test status
Simulation time 8331787564 ps
CPU time 10.82 seconds
Started Aug 08 04:36:45 PM PDT 24
Finished Aug 08 04:36:56 PM PDT 24
Peak memory 199660 kb
Host smart-a9f83838-58a9-4d37-bc4a-fb5034138529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284146786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3284146786
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2562342250
Short name T1126
Test name
Test status
Simulation time 71415853718 ps
CPU time 59.01 seconds
Started Aug 08 04:36:44 PM PDT 24
Finished Aug 08 04:37:43 PM PDT 24
Peak memory 199820 kb
Host smart-28d26eea-806b-4dd5-8c19-e04f3ac26e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562342250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2562342250
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.925928053
Short name T347
Test name
Test status
Simulation time 31537205 ps
CPU time 0.57 seconds
Started Aug 08 04:36:56 PM PDT 24
Finished Aug 08 04:36:56 PM PDT 24
Peak memory 195444 kb
Host smart-df177524-8fce-4d66-9508-e1755b6c657a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925928053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.925928053
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.66253007
Short name T114
Test name
Test status
Simulation time 46388712194 ps
CPU time 89.67 seconds
Started Aug 08 04:36:56 PM PDT 24
Finished Aug 08 04:38:26 PM PDT 24
Peak memory 199792 kb
Host smart-c26f4226-bb91-4862-b164-a74a56ec2049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66253007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.66253007
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1650814253
Short name T582
Test name
Test status
Simulation time 27608063538 ps
CPU time 44.07 seconds
Started Aug 08 04:36:55 PM PDT 24
Finished Aug 08 04:37:39 PM PDT 24
Peak memory 199752 kb
Host smart-70b88b41-318a-4db8-86a8-f2ebb8f5af53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650814253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1650814253
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.4275681754
Short name T794
Test name
Test status
Simulation time 87108680236 ps
CPU time 31.43 seconds
Started Aug 08 04:36:56 PM PDT 24
Finished Aug 08 04:37:28 PM PDT 24
Peak memory 199456 kb
Host smart-7211d538-9368-424e-aa18-10d2d8332f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275681754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.4275681754
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.1666943026
Short name T1102
Test name
Test status
Simulation time 282619723269 ps
CPU time 448.82 seconds
Started Aug 08 04:38:19 PM PDT 24
Finished Aug 08 04:45:48 PM PDT 24
Peak memory 197384 kb
Host smart-4b92bdb8-680c-42dd-bdc7-d9b8db2faffa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666943026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1666943026
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3493259759
Short name T557
Test name
Test status
Simulation time 99758381881 ps
CPU time 845.76 seconds
Started Aug 08 04:36:56 PM PDT 24
Finished Aug 08 04:51:02 PM PDT 24
Peak memory 199940 kb
Host smart-031ba02d-bdd7-40b8-b814-aa0a86958f45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3493259759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3493259759
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.4088917049
Short name T701
Test name
Test status
Simulation time 8442244220 ps
CPU time 9.84 seconds
Started Aug 08 04:36:57 PM PDT 24
Finished Aug 08 04:37:07 PM PDT 24
Peak memory 199700 kb
Host smart-0df9816b-733d-4c44-8084-e49cdb0da6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088917049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.4088917049
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.2575848698
Short name T568
Test name
Test status
Simulation time 82116470332 ps
CPU time 20.65 seconds
Started Aug 08 04:38:20 PM PDT 24
Finished Aug 08 04:38:41 PM PDT 24
Peak memory 199952 kb
Host smart-c638d48a-6cc7-4ee7-a66d-2bef2f0bf60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575848698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2575848698
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.4006625017
Short name T811
Test name
Test status
Simulation time 16592870403 ps
CPU time 811.11 seconds
Started Aug 08 04:36:56 PM PDT 24
Finished Aug 08 04:50:28 PM PDT 24
Peak memory 198588 kb
Host smart-227cadcf-ed6f-41eb-a80d-298ec8c66c71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006625017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.4006625017
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.57547094
Short name T635
Test name
Test status
Simulation time 5397409028 ps
CPU time 14.74 seconds
Started Aug 08 04:36:56 PM PDT 24
Finished Aug 08 04:37:11 PM PDT 24
Peak memory 199048 kb
Host smart-4d1f9bae-82b6-48b2-bca6-afc6f49725c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57547094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.57547094
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.4167302177
Short name T747
Test name
Test status
Simulation time 37097546541 ps
CPU time 68.85 seconds
Started Aug 08 04:38:19 PM PDT 24
Finished Aug 08 04:39:28 PM PDT 24
Peak memory 199496 kb
Host smart-1e79160b-4452-49f3-83cd-db32df089943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167302177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.4167302177
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3356628967
Short name T698
Test name
Test status
Simulation time 1661296480 ps
CPU time 1.87 seconds
Started Aug 08 04:38:19 PM PDT 24
Finished Aug 08 04:38:21 PM PDT 24
Peak memory 195020 kb
Host smart-84a3437e-d700-4a16-8614-229e4ed0ac02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356628967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3356628967
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1510209449
Short name T996
Test name
Test status
Simulation time 489328300 ps
CPU time 2.44 seconds
Started Aug 08 04:36:54 PM PDT 24
Finished Aug 08 04:36:56 PM PDT 24
Peak memory 198352 kb
Host smart-3643eafe-a753-4c4c-9ed3-e158eba97f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510209449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1510209449
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.468337067
Short name T690
Test name
Test status
Simulation time 70965130460 ps
CPU time 101.5 seconds
Started Aug 08 04:38:22 PM PDT 24
Finished Aug 08 04:40:03 PM PDT 24
Peak memory 199712 kb
Host smart-96bd6154-0ce4-48ed-9d44-3d2dc4c11c1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468337067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.468337067
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2877753237
Short name T442
Test name
Test status
Simulation time 1877722275 ps
CPU time 1.87 seconds
Started Aug 08 04:36:56 PM PDT 24
Finished Aug 08 04:36:58 PM PDT 24
Peak memory 198556 kb
Host smart-118bb210-00fa-4111-8d76-7f149617e901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877753237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2877753237
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.202252026
Short name T1088
Test name
Test status
Simulation time 24858107135 ps
CPU time 22.56 seconds
Started Aug 08 04:36:56 PM PDT 24
Finished Aug 08 04:37:18 PM PDT 24
Peak memory 199688 kb
Host smart-e3f72c27-6e95-4c32-a618-c0ee71c2bacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202252026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.202252026
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2322420676
Short name T554
Test name
Test status
Simulation time 41296017 ps
CPU time 0.54 seconds
Started Aug 08 04:37:07 PM PDT 24
Finished Aug 08 04:37:07 PM PDT 24
Peak memory 195188 kb
Host smart-b5c2fcbb-c0b2-409a-bfe4-52b7a1448019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322420676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2322420676
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.940205603
Short name T654
Test name
Test status
Simulation time 14656386741 ps
CPU time 27.63 seconds
Started Aug 08 04:38:09 PM PDT 24
Finished Aug 08 04:38:37 PM PDT 24
Peak memory 198948 kb
Host smart-a953cc31-9234-4728-badd-189fd776adcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940205603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.940205603
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3003157101
Short name T1115
Test name
Test status
Simulation time 184936677737 ps
CPU time 282.8 seconds
Started Aug 08 04:36:57 PM PDT 24
Finished Aug 08 04:41:40 PM PDT 24
Peak memory 199828 kb
Host smart-ece5b86a-25ec-44a4-89dd-3d2cca971896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003157101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3003157101
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1079554315
Short name T129
Test name
Test status
Simulation time 249687835402 ps
CPU time 172.7 seconds
Started Aug 08 04:36:55 PM PDT 24
Finished Aug 08 04:39:48 PM PDT 24
Peak memory 199756 kb
Host smart-a18ccdb0-e7c5-44e2-834f-40203621b20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079554315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1079554315
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3128637800
Short name T368
Test name
Test status
Simulation time 33154406964 ps
CPU time 8.58 seconds
Started Aug 08 04:36:55 PM PDT 24
Finished Aug 08 04:37:04 PM PDT 24
Peak memory 199088 kb
Host smart-da4c46cb-3c8f-4113-be1f-06c78db3ad01
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128637800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3128637800
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3903550187
Short name T978
Test name
Test status
Simulation time 142051769636 ps
CPU time 1106.19 seconds
Started Aug 08 04:37:05 PM PDT 24
Finished Aug 08 04:55:31 PM PDT 24
Peak memory 199824 kb
Host smart-1b782efe-4b9d-440a-8303-080eb56d3a58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3903550187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3903550187
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.758126128
Short name T536
Test name
Test status
Simulation time 7186041290 ps
CPU time 9.07 seconds
Started Aug 08 04:37:10 PM PDT 24
Finished Aug 08 04:37:19 PM PDT 24
Peak memory 198644 kb
Host smart-f3568b63-dd6f-4449-a8e7-5ec7813154c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758126128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.758126128
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.56813227
Short name T767
Test name
Test status
Simulation time 143260799613 ps
CPU time 51.27 seconds
Started Aug 08 04:38:19 PM PDT 24
Finished Aug 08 04:39:10 PM PDT 24
Peak memory 199036 kb
Host smart-0df75a06-4637-4ae9-bbbb-4fc18757a2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56813227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.56813227
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1734359014
Short name T496
Test name
Test status
Simulation time 10077909116 ps
CPU time 532.18 seconds
Started Aug 08 04:37:06 PM PDT 24
Finished Aug 08 04:45:58 PM PDT 24
Peak memory 199708 kb
Host smart-a09412fa-0c5c-4f0b-9af8-26d0932f4e0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1734359014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1734359014
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3247090363
Short name T1133
Test name
Test status
Simulation time 3381345678 ps
CPU time 23.69 seconds
Started Aug 08 04:36:59 PM PDT 24
Finished Aug 08 04:37:22 PM PDT 24
Peak memory 198860 kb
Host smart-d3007f32-a3ff-4b85-a823-22724bdcc1ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3247090363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3247090363
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.851797872
Short name T321
Test name
Test status
Simulation time 73211846801 ps
CPU time 71.46 seconds
Started Aug 08 04:37:05 PM PDT 24
Finished Aug 08 04:38:17 PM PDT 24
Peak memory 199516 kb
Host smart-9984e85b-d1bf-45b6-b887-4e119b77e1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851797872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.851797872
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1178643598
Short name T377
Test name
Test status
Simulation time 5011194408 ps
CPU time 7.24 seconds
Started Aug 08 04:37:11 PM PDT 24
Finished Aug 08 04:37:18 PM PDT 24
Peak memory 196096 kb
Host smart-95422867-2e2a-416f-b43f-405bbcacee26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178643598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1178643598
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1241527498
Short name T375
Test name
Test status
Simulation time 248026635 ps
CPU time 1.34 seconds
Started Aug 08 04:38:19 PM PDT 24
Finished Aug 08 04:38:20 PM PDT 24
Peak memory 199080 kb
Host smart-e0b625b7-dac6-4aa3-813b-ac89189e5fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241527498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1241527498
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.355310227
Short name T903
Test name
Test status
Simulation time 498440782321 ps
CPU time 508.17 seconds
Started Aug 08 04:37:05 PM PDT 24
Finished Aug 08 04:45:33 PM PDT 24
Peak memory 199692 kb
Host smart-70972c30-c929-41ee-a1a9-5c3b46a1c7b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355310227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.355310227
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3232027782
Short name T787
Test name
Test status
Simulation time 235672221217 ps
CPU time 469.67 seconds
Started Aug 08 04:37:07 PM PDT 24
Finished Aug 08 04:44:56 PM PDT 24
Peak memory 216496 kb
Host smart-6bbf36e6-6084-426b-99b0-ebe61eb225b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232027782 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3232027782
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1049814756
Short name T832
Test name
Test status
Simulation time 7168704121 ps
CPU time 11.52 seconds
Started Aug 08 04:37:05 PM PDT 24
Finished Aug 08 04:37:16 PM PDT 24
Peak memory 199828 kb
Host smart-8afb772a-ce48-44e4-ad21-91ef5cc103ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049814756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1049814756
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1545299997
Short name T924
Test name
Test status
Simulation time 109534439881 ps
CPU time 40.61 seconds
Started Aug 08 04:36:56 PM PDT 24
Finished Aug 08 04:37:37 PM PDT 24
Peak memory 199748 kb
Host smart-c6202462-bab6-47e7-95d4-a0191bc8a55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545299997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1545299997
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3302548348
Short name T1165
Test name
Test status
Simulation time 11305817 ps
CPU time 0.54 seconds
Started Aug 08 04:32:23 PM PDT 24
Finished Aug 08 04:32:24 PM PDT 24
Peak memory 194124 kb
Host smart-9187fc91-0c3a-40dc-8846-92e531c09ab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302548348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3302548348
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2500556006
Short name T1007
Test name
Test status
Simulation time 98342884036 ps
CPU time 68.67 seconds
Started Aug 08 04:32:22 PM PDT 24
Finished Aug 08 04:33:31 PM PDT 24
Peak memory 199820 kb
Host smart-87928704-231b-471d-b22e-952b959a5a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500556006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2500556006
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3860055081
Short name T545
Test name
Test status
Simulation time 25001464039 ps
CPU time 28.91 seconds
Started Aug 08 04:32:22 PM PDT 24
Finished Aug 08 04:32:51 PM PDT 24
Peak memory 199800 kb
Host smart-1614c6ae-3a2c-466f-8aca-3f1d856de1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860055081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3860055081
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3261211099
Short name T951
Test name
Test status
Simulation time 165778393478 ps
CPU time 17.42 seconds
Started Aug 08 04:32:22 PM PDT 24
Finished Aug 08 04:32:40 PM PDT 24
Peak memory 199820 kb
Host smart-e705591e-6b9b-4f7d-ad56-3bf8a322ad1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261211099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3261211099
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3076284272
Short name T610
Test name
Test status
Simulation time 5675202653 ps
CPU time 9.27 seconds
Started Aug 08 04:32:21 PM PDT 24
Finished Aug 08 04:32:31 PM PDT 24
Peak memory 195780 kb
Host smart-a2ad40eb-8975-49e7-b3d7-fa41489dcd8e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076284272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3076284272
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.695090505
Short name T1093
Test name
Test status
Simulation time 72620237997 ps
CPU time 771.06 seconds
Started Aug 08 04:32:23 PM PDT 24
Finished Aug 08 04:45:14 PM PDT 24
Peak memory 199752 kb
Host smart-0f68d482-3681-461d-b102-1ed6a5d782aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=695090505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.695090505
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2815808539
Short name T982
Test name
Test status
Simulation time 402271783 ps
CPU time 1.66 seconds
Started Aug 08 04:32:23 PM PDT 24
Finished Aug 08 04:32:25 PM PDT 24
Peak memory 199476 kb
Host smart-7533ebfc-4d24-47a6-b28a-3c2112dd4e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815808539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2815808539
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3059174741
Short name T252
Test name
Test status
Simulation time 179882876066 ps
CPU time 62.53 seconds
Started Aug 08 04:32:22 PM PDT 24
Finished Aug 08 04:33:25 PM PDT 24
Peak memory 199968 kb
Host smart-827551e8-15e2-49d6-80f5-04f44bdb44f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059174741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3059174741
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1068996212
Short name T436
Test name
Test status
Simulation time 6394509077 ps
CPU time 372.17 seconds
Started Aug 08 04:32:22 PM PDT 24
Finished Aug 08 04:38:34 PM PDT 24
Peak memory 199828 kb
Host smart-459b5e80-c8b8-458f-8746-2793404f498e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1068996212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1068996212
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2624608709
Short name T579
Test name
Test status
Simulation time 4202371754 ps
CPU time 29.61 seconds
Started Aug 08 04:32:24 PM PDT 24
Finished Aug 08 04:32:54 PM PDT 24
Peak memory 197788 kb
Host smart-5b5ce52f-b236-409f-9f28-7c54031c2eb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2624608709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2624608709
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.762234908
Short name T947
Test name
Test status
Simulation time 26996505047 ps
CPU time 40.87 seconds
Started Aug 08 04:32:23 PM PDT 24
Finished Aug 08 04:33:04 PM PDT 24
Peak memory 199772 kb
Host smart-ea200a95-8061-4895-9967-2f2dce850f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762234908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.762234908
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3048906334
Short name T448
Test name
Test status
Simulation time 34545187281 ps
CPU time 47.17 seconds
Started Aug 08 04:32:21 PM PDT 24
Finished Aug 08 04:33:08 PM PDT 24
Peak memory 196688 kb
Host smart-ec0feb42-aa5e-4209-9117-b2ab64370289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048906334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3048906334
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2537828591
Short name T94
Test name
Test status
Simulation time 79164945 ps
CPU time 0.83 seconds
Started Aug 08 04:32:22 PM PDT 24
Finished Aug 08 04:32:23 PM PDT 24
Peak memory 218180 kb
Host smart-1a08b4d1-a687-4d8d-a047-b253de2975c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537828591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2537828591
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2313700795
Short name T388
Test name
Test status
Simulation time 5673888905 ps
CPU time 11.13 seconds
Started Aug 08 04:32:23 PM PDT 24
Finished Aug 08 04:32:34 PM PDT 24
Peak memory 199756 kb
Host smart-af699b03-c8c8-4446-8b9d-54724e1041ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313700795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2313700795
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2192544576
Short name T762
Test name
Test status
Simulation time 17208229051 ps
CPU time 188.93 seconds
Started Aug 08 04:32:24 PM PDT 24
Finished Aug 08 04:35:33 PM PDT 24
Peak memory 216236 kb
Host smart-cf2c41e7-a7a0-46a9-bc08-1d467baca90f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192544576 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2192544576
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1598975551
Short name T707
Test name
Test status
Simulation time 6691263043 ps
CPU time 13.53 seconds
Started Aug 08 04:32:23 PM PDT 24
Finished Aug 08 04:32:36 PM PDT 24
Peak memory 199676 kb
Host smart-efef77fd-b86a-4ea6-a9ce-af8f09fa5a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598975551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1598975551
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1104902928
Short name T250
Test name
Test status
Simulation time 41283708211 ps
CPU time 57.65 seconds
Started Aug 08 04:32:23 PM PDT 24
Finished Aug 08 04:33:21 PM PDT 24
Peak memory 199800 kb
Host smart-f23b428d-99f9-48c0-9acb-fc57057ddf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104902928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1104902928
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2059510300
Short name T597
Test name
Test status
Simulation time 91605940 ps
CPU time 0.55 seconds
Started Aug 08 04:38:19 PM PDT 24
Finished Aug 08 04:38:20 PM PDT 24
Peak memory 194884 kb
Host smart-6b7a07e9-7e1b-4af2-b9ec-cf5b70ab4635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059510300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2059510300
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1109354825
Short name T165
Test name
Test status
Simulation time 20721063941 ps
CPU time 15.41 seconds
Started Aug 08 04:37:07 PM PDT 24
Finished Aug 08 04:37:23 PM PDT 24
Peak memory 199780 kb
Host smart-8f6a0cdc-5876-4e9c-a100-e28041a2f6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109354825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1109354825
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1600956148
Short name T266
Test name
Test status
Simulation time 8475915224 ps
CPU time 14.47 seconds
Started Aug 08 04:37:10 PM PDT 24
Finished Aug 08 04:37:25 PM PDT 24
Peak memory 199768 kb
Host smart-fb110747-145d-47ac-aeea-64026babe055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600956148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1600956148
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2308557553
Short name T1154
Test name
Test status
Simulation time 115542626696 ps
CPU time 31.85 seconds
Started Aug 08 04:37:23 PM PDT 24
Finished Aug 08 04:37:55 PM PDT 24
Peak memory 199296 kb
Host smart-88c00f9b-ce2d-4f64-a1b5-87ad1393627b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308557553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2308557553
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1860136954
Short name T796
Test name
Test status
Simulation time 41265224634 ps
CPU time 55.27 seconds
Started Aug 08 04:37:08 PM PDT 24
Finished Aug 08 04:38:03 PM PDT 24
Peak memory 195892 kb
Host smart-b8a59183-6a9b-4e9e-899b-4ee7fbd1ec5b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860136954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1860136954
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.4102315919
Short name T1
Test name
Test status
Simulation time 71826457225 ps
CPU time 453.81 seconds
Started Aug 08 04:37:07 PM PDT 24
Finished Aug 08 04:44:41 PM PDT 24
Peak memory 199820 kb
Host smart-91ac522c-b4d3-4613-b966-e9a5994af92c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4102315919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.4102315919
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2871834241
Short name T355
Test name
Test status
Simulation time 2494613865 ps
CPU time 4.86 seconds
Started Aug 08 04:37:06 PM PDT 24
Finished Aug 08 04:37:11 PM PDT 24
Peak memory 197360 kb
Host smart-ed48cbfb-afe2-4e5c-86fd-c96ab6ebe01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871834241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2871834241
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.661043418
Short name T921
Test name
Test status
Simulation time 126066336923 ps
CPU time 27.47 seconds
Started Aug 08 04:37:16 PM PDT 24
Finished Aug 08 04:37:44 PM PDT 24
Peak memory 200060 kb
Host smart-a09d2697-6ca6-4bc8-a25b-96d0e4756a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661043418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.661043418
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.243195074
Short name T576
Test name
Test status
Simulation time 19378446446 ps
CPU time 947.22 seconds
Started Aug 08 04:38:19 PM PDT 24
Finished Aug 08 04:54:06 PM PDT 24
Peak memory 199460 kb
Host smart-7692a0f7-db1e-4580-b4ef-1286b4496615
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=243195074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.243195074
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.949171737
Short name T857
Test name
Test status
Simulation time 4646656301 ps
CPU time 35.16 seconds
Started Aug 08 04:37:07 PM PDT 24
Finished Aug 08 04:37:42 PM PDT 24
Peak memory 198824 kb
Host smart-67df5888-0b54-4d8f-84c0-f7a8d839fdc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=949171737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.949171737
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1609984981
Short name T954
Test name
Test status
Simulation time 31455584354 ps
CPU time 46.02 seconds
Started Aug 08 04:37:07 PM PDT 24
Finished Aug 08 04:37:53 PM PDT 24
Peak memory 199780 kb
Host smart-df2a520a-2c7d-4669-858c-cee792adc6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609984981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1609984981
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.4142525066
Short name T407
Test name
Test status
Simulation time 4347614360 ps
CPU time 4.34 seconds
Started Aug 08 04:37:05 PM PDT 24
Finished Aug 08 04:37:10 PM PDT 24
Peak memory 196132 kb
Host smart-2ccc18e4-57cb-4b80-861b-88b14b2d11de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142525066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.4142525066
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1211192056
Short name T97
Test name
Test status
Simulation time 1007965204 ps
CPU time 1.87 seconds
Started Aug 08 04:37:24 PM PDT 24
Finished Aug 08 04:37:26 PM PDT 24
Peak memory 198008 kb
Host smart-bd15329c-d586-4551-9ccb-8d83d44d705e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211192056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1211192056
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2245140890
Short name T174
Test name
Test status
Simulation time 329104387335 ps
CPU time 440.13 seconds
Started Aug 08 04:37:06 PM PDT 24
Finished Aug 08 04:44:27 PM PDT 24
Peak memory 208084 kb
Host smart-0ecd1e13-5b94-4d53-bd1b-35e260671c9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245140890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2245140890
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3998693725
Short name T709
Test name
Test status
Simulation time 85934329787 ps
CPU time 235.88 seconds
Started Aug 08 04:38:19 PM PDT 24
Finished Aug 08 04:42:15 PM PDT 24
Peak memory 215432 kb
Host smart-209bb7ef-7696-4874-9251-e78fceb04d7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998693725 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3998693725
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1100317724
Short name T766
Test name
Test status
Simulation time 8115046187 ps
CPU time 11.08 seconds
Started Aug 08 04:37:07 PM PDT 24
Finished Aug 08 04:37:18 PM PDT 24
Peak memory 199504 kb
Host smart-d26cf037-9ccb-47c1-bffe-2ac069ef0acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100317724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1100317724
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.596962276
Short name T425
Test name
Test status
Simulation time 9634777003 ps
CPU time 9.2 seconds
Started Aug 08 04:37:06 PM PDT 24
Finished Aug 08 04:37:15 PM PDT 24
Peak memory 199856 kb
Host smart-fcd13449-618a-432e-83e4-9e28bd3e8779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596962276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.596962276
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2609538393
Short name T807
Test name
Test status
Simulation time 38282287 ps
CPU time 0.57 seconds
Started Aug 08 04:37:15 PM PDT 24
Finished Aug 08 04:37:16 PM PDT 24
Peak memory 195232 kb
Host smart-b667978e-c45b-429e-beca-c019071751d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609538393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2609538393
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1508988845
Short name T515
Test name
Test status
Simulation time 59804333064 ps
CPU time 20.13 seconds
Started Aug 08 04:37:05 PM PDT 24
Finished Aug 08 04:37:25 PM PDT 24
Peak memory 199728 kb
Host smart-41672750-2778-40c0-9fde-87b8a2bdc186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508988845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1508988845
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3454376138
Short name T783
Test name
Test status
Simulation time 37917229016 ps
CPU time 15.46 seconds
Started Aug 08 04:37:05 PM PDT 24
Finished Aug 08 04:37:21 PM PDT 24
Peak memory 199836 kb
Host smart-073da23c-0c3f-419e-acbc-084c63913ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454376138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3454376138
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2259741505
Short name T835
Test name
Test status
Simulation time 92166337540 ps
CPU time 134.7 seconds
Started Aug 08 04:37:05 PM PDT 24
Finished Aug 08 04:39:19 PM PDT 24
Peak memory 199788 kb
Host smart-bb2d0a96-be8b-413f-bcc6-cf34d4365411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259741505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2259741505
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2173366463
Short name T1168
Test name
Test status
Simulation time 56932247000 ps
CPU time 27.31 seconds
Started Aug 08 04:37:17 PM PDT 24
Finished Aug 08 04:37:44 PM PDT 24
Peak memory 199608 kb
Host smart-9048e689-52b3-4767-9f1d-cef8bf6a3339
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173366463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2173366463
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.729573100
Short name T474
Test name
Test status
Simulation time 162817949666 ps
CPU time 57.95 seconds
Started Aug 08 04:37:16 PM PDT 24
Finished Aug 08 04:38:14 PM PDT 24
Peak memory 199692 kb
Host smart-776a16f1-1673-48c1-8958-c1ac7b736fd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=729573100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.729573100
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1566457372
Short name T1162
Test name
Test status
Simulation time 4612807819 ps
CPU time 4.56 seconds
Started Aug 08 04:37:17 PM PDT 24
Finished Aug 08 04:37:22 PM PDT 24
Peak memory 199460 kb
Host smart-c861ca3a-4399-4549-b0b9-443d14e9cea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566457372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1566457372
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2515695974
Short name T681
Test name
Test status
Simulation time 1893293321 ps
CPU time 3.69 seconds
Started Aug 08 04:37:14 PM PDT 24
Finished Aug 08 04:37:18 PM PDT 24
Peak memory 194300 kb
Host smart-62354606-f872-4334-aaf7-f40365578c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515695974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2515695974
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.170931315
Short name T966
Test name
Test status
Simulation time 16500465728 ps
CPU time 128.77 seconds
Started Aug 08 04:37:16 PM PDT 24
Finished Aug 08 04:39:25 PM PDT 24
Peak memory 199872 kb
Host smart-d7109e7c-208e-43f0-a6c1-7daca46a0ab7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=170931315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.170931315
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.342467156
Short name T1103
Test name
Test status
Simulation time 1684557897 ps
CPU time 4.42 seconds
Started Aug 08 04:37:07 PM PDT 24
Finished Aug 08 04:37:11 PM PDT 24
Peak memory 197852 kb
Host smart-5e0134e1-c315-478d-a845-04daabc94202
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=342467156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.342467156
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.3475254518
Short name T145
Test name
Test status
Simulation time 51752042481 ps
CPU time 79.76 seconds
Started Aug 08 04:37:17 PM PDT 24
Finished Aug 08 04:38:36 PM PDT 24
Peak memory 199592 kb
Host smart-0781265e-1a57-4494-926c-8913759e62b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475254518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3475254518
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1119027318
Short name T911
Test name
Test status
Simulation time 2176931749 ps
CPU time 1.64 seconds
Started Aug 08 04:37:16 PM PDT 24
Finished Aug 08 04:37:18 PM PDT 24
Peak memory 195404 kb
Host smart-e97ed971-d2a0-4080-a570-105cfdda0ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119027318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1119027318
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.4141969047
Short name T825
Test name
Test status
Simulation time 466611971 ps
CPU time 1.63 seconds
Started Aug 08 04:37:06 PM PDT 24
Finished Aug 08 04:37:08 PM PDT 24
Peak memory 198660 kb
Host smart-ce8175dd-7f1e-457e-8a9e-808164af27fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141969047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.4141969047
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3034380107
Short name T215
Test name
Test status
Simulation time 21866850873 ps
CPU time 177.75 seconds
Started Aug 08 04:37:18 PM PDT 24
Finished Aug 08 04:40:16 PM PDT 24
Peak memory 216428 kb
Host smart-5c2fa1d4-ac6b-4928-bbe3-be0cc0b8fbe8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034380107 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3034380107
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1181908577
Short name T286
Test name
Test status
Simulation time 1165510280 ps
CPU time 1.81 seconds
Started Aug 08 04:37:16 PM PDT 24
Finished Aug 08 04:37:18 PM PDT 24
Peak memory 199336 kb
Host smart-ec261383-8b83-4449-a85d-14c3d00010f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181908577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1181908577
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3734005429
Short name T829
Test name
Test status
Simulation time 26100562444 ps
CPU time 37.18 seconds
Started Aug 08 04:37:07 PM PDT 24
Finished Aug 08 04:37:44 PM PDT 24
Peak memory 199848 kb
Host smart-3e8cd12f-bcfe-425b-9f80-5febd851fee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734005429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3734005429
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3252944856
Short name T519
Test name
Test status
Simulation time 45314223 ps
CPU time 0.56 seconds
Started Aug 08 04:37:24 PM PDT 24
Finished Aug 08 04:37:25 PM PDT 24
Peak memory 195160 kb
Host smart-4e1684f4-72f6-4845-9e7d-7b0cff795a6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252944856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3252944856
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3974280663
Short name T330
Test name
Test status
Simulation time 154731478469 ps
CPU time 216.07 seconds
Started Aug 08 04:37:20 PM PDT 24
Finished Aug 08 04:40:56 PM PDT 24
Peak memory 199768 kb
Host smart-ed452a32-9f83-45b9-bb2c-d616b7cfbb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974280663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3974280663
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1525500902
Short name T895
Test name
Test status
Simulation time 176680864711 ps
CPU time 27 seconds
Started Aug 08 04:37:16 PM PDT 24
Finished Aug 08 04:37:43 PM PDT 24
Peak memory 199844 kb
Host smart-5dd21b4c-8856-4d20-8745-eba8ebcc9447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525500902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1525500902
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2183209708
Short name T228
Test name
Test status
Simulation time 24470731021 ps
CPU time 32.56 seconds
Started Aug 08 04:37:17 PM PDT 24
Finished Aug 08 04:37:50 PM PDT 24
Peak memory 199752 kb
Host smart-1ab39a51-97eb-4dd0-bd93-9ac5403b2c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183209708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2183209708
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2963987998
Short name T906
Test name
Test status
Simulation time 42991100960 ps
CPU time 159.3 seconds
Started Aug 08 04:37:20 PM PDT 24
Finished Aug 08 04:40:00 PM PDT 24
Peak memory 199800 kb
Host smart-78ef9927-bea8-4f4c-836c-5f2f4a05f6ec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963987998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2963987998
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.279441458
Short name T293
Test name
Test status
Simulation time 145555690529 ps
CPU time 920.46 seconds
Started Aug 08 04:38:04 PM PDT 24
Finished Aug 08 04:53:24 PM PDT 24
Peak memory 199756 kb
Host smart-be982d9a-4255-4c87-b7b1-1ae9b2b37a9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=279441458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.279441458
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1064911921
Short name T471
Test name
Test status
Simulation time 5539473484 ps
CPU time 10.26 seconds
Started Aug 08 04:37:16 PM PDT 24
Finished Aug 08 04:37:26 PM PDT 24
Peak memory 197548 kb
Host smart-24247b58-8b8a-43e2-ae87-2a52e5804e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064911921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1064911921
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2501341269
Short name T339
Test name
Test status
Simulation time 459025566750 ps
CPU time 108.8 seconds
Started Aug 08 04:37:17 PM PDT 24
Finished Aug 08 04:39:06 PM PDT 24
Peak memory 208000 kb
Host smart-fb809293-0fe5-4e92-b535-68266e935671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501341269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2501341269
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.4227742827
Short name T562
Test name
Test status
Simulation time 34183480226 ps
CPU time 282.29 seconds
Started Aug 08 04:37:25 PM PDT 24
Finished Aug 08 04:42:08 PM PDT 24
Peak memory 199732 kb
Host smart-77694269-d34a-408d-8fc1-e417e62e677c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4227742827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.4227742827
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3325284147
Short name T335
Test name
Test status
Simulation time 1296964968 ps
CPU time 1.15 seconds
Started Aug 08 04:37:17 PM PDT 24
Finished Aug 08 04:37:18 PM PDT 24
Peak memory 195440 kb
Host smart-784cb4f6-8ebb-41de-b898-ff44bf87e304
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3325284147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3325284147
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3495579008
Short name T511
Test name
Test status
Simulation time 64653569278 ps
CPU time 45.39 seconds
Started Aug 08 04:37:17 PM PDT 24
Finished Aug 08 04:38:03 PM PDT 24
Peak memory 199832 kb
Host smart-094984b6-bfce-47dd-b7b0-f9101223a0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495579008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3495579008
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1860395123
Short name T480
Test name
Test status
Simulation time 40027685551 ps
CPU time 7.28 seconds
Started Aug 08 04:37:16 PM PDT 24
Finished Aug 08 04:37:24 PM PDT 24
Peak memory 195888 kb
Host smart-1c1f145b-2071-4c30-9e1e-908e607047ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860395123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1860395123
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2191797662
Short name T587
Test name
Test status
Simulation time 661710104 ps
CPU time 3.11 seconds
Started Aug 08 04:37:16 PM PDT 24
Finished Aug 08 04:37:19 PM PDT 24
Peak memory 197992 kb
Host smart-7b4c5d9a-13f3-45ea-9d8c-636c5c77533d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191797662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2191797662
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.3482026578
Short name T578
Test name
Test status
Simulation time 386219611416 ps
CPU time 677.99 seconds
Started Aug 08 04:37:25 PM PDT 24
Finished Aug 08 04:48:43 PM PDT 24
Peak memory 199720 kb
Host smart-958f5b8f-ca74-4dbd-af30-ef51ca1a4a26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482026578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3482026578
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1039240927
Short name T849
Test name
Test status
Simulation time 297574574404 ps
CPU time 455.08 seconds
Started Aug 08 04:37:24 PM PDT 24
Finished Aug 08 04:44:59 PM PDT 24
Peak memory 216364 kb
Host smart-5ba65433-3601-4a85-82c9-b0f427c2936b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039240927 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1039240927
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3623294830
Short name T967
Test name
Test status
Simulation time 776359595 ps
CPU time 2.53 seconds
Started Aug 08 04:37:15 PM PDT 24
Finished Aug 08 04:37:18 PM PDT 24
Peak memory 198252 kb
Host smart-16991506-1524-47da-9e2a-774c64d8d70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623294830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3623294830
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.505413506
Short name T770
Test name
Test status
Simulation time 35640654674 ps
CPU time 14.17 seconds
Started Aug 08 04:37:17 PM PDT 24
Finished Aug 08 04:37:31 PM PDT 24
Peak memory 199852 kb
Host smart-540084c2-4ee7-4d15-8ea2-dcbf2cedfc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505413506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.505413506
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1222673099
Short name T5
Test name
Test status
Simulation time 13944089 ps
CPU time 0.58 seconds
Started Aug 08 04:37:28 PM PDT 24
Finished Aug 08 04:37:29 PM PDT 24
Peak memory 195564 kb
Host smart-fb3d5ac1-8f6e-45e9-b3c4-c59818e97653
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222673099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1222673099
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3621094498
Short name T769
Test name
Test status
Simulation time 127586823547 ps
CPU time 275.47 seconds
Started Aug 08 04:37:26 PM PDT 24
Finished Aug 08 04:42:02 PM PDT 24
Peak memory 199780 kb
Host smart-0dcab8b0-3968-4dd8-a775-063d27344210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621094498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3621094498
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2047738913
Short name T566
Test name
Test status
Simulation time 16815826163 ps
CPU time 25.46 seconds
Started Aug 08 04:37:26 PM PDT 24
Finished Aug 08 04:37:52 PM PDT 24
Peak memory 199784 kb
Host smart-081fa519-5552-4f8a-8079-c17a3c465387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047738913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2047738913
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2549210305
Short name T232
Test name
Test status
Simulation time 37186724450 ps
CPU time 47.06 seconds
Started Aug 08 04:37:27 PM PDT 24
Finished Aug 08 04:38:14 PM PDT 24
Peak memory 200164 kb
Host smart-75adf15f-3242-4417-9a62-1abea8f59b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549210305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2549210305
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3660571677
Short name T670
Test name
Test status
Simulation time 366924963377 ps
CPU time 155.89 seconds
Started Aug 08 04:37:34 PM PDT 24
Finished Aug 08 04:40:10 PM PDT 24
Peak memory 199784 kb
Host smart-9fbdc79a-d87f-41ee-a51b-382798432e1e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660571677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3660571677
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.2968766281
Short name T806
Test name
Test status
Simulation time 82852800116 ps
CPU time 233.79 seconds
Started Aug 08 04:37:24 PM PDT 24
Finished Aug 08 04:41:18 PM PDT 24
Peak memory 199816 kb
Host smart-1e02a8c5-0561-47fd-93f5-8f4b4f18ab2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2968766281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2968766281
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3583578899
Short name T4
Test name
Test status
Simulation time 2720784213 ps
CPU time 5.89 seconds
Started Aug 08 04:37:25 PM PDT 24
Finished Aug 08 04:37:31 PM PDT 24
Peak memory 198220 kb
Host smart-f65a0eed-2b25-4c77-b2ea-090224b0616f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583578899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3583578899
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.286573097
Short name T304
Test name
Test status
Simulation time 173936401665 ps
CPU time 52.9 seconds
Started Aug 08 04:37:45 PM PDT 24
Finished Aug 08 04:38:38 PM PDT 24
Peak memory 208120 kb
Host smart-7ee66eb6-7a59-4aa2-b432-2f8c3c3fcc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286573097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.286573097
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.3926276709
Short name T732
Test name
Test status
Simulation time 13683759272 ps
CPU time 781.56 seconds
Started Aug 08 04:37:52 PM PDT 24
Finished Aug 08 04:50:54 PM PDT 24
Peak memory 199804 kb
Host smart-b89fd0a4-fb6f-4807-bbdf-9e11ad1405f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926276709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3926276709
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1194540269
Short name T1000
Test name
Test status
Simulation time 4569302096 ps
CPU time 39.84 seconds
Started Aug 08 04:37:38 PM PDT 24
Finished Aug 08 04:38:18 PM PDT 24
Peak memory 198280 kb
Host smart-89cff45a-5ffc-40b8-8647-99081dd064cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1194540269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1194540269
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2156783409
Short name T365
Test name
Test status
Simulation time 19184558067 ps
CPU time 36.34 seconds
Started Aug 08 04:38:02 PM PDT 24
Finished Aug 08 04:38:39 PM PDT 24
Peak memory 199764 kb
Host smart-ce2dbe16-7797-47d5-81c1-eeb29881a1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156783409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2156783409
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1467551660
Short name T594
Test name
Test status
Simulation time 2928445718 ps
CPU time 4.57 seconds
Started Aug 08 04:37:29 PM PDT 24
Finished Aug 08 04:37:34 PM PDT 24
Peak memory 196336 kb
Host smart-f3483f56-4283-49c1-a43a-de67ec3dea1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467551660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1467551660
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1453599402
Short name T592
Test name
Test status
Simulation time 6081721551 ps
CPU time 5.43 seconds
Started Aug 08 04:37:25 PM PDT 24
Finished Aug 08 04:37:31 PM PDT 24
Peak memory 199860 kb
Host smart-824fada8-0118-4382-a39e-edd59d4d74da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453599402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1453599402
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.785943861
Short name T412
Test name
Test status
Simulation time 44467433889 ps
CPU time 285.03 seconds
Started Aug 08 04:37:25 PM PDT 24
Finished Aug 08 04:42:11 PM PDT 24
Peak memory 199784 kb
Host smart-4b2d1fff-6dd9-4668-8dc2-79b60b52013a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785943861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.785943861
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.382195134
Short name T332
Test name
Test status
Simulation time 14749157892 ps
CPU time 244.71 seconds
Started Aug 08 04:37:25 PM PDT 24
Finished Aug 08 04:41:30 PM PDT 24
Peak memory 215384 kb
Host smart-455dff73-e171-4d2b-bf11-9c5e9626c7e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382195134 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.382195134
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3395330807
Short name T506
Test name
Test status
Simulation time 1427802584 ps
CPU time 1.89 seconds
Started Aug 08 04:37:34 PM PDT 24
Finished Aug 08 04:37:36 PM PDT 24
Peak memory 199332 kb
Host smart-05b3d47a-fbdd-4d65-aae5-dcbe8c5735f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395330807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3395330807
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1745757640
Short name T316
Test name
Test status
Simulation time 165255644251 ps
CPU time 144.35 seconds
Started Aug 08 04:37:25 PM PDT 24
Finished Aug 08 04:39:50 PM PDT 24
Peak memory 199708 kb
Host smart-0fdb6b1c-1bc1-4b76-a2b4-49bb853cd3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745757640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1745757640
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.747230086
Short name T852
Test name
Test status
Simulation time 20472759 ps
CPU time 0.58 seconds
Started Aug 08 04:38:01 PM PDT 24
Finished Aug 08 04:38:01 PM PDT 24
Peak memory 195424 kb
Host smart-58eecafc-17f1-44ae-8099-bd3aaa9e9afe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747230086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.747230086
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.2392619009
Short name T130
Test name
Test status
Simulation time 28751978671 ps
CPU time 40.44 seconds
Started Aug 08 04:37:41 PM PDT 24
Finished Aug 08 04:38:22 PM PDT 24
Peak memory 199704 kb
Host smart-c3e48972-cfe0-407a-ba91-5d0aceda842c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392619009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2392619009
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.2649885470
Short name T994
Test name
Test status
Simulation time 120954267311 ps
CPU time 134.61 seconds
Started Aug 08 04:37:40 PM PDT 24
Finished Aug 08 04:39:55 PM PDT 24
Peak memory 199816 kb
Host smart-e53297f1-a2e1-42dd-9eba-310a60791727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649885470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2649885470
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2316378531
Short name T919
Test name
Test status
Simulation time 24211060414 ps
CPU time 40.77 seconds
Started Aug 08 04:37:42 PM PDT 24
Finished Aug 08 04:38:23 PM PDT 24
Peak memory 199816 kb
Host smart-ebeeb4ab-0e9f-413a-8f7f-6ab07cb5a45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316378531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2316378531
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3772220102
Short name T522
Test name
Test status
Simulation time 326065879882 ps
CPU time 99.14 seconds
Started Aug 08 04:37:38 PM PDT 24
Finished Aug 08 04:39:17 PM PDT 24
Peak memory 199780 kb
Host smart-14f002de-e813-44dd-a8dd-99476c227195
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772220102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3772220102
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3569874261
Short name T525
Test name
Test status
Simulation time 112918028082 ps
CPU time 261.21 seconds
Started Aug 08 04:37:37 PM PDT 24
Finished Aug 08 04:41:58 PM PDT 24
Peak memory 199708 kb
Host smart-f3142939-19cd-42b7-9c0a-5199a9a7dab3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3569874261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3569874261
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.4006452818
Short name T600
Test name
Test status
Simulation time 4344325922 ps
CPU time 5.53 seconds
Started Aug 08 04:37:37 PM PDT 24
Finished Aug 08 04:37:43 PM PDT 24
Peak memory 198092 kb
Host smart-beb8a3de-65ca-49db-a4ca-851dca8a67d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006452818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.4006452818
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.4050977262
Short name T1130
Test name
Test status
Simulation time 85207541723 ps
CPU time 65.47 seconds
Started Aug 08 04:37:36 PM PDT 24
Finished Aug 08 04:38:42 PM PDT 24
Peak memory 199908 kb
Host smart-b86a38d7-c00c-498c-b6b1-4384426c455f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050977262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.4050977262
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2995459677
Short name T520
Test name
Test status
Simulation time 11615177010 ps
CPU time 106.51 seconds
Started Aug 08 04:37:37 PM PDT 24
Finished Aug 08 04:39:24 PM PDT 24
Peak memory 199828 kb
Host smart-679b14a4-ddc2-4f10-88f2-26a7bb93b63e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995459677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2995459677
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1647914117
Short name T399
Test name
Test status
Simulation time 2471715749 ps
CPU time 2.62 seconds
Started Aug 08 04:37:39 PM PDT 24
Finished Aug 08 04:37:42 PM PDT 24
Peak memory 197760 kb
Host smart-f613df6a-7646-42d4-ab42-d829d481e312
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647914117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1647914117
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.438888476
Short name T959
Test name
Test status
Simulation time 172015750425 ps
CPU time 103.38 seconds
Started Aug 08 04:37:38 PM PDT 24
Finished Aug 08 04:39:22 PM PDT 24
Peak memory 200104 kb
Host smart-36b140ce-c6c5-4e00-a7c1-dd03d5a8d595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438888476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.438888476
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3568727945
Short name T591
Test name
Test status
Simulation time 3571044031 ps
CPU time 3.06 seconds
Started Aug 08 04:37:38 PM PDT 24
Finished Aug 08 04:37:41 PM PDT 24
Peak memory 196280 kb
Host smart-801a40d4-6b7d-4ed2-9c76-db7265664a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568727945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3568727945
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3055058187
Short name T373
Test name
Test status
Simulation time 6069887535 ps
CPU time 25.19 seconds
Started Aug 08 04:37:25 PM PDT 24
Finished Aug 08 04:37:50 PM PDT 24
Peak memory 199748 kb
Host smart-5bc30c69-9f3c-4738-9b59-e329d5fef569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055058187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3055058187
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.426227576
Short name T1166
Test name
Test status
Simulation time 159553241290 ps
CPU time 215.49 seconds
Started Aug 08 04:37:37 PM PDT 24
Finished Aug 08 04:41:13 PM PDT 24
Peak memory 199828 kb
Host smart-6e8be784-f44b-4273-8029-bbc5b14ff1bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426227576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.426227576
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.2275975086
Short name T1179
Test name
Test status
Simulation time 59281862770 ps
CPU time 304.19 seconds
Started Aug 08 04:37:36 PM PDT 24
Finished Aug 08 04:42:40 PM PDT 24
Peak memory 216352 kb
Host smart-7f13dd58-10ae-4099-be34-d4f33f24db5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275975086 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2275975086
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.3796544135
Short name T616
Test name
Test status
Simulation time 7121061820 ps
CPU time 23.26 seconds
Started Aug 08 04:37:37 PM PDT 24
Finished Aug 08 04:38:00 PM PDT 24
Peak memory 199148 kb
Host smart-8657a58b-1cc2-4f14-bc59-e5588aa7cbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796544135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3796544135
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.497801113
Short name T382
Test name
Test status
Simulation time 13863975594 ps
CPU time 10.65 seconds
Started Aug 08 04:37:37 PM PDT 24
Finished Aug 08 04:37:48 PM PDT 24
Peak memory 197636 kb
Host smart-6817baf8-b583-460b-9853-0601bc1b6f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497801113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.497801113
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2489812816
Short name T440
Test name
Test status
Simulation time 15940120 ps
CPU time 0.53 seconds
Started Aug 08 04:37:47 PM PDT 24
Finished Aug 08 04:37:48 PM PDT 24
Peak memory 194124 kb
Host smart-2c7dc1c7-fb9c-4c98-a7ab-3eaece687f3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489812816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2489812816
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1929382883
Short name T896
Test name
Test status
Simulation time 69828634764 ps
CPU time 101.91 seconds
Started Aug 08 04:37:47 PM PDT 24
Finished Aug 08 04:39:29 PM PDT 24
Peak memory 199844 kb
Host smart-6d6cbe6b-fb41-4de1-b358-9078603e3781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929382883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1929382883
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2304434471
Short name T549
Test name
Test status
Simulation time 21383761285 ps
CPU time 92.8 seconds
Started Aug 08 04:37:47 PM PDT 24
Finished Aug 08 04:39:20 PM PDT 24
Peak memory 199800 kb
Host smart-9a8edb9e-a17a-4bcb-be8a-35e5299098a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304434471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2304434471
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2573154531
Short name T517
Test name
Test status
Simulation time 58330401178 ps
CPU time 15.15 seconds
Started Aug 08 04:37:46 PM PDT 24
Finished Aug 08 04:38:01 PM PDT 24
Peak memory 199740 kb
Host smart-3bc2883c-f609-4874-9830-7d07d2189e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573154531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2573154531
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.4281029770
Short name T290
Test name
Test status
Simulation time 468948874341 ps
CPU time 166.44 seconds
Started Aug 08 04:37:47 PM PDT 24
Finished Aug 08 04:40:34 PM PDT 24
Peak memory 199696 kb
Host smart-d5c3b027-2553-4027-96fc-30332ff11103
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281029770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.4281029770
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3528818568
Short name T710
Test name
Test status
Simulation time 80268740928 ps
CPU time 469.53 seconds
Started Aug 08 04:37:56 PM PDT 24
Finished Aug 08 04:45:46 PM PDT 24
Peak memory 199744 kb
Host smart-ba47db03-c39a-40f7-9fe3-b986fd673b7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3528818568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3528818568
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.461508007
Short name T676
Test name
Test status
Simulation time 1157142337 ps
CPU time 0.91 seconds
Started Aug 08 04:37:47 PM PDT 24
Finished Aug 08 04:37:48 PM PDT 24
Peak memory 196984 kb
Host smart-78cd5aee-9d5c-4562-b347-2cb747f52f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461508007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.461508007
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.238681535
Short name T637
Test name
Test status
Simulation time 53637240434 ps
CPU time 79.87 seconds
Started Aug 08 04:37:49 PM PDT 24
Finished Aug 08 04:39:09 PM PDT 24
Peak memory 199888 kb
Host smart-aa800888-804f-4078-aaf3-546b4b793eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238681535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.238681535
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3403104055
Short name T910
Test name
Test status
Simulation time 32776999718 ps
CPU time 186.74 seconds
Started Aug 08 04:37:47 PM PDT 24
Finished Aug 08 04:40:54 PM PDT 24
Peak memory 199832 kb
Host smart-8e6172a5-bf91-43be-ba1d-c7b29b721c34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3403104055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3403104055
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.375247283
Short name T843
Test name
Test status
Simulation time 1992843272 ps
CPU time 11.69 seconds
Started Aug 08 04:37:46 PM PDT 24
Finished Aug 08 04:37:57 PM PDT 24
Peak memory 196556 kb
Host smart-bdab323e-979b-4eb2-ba39-4643aa6ed557
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=375247283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.375247283
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.535672608
Short name T389
Test name
Test status
Simulation time 94554837836 ps
CPU time 36.86 seconds
Started Aug 08 04:37:47 PM PDT 24
Finished Aug 08 04:38:24 PM PDT 24
Peak memory 199820 kb
Host smart-956e84f4-71a3-4130-a04a-b51f0e263f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535672608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.535672608
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2096129360
Short name T716
Test name
Test status
Simulation time 4531525180 ps
CPU time 7.72 seconds
Started Aug 08 04:37:47 PM PDT 24
Finished Aug 08 04:37:55 PM PDT 24
Peak memory 196320 kb
Host smart-49c0721d-eb28-48a5-a212-cd7670962517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096129360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2096129360
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3602916479
Short name T8
Test name
Test status
Simulation time 6212871854 ps
CPU time 8.37 seconds
Started Aug 08 04:37:48 PM PDT 24
Finished Aug 08 04:37:56 PM PDT 24
Peak memory 199768 kb
Host smart-91bd8d0e-634d-4d55-a2e3-5bd7a3d64a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602916479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3602916479
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.191897186
Short name T671
Test name
Test status
Simulation time 154339528264 ps
CPU time 161.53 seconds
Started Aug 08 04:37:47 PM PDT 24
Finished Aug 08 04:40:29 PM PDT 24
Peak memory 215576 kb
Host smart-181b7f24-06d1-4e66-bc2b-6b0e1d39e4e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191897186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.191897186
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1559636317
Short name T539
Test name
Test status
Simulation time 16075689170 ps
CPU time 191.99 seconds
Started Aug 08 04:37:49 PM PDT 24
Finished Aug 08 04:41:01 PM PDT 24
Peak memory 216268 kb
Host smart-2516b030-95ad-4de7-a30e-81356c344ce6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559636317 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1559636317
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2379384639
Short name T2
Test name
Test status
Simulation time 269038908 ps
CPU time 1.27 seconds
Started Aug 08 04:37:47 PM PDT 24
Finished Aug 08 04:37:49 PM PDT 24
Peak memory 197704 kb
Host smart-e6fe1717-524e-4602-bbd6-69103e7c04bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379384639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2379384639
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.4115084080
Short name T548
Test name
Test status
Simulation time 27059680998 ps
CPU time 19.34 seconds
Started Aug 08 04:37:47 PM PDT 24
Finished Aug 08 04:38:07 PM PDT 24
Peak memory 198240 kb
Host smart-dbc603fb-11ae-45a8-8f88-4417798c0259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115084080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.4115084080
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.352895547
Short name T629
Test name
Test status
Simulation time 40306337 ps
CPU time 0.55 seconds
Started Aug 08 04:37:58 PM PDT 24
Finished Aug 08 04:37:59 PM PDT 24
Peak memory 195424 kb
Host smart-9e50068b-fdfb-4d63-a9ac-679cb97b08c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352895547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.352895547
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3180813826
Short name T1079
Test name
Test status
Simulation time 150219159295 ps
CPU time 90.77 seconds
Started Aug 08 04:37:47 PM PDT 24
Finished Aug 08 04:39:18 PM PDT 24
Peak memory 199696 kb
Host smart-1e1d42c1-6330-4412-8b8c-1bd63c168809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180813826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3180813826
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_intr.308856459
Short name T891
Test name
Test status
Simulation time 326367739876 ps
CPU time 158.63 seconds
Started Aug 08 04:38:01 PM PDT 24
Finished Aug 08 04:40:40 PM PDT 24
Peak memory 199796 kb
Host smart-4b0b1245-5b94-4ebb-8e66-7e937be46641
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308856459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.308856459
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1851310438
Short name T673
Test name
Test status
Simulation time 54823143621 ps
CPU time 82.2 seconds
Started Aug 08 04:38:02 PM PDT 24
Finished Aug 08 04:39:24 PM PDT 24
Peak memory 199720 kb
Host smart-6431bd1d-62a6-4257-84ac-3b88bd0f60a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1851310438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1851310438
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.157792339
Short name T426
Test name
Test status
Simulation time 2881657626 ps
CPU time 10.87 seconds
Started Aug 08 04:38:02 PM PDT 24
Finished Aug 08 04:38:13 PM PDT 24
Peak memory 198348 kb
Host smart-fe706067-45ce-48df-87b0-d193a7d101b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157792339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.157792339
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3290856640
Short name T348
Test name
Test status
Simulation time 33894328870 ps
CPU time 12.99 seconds
Started Aug 08 04:37:59 PM PDT 24
Finished Aug 08 04:38:13 PM PDT 24
Peak memory 195740 kb
Host smart-47f977c5-5ac9-48ee-a0a3-6801f0a5ec13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290856640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3290856640
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1137988607
Short name T552
Test name
Test status
Simulation time 20783136664 ps
CPU time 235.22 seconds
Started Aug 08 04:37:56 PM PDT 24
Finished Aug 08 04:41:51 PM PDT 24
Peak memory 199872 kb
Host smart-095adf88-b062-4051-8ff1-cf9e90a68008
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1137988607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1137988607
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2250589854
Short name T564
Test name
Test status
Simulation time 1171748211 ps
CPU time 1.55 seconds
Started Aug 08 04:37:57 PM PDT 24
Finished Aug 08 04:37:59 PM PDT 24
Peak memory 196712 kb
Host smart-2fd705e1-fd47-43fe-b2ad-a2e01ea21056
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2250589854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2250589854
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1814109045
Short name T534
Test name
Test status
Simulation time 444919909324 ps
CPU time 185.38 seconds
Started Aug 08 04:38:16 PM PDT 24
Finished Aug 08 04:41:21 PM PDT 24
Peak memory 199700 kb
Host smart-32a67f8a-0949-44cb-905f-7453daf8e168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814109045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1814109045
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.708373902
Short name T1074
Test name
Test status
Simulation time 39267406003 ps
CPU time 63.87 seconds
Started Aug 08 04:37:58 PM PDT 24
Finished Aug 08 04:39:02 PM PDT 24
Peak memory 196120 kb
Host smart-c01ca229-9dad-4f5a-980c-f4b65db17f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708373902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.708373902
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.4112711399
Short name T444
Test name
Test status
Simulation time 308216757 ps
CPU time 1.59 seconds
Started Aug 08 04:37:49 PM PDT 24
Finished Aug 08 04:37:51 PM PDT 24
Peak memory 198928 kb
Host smart-691862d2-2c89-4ab0-a1dd-282868f2f15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112711399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.4112711399
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1875616171
Short name T430
Test name
Test status
Simulation time 183031605354 ps
CPU time 113.1 seconds
Started Aug 08 04:38:00 PM PDT 24
Finished Aug 08 04:39:53 PM PDT 24
Peak memory 199844 kb
Host smart-4c5221ab-ebe0-4732-abb7-61dc823bf6c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875616171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1875616171
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1157531776
Short name T320
Test name
Test status
Simulation time 93684020585 ps
CPU time 142.58 seconds
Started Aug 08 04:37:58 PM PDT 24
Finished Aug 08 04:40:21 PM PDT 24
Peak memory 214436 kb
Host smart-974f4f94-ea65-4a41-ac7c-3d2192d192f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157531776 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1157531776
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.4234244273
Short name T1146
Test name
Test status
Simulation time 7146416829 ps
CPU time 34.39 seconds
Started Aug 08 04:38:04 PM PDT 24
Finished Aug 08 04:38:39 PM PDT 24
Peak memory 199648 kb
Host smart-246ffae0-185e-453b-9860-0487d7fbe97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234244273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.4234244273
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.190257233
Short name T282
Test name
Test status
Simulation time 129439011766 ps
CPU time 64.17 seconds
Started Aug 08 04:37:50 PM PDT 24
Finished Aug 08 04:38:55 PM PDT 24
Peak memory 199740 kb
Host smart-9a4dbd80-fa15-4fe9-8fbd-c40a3da5ef74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190257233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.190257233
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.318501572
Short name T962
Test name
Test status
Simulation time 25835289 ps
CPU time 0.58 seconds
Started Aug 08 04:38:11 PM PDT 24
Finished Aug 08 04:38:12 PM PDT 24
Peak memory 195552 kb
Host smart-73561dc9-c8f3-4f96-b147-e722044949f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318501572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.318501572
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.613519486
Short name T661
Test name
Test status
Simulation time 51938988479 ps
CPU time 93.28 seconds
Started Aug 08 04:38:03 PM PDT 24
Finished Aug 08 04:39:37 PM PDT 24
Peak memory 199808 kb
Host smart-bd94f5a6-acc0-4f16-85ff-e77ec35e05a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613519486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.613519486
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2868326563
Short name T418
Test name
Test status
Simulation time 78123344930 ps
CPU time 91.42 seconds
Started Aug 08 04:37:58 PM PDT 24
Finished Aug 08 04:39:30 PM PDT 24
Peak memory 199764 kb
Host smart-757a1dde-828c-4f34-9db6-af5acc0a0a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868326563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2868326563
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3586866251
Short name T153
Test name
Test status
Simulation time 134478494681 ps
CPU time 114.46 seconds
Started Aug 08 04:38:01 PM PDT 24
Finished Aug 08 04:39:56 PM PDT 24
Peak memory 199816 kb
Host smart-88780e29-f35d-4ea7-976e-8b6dc3e03e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586866251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3586866251
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2858763770
Short name T1094
Test name
Test status
Simulation time 534965888472 ps
CPU time 186.58 seconds
Started Aug 08 04:37:59 PM PDT 24
Finished Aug 08 04:41:05 PM PDT 24
Peak memory 199532 kb
Host smart-050735e9-3a52-4c26-a09c-72ea3b6bb2e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858763770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2858763770
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.612351383
Short name T1160
Test name
Test status
Simulation time 142017462175 ps
CPU time 971.73 seconds
Started Aug 08 04:37:58 PM PDT 24
Finished Aug 08 04:54:09 PM PDT 24
Peak memory 199828 kb
Host smart-e47fb47f-f5ee-45c1-92a1-34e7a95637a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612351383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.612351383
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.1921302153
Short name T363
Test name
Test status
Simulation time 1878519891 ps
CPU time 6.42 seconds
Started Aug 08 04:37:58 PM PDT 24
Finished Aug 08 04:38:05 PM PDT 24
Peak memory 198164 kb
Host smart-6f2cc5ff-7993-496f-9d37-09c7368751f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921302153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1921302153
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2098400921
Short name T1176
Test name
Test status
Simulation time 66862956406 ps
CPU time 62.38 seconds
Started Aug 08 04:38:15 PM PDT 24
Finished Aug 08 04:39:17 PM PDT 24
Peak memory 199700 kb
Host smart-1809b82e-994d-45f1-a132-8ce279b6f94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098400921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2098400921
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.386383534
Short name T897
Test name
Test status
Simulation time 17239348770 ps
CPU time 234.76 seconds
Started Aug 08 04:37:59 PM PDT 24
Finished Aug 08 04:41:54 PM PDT 24
Peak memory 199820 kb
Host smart-51babc2c-437f-4979-9e3b-90777d204b37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386383534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.386383534
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.784486094
Short name T1123
Test name
Test status
Simulation time 5952001220 ps
CPU time 26.92 seconds
Started Aug 08 04:38:00 PM PDT 24
Finished Aug 08 04:38:27 PM PDT 24
Peak memory 198572 kb
Host smart-4977e481-678a-4d94-8993-624e4239a8ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=784486094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.784486094
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.132836749
Short name T651
Test name
Test status
Simulation time 103349629802 ps
CPU time 171.89 seconds
Started Aug 08 04:38:02 PM PDT 24
Finished Aug 08 04:40:54 PM PDT 24
Peak memory 199796 kb
Host smart-27692f91-d040-4410-b198-872a40d1cb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132836749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.132836749
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.4292302714
Short name T619
Test name
Test status
Simulation time 2777231710 ps
CPU time 2.47 seconds
Started Aug 08 04:38:00 PM PDT 24
Finished Aug 08 04:38:02 PM PDT 24
Peak memory 195808 kb
Host smart-e287cfab-ec04-4b70-9f3f-4cd2d236a27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292302714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.4292302714
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.1736078021
Short name T834
Test name
Test status
Simulation time 742090473 ps
CPU time 1.56 seconds
Started Aug 08 04:38:04 PM PDT 24
Finished Aug 08 04:38:06 PM PDT 24
Peak memory 198148 kb
Host smart-1d0562c9-31df-457d-8689-b8a2f83b7218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736078021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1736078021
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2816228072
Short name T1067
Test name
Test status
Simulation time 1699941035832 ps
CPU time 725.2 seconds
Started Aug 08 04:38:04 PM PDT 24
Finished Aug 08 04:50:09 PM PDT 24
Peak memory 224668 kb
Host smart-f504988b-0850-4af7-a36f-b51e597c7d39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816228072 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2816228072
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3255828151
Short name T41
Test name
Test status
Simulation time 2599214612 ps
CPU time 1.66 seconds
Started Aug 08 04:38:00 PM PDT 24
Finished Aug 08 04:38:01 PM PDT 24
Peak memory 198264 kb
Host smart-ef4fb4d3-f9d0-49a5-939a-17b926fa3a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255828151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3255828151
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.4129738733
Short name T310
Test name
Test status
Simulation time 67447777987 ps
CPU time 133.44 seconds
Started Aug 08 04:37:59 PM PDT 24
Finished Aug 08 04:40:12 PM PDT 24
Peak memory 199844 kb
Host smart-9e027710-2647-429e-8c48-8b984a3f1291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129738733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.4129738733
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.1640521606
Short name T359
Test name
Test status
Simulation time 12231654 ps
CPU time 0.57 seconds
Started Aug 08 04:38:14 PM PDT 24
Finished Aug 08 04:38:15 PM PDT 24
Peak memory 195436 kb
Host smart-948fb127-1084-4e79-a0c1-3c7cab83bdd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640521606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1640521606
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3077838126
Short name T1004
Test name
Test status
Simulation time 287951546338 ps
CPU time 51.34 seconds
Started Aug 08 04:38:13 PM PDT 24
Finished Aug 08 04:39:04 PM PDT 24
Peak memory 199764 kb
Host smart-154a7fed-d5d9-4db2-8db9-c474adc43236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077838126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3077838126
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2580290872
Short name T1063
Test name
Test status
Simulation time 14154197572 ps
CPU time 21.39 seconds
Started Aug 08 04:38:08 PM PDT 24
Finished Aug 08 04:38:29 PM PDT 24
Peak memory 199336 kb
Host smart-8956e4cb-3e2f-4493-bfe9-43286f4b97bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580290872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2580290872
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.713903968
Short name T952
Test name
Test status
Simulation time 18400717038 ps
CPU time 33.76 seconds
Started Aug 08 04:38:09 PM PDT 24
Finished Aug 08 04:38:43 PM PDT 24
Peak memory 199788 kb
Host smart-2ca3f022-54a2-4bd1-b67e-0a9bb6f7f285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713903968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.713903968
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.36229231
Short name T664
Test name
Test status
Simulation time 54301442354 ps
CPU time 26.84 seconds
Started Aug 08 04:38:14 PM PDT 24
Finished Aug 08 04:38:41 PM PDT 24
Peak memory 199728 kb
Host smart-68e73b02-c336-4668-8005-2065dce6a526
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36229231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.36229231
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2476257753
Short name T457
Test name
Test status
Simulation time 73146339071 ps
CPU time 213.08 seconds
Started Aug 08 04:38:09 PM PDT 24
Finished Aug 08 04:41:42 PM PDT 24
Peak memory 199712 kb
Host smart-f6fa288b-842c-4d80-a905-ad8004d648f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2476257753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2476257753
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.158386580
Short name T1129
Test name
Test status
Simulation time 6294669763 ps
CPU time 12.33 seconds
Started Aug 08 04:38:09 PM PDT 24
Finished Aug 08 04:38:22 PM PDT 24
Peak memory 198948 kb
Host smart-2d16c66d-4275-4d87-b3ff-4434ed6d8f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158386580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.158386580
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2625877002
Short name T1150
Test name
Test status
Simulation time 176809729123 ps
CPU time 37.5 seconds
Started Aug 08 04:38:09 PM PDT 24
Finished Aug 08 04:38:47 PM PDT 24
Peak memory 199952 kb
Host smart-9cc6b3de-3ee8-4f98-93d1-34809aee31b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625877002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2625877002
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.16367473
Short name T419
Test name
Test status
Simulation time 14663460828 ps
CPU time 57.03 seconds
Started Aug 08 04:38:12 PM PDT 24
Finished Aug 08 04:39:09 PM PDT 24
Peak memory 200140 kb
Host smart-3dc26712-49cb-4a22-892d-f195e5792976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16367473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.16367473
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1179776822
Short name T589
Test name
Test status
Simulation time 2793543147 ps
CPU time 3.08 seconds
Started Aug 08 04:38:11 PM PDT 24
Finished Aug 08 04:38:14 PM PDT 24
Peak memory 198616 kb
Host smart-29f2f5d8-5799-468b-b474-4d6ccca175cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1179776822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1179776822
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2269778222
Short name T618
Test name
Test status
Simulation time 92579674202 ps
CPU time 14.45 seconds
Started Aug 08 04:38:14 PM PDT 24
Finished Aug 08 04:38:29 PM PDT 24
Peak memory 199704 kb
Host smart-bc62089f-3083-4dc0-a60e-203aae8aebd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269778222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2269778222
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.890199030
Short name T930
Test name
Test status
Simulation time 3528423742 ps
CPU time 1.02 seconds
Started Aug 08 04:38:15 PM PDT 24
Finished Aug 08 04:38:16 PM PDT 24
Peak memory 196664 kb
Host smart-a7e11689-d752-4cf1-b7fc-dccbf4586341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890199030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.890199030
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3723779311
Short name T740
Test name
Test status
Simulation time 6067992957 ps
CPU time 20.34 seconds
Started Aug 08 04:38:09 PM PDT 24
Finished Aug 08 04:38:29 PM PDT 24
Peak memory 199688 kb
Host smart-2f600d7b-a5cc-468d-b6ba-856b85703e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723779311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3723779311
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.3232186164
Short name T432
Test name
Test status
Simulation time 221579701322 ps
CPU time 595.16 seconds
Started Aug 08 04:38:09 PM PDT 24
Finished Aug 08 04:48:05 PM PDT 24
Peak memory 199740 kb
Host smart-640e26cb-65e8-4348-b3f6-60f1c7f28636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232186164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3232186164
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2643795470
Short name T120
Test name
Test status
Simulation time 108270231720 ps
CPU time 327.35 seconds
Started Aug 08 04:38:10 PM PDT 24
Finished Aug 08 04:43:37 PM PDT 24
Peak memory 216320 kb
Host smart-fe918a9c-5e48-48e3-9bd9-140e90fb3ebc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643795470 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2643795470
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1450979099
Short name T855
Test name
Test status
Simulation time 655747056 ps
CPU time 2.44 seconds
Started Aug 08 04:38:10 PM PDT 24
Finished Aug 08 04:38:12 PM PDT 24
Peak memory 198176 kb
Host smart-7c3f1160-f42c-4ed1-ab44-01671ba38baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450979099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1450979099
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3242614003
Short name T1056
Test name
Test status
Simulation time 147302635503 ps
CPU time 30.7 seconds
Started Aug 08 04:38:10 PM PDT 24
Finished Aug 08 04:38:41 PM PDT 24
Peak memory 199844 kb
Host smart-d4d8b64f-a698-4e7d-b5cd-fcedb3635ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242614003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3242614003
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.3425941807
Short name T556
Test name
Test status
Simulation time 62595478 ps
CPU time 0.57 seconds
Started Aug 08 04:38:21 PM PDT 24
Finished Aug 08 04:38:22 PM PDT 24
Peak memory 195268 kb
Host smart-5aca2de2-1136-42b2-9f66-5cc3f180d322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425941807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.3425941807
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1164530579
Short name T791
Test name
Test status
Simulation time 151729083760 ps
CPU time 56.03 seconds
Started Aug 08 04:38:21 PM PDT 24
Finished Aug 08 04:39:17 PM PDT 24
Peak memory 199640 kb
Host smart-258df9dd-b7ce-4595-aa57-629081767c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164530579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1164530579
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.4177497202
Short name T259
Test name
Test status
Simulation time 133609630371 ps
CPU time 68.73 seconds
Started Aug 08 04:38:19 PM PDT 24
Finished Aug 08 04:39:27 PM PDT 24
Peak memory 199872 kb
Host smart-ce8a9c41-1821-443e-82b6-4524267cb4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177497202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.4177497202
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2724978702
Short name T863
Test name
Test status
Simulation time 20215030816 ps
CPU time 14.76 seconds
Started Aug 08 04:38:21 PM PDT 24
Finished Aug 08 04:38:36 PM PDT 24
Peak memory 198316 kb
Host smart-4b376a04-da15-4000-af5a-13129080c0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724978702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2724978702
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1740449210
Short name T527
Test name
Test status
Simulation time 48676631174 ps
CPU time 85.32 seconds
Started Aug 08 04:38:20 PM PDT 24
Finished Aug 08 04:39:46 PM PDT 24
Peak memory 199788 kb
Host smart-6342f08e-2176-48fa-9acd-56372d91e2a0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740449210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1740449210
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1872023065
Short name T298
Test name
Test status
Simulation time 75691203208 ps
CPU time 321.13 seconds
Started Aug 08 04:38:22 PM PDT 24
Finished Aug 08 04:43:43 PM PDT 24
Peak memory 199764 kb
Host smart-fb9c7b88-f3e4-4376-a352-1b978fba9510
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1872023065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1872023065
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.4011060551
Short name T371
Test name
Test status
Simulation time 2312013585 ps
CPU time 5.94 seconds
Started Aug 08 04:38:24 PM PDT 24
Finished Aug 08 04:38:30 PM PDT 24
Peak memory 198504 kb
Host smart-88a6cd22-d8ff-4d19-989b-2bd95b295286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011060551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.4011060551
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2250896352
Short name T774
Test name
Test status
Simulation time 197837083245 ps
CPU time 32.71 seconds
Started Aug 08 04:38:20 PM PDT 24
Finished Aug 08 04:38:53 PM PDT 24
Peak memory 199920 kb
Host smart-b0e11ce5-1792-4061-af51-9f1ee70fe783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250896352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2250896352
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3349157931
Short name T329
Test name
Test status
Simulation time 24109359024 ps
CPU time 335.4 seconds
Started Aug 08 04:38:24 PM PDT 24
Finished Aug 08 04:44:00 PM PDT 24
Peak memory 199720 kb
Host smart-97e2ad00-c6bd-4c00-9cb6-6ae6ce373933
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349157931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3349157931
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.325323092
Short name T797
Test name
Test status
Simulation time 6068711090 ps
CPU time 3.79 seconds
Started Aug 08 04:38:21 PM PDT 24
Finished Aug 08 04:38:25 PM PDT 24
Peak memory 197944 kb
Host smart-74bf6ca4-829c-45cf-ad97-cd089615769a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=325323092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.325323092
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.143787291
Short name T565
Test name
Test status
Simulation time 44141173861 ps
CPU time 62.29 seconds
Started Aug 08 04:38:21 PM PDT 24
Finished Aug 08 04:39:23 PM PDT 24
Peak memory 199788 kb
Host smart-68bab6e5-fab8-42ef-adf0-df77b97bbc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143787291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.143787291
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.775773230
Short name T1068
Test name
Test status
Simulation time 45220160003 ps
CPU time 19.51 seconds
Started Aug 08 04:38:23 PM PDT 24
Finished Aug 08 04:38:43 PM PDT 24
Peak memory 195644 kb
Host smart-8b5ebf60-d9d3-4fc7-8866-9ce6632f1e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775773230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.775773230
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3973086336
Short name T398
Test name
Test status
Simulation time 720901385 ps
CPU time 1.23 seconds
Started Aug 08 04:38:10 PM PDT 24
Finished Aug 08 04:38:12 PM PDT 24
Peak memory 199484 kb
Host smart-276ee361-bf51-436a-b739-d2948f0421d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973086336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3973086336
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.3890727198
Short name T338
Test name
Test status
Simulation time 40920204971 ps
CPU time 175.97 seconds
Started Aug 08 04:38:21 PM PDT 24
Finished Aug 08 04:41:17 PM PDT 24
Peak memory 216460 kb
Host smart-6633c052-5b81-4f3a-b7c0-fbf76e057b59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890727198 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.3890727198
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3210564868
Short name T1076
Test name
Test status
Simulation time 6650457575 ps
CPU time 16.16 seconds
Started Aug 08 04:38:21 PM PDT 24
Finished Aug 08 04:38:37 PM PDT 24
Peak memory 199748 kb
Host smart-bde8fcc0-5676-4c0c-ae77-b4f040bfc24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210564868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3210564868
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1131087720
Short name T940
Test name
Test status
Simulation time 24471933793 ps
CPU time 9.26 seconds
Started Aug 08 04:38:13 PM PDT 24
Finished Aug 08 04:38:22 PM PDT 24
Peak memory 196904 kb
Host smart-45146ddd-d5ac-45bc-93b2-61c56c96a07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131087720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1131087720
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.465526775
Short name T482
Test name
Test status
Simulation time 27146679 ps
CPU time 0.58 seconds
Started Aug 08 04:32:37 PM PDT 24
Finished Aug 08 04:32:38 PM PDT 24
Peak memory 195172 kb
Host smart-97d978a9-13c4-4c11-8465-7c42016a9273
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465526775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.465526775
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1157025817
Short name T529
Test name
Test status
Simulation time 43634820969 ps
CPU time 72.08 seconds
Started Aug 08 04:32:23 PM PDT 24
Finished Aug 08 04:33:35 PM PDT 24
Peak memory 199772 kb
Host smart-3abc0c47-bb45-4ea9-9a96-d771aad6af3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157025817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1157025817
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.855029482
Short name T513
Test name
Test status
Simulation time 47076870381 ps
CPU time 19.33 seconds
Started Aug 08 04:32:23 PM PDT 24
Finished Aug 08 04:32:42 PM PDT 24
Peak memory 199716 kb
Host smart-97b8f65b-82b4-4741-b325-512f07f2958c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855029482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.855029482
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2901091657
Short name T586
Test name
Test status
Simulation time 147809660022 ps
CPU time 234.01 seconds
Started Aug 08 04:32:24 PM PDT 24
Finished Aug 08 04:36:18 PM PDT 24
Peak memory 199744 kb
Host smart-5c7476c6-5cb8-441c-a5c6-f32ffc85200c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901091657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2901091657
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1708140792
Short name T404
Test name
Test status
Simulation time 113814131765 ps
CPU time 53.84 seconds
Started Aug 08 04:32:37 PM PDT 24
Finished Aug 08 04:33:31 PM PDT 24
Peak memory 199732 kb
Host smart-44dca51b-31d1-477b-b61e-b904b90052ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708140792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1708140792
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3605423916
Short name T385
Test name
Test status
Simulation time 206490963309 ps
CPU time 367.19 seconds
Started Aug 08 04:32:36 PM PDT 24
Finished Aug 08 04:38:44 PM PDT 24
Peak memory 199668 kb
Host smart-a5f0746a-d5e2-4379-b26c-faf23b2803ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3605423916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3605423916
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1855309211
Short name T841
Test name
Test status
Simulation time 4916416767 ps
CPU time 8.98 seconds
Started Aug 08 04:32:38 PM PDT 24
Finished Aug 08 04:32:47 PM PDT 24
Peak memory 198232 kb
Host smart-bf05b981-190b-4be4-b76e-77aeef022361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855309211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1855309211
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.718607392
Short name T640
Test name
Test status
Simulation time 32004820983 ps
CPU time 47.9 seconds
Started Aug 08 04:32:34 PM PDT 24
Finished Aug 08 04:33:22 PM PDT 24
Peak memory 199068 kb
Host smart-73463c26-8093-4f7d-baab-f949676899b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718607392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.718607392
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.1121924772
Short name T301
Test name
Test status
Simulation time 16278355394 ps
CPU time 370.75 seconds
Started Aug 08 04:32:35 PM PDT 24
Finished Aug 08 04:38:46 PM PDT 24
Peak memory 199804 kb
Host smart-36ccf37f-0ab6-43d5-bef0-cac4cb223d55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1121924772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1121924772
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1842295933
Short name T998
Test name
Test status
Simulation time 2104476060 ps
CPU time 12.08 seconds
Started Aug 08 04:32:23 PM PDT 24
Finished Aug 08 04:32:35 PM PDT 24
Peak memory 197800 kb
Host smart-9e325d76-2fb6-452c-b071-47b340c9aae2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1842295933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1842295933
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.178934921
Short name T406
Test name
Test status
Simulation time 27534715929 ps
CPU time 33.63 seconds
Started Aug 08 04:32:39 PM PDT 24
Finished Aug 08 04:33:12 PM PDT 24
Peak memory 199756 kb
Host smart-fb2925ab-f9fb-465c-ad0c-4ee40ec415a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178934921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.178934921
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2537882868
Short name T465
Test name
Test status
Simulation time 2636512012 ps
CPU time 4.88 seconds
Started Aug 08 04:32:36 PM PDT 24
Finished Aug 08 04:32:41 PM PDT 24
Peak memory 196428 kb
Host smart-58361c50-e657-43d9-869e-3b2884fbd136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537882868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2537882868
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.436385548
Short name T1028
Test name
Test status
Simulation time 6354960699 ps
CPU time 4.8 seconds
Started Aug 08 04:32:26 PM PDT 24
Finished Aug 08 04:32:31 PM PDT 24
Peak memory 199708 kb
Host smart-e651982f-76fa-4745-a469-89a17a71330c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436385548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.436385548
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3212171722
Short name T461
Test name
Test status
Simulation time 212328487723 ps
CPU time 181.94 seconds
Started Aug 08 04:32:38 PM PDT 24
Finished Aug 08 04:35:40 PM PDT 24
Peak memory 208188 kb
Host smart-f47bbc90-5a42-4e39-aab0-5d95fdc4192f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212171722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3212171722
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2174660710
Short name T848
Test name
Test status
Simulation time 7163168088 ps
CPU time 7.66 seconds
Started Aug 08 04:32:36 PM PDT 24
Finished Aug 08 04:32:44 PM PDT 24
Peak memory 199452 kb
Host smart-91a801be-26c1-4f46-a8e9-9b55346088e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174660710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2174660710
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3775824536
Short name T1105
Test name
Test status
Simulation time 80857873862 ps
CPU time 15.55 seconds
Started Aug 08 04:32:23 PM PDT 24
Finished Aug 08 04:32:39 PM PDT 24
Peak memory 199848 kb
Host smart-14c0e8c5-ad12-4e7b-b79e-a2fd2d84c32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775824536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3775824536
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1634225445
Short name T644
Test name
Test status
Simulation time 31854793485 ps
CPU time 13.63 seconds
Started Aug 08 04:38:21 PM PDT 24
Finished Aug 08 04:38:35 PM PDT 24
Peak memory 199680 kb
Host smart-13037032-fc72-4845-a288-795354c0ea35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634225445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1634225445
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.2130641144
Short name T29
Test name
Test status
Simulation time 31359242472 ps
CPU time 560.35 seconds
Started Aug 08 04:38:20 PM PDT 24
Finished Aug 08 04:47:41 PM PDT 24
Peak memory 216380 kb
Host smart-a1f7a105-c749-4f6b-a271-0054f235cfdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130641144 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.2130641144
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.303449013
Short name T1036
Test name
Test status
Simulation time 91520986879 ps
CPU time 66.35 seconds
Started Aug 08 04:38:22 PM PDT 24
Finished Aug 08 04:39:28 PM PDT 24
Peak memory 199700 kb
Host smart-729766e0-f9bd-4e4f-9972-7d9e89eb6bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303449013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.303449013
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1114387512
Short name T604
Test name
Test status
Simulation time 109048741268 ps
CPU time 790.27 seconds
Started Aug 08 04:38:22 PM PDT 24
Finished Aug 08 04:51:32 PM PDT 24
Peak memory 214940 kb
Host smart-fcc3c759-89aa-4f4b-b9ea-0705acf3e515
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114387512 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1114387512
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.448315943
Short name T946
Test name
Test status
Simulation time 28254015489 ps
CPU time 23.51 seconds
Started Aug 08 04:38:22 PM PDT 24
Finished Aug 08 04:38:45 PM PDT 24
Peak memory 199740 kb
Host smart-2683d6e0-5098-4ed7-8b41-52bdcce8f15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448315943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.448315943
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3245654227
Short name T54
Test name
Test status
Simulation time 71430139382 ps
CPU time 416.16 seconds
Started Aug 08 04:38:20 PM PDT 24
Finished Aug 08 04:45:16 PM PDT 24
Peak memory 216468 kb
Host smart-b49a7997-32a2-4279-b3e7-08b154cc14e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245654227 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3245654227
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.643515353
Short name T112
Test name
Test status
Simulation time 76338154235 ps
CPU time 57.02 seconds
Started Aug 08 04:38:33 PM PDT 24
Finished Aug 08 04:39:31 PM PDT 24
Peak memory 199744 kb
Host smart-8a7d7a49-2820-454b-bb08-86279f75b39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643515353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.643515353
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1168038605
Short name T628
Test name
Test status
Simulation time 171713352106 ps
CPU time 1165.63 seconds
Started Aug 08 04:38:31 PM PDT 24
Finished Aug 08 04:57:57 PM PDT 24
Peak memory 224652 kb
Host smart-428eeb51-54f0-46a2-8055-f0e06fe09b76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168038605 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1168038605
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.4174545452
Short name T1081
Test name
Test status
Simulation time 17417663673 ps
CPU time 12.6 seconds
Started Aug 08 04:38:31 PM PDT 24
Finished Aug 08 04:38:44 PM PDT 24
Peak memory 199756 kb
Host smart-e8505479-668b-4d54-a5a4-a44a45151d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174545452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.4174545452
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2759011009
Short name T754
Test name
Test status
Simulation time 706405050355 ps
CPU time 670.5 seconds
Started Aug 08 04:38:33 PM PDT 24
Finished Aug 08 04:49:44 PM PDT 24
Peak memory 230044 kb
Host smart-0c924e9d-b3a8-41fa-8cf4-d8ce8adb9594
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759011009 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2759011009
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3805886803
Short name T995
Test name
Test status
Simulation time 366674062788 ps
CPU time 48.14 seconds
Started Aug 08 04:38:33 PM PDT 24
Finished Aug 08 04:39:21 PM PDT 24
Peak memory 199812 kb
Host smart-53505652-0ec9-4fa1-9a20-f8440f21380b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805886803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3805886803
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3370142271
Short name T105
Test name
Test status
Simulation time 46714851220 ps
CPU time 511.28 seconds
Started Aug 08 04:38:35 PM PDT 24
Finished Aug 08 04:47:06 PM PDT 24
Peak memory 216432 kb
Host smart-f140baca-9581-4fba-b637-e00aff1263fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370142271 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3370142271
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2006242567
Short name T1120
Test name
Test status
Simulation time 63462132537 ps
CPU time 30.55 seconds
Started Aug 08 04:38:39 PM PDT 24
Finished Aug 08 04:39:10 PM PDT 24
Peak memory 199760 kb
Host smart-ba13adc7-f86b-4b2e-b4b8-5be0fee6a405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006242567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2006242567
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1143061442
Short name T27
Test name
Test status
Simulation time 15506416344 ps
CPU time 20.73 seconds
Started Aug 08 04:38:34 PM PDT 24
Finished Aug 08 04:38:55 PM PDT 24
Peak memory 208184 kb
Host smart-685df04b-816c-4e46-80b5-7d300e83ae76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143061442 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1143061442
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.559052865
Short name T507
Test name
Test status
Simulation time 61423148206 ps
CPU time 28.4 seconds
Started Aug 08 04:38:34 PM PDT 24
Finished Aug 08 04:39:02 PM PDT 24
Peak memory 199820 kb
Host smart-95798de1-bae7-4bb8-9056-e03ba06602c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559052865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.559052865
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2742857339
Short name T725
Test name
Test status
Simulation time 200357897101 ps
CPU time 317.5 seconds
Started Aug 08 04:38:33 PM PDT 24
Finished Aug 08 04:43:51 PM PDT 24
Peak memory 208108 kb
Host smart-2dd85e2b-4d2c-4c7a-bdf4-7e1119ae40bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742857339 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2742857339
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3219029410
Short name T563
Test name
Test status
Simulation time 121511934430 ps
CPU time 165.43 seconds
Started Aug 08 04:38:34 PM PDT 24
Finished Aug 08 04:41:20 PM PDT 24
Peak memory 199608 kb
Host smart-0d84d93a-e58f-478a-a211-16d45f8ec3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219029410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3219029410
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3079955634
Short name T645
Test name
Test status
Simulation time 48989327963 ps
CPU time 290.95 seconds
Started Aug 08 04:38:33 PM PDT 24
Finished Aug 08 04:43:24 PM PDT 24
Peak memory 215860 kb
Host smart-c5b5c1fa-9f6a-41f6-83c0-14b2534e21e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079955634 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3079955634
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1964139900
Short name T907
Test name
Test status
Simulation time 70690965739 ps
CPU time 25.34 seconds
Started Aug 08 04:38:31 PM PDT 24
Finished Aug 08 04:38:56 PM PDT 24
Peak memory 199760 kb
Host smart-c93d8060-1c23-4e75-b25f-e08c2d33dcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964139900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1964139900
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3222812311
Short name T749
Test name
Test status
Simulation time 20607382 ps
CPU time 0.55 seconds
Started Aug 08 04:32:38 PM PDT 24
Finished Aug 08 04:32:39 PM PDT 24
Peak memory 195200 kb
Host smart-1728b902-4595-409e-a470-65868db03c69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222812311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3222812311
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1020061325
Short name T588
Test name
Test status
Simulation time 140977378759 ps
CPU time 59.18 seconds
Started Aug 08 04:32:37 PM PDT 24
Finished Aug 08 04:33:36 PM PDT 24
Peak memory 199772 kb
Host smart-b2e361a9-cd5a-49f8-a308-5aa7d0b575c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020061325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1020061325
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1860369694
Short name T742
Test name
Test status
Simulation time 98045335297 ps
CPU time 44.63 seconds
Started Aug 08 04:32:35 PM PDT 24
Finished Aug 08 04:33:20 PM PDT 24
Peak memory 199732 kb
Host smart-00be385a-f7f4-4729-9659-48c43544b5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860369694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1860369694
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1085777501
Short name T842
Test name
Test status
Simulation time 74383075977 ps
CPU time 24.94 seconds
Started Aug 08 04:32:37 PM PDT 24
Finished Aug 08 04:33:02 PM PDT 24
Peak memory 199504 kb
Host smart-0e1fa217-923a-4155-bfc2-9e933e9f4e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085777501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1085777501
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.4236576670
Short name T523
Test name
Test status
Simulation time 34338977962 ps
CPU time 44.98 seconds
Started Aug 08 04:32:38 PM PDT 24
Finished Aug 08 04:33:23 PM PDT 24
Peak memory 199792 kb
Host smart-a962a83b-0870-4fa1-b31e-c39a7b957eca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236576670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.4236576670
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1577910678
Short name T890
Test name
Test status
Simulation time 48847340603 ps
CPU time 216.1 seconds
Started Aug 08 04:32:38 PM PDT 24
Finished Aug 08 04:36:14 PM PDT 24
Peak memory 199780 kb
Host smart-3d150c56-11e2-48de-b781-e31fda85460f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1577910678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1577910678
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.576885048
Short name T1125
Test name
Test status
Simulation time 9701988359 ps
CPU time 18.83 seconds
Started Aug 08 04:32:38 PM PDT 24
Finished Aug 08 04:32:57 PM PDT 24
Peak memory 199632 kb
Host smart-6d95999f-18ac-452c-9762-5902552f8f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576885048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.576885048
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1242086405
Short name T646
Test name
Test status
Simulation time 47545249399 ps
CPU time 41.61 seconds
Started Aug 08 04:32:40 PM PDT 24
Finished Aug 08 04:33:22 PM PDT 24
Peak memory 199204 kb
Host smart-320bafe8-ed1e-4aac-9795-064fa12efc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242086405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1242086405
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.3270744289
Short name T1054
Test name
Test status
Simulation time 622663296 ps
CPU time 4.14 seconds
Started Aug 08 04:32:38 PM PDT 24
Finished Aug 08 04:32:42 PM PDT 24
Peak memory 199680 kb
Host smart-0853e016-34ac-41d9-abb9-74c275a494dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3270744289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3270744289
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2256631227
Short name T1021
Test name
Test status
Simulation time 1707216288 ps
CPU time 1.93 seconds
Started Aug 08 04:32:37 PM PDT 24
Finished Aug 08 04:32:39 PM PDT 24
Peak memory 197740 kb
Host smart-8b9461f2-0b2f-4587-b95d-7cf40f5cbb56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2256631227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2256631227
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.4022552184
Short name T1086
Test name
Test status
Simulation time 121803758692 ps
CPU time 115.77 seconds
Started Aug 08 04:32:38 PM PDT 24
Finished Aug 08 04:34:34 PM PDT 24
Peak memory 199712 kb
Host smart-a0738286-2d6d-4806-832f-32f28ed22605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022552184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.4022552184
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.874305444
Short name T958
Test name
Test status
Simulation time 1236192599 ps
CPU time 2.35 seconds
Started Aug 08 04:32:36 PM PDT 24
Finished Aug 08 04:32:39 PM PDT 24
Peak memory 195428 kb
Host smart-36757c66-cf06-47a3-9350-eec5aa6a80fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874305444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.874305444
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3033719676
Short name T50
Test name
Test status
Simulation time 497506714 ps
CPU time 1.59 seconds
Started Aug 08 04:32:38 PM PDT 24
Finished Aug 08 04:32:39 PM PDT 24
Peak memory 198352 kb
Host smart-1f858ad0-e3c3-4ac0-9dad-66b06d131245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033719676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3033719676
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.3581939904
Short name T1066
Test name
Test status
Simulation time 554319313517 ps
CPU time 481.67 seconds
Started Aug 08 04:32:40 PM PDT 24
Finished Aug 08 04:40:42 PM PDT 24
Peak memory 215416 kb
Host smart-f9ec086a-a880-4e9e-8c1d-d2b07bbbe964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581939904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3581939904
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3577769377
Short name T821
Test name
Test status
Simulation time 187630950019 ps
CPU time 187.2 seconds
Started Aug 08 04:32:40 PM PDT 24
Finished Aug 08 04:35:48 PM PDT 24
Peak memory 214712 kb
Host smart-86472070-6e88-4e85-931a-c8db3246ddfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577769377 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3577769377
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2867088452
Short name T999
Test name
Test status
Simulation time 6115892139 ps
CPU time 16.7 seconds
Started Aug 08 04:32:36 PM PDT 24
Finished Aug 08 04:32:53 PM PDT 24
Peak memory 199692 kb
Host smart-f0c926d9-1656-405f-ae4f-e7324f6614cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867088452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2867088452
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.34968250
Short name T971
Test name
Test status
Simulation time 78742612362 ps
CPU time 117.31 seconds
Started Aug 08 04:32:37 PM PDT 24
Finished Aug 08 04:34:34 PM PDT 24
Peak memory 199756 kb
Host smart-78916e86-635e-4143-8575-80f3e278fe3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34968250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.34968250
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2242173329
Short name T221
Test name
Test status
Simulation time 113346502718 ps
CPU time 152.34 seconds
Started Aug 08 04:38:32 PM PDT 24
Finished Aug 08 04:41:04 PM PDT 24
Peak memory 199864 kb
Host smart-94abf646-b7d6-41ff-aaa9-198d0fad3694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242173329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2242173329
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1932001254
Short name T1031
Test name
Test status
Simulation time 42140203204 ps
CPU time 587.49 seconds
Started Aug 08 04:38:33 PM PDT 24
Finished Aug 08 04:48:21 PM PDT 24
Peak memory 225148 kb
Host smart-af21cbab-6ec3-4c33-abc1-98f85ee3d683
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932001254 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1932001254
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3266847836
Short name T611
Test name
Test status
Simulation time 11523997973 ps
CPU time 17.67 seconds
Started Aug 08 04:38:36 PM PDT 24
Finished Aug 08 04:38:54 PM PDT 24
Peak memory 199804 kb
Host smart-8c3be957-32cd-464f-9a3f-58bed05ca441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266847836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3266847836
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.421286165
Short name T1124
Test name
Test status
Simulation time 62338627043 ps
CPU time 678.78 seconds
Started Aug 08 04:38:33 PM PDT 24
Finished Aug 08 04:49:52 PM PDT 24
Peak memory 216252 kb
Host smart-f0e19482-0865-4729-a711-2245581bdfc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421286165 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.421286165
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3772261247
Short name T649
Test name
Test status
Simulation time 84132313960 ps
CPU time 33.92 seconds
Started Aug 08 04:38:31 PM PDT 24
Finished Aug 08 04:39:05 PM PDT 24
Peak memory 199800 kb
Host smart-9ef5bbc8-200d-443c-87b0-adff15b5611e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772261247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3772261247
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1406022430
Short name T1060
Test name
Test status
Simulation time 141632814770 ps
CPU time 557.08 seconds
Started Aug 08 04:38:33 PM PDT 24
Finished Aug 08 04:47:50 PM PDT 24
Peak memory 215176 kb
Host smart-444e94d3-4b16-4bc3-a10b-a9199eb70db3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406022430 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1406022430
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.1448312321
Short name T1175
Test name
Test status
Simulation time 129942933420 ps
CPU time 71.12 seconds
Started Aug 08 04:38:33 PM PDT 24
Finished Aug 08 04:39:44 PM PDT 24
Peak memory 199784 kb
Host smart-81cf7c2a-bff3-4fe8-9796-12240de08354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448312321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1448312321
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3594442828
Short name T142
Test name
Test status
Simulation time 72565146136 ps
CPU time 367.49 seconds
Started Aug 08 04:38:34 PM PDT 24
Finished Aug 08 04:44:41 PM PDT 24
Peak memory 216384 kb
Host smart-5e114b95-f461-4be8-99b5-602ea74a9039
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594442828 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3594442828
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1159454945
Short name T179
Test name
Test status
Simulation time 97233627372 ps
CPU time 41.03 seconds
Started Aug 08 04:38:34 PM PDT 24
Finished Aug 08 04:39:15 PM PDT 24
Peak memory 199724 kb
Host smart-8ba5d209-cf00-4f0a-8361-867b6305935e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159454945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1159454945
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.1509705840
Short name T560
Test name
Test status
Simulation time 14889855086 ps
CPU time 260.88 seconds
Started Aug 08 04:38:33 PM PDT 24
Finished Aug 08 04:42:54 PM PDT 24
Peak memory 210572 kb
Host smart-8f6fe446-f54b-4e63-8944-cad0c3a1e4c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509705840 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1509705840
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1701545498
Short name T768
Test name
Test status
Simulation time 35824710499 ps
CPU time 20.78 seconds
Started Aug 08 04:39:03 PM PDT 24
Finished Aug 08 04:39:24 PM PDT 24
Peak memory 199756 kb
Host smart-719f1ed0-b0fd-4261-b8ed-8dfd2e905c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701545498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1701545498
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.1033801753
Short name T533
Test name
Test status
Simulation time 153894645989 ps
CPU time 255.45 seconds
Started Aug 08 04:38:43 PM PDT 24
Finished Aug 08 04:42:58 PM PDT 24
Peak memory 199760 kb
Host smart-1d6288c4-a1c0-4c77-8569-90684aa5e0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033801753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1033801753
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2299773447
Short name T622
Test name
Test status
Simulation time 429648312317 ps
CPU time 697.65 seconds
Started Aug 08 04:38:46 PM PDT 24
Finished Aug 08 04:50:24 PM PDT 24
Peak memory 224652 kb
Host smart-f868e4bb-a9eb-41ce-a3d7-989501d44ec5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299773447 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2299773447
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.5494382
Short name T601
Test name
Test status
Simulation time 25096122685 ps
CPU time 10.09 seconds
Started Aug 08 04:38:43 PM PDT 24
Finished Aug 08 04:38:53 PM PDT 24
Peak memory 199764 kb
Host smart-27e2e3ea-798c-426c-b0b9-f68c4d851951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5494382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.5494382
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.1996025932
Short name T854
Test name
Test status
Simulation time 54724624933 ps
CPU time 704.99 seconds
Started Aug 08 04:39:02 PM PDT 24
Finished Aug 08 04:50:47 PM PDT 24
Peak memory 216352 kb
Host smart-8368b18b-79c2-4566-bc03-82458d591639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996025932 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1996025932
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.594419379
Short name T735
Test name
Test status
Simulation time 39930389 ps
CPU time 0.57 seconds
Started Aug 08 04:32:52 PM PDT 24
Finished Aug 08 04:32:53 PM PDT 24
Peak memory 195216 kb
Host smart-1742d6fd-5ca6-4c2b-a28d-1b738a45946a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594419379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.594419379
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.4281869727
Short name T577
Test name
Test status
Simulation time 79608614741 ps
CPU time 62.1 seconds
Started Aug 08 04:32:40 PM PDT 24
Finished Aug 08 04:33:42 PM PDT 24
Peak memory 199764 kb
Host smart-24b0ea81-8609-494e-b99d-f52a9197ea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281869727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.4281869727
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2081451874
Short name T838
Test name
Test status
Simulation time 11839359045 ps
CPU time 25.5 seconds
Started Aug 08 04:32:41 PM PDT 24
Finished Aug 08 04:33:06 PM PDT 24
Peak memory 199852 kb
Host smart-408f2424-cca9-49ae-8f78-bf2ab94dec02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081451874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2081451874
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2493765653
Short name T344
Test name
Test status
Simulation time 80459801682 ps
CPU time 117.69 seconds
Started Aug 08 04:32:39 PM PDT 24
Finished Aug 08 04:34:37 PM PDT 24
Peak memory 199680 kb
Host smart-14ffaad3-1fb0-4c3a-8203-b2c1192bf19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493765653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2493765653
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1567142958
Short name T932
Test name
Test status
Simulation time 21858368148 ps
CPU time 16.97 seconds
Started Aug 08 04:32:37 PM PDT 24
Finished Aug 08 04:32:54 PM PDT 24
Peak memory 199588 kb
Host smart-4b846805-e144-4535-a34d-5a1a03ff05c6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567142958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1567142958
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.2991499955
Short name T720
Test name
Test status
Simulation time 91338064946 ps
CPU time 176.98 seconds
Started Aug 08 04:32:53 PM PDT 24
Finished Aug 08 04:35:50 PM PDT 24
Peak memory 199748 kb
Host smart-64e97de9-1a7b-4c57-8fca-feba26d165e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2991499955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2991499955
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3526501663
Short name T387
Test name
Test status
Simulation time 9670445274 ps
CPU time 9.59 seconds
Started Aug 08 04:32:51 PM PDT 24
Finished Aug 08 04:33:01 PM PDT 24
Peak memory 199316 kb
Host smart-d829874e-e36e-4b92-874b-4b0073c12b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526501663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3526501663
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.3746079906
Short name T394
Test name
Test status
Simulation time 109023599233 ps
CPU time 84.52 seconds
Started Aug 08 04:32:51 PM PDT 24
Finished Aug 08 04:34:16 PM PDT 24
Peak memory 199016 kb
Host smart-03804e9c-fd01-4e52-a4d3-5d04799987e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746079906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3746079906
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.3626430263
Short name T1064
Test name
Test status
Simulation time 19443942849 ps
CPU time 182.28 seconds
Started Aug 08 04:32:51 PM PDT 24
Finished Aug 08 04:35:54 PM PDT 24
Peak memory 199668 kb
Host smart-c284fa36-5540-4cf2-9794-6f5a7c159d64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3626430263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3626430263
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.356561478
Short name T785
Test name
Test status
Simulation time 6819979777 ps
CPU time 12.83 seconds
Started Aug 08 04:32:39 PM PDT 24
Finished Aug 08 04:32:52 PM PDT 24
Peak memory 197960 kb
Host smart-170e76d0-44fd-4f4b-9392-fb7dc688ef6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=356561478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.356561478
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.695054253
Short name T685
Test name
Test status
Simulation time 70170765838 ps
CPU time 33.66 seconds
Started Aug 08 04:32:52 PM PDT 24
Finished Aug 08 04:33:26 PM PDT 24
Peak memory 199776 kb
Host smart-64a85704-bb7e-4ee2-b3bf-48a4a2bda21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695054253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.695054253
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1994081244
Short name T352
Test name
Test status
Simulation time 2743631259 ps
CPU time 0.98 seconds
Started Aug 08 04:32:51 PM PDT 24
Finished Aug 08 04:32:53 PM PDT 24
Peak memory 195848 kb
Host smart-f2573b2f-37d9-4500-871b-e2922e53de89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994081244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1994081244
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1189417240
Short name T714
Test name
Test status
Simulation time 300278918 ps
CPU time 1.17 seconds
Started Aug 08 04:32:40 PM PDT 24
Finished Aug 08 04:32:42 PM PDT 24
Peak memory 198280 kb
Host smart-68c1c65e-f30e-405f-927f-d2d67ec38ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189417240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1189417240
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2645955205
Short name T979
Test name
Test status
Simulation time 113703574389 ps
CPU time 12.35 seconds
Started Aug 08 04:32:50 PM PDT 24
Finished Aug 08 04:33:03 PM PDT 24
Peak memory 199900 kb
Host smart-ab78d7d5-3942-4dcc-bdb4-e8ca6660985d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645955205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2645955205
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.1168017538
Short name T936
Test name
Test status
Simulation time 406022102223 ps
CPU time 740.09 seconds
Started Aug 08 04:32:53 PM PDT 24
Finished Aug 08 04:45:13 PM PDT 24
Peak memory 216412 kb
Host smart-d93ed885-9a6e-420b-83ca-b208a388737c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168017538 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1168017538
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3488785422
Short name T103
Test name
Test status
Simulation time 6786264859 ps
CPU time 19.44 seconds
Started Aug 08 04:32:54 PM PDT 24
Finished Aug 08 04:33:14 PM PDT 24
Peak memory 199696 kb
Host smart-e7260a74-9d4c-4a60-8b9b-8a224c6fbe9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488785422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3488785422
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2717432661
Short name T719
Test name
Test status
Simulation time 133061433641 ps
CPU time 42.36 seconds
Started Aug 08 04:32:38 PM PDT 24
Finished Aug 08 04:33:20 PM PDT 24
Peak memory 199824 kb
Host smart-77222900-a421-4031-a80a-9dccae3de06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717432661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2717432661
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1661746334
Short name T1020
Test name
Test status
Simulation time 103209231376 ps
CPU time 96.45 seconds
Started Aug 08 04:38:44 PM PDT 24
Finished Aug 08 04:40:21 PM PDT 24
Peak memory 199728 kb
Host smart-83bcd693-a20f-4821-8445-bef0e5009d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661746334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1661746334
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2917524533
Short name T60
Test name
Test status
Simulation time 48630633917 ps
CPU time 683.53 seconds
Started Aug 08 04:38:44 PM PDT 24
Finished Aug 08 04:50:07 PM PDT 24
Peak memory 213396 kb
Host smart-44d2dd62-4f43-4fde-a2f5-c8df30d94a50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917524533 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2917524533
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3921127100
Short name T208
Test name
Test status
Simulation time 34345869813 ps
CPU time 47.1 seconds
Started Aug 08 04:38:43 PM PDT 24
Finished Aug 08 04:39:30 PM PDT 24
Peak memory 199780 kb
Host smart-05d7bb96-e6bb-4bdd-a871-3b267222f678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921127100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3921127100
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1776700556
Short name T776
Test name
Test status
Simulation time 93564631043 ps
CPU time 528.3 seconds
Started Aug 08 04:38:45 PM PDT 24
Finished Aug 08 04:47:33 PM PDT 24
Peak memory 225924 kb
Host smart-9a016694-4863-43bc-b6cd-ce791f17b4d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776700556 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1776700556
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.103938250
Short name T220
Test name
Test status
Simulation time 83612323854 ps
CPU time 37.4 seconds
Started Aug 08 04:38:44 PM PDT 24
Finished Aug 08 04:39:22 PM PDT 24
Peak memory 199728 kb
Host smart-535f4767-1e5e-4620-ad0b-0088650df4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103938250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.103938250
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1098138964
Short name T893
Test name
Test status
Simulation time 48056622923 ps
CPU time 188.4 seconds
Started Aug 08 04:38:43 PM PDT 24
Finished Aug 08 04:41:52 PM PDT 24
Peak memory 208120 kb
Host smart-0c6d7aea-80be-4d83-8020-1a65084d9f86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098138964 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1098138964
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3329240630
Short name T193
Test name
Test status
Simulation time 18889354701 ps
CPU time 14.7 seconds
Started Aug 08 04:38:52 PM PDT 24
Finished Aug 08 04:39:07 PM PDT 24
Peak memory 199756 kb
Host smart-6eee6fbf-f620-4ca3-862c-851091fadaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329240630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3329240630
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3485252028
Short name T223
Test name
Test status
Simulation time 21710948991 ps
CPU time 31.84 seconds
Started Aug 08 04:38:45 PM PDT 24
Finished Aug 08 04:39:17 PM PDT 24
Peak memory 199792 kb
Host smart-39ee020d-9ea1-4cd5-9a77-137c3d30c92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485252028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3485252028
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1148101561
Short name T984
Test name
Test status
Simulation time 231010974162 ps
CPU time 430.26 seconds
Started Aug 08 04:39:06 PM PDT 24
Finished Aug 08 04:46:16 PM PDT 24
Peak memory 216236 kb
Host smart-9ffef43d-6723-4b39-a91e-0b69a2a44bc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148101561 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1148101561
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2044191701
Short name T245
Test name
Test status
Simulation time 58231817304 ps
CPU time 25.66 seconds
Started Aug 08 04:38:48 PM PDT 24
Finished Aug 08 04:39:13 PM PDT 24
Peak memory 199836 kb
Host smart-1ab6da40-03a1-4a76-ae99-d1e178faff42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044191701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2044191701
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3079950415
Short name T955
Test name
Test status
Simulation time 165989785176 ps
CPU time 1557.77 seconds
Started Aug 08 04:38:48 PM PDT 24
Finished Aug 08 05:04:46 PM PDT 24
Peak memory 224668 kb
Host smart-69f43ddb-ee75-4e1d-9da7-4afc91fc9358
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079950415 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3079950415
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.922810318
Short name T238
Test name
Test status
Simulation time 30898320611 ps
CPU time 20.66 seconds
Started Aug 08 04:38:43 PM PDT 24
Finished Aug 08 04:39:04 PM PDT 24
Peak memory 199764 kb
Host smart-fd7f1289-6ba6-410a-ac34-dca392772667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922810318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.922810318
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.291257674
Short name T472
Test name
Test status
Simulation time 352497821105 ps
CPU time 946.49 seconds
Started Aug 08 04:38:45 PM PDT 24
Finished Aug 08 04:54:31 PM PDT 24
Peak memory 216576 kb
Host smart-8a5d4daa-93e0-4923-a8dc-7833a83fe57c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291257674 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.291257674
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.915581753
Short name T168
Test name
Test status
Simulation time 119908803346 ps
CPU time 187.19 seconds
Started Aug 08 04:39:00 PM PDT 24
Finished Aug 08 04:42:07 PM PDT 24
Peak memory 199636 kb
Host smart-09e748eb-96a8-47e2-a256-013aabe10559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915581753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.915581753
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.4034632274
Short name T949
Test name
Test status
Simulation time 574377436407 ps
CPU time 1654.53 seconds
Started Aug 08 04:39:00 PM PDT 24
Finished Aug 08 05:06:35 PM PDT 24
Peak memory 224432 kb
Host smart-447acca6-dae9-4de3-ad7f-bfdaf102ef57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034632274 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.4034632274
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.176831831
Short name T748
Test name
Test status
Simulation time 27651532529 ps
CPU time 12.08 seconds
Started Aug 08 04:38:43 PM PDT 24
Finished Aug 08 04:38:55 PM PDT 24
Peak memory 199540 kb
Host smart-6c844c24-b267-4a1f-be62-851e7f4d91d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176831831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.176831831
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.919081027
Short name T386
Test name
Test status
Simulation time 13298803 ps
CPU time 0.56 seconds
Started Aug 08 04:32:51 PM PDT 24
Finished Aug 08 04:32:52 PM PDT 24
Peak memory 195140 kb
Host smart-5bc5ea31-ca38-48ea-932b-76584b854e51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919081027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.919081027
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2073317067
Short name T983
Test name
Test status
Simulation time 31119258512 ps
CPU time 23.86 seconds
Started Aug 08 04:32:51 PM PDT 24
Finished Aug 08 04:33:15 PM PDT 24
Peak memory 199760 kb
Host smart-c1759308-e9e1-41f9-8c8c-8945ed4bf930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073317067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2073317067
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2685479650
Short name T752
Test name
Test status
Simulation time 88615335953 ps
CPU time 55.11 seconds
Started Aug 08 04:32:52 PM PDT 24
Finished Aug 08 04:33:47 PM PDT 24
Peak memory 199700 kb
Host smart-f743f08a-3a64-4363-9cb2-f7bdd3e12b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685479650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2685479650
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2150249640
Short name T1139
Test name
Test status
Simulation time 24094797931 ps
CPU time 26.52 seconds
Started Aug 08 04:32:53 PM PDT 24
Finished Aug 08 04:33:19 PM PDT 24
Peak memory 199908 kb
Host smart-c2213e9d-8d46-49c9-baef-ca065aa64140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150249640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2150249640
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.1112196350
Short name T273
Test name
Test status
Simulation time 29273933240 ps
CPU time 26.75 seconds
Started Aug 08 04:32:53 PM PDT 24
Finished Aug 08 04:33:20 PM PDT 24
Peak memory 199800 kb
Host smart-3370dd0b-6121-4f34-8143-2fdeb04bbbe4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112196350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1112196350
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.815832200
Short name T745
Test name
Test status
Simulation time 93524908902 ps
CPU time 759.15 seconds
Started Aug 08 04:32:54 PM PDT 24
Finished Aug 08 04:45:33 PM PDT 24
Peak memory 199728 kb
Host smart-d4323fdd-98ff-4d92-a269-d45c3067041b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=815832200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.815832200
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3795942151
Short name T364
Test name
Test status
Simulation time 11086664297 ps
CPU time 19.15 seconds
Started Aug 08 04:32:51 PM PDT 24
Finished Aug 08 04:33:10 PM PDT 24
Peak memory 199424 kb
Host smart-47a6a3d8-fb7d-48af-9b36-9c851e185ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795942151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3795942151
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2782421867
Short name T869
Test name
Test status
Simulation time 14564108948 ps
CPU time 38.16 seconds
Started Aug 08 04:32:56 PM PDT 24
Finished Aug 08 04:33:34 PM PDT 24
Peak memory 199968 kb
Host smart-739def9a-aab6-47c8-80d4-37cec3374354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782421867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2782421867
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3750825380
Short name T484
Test name
Test status
Simulation time 20231739128 ps
CPU time 271.23 seconds
Started Aug 08 04:32:53 PM PDT 24
Finished Aug 08 04:37:24 PM PDT 24
Peak memory 200172 kb
Host smart-cefc0258-ce81-468f-9c05-b057b313e3ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3750825380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3750825380
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3161464444
Short name T1082
Test name
Test status
Simulation time 7456689309 ps
CPU time 30.44 seconds
Started Aug 08 04:32:51 PM PDT 24
Finished Aug 08 04:33:21 PM PDT 24
Peak memory 197772 kb
Host smart-54950248-75e7-4f85-98b3-2b1159777f66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3161464444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3161464444
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2512173633
Short name T846
Test name
Test status
Simulation time 15148344744 ps
CPU time 13.18 seconds
Started Aug 08 04:32:54 PM PDT 24
Finished Aug 08 04:33:07 PM PDT 24
Peak memory 199760 kb
Host smart-48ca1a5a-1a80-4d01-b78f-99c46e14964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512173633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2512173633
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.4001376097
Short name T831
Test name
Test status
Simulation time 47102138383 ps
CPU time 17.08 seconds
Started Aug 08 04:32:56 PM PDT 24
Finished Aug 08 04:33:13 PM PDT 24
Peak memory 195892 kb
Host smart-4f06398a-e1a4-4bfb-bd56-23a37ff5eae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001376097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.4001376097
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2488663353
Short name T816
Test name
Test status
Simulation time 780222057 ps
CPU time 1.19 seconds
Started Aug 08 04:32:51 PM PDT 24
Finished Aug 08 04:32:53 PM PDT 24
Peak memory 199496 kb
Host smart-40584c99-92c2-4dd2-9ca9-d6dd3d245ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488663353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2488663353
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.582983523
Short name T573
Test name
Test status
Simulation time 27395416784 ps
CPU time 95.66 seconds
Started Aug 08 04:32:54 PM PDT 24
Finished Aug 08 04:34:30 PM PDT 24
Peak memory 199844 kb
Host smart-3c77ae2a-ad01-443f-9712-4b8d91e51852
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582983523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.582983523
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3810525381
Short name T108
Test name
Test status
Simulation time 593936519062 ps
CPU time 1008.48 seconds
Started Aug 08 04:32:52 PM PDT 24
Finished Aug 08 04:49:41 PM PDT 24
Peak memory 224744 kb
Host smart-295d3e0b-e8b1-4bb5-a484-081e734e0d90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810525381 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3810525381
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1687174284
Short name T314
Test name
Test status
Simulation time 10145791934 ps
CPU time 8.22 seconds
Started Aug 08 04:32:56 PM PDT 24
Finished Aug 08 04:33:04 PM PDT 24
Peak memory 199528 kb
Host smart-a27f303c-9fdd-4dfd-bdf8-3b6f781d3438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687174284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1687174284
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2053654772
Short name T961
Test name
Test status
Simulation time 97913650355 ps
CPU time 197.94 seconds
Started Aug 08 04:32:54 PM PDT 24
Finished Aug 08 04:36:12 PM PDT 24
Peak memory 199792 kb
Host smart-4721e5c7-b97f-49ef-b18d-eb9a84501d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053654772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2053654772
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2594200566
Short name T47
Test name
Test status
Simulation time 229909486277 ps
CPU time 99.66 seconds
Started Aug 08 04:38:43 PM PDT 24
Finished Aug 08 04:40:23 PM PDT 24
Peak memory 199740 kb
Host smart-901216c6-2915-40f2-86b6-66ff116215e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594200566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2594200566
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3130630974
Short name T602
Test name
Test status
Simulation time 153580778651 ps
CPU time 837.8 seconds
Started Aug 08 04:38:45 PM PDT 24
Finished Aug 08 04:52:43 PM PDT 24
Peak memory 224492 kb
Host smart-46b5f078-17b2-424d-aaed-a4c531833185
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130630974 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3130630974
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1485365756
Short name T674
Test name
Test status
Simulation time 35945358271 ps
CPU time 28.25 seconds
Started Aug 08 04:38:46 PM PDT 24
Finished Aug 08 04:39:14 PM PDT 24
Peak memory 199608 kb
Host smart-56b79928-9efc-47f5-a863-63c8ee432d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485365756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1485365756
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.4249094485
Short name T689
Test name
Test status
Simulation time 766362213976 ps
CPU time 542.53 seconds
Started Aug 08 04:38:53 PM PDT 24
Finished Aug 08 04:47:55 PM PDT 24
Peak memory 216320 kb
Host smart-3aa61ec2-bbc6-4346-8572-f582dc40858e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249094485 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.4249094485
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1752519569
Short name T792
Test name
Test status
Simulation time 65967146296 ps
CPU time 98.57 seconds
Started Aug 08 04:38:46 PM PDT 24
Finished Aug 08 04:40:25 PM PDT 24
Peak memory 199616 kb
Host smart-4962b16f-72f1-4fa9-a2a6-3d68aaea74c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752519569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1752519569
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3977453895
Short name T43
Test name
Test status
Simulation time 73378186277 ps
CPU time 931.8 seconds
Started Aug 08 04:38:43 PM PDT 24
Finished Aug 08 04:54:15 PM PDT 24
Peak memory 224636 kb
Host smart-038e2911-a75e-4bb4-ace5-f511426cab07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977453895 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3977453895
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.879963803
Short name T730
Test name
Test status
Simulation time 177205212287 ps
CPU time 22.99 seconds
Started Aug 08 04:38:44 PM PDT 24
Finished Aug 08 04:39:08 PM PDT 24
Peak memory 199616 kb
Host smart-11e56c87-f019-4d81-ac68-3684003dcaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879963803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.879963803
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2897577048
Short name T802
Test name
Test status
Simulation time 61833301567 ps
CPU time 363.47 seconds
Started Aug 08 04:38:46 PM PDT 24
Finished Aug 08 04:44:50 PM PDT 24
Peak memory 208092 kb
Host smart-3651e558-4d27-4a6f-bc97-24cc845c7d67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897577048 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2897577048
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1205928762
Short name T160
Test name
Test status
Simulation time 30077968543 ps
CPU time 16.97 seconds
Started Aug 08 04:38:47 PM PDT 24
Finished Aug 08 04:39:05 PM PDT 24
Peak memory 199776 kb
Host smart-dc30b648-6bf4-4c15-a4a2-87c46f19c66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205928762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1205928762
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2653249069
Short name T1114
Test name
Test status
Simulation time 170067145888 ps
CPU time 250.37 seconds
Started Aug 08 04:39:02 PM PDT 24
Finished Aug 08 04:43:12 PM PDT 24
Peak memory 216516 kb
Host smart-89901e34-b3ba-4ca5-8711-44ade367a8f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653249069 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2653249069
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1206928917
Short name T136
Test name
Test status
Simulation time 15484939179 ps
CPU time 12.65 seconds
Started Aug 08 04:38:43 PM PDT 24
Finished Aug 08 04:38:56 PM PDT 24
Peak memory 199836 kb
Host smart-546bbd0b-cc2e-41ac-890d-165375af4645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206928917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1206928917
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3387340187
Short name T143
Test name
Test status
Simulation time 120409827086 ps
CPU time 2602.99 seconds
Started Aug 08 04:38:53 PM PDT 24
Finished Aug 08 05:22:17 PM PDT 24
Peak memory 224436 kb
Host smart-d6583b92-95df-4230-8f2f-ffd11d262ea5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387340187 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3387340187
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3646293988
Short name T1018
Test name
Test status
Simulation time 339664584375 ps
CPU time 71.36 seconds
Started Aug 08 04:38:52 PM PDT 24
Finished Aug 08 04:40:03 PM PDT 24
Peak memory 199776 kb
Host smart-ba6833de-b438-4d28-82ab-cf17aefe9c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646293988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3646293988
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1767999987
Short name T1169
Test name
Test status
Simulation time 26743153656 ps
CPU time 14.92 seconds
Started Aug 08 04:40:54 PM PDT 24
Finished Aug 08 04:41:09 PM PDT 24
Peak memory 199840 kb
Host smart-845ab7db-c57d-49bf-b89d-6e99704701ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767999987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1767999987
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.4152392268
Short name T30
Test name
Test status
Simulation time 47643084625 ps
CPU time 731.5 seconds
Started Aug 08 04:41:33 PM PDT 24
Finished Aug 08 04:53:44 PM PDT 24
Peak memory 211304 kb
Host smart-8dc08a3a-f640-439b-b270-dbc4dc648dfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152392268 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.4152392268
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.3481479676
Short name T722
Test name
Test status
Simulation time 100903519783 ps
CPU time 91.29 seconds
Started Aug 08 04:39:06 PM PDT 24
Finished Aug 08 04:40:37 PM PDT 24
Peak memory 199692 kb
Host smart-619f7d33-4f7f-457b-9819-0402a65ab043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481479676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3481479676
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2369147177
Short name T154
Test name
Test status
Simulation time 93314320295 ps
CPU time 1197.75 seconds
Started Aug 08 04:39:11 PM PDT 24
Finished Aug 08 04:59:09 PM PDT 24
Peak memory 232844 kb
Host smart-ce958283-2a01-43e3-a613-e78e66d05daf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369147177 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2369147177
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3493348144
Short name T434
Test name
Test status
Simulation time 10860394198 ps
CPU time 9.69 seconds
Started Aug 08 04:39:19 PM PDT 24
Finished Aug 08 04:39:29 PM PDT 24
Peak memory 199668 kb
Host smart-5abb5a98-4a93-4fec-bc75-a6f35ff93745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493348144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3493348144
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1301715027
Short name T837
Test name
Test status
Simulation time 14503858 ps
CPU time 0.57 seconds
Started Aug 08 04:33:10 PM PDT 24
Finished Aug 08 04:33:10 PM PDT 24
Peak memory 195200 kb
Host smart-8e9bc7a1-a0ce-454e-8dc6-15c500b03076
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301715027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1301715027
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.892360060
Short name T684
Test name
Test status
Simulation time 104762056285 ps
CPU time 154.37 seconds
Started Aug 08 04:32:51 PM PDT 24
Finished Aug 08 04:35:26 PM PDT 24
Peak memory 199780 kb
Host smart-5143832f-332e-4d78-ae15-575664690c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892360060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.892360060
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1784209219
Short name T1008
Test name
Test status
Simulation time 51381265850 ps
CPU time 21.81 seconds
Started Aug 08 04:32:55 PM PDT 24
Finished Aug 08 04:33:17 PM PDT 24
Peak memory 199720 kb
Host smart-7461009b-4263-4691-b0a5-68d219acc58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784209219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1784209219
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2252745238
Short name T1087
Test name
Test status
Simulation time 8805739397 ps
CPU time 15.23 seconds
Started Aug 08 04:32:50 PM PDT 24
Finished Aug 08 04:33:06 PM PDT 24
Peak memory 199620 kb
Host smart-96381bb2-2ef9-4bd3-b3f5-309f1e56fd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252745238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2252745238
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1456489173
Short name T379
Test name
Test status
Simulation time 3801973140 ps
CPU time 7.59 seconds
Started Aug 08 04:32:51 PM PDT 24
Finished Aug 08 04:32:59 PM PDT 24
Peak memory 199660 kb
Host smart-8cc2d05e-dc65-4272-a605-abf15a2404a2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456489173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1456489173
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3595388077
Short name T391
Test name
Test status
Simulation time 34566278399 ps
CPU time 115.98 seconds
Started Aug 08 04:33:04 PM PDT 24
Finished Aug 08 04:35:01 PM PDT 24
Peak memory 199868 kb
Host smart-d55c68c5-c091-4c0c-91b2-c8a122a3c685
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595388077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3595388077
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2446680610
Short name T718
Test name
Test status
Simulation time 5505945214 ps
CPU time 5.94 seconds
Started Aug 08 04:33:03 PM PDT 24
Finished Aug 08 04:33:09 PM PDT 24
Peak memory 198148 kb
Host smart-8204c299-7cab-40f3-a6a0-6c4b21c776d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446680610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2446680610
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3129431651
Short name T416
Test name
Test status
Simulation time 31614114128 ps
CPU time 16.1 seconds
Started Aug 08 04:32:55 PM PDT 24
Finished Aug 08 04:33:11 PM PDT 24
Peak memory 199936 kb
Host smart-1246fee1-3f7c-4e82-849d-5aed0e3d8c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129431651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3129431651
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3650832028
Short name T964
Test name
Test status
Simulation time 15575093539 ps
CPU time 787.6 seconds
Started Aug 08 04:33:04 PM PDT 24
Finished Aug 08 04:46:12 PM PDT 24
Peak memory 199704 kb
Host smart-35969447-209d-4cc7-9b77-4959bca98c11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3650832028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3650832028
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.3370766402
Short name T447
Test name
Test status
Simulation time 6333092704 ps
CPU time 26.01 seconds
Started Aug 08 04:32:53 PM PDT 24
Finished Aug 08 04:33:19 PM PDT 24
Peak memory 198752 kb
Host smart-3b47b421-bc29-415f-a927-010cbfac05cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3370766402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3370766402
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.915911881
Short name T148
Test name
Test status
Simulation time 168143644569 ps
CPU time 46.16 seconds
Started Aug 08 04:32:52 PM PDT 24
Finished Aug 08 04:33:38 PM PDT 24
Peak memory 199688 kb
Host smart-2076030f-47e3-4de0-85f6-e97f2c613a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915911881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.915911881
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3600338708
Short name T612
Test name
Test status
Simulation time 32474334084 ps
CPU time 4.93 seconds
Started Aug 08 04:32:51 PM PDT 24
Finished Aug 08 04:32:56 PM PDT 24
Peak memory 195884 kb
Host smart-b33bad93-addf-4bb6-8bbc-e4ed8f5e24ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600338708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3600338708
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.2557683693
Short name T775
Test name
Test status
Simulation time 551036376 ps
CPU time 3.52 seconds
Started Aug 08 04:32:52 PM PDT 24
Finished Aug 08 04:32:56 PM PDT 24
Peak memory 198548 kb
Host smart-b29bc056-e032-4f9f-817d-5401596d1ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557683693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2557683693
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.448546706
Short name T642
Test name
Test status
Simulation time 540701238817 ps
CPU time 618.85 seconds
Started Aug 08 04:33:04 PM PDT 24
Finished Aug 08 04:43:23 PM PDT 24
Peak memory 199728 kb
Host smart-21dee4df-82ff-4713-b7d1-19f7c6793ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448546706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.448546706
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3175795939
Short name T819
Test name
Test status
Simulation time 71373766219 ps
CPU time 698.1 seconds
Started Aug 08 04:33:03 PM PDT 24
Finished Aug 08 04:44:41 PM PDT 24
Peak memory 216300 kb
Host smart-a1f910ae-70f3-49d6-913d-219617b81e90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175795939 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3175795939
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.618102215
Short name T898
Test name
Test status
Simulation time 1248983706 ps
CPU time 1.46 seconds
Started Aug 08 04:33:03 PM PDT 24
Finished Aug 08 04:33:05 PM PDT 24
Peak memory 198156 kb
Host smart-083bcb9b-9607-4510-9179-25bd787d623e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618102215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.618102215
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1019385742
Short name T881
Test name
Test status
Simulation time 51241997382 ps
CPU time 96.47 seconds
Started Aug 08 04:32:53 PM PDT 24
Finished Aug 08 04:34:29 PM PDT 24
Peak memory 199700 kb
Host smart-a98e3f6d-ac6c-41a2-b43c-7f2a2977b39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019385742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1019385742
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1336638516
Short name T196
Test name
Test status
Simulation time 20014428661 ps
CPU time 39.75 seconds
Started Aug 08 04:38:52 PM PDT 24
Finished Aug 08 04:39:32 PM PDT 24
Peak memory 199836 kb
Host smart-48aea79c-1477-4ef3-93fa-aab24cc60d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336638516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1336638516
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3074097095
Short name T55
Test name
Test status
Simulation time 185851746235 ps
CPU time 497.68 seconds
Started Aug 08 04:38:58 PM PDT 24
Finished Aug 08 04:47:15 PM PDT 24
Peak memory 216220 kb
Host smart-11e9631d-1bf9-476c-be77-5e9e9b630655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074097095 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3074097095
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.542964173
Short name T106
Test name
Test status
Simulation time 33837047372 ps
CPU time 161.79 seconds
Started Aug 08 04:38:58 PM PDT 24
Finished Aug 08 04:41:40 PM PDT 24
Peak memory 216292 kb
Host smart-40f2fe52-7276-4080-ac94-74b5a51fd0a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542964173 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.542964173
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.4052642349
Short name T945
Test name
Test status
Simulation time 37246354208 ps
CPU time 57.86 seconds
Started Aug 08 04:38:56 PM PDT 24
Finished Aug 08 04:39:54 PM PDT 24
Peak memory 199716 kb
Host smart-e876d26e-5419-472e-b2a5-aaae363a3b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052642349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4052642349
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3928356943
Short name T703
Test name
Test status
Simulation time 204736452387 ps
CPU time 654.91 seconds
Started Aug 08 04:40:33 PM PDT 24
Finished Aug 08 04:51:28 PM PDT 24
Peak memory 224648 kb
Host smart-7d1a7e8c-4f63-46ec-8a46-8c3e6590c2d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928356943 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3928356943
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3640582672
Short name T306
Test name
Test status
Simulation time 64911618577 ps
CPU time 96.67 seconds
Started Aug 08 04:38:52 PM PDT 24
Finished Aug 08 04:40:29 PM PDT 24
Peak memory 199800 kb
Host smart-248ff034-e231-4f4b-a26e-696a2a702315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640582672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3640582672
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1772959257
Short name T922
Test name
Test status
Simulation time 96522881035 ps
CPU time 476.94 seconds
Started Aug 08 04:39:24 PM PDT 24
Finished Aug 08 04:47:21 PM PDT 24
Peak memory 215416 kb
Host smart-cf8aa74e-5879-46c9-8a12-f787ea878f2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772959257 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1772959257
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.990119933
Short name T1023
Test name
Test status
Simulation time 170817233075 ps
CPU time 1195.28 seconds
Started Aug 08 04:39:31 PM PDT 24
Finished Aug 08 04:59:26 PM PDT 24
Peak memory 224616 kb
Host smart-5cc3ab09-ba5a-46bb-a466-0c6ce6e35d88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990119933 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.990119933
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.162154440
Short name T916
Test name
Test status
Simulation time 22906157407 ps
CPU time 49.62 seconds
Started Aug 08 04:39:05 PM PDT 24
Finished Aug 08 04:39:55 PM PDT 24
Peak memory 199800 kb
Host smart-6aa87c86-5680-48ae-952c-7a4c2d0b18a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162154440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.162154440
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.4064648367
Short name T630
Test name
Test status
Simulation time 63026647251 ps
CPU time 404.34 seconds
Started Aug 08 04:39:05 PM PDT 24
Finished Aug 08 04:45:50 PM PDT 24
Peak memory 225404 kb
Host smart-d092b338-b250-467f-93ab-92e2dace72c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064648367 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.4064648367
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.444408113
Short name T550
Test name
Test status
Simulation time 119015853073 ps
CPU time 60.67 seconds
Started Aug 08 04:39:07 PM PDT 24
Finished Aug 08 04:40:08 PM PDT 24
Peak memory 199752 kb
Host smart-a9b2184c-3dd2-4f2a-97ab-8e07247d3db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444408113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.444408113
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3036528512
Short name T101
Test name
Test status
Simulation time 239889678012 ps
CPU time 731.74 seconds
Started Aug 08 04:39:07 PM PDT 24
Finished Aug 08 04:51:19 PM PDT 24
Peak memory 225740 kb
Host smart-c78c3a1e-8784-4873-86d0-8b962cd880c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036528512 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3036528512
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.3353346736
Short name T44
Test name
Test status
Simulation time 26363668383 ps
CPU time 40.87 seconds
Started Aug 08 04:39:05 PM PDT 24
Finished Aug 08 04:39:46 PM PDT 24
Peak memory 199708 kb
Host smart-19c7f2fd-b0df-4969-a96a-8a6f26a6e4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353346736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3353346736
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1078793618
Short name T833
Test name
Test status
Simulation time 55735717796 ps
CPU time 90.05 seconds
Started Aug 08 04:39:10 PM PDT 24
Finished Aug 08 04:40:40 PM PDT 24
Peak memory 199784 kb
Host smart-e9107d34-96e5-4c3b-8aa1-87794a0f695e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078793618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1078793618
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.698900587
Short name T885
Test name
Test status
Simulation time 16405272091 ps
CPU time 169.69 seconds
Started Aug 08 04:41:32 PM PDT 24
Finished Aug 08 04:44:22 PM PDT 24
Peak memory 215544 kb
Host smart-77bf292e-54fc-412b-9cd5-511549583ce9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698900587 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.698900587
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.4210466399
Short name T116
Test name
Test status
Simulation time 116603678536 ps
CPU time 98.63 seconds
Started Aug 08 04:39:03 PM PDT 24
Finished Aug 08 04:40:42 PM PDT 24
Peak memory 199724 kb
Host smart-c00ee0e2-0974-4706-b98b-42c0d876893b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210466399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.4210466399
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1102562846
Short name T173
Test name
Test status
Simulation time 85235212336 ps
CPU time 1230.83 seconds
Started Aug 08 04:39:17 PM PDT 24
Finished Aug 08 04:59:48 PM PDT 24
Peak memory 232804 kb
Host smart-82446737-9d80-487f-a46b-da7df7880837
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102562846 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1102562846
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%