Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	117656	1			T1	15		T3	91		T4	2
all_values[1]	117656	1			T1	15		T3	91		T4	2
all_values[2]	117656	1			T1	15		T3	91		T4	2
all_values[3]	117656	1			T1	15		T3	91		T4	2
all_values[4]	117656	1			T1	15		T3	91		T4	2
all_values[5]	117656	1			T1	15		T3	91		T4	2
all_values[6]	117656	1			T1	15		T3	91		T4	2
all_values[7]	117656	1			T1	15		T3	91		T4	2
all_values[8]	117656	1			T1	15		T3	91		T4	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

528025

1

T1

91

T3

459

T4

18

auto[1]

530879

1

T1

44

T3

360

T6

2981

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

958326

1

T1

128

T3

682

T4

13

auto[1]

100578

1

T1

7

T3

137

T4

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	31288	1			T3	23		T6	548		T7	1
all_values[0]	auto[0]	auto[1]	25308	1			T3	35		T4	2		T5	2
all_values[0]	auto[1]	auto[0]	36834	1			T1	12		T3	17		T6	43
all_values[0]	auto[1]	auto[1]	24226	1			T1	3		T3	16		T6	45
all_values[1]	auto[0]	auto[0]	61185	1			T3	45		T4	2		T5	2
all_values[1]	auto[0]	auto[1]	1566	1			T1	1		T16	1		T17	12
all_values[1]	auto[1]	auto[0]	53252	1			T1	14		T3	35		T6	770
all_values[1]	auto[1]	auto[1]	1653	1			T3	11		T16	3		T17	9
all_values[2]	auto[0]	auto[0]	60071	1			T1	14		T3	61		T4	1
all_values[2]	auto[0]	auto[1]	2875	1			T1	1		T3	11		T4	1
all_values[2]	auto[1]	auto[0]	52171	1			T3	15		T6	117		T7	1
all_values[2]	auto[1]	auto[1]	2539	1			T3	4		T6	1		T7	1
all_values[3]	auto[0]	auto[0]	55969	1			T1	15		T3	52		T4	2
all_values[3]	auto[0]	auto[1]	264	1			T13	1		T17	2		T15	1
all_values[3]	auto[1]	auto[0]	61119	1			T3	39		T6	168		T9	10
all_values[3]	auto[1]	auto[1]	304	1			T16	3		T14	1		T17	3
all_values[4]	auto[0]	auto[0]	55397	1			T1	14		T3	40		T4	2
all_values[4]	auto[0]	auto[1]	432	1			T16	1		T17	3		T18	12
all_values[4]	auto[1]	auto[0]	61327	1			T1	1		T3	51		T6	774
all_values[4]	auto[1]	auto[1]	500	1			T16	2		T17	13		T34	9
all_values[5]	auto[0]	auto[0]	59950	1			T1	15		T3	42		T4	2
all_values[5]	auto[0]	auto[1]	176	1			T16	1		T17	3		T33	2
all_values[5]	auto[1]	auto[0]	57329	1			T3	49		T6	105		T7	2
all_values[5]	auto[1]	auto[1]	201	1			T16	4		T17	4		T33	1
all_values[6]	auto[0]	auto[0]	57868	1			T1	1		T3	41		T4	2
all_values[6]	auto[0]	auto[1]	167	1			T16	1		T17	6		T33	1
all_values[6]	auto[1]	auto[0]	59428	1			T1	14		T3	50		T6	89
all_values[6]	auto[1]	auto[1]	193	1			T16	1		T17	1		T33	3
all_values[7]	auto[0]	auto[0]	55562	1			T1	15		T3	68		T4	2
all_values[7]	auto[0]	auto[1]	392	1			T3	15		T16	1		T17	2
all_values[7]	auto[1]	auto[0]	61340	1			T3	8		T6	728		T7	3
all_values[7]	auto[1]	auto[1]	362	1			T16	3		T17	2		T140	5
all_values[8]	auto[0]	auto[0]	38761	1			T1	13		T3	24		T6	535
all_values[8]	auto[0]	auto[1]	20794	1			T1	2		T3	2		T4	2
all_values[8]	auto[1]	auto[0]	39475	1			T3	22		T6	139		T7	1
all_values[8]	auto[1]	auto[1]	18626	1			T3	43		T6	2		T7	2