Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2579

1

T1

1

T2

1

T3

3

auto[UartRx]

2579

1

T1

1

T2

1

T3

3

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4573	1			T1	2		T2	2		T3	6
values[1]	50	1			T14	2		T17	1		T29	1
values[2]	43	1			T17	3		T35	1		T46	1
values[3]	57	1			T14	2		T17	1		T29	1
values[4]	45	1			T14	1		T17	2		T30	1
values[5]	48	1			T14	1		T34	1		T46	1
values[6]	62	1			T6	3		T31	1		T35	1
values[7]	66	1			T6	2		T14	1		T31	1
values[8]	58	1			T14	1		T17	1		T29	1
values[9]	69	1			T29	1		T31	2		T33	1
values[10]	61	1			T17	1		T32	1		T34	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2380	1			T1	1		T2	1		T3	3
auto[UartTx]	values[1]	10	1			T17	1		T48	1		T209	1
auto[UartTx]	values[2]	14	1			T17	1		T46	1		T138	1
auto[UartTx]	values[3]	21	1			T14	1		T30	1		T320	1
auto[UartTx]	values[4]	19	1			T14	1		T17	2		T30	1
auto[UartTx]	values[5]	16	1			T46	1		T320	1		T161	1
auto[UartTx]	values[6]	21	1			T6	1		T46	1		T48	1
auto[UartTx]	values[7]	26	1			T6	1		T31	1		T34	1
auto[UartTx]	values[8]	21	1			T30	1		T33	1		T138	1
auto[UartTx]	values[9]	21	1			T29	1		T47	2		T321	1
auto[UartTx]	values[10]	21	1			T32	1		T34	1		T101	2
auto[UartRx]	values[0]	2193	1			T1	1		T2	1		T3	3
auto[UartRx]	values[1]	40	1			T14	2		T29	1		T46	1
auto[UartRx]	values[2]	29	1			T17	2		T35	1		T101	1
auto[UartRx]	values[3]	36	1			T14	1		T17	1		T29	1
auto[UartRx]	values[4]	26	1			T32	1		T33	1		T47	1
auto[UartRx]	values[5]	32	1			T14	1		T34	1		T138	1
auto[UartRx]	values[6]	41	1			T6	2		T31	1		T35	1
auto[UartRx]	values[7]	40	1			T6	1		T14	1		T32	2
auto[UartRx]	values[8]	37	1			T14	1		T17	1		T29	1
auto[UartRx]	values[9]	48	1			T31	2		T33	1		T46	1
auto[UartRx]	values[10]	40	1			T17	1		T35	1		T101	1