Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2382	1			T3	3		T12	1		T13	11
auto[BaudRate115200]	2115	1			T1	1		T3	2		T6	1
auto[BaudRate230400]	2134	1			T1	1		T3	5		T4	1
auto[BaudRate128Kbps]	2102	1			T3	2		T4	1		T6	4
auto[BaudRate256Kbps]	2443	1			T1	3		T3	1		T6	2
auto[BaudRate1Mbps]	1927	1			T1	2		T3	4		T5	1
auto[BaudRate1p5Mbps]	1375	1			T6	3		T7	3		T9	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1795	1			T1	7		T8	2		T9	8
freqs[25]	1177	1			T4	2		T251	6		T40	10
freqs[48]	386	1			T37	8		T322	6		T165	31
freqs[50]	745	1			T5	2		T311	2		T127	10
freqs[100]	1310	1			T11	10		T22	6		T282	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	265	1			T41	2		T130	4		T267	2
auto[BaudRate9600]	freqs[25]	224	1			T251	1		T40	2		T23	2
auto[BaudRate9600]	freqs[48]	52	1			T94	1		T323	1		T157	2
auto[BaudRate9600]	freqs[50]	109	1			T291	1		T257	4		T149	1
auto[BaudRate9600]	freqs[100]	196	1			T282	1		T30	2		T258	1
auto[BaudRate115200]	freqs[24]	265	1			T1	1		T9	1		T41	2
auto[BaudRate115200]	freqs[25]	161	1			T23	1		T44	2		T125	2
auto[BaudRate115200]	freqs[48]	49	1			T165	7		T94	1		T157	1
auto[BaudRate115200]	freqs[50]	119	1			T127	2		T291	3		T149	1
auto[BaudRate115200]	freqs[100]	185	1			T39	2		T30	2		T105	3
auto[BaudRate230400]	freqs[24]	276	1			T1	1		T41	2		T284	1
auto[BaudRate230400]	freqs[25]	159	1			T4	1		T251	1		T23	1
auto[BaudRate230400]	freqs[48]	47	1			T165	6		T94	2		T324	2
auto[BaudRate230400]	freqs[50]	98	1			T5	1		T127	2		T291	1
auto[BaudRate230400]	freqs[100]	182	1			T22	3		T282	1		T39	1
auto[BaudRate128Kbps]	freqs[24]	266	1			T8	1		T9	2		T41	1
auto[BaudRate128Kbps]	freqs[25]	169	1			T4	1		T251	1		T40	3
auto[BaudRate128Kbps]	freqs[48]	46	1			T37	3		T322	2		T165	4
auto[BaudRate128Kbps]	freqs[50]	88	1			T311	2		T127	1		T291	1
auto[BaudRate128Kbps]	freqs[100]	164	1			T293	1		T264	1		T30	1
auto[BaudRate256Kbps]	freqs[24]	308	1			T1	3		T8	1		T9	3
auto[BaudRate256Kbps]	freqs[25]	166	1			T125	1		T140	1		T126	2
auto[BaudRate256Kbps]	freqs[48]	57	1			T37	2		T322	1		T165	7
auto[BaudRate256Kbps]	freqs[50]	114	1			T127	1		T291	2		T257	1
auto[BaudRate256Kbps]	freqs[100]	167	1			T11	3		T39	3		T264	2
auto[BaudRate1Mbps]	freqs[24]	260	1			T1	2		T9	1		T41	2
auto[BaudRate1Mbps]	freqs[25]	197	1			T251	1		T40	4		T44	1
auto[BaudRate1Mbps]	freqs[48]	78	1			T37	2		T322	2		T165	5
auto[BaudRate1Mbps]	freqs[50]	110	1			T5	1		T127	2		T291	1
auto[BaudRate1Mbps]	freqs[100]	207	1			T11	4		T22	3		T39	3
auto[BaudRate1p5Mbps]	freqs[25]	101	1			T251	2		T40	1		T44	1
auto[BaudRate1p5Mbps]	freqs[48]	57	1			T37	1		T322	1		T165	2
auto[BaudRate1p5Mbps]	freqs[50]	107	1			T127	2		T291	1		T149	1
auto[BaudRate1p5Mbps]	freqs[100]	209	1			T11	3		T39	1		T264	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded