Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	11	119	91.54

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	11	119	91.54	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	33300158	1			T1	11		T3	71		T6	342210
all_levels[1]	190876	1			T1	1		T3	6		T6	1139
all_levels[2]	2763	1			T3	6		T10	7		T14	6
all_levels[3]	1210	1			T14	5		T38	4		T23	7
all_levels[4]	802	1			T3	8		T37	1		T14	2
all_levels[5]	610	1			T3	3		T13	1		T14	3
all_levels[6]	437	1			T3	1		T7	1		T9	1
all_levels[7]	371	1			T3	1		T37	1		T13	1
all_levels[8]	346	1			T3	3		T7	1		T13	1
all_levels[9]	278	1			T3	2		T13	1		T14	10
all_levels[10]	237	1			T3	2		T13	2		T14	1
all_levels[11]	211	1			T14	1		T38	4		T42	1
all_levels[12]	156	1			T37	1		T13	2		T14	4
all_levels[13]	168	1			T3	1		T7	3		T37	1
all_levels[14]	131	1			T37	1		T114	1		T115	1
all_levels[15]	107	1			T9	1		T114	1		T123	1
all_levels[16]	108	1			T38	1		T114	1		T124	1
all_levels[17]	100	1			T37	2		T38	1		T114	1
all_levels[18]	78	1			T13	1		T38	1		T114	1
all_levels[19]	85	1			T125	1		T115	1		T126	5
all_levels[20]	83	1			T3	2		T124	1		T105	1
all_levels[21]	75	1			T14	1		T126	1		T127	1
all_levels[22]	57	1			T40	1		T128	1		T129	1
all_levels[23]	46	1			T1	1		T13	1		T38	2
all_levels[24]	55	1			T23	1		T105	1		T130	1
all_levels[25]	59	1			T17	1		T125	1		T115	1
all_levels[26]	65	1			T3	1		T37	2		T40	1
all_levels[27]	45	1			T3	1		T40	1		T131	2
all_levels[28]	50	1			T13	2		T40	1		T17	1
all_levels[29]	48	1			T132	1		T127	1		T133	1
all_levels[30]	37	1			T3	1		T125	1		T134	1
all_levels[31]	41	1			T40	4		T125	1		T135	1
all_levels[32]	34	1			T130	1		T136	2		T137	1
all_levels[33]	32	1			T127	1		T138	1		T139	1
all_levels[34]	23	1			T1	1		T125	2		T15	1
all_levels[35]	24	1			T140	1		T127	1		T141	1
all_levels[36]	27	1			T135	1		T34	2		T141	1
all_levels[37]	20	1			T94	1		T142	1		T143	2
all_levels[38]	28	1			T144	2		T145	1		T146	1
all_levels[39]	21	1			T134	3		T147	1		T148	1
all_levels[40]	27	1			T149	1		T150	1		T119	1
all_levels[41]	17	1			T14	1		T144	1		T101	1
all_levels[42]	23	1			T3	1		T115	1		T151	1
all_levels[43]	15	1			T94	1		T152	1		T153	1
all_levels[44]	17	1			T115	1		T154	1		T155	1
all_levels[45]	12	1			T130	1		T144	1		T138	1
all_levels[46]	10	1			T9	3		T156	2		T157	1
all_levels[47]	19	1			T158	1		T117	1		T159	1
all_levels[48]	11	1			T160	1		T141	1		T161	1
all_levels[49]	13	1			T1	1		T126	1		T132	1
all_levels[50]	17	1			T135	1		T162	1		T136	1
all_levels[51]	6	1			T112	1		T148	1		T163	1
all_levels[52]	15	1			T13	1		T159	1		T164	1
all_levels[53]	10	1			T101	1		T165	1		T166	1
all_levels[54]	11	1			T15	1		T167	2		T168	1
all_levels[55]	8	1			T169	1		T170	1		T171	2
all_levels[56]	3	1			T172	1		T173	1		T174	1
all_levels[57]	8	1			T133	2		T92	2		T175	1
all_levels[58]	6	1			T176	1		T177	1		T178	1
all_levels[59]	8	1			T15	1		T179	1		T180	1
all_levels[60]	7	1			T156	1		T161	1		T166	1
all_levels[61]	3	1			T13	2		T181	1		-	-
all_levels[62]	6	1			T182	1		T183	1		T184	1
all_levels[63]	4	1			T185	1		T186	1		T187	1
all_levels[64]	104	1			T12	1		T13	5		T15	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33495355

1

T1

10

T3

110

T6

343349

auto[1]

5127

1

T1

5

T7

8

T9

8

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	11	119	91.54	11

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[30]]	[auto[1]]	0	1	1
[all_levels[35]]	[auto[1]]	0	1	1
[all_levels[48] , all_levels[49]]	[auto[1]]	--	--	2
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[59] , all_levels[60] , all_levels[61] , all_levels[62] , all_levels[63]]	[auto[1]]	--	--	5

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	33295460	1			T1	6		T3	71		T6	342210
all_levels[0]	auto[1]	4698	1			T1	5		T7	6		T9	6
all_levels[1]	auto[0]	190792	1			T1	1		T3	6		T6	1139
all_levels[1]	auto[1]	84	1			T12	2		T17	2		T115	2
all_levels[2]	auto[0]	2749	1			T3	6		T10	7		T14	6
all_levels[2]	auto[1]	14	1			T188	1		T146	1		T163	1
all_levels[3]	auto[0]	1173	1			T14	5		T38	3		T23	7
all_levels[3]	auto[1]	37	1			T38	1		T44	2		T15	1
all_levels[4]	auto[0]	786	1			T3	8		T37	1		T14	2
all_levels[4]	auto[1]	16	1			T189	1		T190	1		T191	2
all_levels[5]	auto[0]	582	1			T3	3		T13	1		T14	3
all_levels[5]	auto[1]	28	1			T160	1		T192	2		T169	1
all_levels[6]	auto[0]	423	1			T3	1		T7	1		T9	1
all_levels[6]	auto[1]	14	1			T130	3		T193	1		T112	1
all_levels[7]	auto[0]	358	1			T3	1		T37	1		T13	1
all_levels[7]	auto[1]	13	1			T194	1		T195	1		T196	2
all_levels[8]	auto[0]	331	1			T3	3		T7	1		T13	1
all_levels[8]	auto[1]	15	1			T197	3		T129	1		T146	1
all_levels[9]	auto[0]	256	1			T3	2		T13	1		T14	6
all_levels[9]	auto[1]	22	1			T14	4		T38	2		T108	1
all_levels[10]	auto[0]	233	1			T3	2		T13	2		T14	1
all_levels[10]	auto[1]	4	1			T150	1		T198	1		T195	1
all_levels[11]	auto[0]	201	1			T14	1		T38	4		T42	1
all_levels[11]	auto[1]	10	1			T169	2		T183	3		T199	2
all_levels[12]	auto[0]	145	1			T37	1		T13	1		T14	4
all_levels[12]	auto[1]	11	1			T13	1		T128	1		T193	3
all_levels[13]	auto[0]	152	1			T3	1		T7	1		T37	1
all_levels[13]	auto[1]	16	1			T7	2		T115	1		T15	2
all_levels[14]	auto[0]	128	1			T37	1		T114	1		T115	1
all_levels[14]	auto[1]	3	1			T200	2		T201	1		-	-
all_levels[15]	auto[0]	103	1			T9	1		T114	1		T123	1
all_levels[15]	auto[1]	4	1			T202	1		T203	1		T204	1
all_levels[16]	auto[0]	102	1			T38	1		T114	1		T124	1
all_levels[16]	auto[1]	6	1			T147	1		T51	2		T205	2
all_levels[17]	auto[0]	94	1			T37	2		T38	1		T114	1
all_levels[17]	auto[1]	6	1			T115	1		T145	3		T206	1
all_levels[18]	auto[0]	76	1			T13	1		T38	1		T114	1
all_levels[18]	auto[1]	2	1			T207	1		T208	1		-	-
all_levels[19]	auto[0]	75	1			T125	1		T115	1		T126	1
all_levels[19]	auto[1]	10	1			T126	4		T209	1		T210	3
all_levels[20]	auto[0]	80	1			T3	2		T124	1		T105	1
all_levels[20]	auto[1]	3	1			T211	2		T212	1		-	-
all_levels[21]	auto[0]	71	1			T14	1		T126	1		T127	1
all_levels[21]	auto[1]	4	1			T213	2		T214	2		-	-
all_levels[22]	auto[0]	54	1			T40	1		T128	1		T129	1
all_levels[22]	auto[1]	3	1			T183	3		-	-		-	-
all_levels[23]	auto[0]	45	1			T1	1		T13	1		T38	2
all_levels[23]	auto[1]	1	1			T215	1		-	-		-	-
all_levels[24]	auto[0]	53	1			T23	1		T105	1		T130	1
all_levels[24]	auto[1]	2	1			T135	1		T216	1		-	-
all_levels[25]	auto[0]	54	1			T17	1		T125	1		T115	1
all_levels[25]	auto[1]	5	1			T217	1		T218	2		T219	2
all_levels[26]	auto[0]	54	1			T3	1		T37	2		T40	1
all_levels[26]	auto[1]	11	1			T121	1		T220	3		T221	1
all_levels[27]	auto[0]	43	1			T3	1		T40	1		T131	2
all_levels[27]	auto[1]	2	1			T222	1		T223	1		-	-
all_levels[28]	auto[0]	40	1			T13	2		T40	1		T17	1
all_levels[28]	auto[1]	10	1			T224	1		T153	1		T225	1
all_levels[29]	auto[0]	44	1			T132	1		T127	1		T133	1
all_levels[29]	auto[1]	4	1			T112	3		T208	1		-	-
all_levels[30]	auto[0]	37	1			T3	1		T125	1		T134	1
all_levels[31]	auto[0]	33	1			T40	1		T125	1		T135	1
all_levels[31]	auto[1]	8	1			T40	3		T226	5		-	-
all_levels[32]	auto[0]	32	1			T130	1		T136	1		T137	1
all_levels[32]	auto[1]	2	1			T136	1		T227	1		-	-
all_levels[33]	auto[0]	30	1			T127	1		T138	1		T139	1
all_levels[33]	auto[1]	2	1			T228	1		T191	1		-	-
all_levels[34]	auto[0]	21	1			T1	1		T125	2		T15	1
all_levels[34]	auto[1]	2	1			T229	2		-	-		-	-
all_levels[35]	auto[0]	24	1			T140	1		T127	1		T141	1
all_levels[36]	auto[0]	25	1			T135	1		T34	1		T141	1
all_levels[36]	auto[1]	2	1			T34	1		T230	1		-	-
all_levels[37]	auto[0]	18	1			T94	1		T142	1		T143	1
all_levels[37]	auto[1]	2	1			T143	1		T231	1		-	-
all_levels[38]	auto[0]	26	1			T144	2		T145	1		T146	1
all_levels[38]	auto[1]	2	1			T232	1		T233	1		-	-
all_levels[39]	auto[0]	15	1			T134	1		T147	1		T148	1
all_levels[39]	auto[1]	6	1			T134	2		T234	1		T230	3
all_levels[40]	auto[0]	22	1			T149	1		T150	1		T119	1
all_levels[40]	auto[1]	5	1			T235	1		T236	1		T170	2
all_levels[41]	auto[0]	14	1			T14	1		T144	1		T101	1
all_levels[41]	auto[1]	3	1			T237	3		-	-		-	-
all_levels[42]	auto[0]	20	1			T3	1		T115	1		T151	1
all_levels[42]	auto[1]	3	1			T238	2		T239	1		-	-
all_levels[43]	auto[0]	14	1			T94	1		T152	1		T153	1
all_levels[43]	auto[1]	1	1			T240	1		-	-		-	-
all_levels[44]	auto[0]	16	1			T115	1		T154	1		T155	1
all_levels[44]	auto[1]	1	1			T241	1		-	-		-	-
all_levels[45]	auto[0]	10	1			T130	1		T144	1		T138	1
all_levels[45]	auto[1]	2	1			T242	2		-	-		-	-
all_levels[46]	auto[0]	7	1			T9	1		T156	1		T157	1
all_levels[46]	auto[1]	3	1			T9	2		T156	1		-	-
all_levels[47]	auto[0]	17	1			T158	1		T117	1		T159	1
all_levels[47]	auto[1]	2	1			T234	2		-	-		-	-
all_levels[48]	auto[0]	11	1			T160	1		T141	1		T161	1
all_levels[49]	auto[0]	13	1			T1	1		T126	1		T132	1
all_levels[50]	auto[0]	16	1			T135	1		T162	1		T136	1
all_levels[50]	auto[1]	1	1			T119	1		-	-		-	-
all_levels[51]	auto[0]	6	1			T112	1		T148	1		T163	1
all_levels[52]	auto[0]	14	1			T13	1		T159	1		T164	1
all_levels[52]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[53]	auto[0]	9	1			T101	1		T165	1		T166	1
all_levels[53]	auto[1]	1	1			T244	1		-	-		-	-
all_levels[54]	auto[0]	10	1			T15	1		T167	1		T168	1
all_levels[54]	auto[1]	1	1			T167	1		-	-		-	-
all_levels[55]	auto[0]	6	1			T169	1		T170	1		T171	1
all_levels[55]	auto[1]	2	1			T171	1		T245	1		-	-
all_levels[56]	auto[0]	3	1			T172	1		T173	1		T174	1
all_levels[57]	auto[0]	7	1			T133	1		T92	2		T175	1
all_levels[57]	auto[1]	1	1			T133	1		-	-		-	-
all_levels[58]	auto[0]	4	1			T176	1		T177	1		T178	1
all_levels[58]	auto[1]	2	1			T246	2		-	-		-	-
all_levels[59]	auto[0]	8	1			T15	1		T179	1		T180	1
all_levels[60]	auto[0]	7	1			T156	1		T161	1		T166	1
all_levels[61]	auto[0]	3	1			T13	2		T181	1		-	-
all_levels[62]	auto[0]	6	1			T182	1		T183	1		T184	1
all_levels[63]	auto[0]	4	1			T185	1		T186	1		T187	1
all_levels[64]	auto[0]	90	1			T12	1		T13	3		T15	1
all_levels[64]	auto[1]	14	1			T13	2		T247	1		T248	2