Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	117656	1			T1	15		T3	91		T4	2
all_pins[1]	117656	1			T1	15		T3	91		T4	2
all_pins[2]	117656	1			T1	15		T3	91		T4	2
all_pins[3]	117656	1			T1	15		T3	91		T4	2
all_pins[4]	117656	1			T1	15		T3	91		T4	2
all_pins[5]	117656	1			T1	15		T3	91		T4	2
all_pins[6]	117656	1			T1	15		T3	91		T4	2
all_pins[7]	117656	1			T1	15		T3	91		T4	2
all_pins[8]	117656	1			T1	15		T3	91		T4	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1009372	1			T1	131		T3	743		T4	18
values[0x1]	49532	1			T1	4		T3	76		T6	48
transitions[0x0=>0x1]	39184	1			T1	4		T3	58		T6	47
transitions[0x1=>0x0]	38990	1			T1	3		T3	58		T6	47

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	93348	1			T1	12		T3	75		T4	2
all_pins[0]	values[0x1]	24308	1			T1	3		T3	16		T6	45
all_pins[0]	transitions[0x0=>0x1]	23700	1			T1	3		T3	9		T6	45
all_pins[0]	transitions[0x1=>0x0]	1039	1			T3	4		T16	1		T17	9
all_pins[1]	values[0x0]	116009	1			T1	15		T3	80		T4	2
all_pins[1]	values[0x1]	1647	1			T3	11		T16	3		T17	9
all_pins[1]	transitions[0x0=>0x1]	1504	1			T3	11		T16	2		T17	3
all_pins[1]	transitions[0x1=>0x0]	2455	1			T3	4		T6	1		T7	1
all_pins[2]	values[0x0]	115058	1			T1	15		T3	87		T4	2
all_pins[2]	values[0x1]	2598	1			T3	4		T6	1		T7	1
all_pins[2]	transitions[0x0=>0x1]	2518	1			T3	4		T6	1		T7	1
all_pins[2]	transitions[0x1=>0x0]	224	1			T16	3		T17	3		T182	2
all_pins[3]	values[0x0]	117352	1			T1	15		T3	91		T4	2
all_pins[3]	values[0x1]	304	1			T16	3		T14	1		T17	3
all_pins[3]	transitions[0x0=>0x1]	237	1			T16	2		T14	1		T17	2
all_pins[3]	transitions[0x1=>0x0]	433	1			T16	1		T17	12		T34	9
all_pins[4]	values[0x0]	117156	1			T1	15		T3	91		T4	2
all_pins[4]	values[0x1]	500	1			T16	2		T17	13		T34	9
all_pins[4]	transitions[0x0=>0x1]	415	1			T16	1		T17	12		T34	9
all_pins[4]	transitions[0x1=>0x0]	172	1			T16	3		T17	3		T33	2
all_pins[5]	values[0x0]	117399	1			T1	15		T3	91		T4	2
all_pins[5]	values[0x1]	257	1			T16	4		T17	4		T33	2
all_pins[5]	transitions[0x0=>0x1]	211	1			T16	4		T17	4		T33	2
all_pins[5]	transitions[0x1=>0x0]	795	1			T1	1		T3	2		T9	6
all_pins[6]	values[0x0]	116815	1			T1	14		T3	89		T4	2
all_pins[6]	values[0x1]	841	1			T1	1		T3	2		T9	6
all_pins[6]	transitions[0x0=>0x1]	788	1			T1	1		T3	2		T9	6
all_pins[6]	transitions[0x1=>0x0]	309	1			T16	3		T17	1		T140	5
all_pins[7]	values[0x0]	117294	1			T1	15		T3	91		T4	2
all_pins[7]	values[0x1]	362	1			T16	3		T17	2		T140	5
all_pins[7]	transitions[0x0=>0x1]	208	1			T16	2		T17	2		T140	1
all_pins[7]	transitions[0x1=>0x0]	18561	1			T3	43		T6	2		T7	2
all_pins[8]	values[0x0]	98941	1			T1	15		T3	48		T4	2
all_pins[8]	values[0x1]	18715	1			T3	43		T6	2		T7	2
all_pins[8]	transitions[0x0=>0x1]	9603	1			T3	32		T6	1		T7	2
all_pins[8]	transitions[0x1=>0x0]	15002	1			T1	2		T3	5		T6	44