Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	9056721	1			T1	5		T3	32		T6	78394
all_levels[1]	1793722	1			T3	1		T6	3685		T7	5
all_levels[2]	481922	1			T3	1		T6	3024		T10	36
all_levels[3]	354911	1			T1	5		T3	1		T6	3553
all_levels[4]	511444	1			T3	3		T6	3087		T9	2
all_levels[5]	255565	1			T6	3385		T10	40		T11	272
all_levels[6]	255712	1			T3	1		T6	3335		T10	49
all_levels[7]	375210	1			T3	4		T6	3685		T10	43
all_levels[8]	265974	1			T3	1		T6	3057		T10	43
all_levels[9]	263609	1			T3	4		T6	3275		T10	45
all_levels[10]	297932	1			T6	3784		T10	59		T11	294
all_levels[11]	318959	1			T6	3591		T10	50		T11	280
all_levels[12]	200574	1			T3	1		T6	3305		T10	51
all_levels[13]	403621	1			T3	2		T6	3160		T10	43
all_levels[14]	285557	1			T6	15583		T7	1		T10	50
all_levels[15]	203594	1			T3	4		T6	3177		T7	3
all_levels[16]	455500	1			T6	3395		T10	54		T11	300
all_levels[17]	345033	1			T3	2		T6	2638		T10	50
all_levels[18]	303625	1			T3	1		T6	3682		T10	38
all_levels[19]	493109	1			T6	3350		T10	37		T11	283
all_levels[20]	279105	1			T6	3440		T10	47		T11	291
all_levels[21]	328755	1			T3	1		T6	3519		T10	52
all_levels[22]	428916	1			T6	3222		T10	50		T11	293
all_levels[23]	206842	1			T6	17625		T10	46		T11	293
all_levels[24]	180954	1			T6	5196		T10	49		T11	293
all_levels[25]	423871	1			T3	2		T6	5714		T10	39
all_levels[26]	173912	1			T3	1		T6	5634		T10	39
all_levels[27]	394155	1			T3	2		T6	5074		T10	44
all_levels[28]	519204	1			T6	5516		T10	47		T11	291
all_levels[29]	545563	1			T6	4190		T10	42		T11	291
all_levels[30]	159494	1			T6	3623		T10	53		T11	305
all_levels[31]	895034	1			T6	7127		T10	1408		T11	11298
all_levels[32]	12041844	1			T1	8		T3	46		T6	119324

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33495355

1

T1

10

T3

110

T6

343349

auto[1]

4588

1

T1

8

T7

7

T9

8

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	9054054	1			T1	4		T3	32		T6	78394
all_levels[0]	auto[1]	2667	1			T1	1		T7	2		T9	3
all_levels[1]	auto[0]	1793368	1			T3	1		T6	3685		T7	3
all_levels[1]	auto[1]	354	1			T7	2		T14	1		T263	2
all_levels[2]	auto[0]	481878	1			T3	1		T6	3024		T10	36
all_levels[2]	auto[1]	44	1			T12	1		T263	1		T188	1
all_levels[3]	auto[0]	354772	1			T1	3		T3	1		T6	3553
all_levels[3]	auto[1]	139	1			T1	2		T40	1		T156	2
all_levels[4]	auto[0]	511430	1			T3	3		T6	3087		T9	1
all_levels[4]	auto[1]	14	1			T9	1		T105	1		T255	1
all_levels[5]	auto[0]	255530	1			T6	3385		T10	40		T11	272
all_levels[5]	auto[1]	35	1			T12	2		T105	2		T33	2
all_levels[6]	auto[0]	255675	1			T3	1		T6	3335		T10	49
all_levels[6]	auto[1]	37	1			T14	2		T115	1		T129	1
all_levels[7]	auto[0]	375098	1			T3	4		T6	3685		T10	43
all_levels[7]	auto[1]	112	1			T108	1		T130	4		T127	1
all_levels[8]	auto[0]	265954	1			T3	1		T6	3057		T10	43
all_levels[8]	auto[1]	20	1			T119	2		T224	1		T327	1
all_levels[9]	auto[0]	263586	1			T3	4		T6	3275		T10	45
all_levels[9]	auto[1]	23	1			T309	1		T58	1		T207	1
all_levels[10]	auto[0]	297901	1			T6	3784		T10	59		T11	294
all_levels[10]	auto[1]	31	1			T121	2		T93	1		T194	3
all_levels[11]	auto[0]	318927	1			T6	3591		T10	50		T11	280
all_levels[11]	auto[1]	32	1			T41	1		T128	1		T328	2
all_levels[12]	auto[0]	200541	1			T3	1		T6	3305		T10	51
all_levels[12]	auto[1]	33	1			T276	1		T277	2		T329	1
all_levels[13]	auto[0]	403595	1			T3	2		T6	3160		T10	43
all_levels[13]	auto[1]	26	1			T43	1		T108	3		T274	1
all_levels[14]	auto[0]	285538	1			T6	15583		T7	1		T10	50
all_levels[14]	auto[1]	19	1			T38	1		T319	1		T128	2
all_levels[15]	auto[0]	203486	1			T3	4		T6	3177		T7	2
all_levels[15]	auto[1]	108	1			T7	1		T18	18		T287	5
all_levels[16]	auto[0]	455468	1			T6	3395		T10	54		T11	300
all_levels[16]	auto[1]	32	1			T269	1		T115	1		T110	1
all_levels[17]	auto[0]	345010	1			T3	2		T6	2638		T10	50
all_levels[17]	auto[1]	23	1			T38	4		T99	1		T330	1
all_levels[18]	auto[0]	303602	1			T3	1		T6	3682		T10	38
all_levels[18]	auto[1]	23	1			T322	1		T100	1		T112	1
all_levels[19]	auto[0]	493089	1			T6	3350		T10	37		T11	283
all_levels[19]	auto[1]	20	1			T304	1		T167	1		T154	1
all_levels[20]	auto[0]	279086	1			T6	3440		T10	47		T11	291
all_levels[20]	auto[1]	19	1			T149	1		T94	1		T331	2
all_levels[21]	auto[0]	328724	1			T3	1		T6	3519		T10	52
all_levels[21]	auto[1]	31	1			T255	3		T134	1		T332	1
all_levels[22]	auto[0]	428893	1			T6	3222		T10	50		T11	293
all_levels[22]	auto[1]	23	1			T31	6		T111	1		T145	3
all_levels[23]	auto[0]	206819	1			T6	17625		T10	46		T11	293
all_levels[23]	auto[1]	23	1			T130	3		T136	1		T151	1
all_levels[24]	auto[0]	180940	1			T6	5196		T10	49		T11	293
all_levels[24]	auto[1]	14	1			T112	1		T333	1		T170	1
all_levels[25]	auto[0]	423850	1			T3	2		T6	5714		T10	39
all_levels[25]	auto[1]	21	1			T146	2		T334	1		T157	1
all_levels[26]	auto[0]	173888	1			T3	1		T6	5634		T10	39
all_levels[26]	auto[1]	24	1			T263	3		T115	1		T105	2
all_levels[27]	auto[0]	394131	1			T3	2		T6	5074		T10	44
all_levels[27]	auto[1]	24	1			T318	1		T108	1		T110	1
all_levels[28]	auto[0]	519179	1			T6	5516		T10	47		T11	291
all_levels[28]	auto[1]	25	1			T38	1		T44	2		T15	1
all_levels[29]	auto[0]	545548	1			T6	4190		T10	42		T11	291
all_levels[29]	auto[1]	15	1			T44	1		T15	1		T274	1
all_levels[30]	auto[0]	159484	1			T6	3623		T10	53		T11	305
all_levels[30]	auto[1]	10	1			T335	1		T226	1		T336	1
all_levels[31]	auto[0]	895017	1			T6	7127		T10	1408		T11	11298
all_levels[31]	auto[1]	17	1			T14	2		T128	1		T158	1
all_levels[32]	auto[0]	12041294	1			T1	3		T3	46		T6	119324
all_levels[32]	auto[1]	550	1			T1	5		T7	2		T9	4