Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	794	1			T16	7		T17	11		T33	7
all_values[1]	794	1			T16	7		T17	11		T33	7
all_values[2]	794	1			T16	7		T17	11		T33	7
all_values[3]	794	1			T16	7		T17	11		T33	7
all_values[4]	794	1			T16	7		T17	11		T33	7
all_values[5]	794	1			T16	7		T17	11		T33	7
all_values[6]	794	1			T16	7		T17	11		T33	7
all_values[7]	794	1			T16	7		T17	11		T33	7
all_values[8]	794	1			T16	7		T17	11		T33	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3728

1

T16

27

T17

65

T33

38

auto[1]

3418

1

T16

36

T17

34

T33

25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2356

1

T16

22

T17

32

T33

12

auto[1]

4790

1

T16

41

T17

67

T33

51

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4319

1

T16

37

T17

59

T33

32

auto[1]

2827

1

T16

26

T17

40

T33

31

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	252	1			T16	1		T17	5		T33	4
all_values[0]	auto[0]	auto[1]	auto[1]	239	1			T16	1		T17	1		T33	1
all_values[0]	auto[1]	auto[0]	auto[1]	150	1			T16	1		T17	1		T33	1
all_values[0]	auto[1]	auto[1]	auto[1]	153	1			T16	4		T17	4		T33	1
all_values[1]	auto[0]	auto[0]	auto[0]	263	1			T16	1		T17	5		T35	2
all_values[1]	auto[0]	auto[1]	auto[0]	218	1			T16	2		T17	4		T33	3
all_values[1]	auto[1]	auto[0]	auto[1]	166	1			T16	2		T17	2		T34	1
all_values[1]	auto[1]	auto[1]	auto[1]	147	1			T16	2		T33	4		T34	3
all_values[2]	auto[0]	auto[0]	auto[0]	159	1			T16	1		T17	6		T33	1
all_values[2]	auto[0]	auto[0]	auto[1]	72	1			T33	1		T34	3		T35	2
all_values[2]	auto[0]	auto[1]	auto[0]	153	1			T16	3		T35	1		T48	4
all_values[2]	auto[0]	auto[1]	auto[1]	94	1			T16	1		T17	1		T33	2
all_values[2]	auto[1]	auto[0]	auto[1]	166	1			T16	1		T17	3		T33	3
all_values[2]	auto[1]	auto[1]	auto[1]	150	1			T16	1		T17	1		T34	1
all_values[3]	auto[0]	auto[0]	auto[0]	177	1			T16	4		T17	3		T33	1
all_values[3]	auto[0]	auto[0]	auto[1]	76	1			T17	2		T33	1		T35	1
all_values[3]	auto[0]	auto[1]	auto[0]	146	1			T34	2		T35	1		T48	1
all_values[3]	auto[0]	auto[1]	auto[1]	88	1			T16	2		T17	1		T33	1
all_values[3]	auto[1]	auto[0]	auto[1]	175	1			T17	4		T33	4		T34	3
all_values[3]	auto[1]	auto[1]	auto[1]	132	1			T16	1		T17	1		T35	1
all_values[4]	auto[0]	auto[0]	auto[0]	154	1			T16	3		T17	2		T33	1
all_values[4]	auto[0]	auto[0]	auto[1]	70	1			T17	2		T34	1		T35	2
all_values[4]	auto[0]	auto[1]	auto[0]	143	1			T17	3		T33	1		T34	2
all_values[4]	auto[0]	auto[1]	auto[1]	106	1			T35	2		T48	4		T121	1
all_values[4]	auto[1]	auto[0]	auto[1]	166	1			T16	2		T17	4		T33	4
all_values[4]	auto[1]	auto[1]	auto[1]	155	1			T16	2		T33	1		T35	3
all_values[5]	auto[0]	auto[0]	auto[0]	173	1			T16	1		T17	2		T34	3
all_values[5]	auto[0]	auto[0]	auto[1]	79	1			T17	2		T33	1		T35	2
all_values[5]	auto[0]	auto[1]	auto[0]	123	1			T17	1		T33	1		T34	4
all_values[5]	auto[0]	auto[1]	auto[1]	85	1			T16	3		T17	2		T33	1
all_values[5]	auto[1]	auto[0]	auto[1]	166	1			T16	1		T17	3		T33	3
all_values[5]	auto[1]	auto[1]	auto[1]	168	1			T16	2		T17	1		T33	1
all_values[6]	auto[0]	auto[0]	auto[0]	180	1			T16	2		T17	3		T33	3
all_values[6]	auto[0]	auto[0]	auto[1]	69	1			T17	3		T33	1		T34	1
all_values[6]	auto[0]	auto[1]	auto[0]	140	1			T16	3		T34	4		T35	1
all_values[6]	auto[0]	auto[1]	auto[1]	85	1			T16	1		T33	1		T35	1
all_values[6]	auto[1]	auto[0]	auto[1]	155	1			T16	1		T17	2		T33	1
all_values[6]	auto[1]	auto[1]	auto[1]	165	1			T17	3		T33	1		T34	1
all_values[7]	auto[0]	auto[0]	auto[0]	173	1			T16	1		T17	2		T33	1
all_values[7]	auto[0]	auto[0]	auto[1]	81	1			T17	1		T33	1		T34	1
all_values[7]	auto[0]	auto[1]	auto[0]	154	1			T16	1		T17	1		T34	1
all_values[7]	auto[0]	auto[1]	auto[1]	77	1			T16	1		T17	1		T33	1
all_values[7]	auto[1]	auto[0]	auto[1]	173	1			T16	2		T17	3		T33	1
all_values[7]	auto[1]	auto[1]	auto[1]	136	1			T16	2		T17	3		T33	3
all_values[8]	auto[0]	auto[0]	auto[1]	263	1			T16	2		T17	1		T33	2
all_values[8]	auto[0]	auto[1]	auto[1]	227	1			T16	3		T17	5		T33	2
all_values[8]	auto[1]	auto[0]	auto[1]	170	1			T16	1		T17	4		T33	3
all_values[8]	auto[1]	auto[1]	auto[1]	134	1			T16	1		T17	1		T34	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal