Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.53


Total test records in report: 1319
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T1255 /workspace/coverage/cover_reg_top/2.uart_tl_errors.619291316 Aug 09 07:14:50 PM PDT 24 Aug 09 07:14:51 PM PDT 24 70575214 ps
T1256 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1069559011 Aug 09 07:15:09 PM PDT 24 Aug 09 07:15:10 PM PDT 24 77905543 ps
T1257 /workspace/coverage/cover_reg_top/34.uart_intr_test.592984680 Aug 09 07:15:09 PM PDT 24 Aug 09 07:15:10 PM PDT 24 43558315 ps
T1258 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.607351928 Aug 09 07:14:56 PM PDT 24 Aug 09 07:14:57 PM PDT 24 30750479 ps
T1259 /workspace/coverage/cover_reg_top/15.uart_intr_test.235612409 Aug 09 07:15:05 PM PDT 24 Aug 09 07:15:05 PM PDT 24 17024795 ps
T1260 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3950418914 Aug 09 07:14:58 PM PDT 24 Aug 09 07:14:59 PM PDT 24 20079994 ps
T1261 /workspace/coverage/cover_reg_top/10.uart_csr_rw.509293254 Aug 09 07:14:56 PM PDT 24 Aug 09 07:14:57 PM PDT 24 44892191 ps
T1262 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2379859609 Aug 09 07:14:54 PM PDT 24 Aug 09 07:14:56 PM PDT 24 197761525 ps
T1263 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3079387053 Aug 09 07:15:10 PM PDT 24 Aug 09 07:15:11 PM PDT 24 16609504 ps
T1264 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3255637476 Aug 09 07:15:03 PM PDT 24 Aug 09 07:15:04 PM PDT 24 65411145 ps
T1265 /workspace/coverage/cover_reg_top/38.uart_intr_test.1584777714 Aug 09 07:15:30 PM PDT 24 Aug 09 07:15:31 PM PDT 24 10942048 ps
T89 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1135682380 Aug 09 07:15:05 PM PDT 24 Aug 09 07:15:06 PM PDT 24 54363835 ps
T1266 /workspace/coverage/cover_reg_top/9.uart_intr_test.3345969169 Aug 09 07:14:59 PM PDT 24 Aug 09 07:15:00 PM PDT 24 62689949 ps
T1267 /workspace/coverage/cover_reg_top/12.uart_tl_errors.654358157 Aug 09 07:15:12 PM PDT 24 Aug 09 07:15:14 PM PDT 24 701080938 ps
T1268 /workspace/coverage/cover_reg_top/48.uart_intr_test.2220131174 Aug 09 07:15:12 PM PDT 24 Aug 09 07:15:12 PM PDT 24 83578661 ps
T1269 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2385166781 Aug 09 07:15:14 PM PDT 24 Aug 09 07:15:15 PM PDT 24 51317132 ps
T1270 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.193268775 Aug 09 07:15:07 PM PDT 24 Aug 09 07:15:13 PM PDT 24 37201903 ps
T1271 /workspace/coverage/cover_reg_top/4.uart_tl_errors.1658496740 Aug 09 07:14:59 PM PDT 24 Aug 09 07:15:00 PM PDT 24 91217648 ps
T1272 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2746563486 Aug 09 07:15:12 PM PDT 24 Aug 09 07:15:13 PM PDT 24 60810161 ps
T1273 /workspace/coverage/cover_reg_top/29.uart_intr_test.3166286950 Aug 09 07:15:09 PM PDT 24 Aug 09 07:15:10 PM PDT 24 23949106 ps
T1274 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1619589992 Aug 09 07:14:58 PM PDT 24 Aug 09 07:14:59 PM PDT 24 95503075 ps
T1275 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1551457751 Aug 09 07:15:08 PM PDT 24 Aug 09 07:15:09 PM PDT 24 158708967 ps
T1276 /workspace/coverage/cover_reg_top/35.uart_intr_test.3997293870 Aug 09 07:15:12 PM PDT 24 Aug 09 07:15:13 PM PDT 24 15876247 ps
T1277 /workspace/coverage/cover_reg_top/7.uart_tl_errors.9909301 Aug 09 07:14:53 PM PDT 24 Aug 09 07:14:55 PM PDT 24 417292977 ps
T1278 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.4015195249 Aug 09 07:14:54 PM PDT 24 Aug 09 07:14:54 PM PDT 24 31301192 ps
T1279 /workspace/coverage/cover_reg_top/22.uart_intr_test.3913649048 Aug 09 07:15:17 PM PDT 24 Aug 09 07:15:18 PM PDT 24 19998110 ps
T84 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.846248772 Aug 09 07:14:49 PM PDT 24 Aug 09 07:14:51 PM PDT 24 338890983 ps
T1280 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.847377277 Aug 09 07:15:12 PM PDT 24 Aug 09 07:15:13 PM PDT 24 49769461 ps
T1281 /workspace/coverage/cover_reg_top/47.uart_intr_test.661622955 Aug 09 07:15:31 PM PDT 24 Aug 09 07:15:32 PM PDT 24 12619507 ps
T1282 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1489464459 Aug 09 07:14:54 PM PDT 24 Aug 09 07:14:56 PM PDT 24 212930255 ps
T1283 /workspace/coverage/cover_reg_top/7.uart_intr_test.3351216145 Aug 09 07:14:46 PM PDT 24 Aug 09 07:14:47 PM PDT 24 24244397 ps
T1284 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3795874823 Aug 09 07:15:05 PM PDT 24 Aug 09 07:15:05 PM PDT 24 49829116 ps
T1285 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3157111118 Aug 09 07:15:04 PM PDT 24 Aug 09 07:15:06 PM PDT 24 271454651 ps
T1286 /workspace/coverage/cover_reg_top/36.uart_intr_test.1301151466 Aug 09 07:15:10 PM PDT 24 Aug 09 07:15:11 PM PDT 24 60517793 ps
T1287 /workspace/coverage/cover_reg_top/8.uart_tl_errors.3648618358 Aug 09 07:15:01 PM PDT 24 Aug 09 07:15:02 PM PDT 24 204240611 ps
T1288 /workspace/coverage/cover_reg_top/21.uart_intr_test.2710868962 Aug 09 07:15:11 PM PDT 24 Aug 09 07:15:12 PM PDT 24 194615140 ps
T1289 /workspace/coverage/cover_reg_top/1.uart_tl_errors.1671338381 Aug 09 07:14:46 PM PDT 24 Aug 09 07:14:48 PM PDT 24 219455104 ps
T1290 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1373853250 Aug 09 07:15:05 PM PDT 24 Aug 09 07:15:06 PM PDT 24 52811573 ps
T1291 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3860525656 Aug 09 07:15:00 PM PDT 24 Aug 09 07:15:05 PM PDT 24 74361344 ps
T1292 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3051555166 Aug 09 07:14:58 PM PDT 24 Aug 09 07:14:59 PM PDT 24 24671721 ps
T1293 /workspace/coverage/cover_reg_top/25.uart_intr_test.1308436511 Aug 09 07:15:18 PM PDT 24 Aug 09 07:15:19 PM PDT 24 156442465 ps
T1294 /workspace/coverage/cover_reg_top/18.uart_intr_test.3568372624 Aug 09 07:15:10 PM PDT 24 Aug 09 07:15:11 PM PDT 24 39543367 ps
T1295 /workspace/coverage/cover_reg_top/16.uart_tl_errors.3685172654 Aug 09 07:15:03 PM PDT 24 Aug 09 07:15:04 PM PDT 24 83626521 ps
T1296 /workspace/coverage/cover_reg_top/16.uart_intr_test.477667813 Aug 09 07:15:05 PM PDT 24 Aug 09 07:15:05 PM PDT 24 13309128 ps
T1297 /workspace/coverage/cover_reg_top/27.uart_intr_test.2400694018 Aug 09 07:15:26 PM PDT 24 Aug 09 07:15:26 PM PDT 24 25021748 ps
T56 /workspace/coverage/cover_reg_top/2.uart_csr_rw.642241381 Aug 09 07:14:46 PM PDT 24 Aug 09 07:14:47 PM PDT 24 12340371 ps
T1298 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1698394553 Aug 09 07:14:58 PM PDT 24 Aug 09 07:14:59 PM PDT 24 137764382 ps
T1299 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1391652580 Aug 09 07:15:05 PM PDT 24 Aug 09 07:15:05 PM PDT 24 201627532 ps
T1300 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2445976577 Aug 09 07:14:58 PM PDT 24 Aug 09 07:14:59 PM PDT 24 31464748 ps
T1301 /workspace/coverage/cover_reg_top/6.uart_csr_rw.1997220869 Aug 09 07:15:06 PM PDT 24 Aug 09 07:15:07 PM PDT 24 12464186 ps
T1302 /workspace/coverage/cover_reg_top/37.uart_intr_test.2925754729 Aug 09 07:15:09 PM PDT 24 Aug 09 07:15:10 PM PDT 24 14833465 ps
T122 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1298691126 Aug 09 07:14:55 PM PDT 24 Aug 09 07:14:56 PM PDT 24 177647857 ps
T1303 /workspace/coverage/cover_reg_top/10.uart_tl_errors.143721461 Aug 09 07:15:12 PM PDT 24 Aug 09 07:15:14 PM PDT 24 344623830 ps
T1304 /workspace/coverage/cover_reg_top/19.uart_tl_errors.3209896434 Aug 09 07:15:12 PM PDT 24 Aug 09 07:15:14 PM PDT 24 49854989 ps
T1305 /workspace/coverage/cover_reg_top/12.uart_csr_rw.1573449891 Aug 09 07:15:10 PM PDT 24 Aug 09 07:15:11 PM PDT 24 16245810 ps
T1306 /workspace/coverage/cover_reg_top/3.uart_intr_test.872378058 Aug 09 07:14:58 PM PDT 24 Aug 09 07:14:59 PM PDT 24 13327996 ps
T1307 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1457404185 Aug 09 07:15:25 PM PDT 24 Aug 09 07:15:25 PM PDT 24 19857066 ps
T1308 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3409770828 Aug 09 07:15:09 PM PDT 24 Aug 09 07:15:10 PM PDT 24 103724143 ps
T1309 /workspace/coverage/cover_reg_top/19.uart_csr_rw.654238185 Aug 09 07:15:07 PM PDT 24 Aug 09 07:15:07 PM PDT 24 11134920 ps
T1310 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3502066147 Aug 09 07:15:10 PM PDT 24 Aug 09 07:15:11 PM PDT 24 107430458 ps
T1311 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3096688499 Aug 09 07:14:55 PM PDT 24 Aug 09 07:14:56 PM PDT 24 72539674 ps
T1312 /workspace/coverage/cover_reg_top/13.uart_intr_test.78438067 Aug 09 07:15:04 PM PDT 24 Aug 09 07:15:05 PM PDT 24 48880781 ps
T1313 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1292880204 Aug 09 07:15:07 PM PDT 24 Aug 09 07:15:09 PM PDT 24 306983004 ps
T1314 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2305632596 Aug 09 07:15:14 PM PDT 24 Aug 09 07:15:14 PM PDT 24 14073513 ps
T1315 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.292632753 Aug 09 07:15:21 PM PDT 24 Aug 09 07:15:22 PM PDT 24 40672279 ps
T1316 /workspace/coverage/cover_reg_top/3.uart_csr_rw.419775068 Aug 09 07:15:10 PM PDT 24 Aug 09 07:15:11 PM PDT 24 77957766 ps
T1317 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1034939364 Aug 09 07:14:55 PM PDT 24 Aug 09 07:14:57 PM PDT 24 96413334 ps
T1318 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1256564226 Aug 09 07:14:50 PM PDT 24 Aug 09 07:14:51 PM PDT 24 97708887 ps
T1319 /workspace/coverage/cover_reg_top/20.uart_intr_test.2543902029 Aug 09 07:15:10 PM PDT 24 Aug 09 07:15:11 PM PDT 24 35896021 ps

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2596636010
Short name T10
Test name
Test status
Simulation time 159958330585 ps
CPU time 350.27 seconds
Started Aug 09 07:18:55 PM PDT 24
Finished Aug 09 07:24:45 PM PDT 24
Peak memory 199964 kb
Host smart-a8c4a180-648e-4f3c-ac33-3c05379699f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2596636010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2596636010
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2905542390
Short name T17
Test name
Test status
Simulation time 53503672020 ps
CPU time 1016.38 seconds
Started Aug 09 07:20:37 PM PDT 24
Finished Aug 09 07:37:34 PM PDT 24
Peak memory 216704 kb
Host smart-27a522d8-a8c6-4121-add2-e1ecd11806c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905542390 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2905542390
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_stress_all.1128202452
Short name T13
Test name
Test status
Simulation time 350793976263 ps
CPU time 259.96 seconds
Started Aug 09 07:18:49 PM PDT 24
Finished Aug 09 07:23:09 PM PDT 24
Peak memory 199980 kb
Host smart-ed0332b6-e955-48e4-9eee-1d9f55d4290b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128202452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1128202452
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all.3646831870
Short name T249
Test name
Test status
Simulation time 279107378194 ps
CPU time 1153.53 seconds
Started Aug 09 07:20:49 PM PDT 24
Finished Aug 09 07:40:03 PM PDT 24
Peak memory 208460 kb
Host smart-23b1630c-bde7-4fd5-8e05-be5c134a482c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646831870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3646831870
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3079866805
Short name T14
Test name
Test status
Simulation time 102708850701 ps
CPU time 1000.56 seconds
Started Aug 09 07:18:41 PM PDT 24
Finished Aug 09 07:35:22 PM PDT 24
Peak memory 224788 kb
Host smart-e1d33115-cb28-40ce-9327-9c7e7ec9f448
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079866805 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3079866805
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2863127381
Short name T265
Test name
Test status
Simulation time 142478340792 ps
CPU time 821.09 seconds
Started Aug 09 07:18:59 PM PDT 24
Finished Aug 09 07:32:40 PM PDT 24
Peak memory 199832 kb
Host smart-976a6f49-8707-4269-b451-f4065455b0dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2863127381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2863127381
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_stress_all.1561079423
Short name T107
Test name
Test status
Simulation time 345390079514 ps
CPU time 202.63 seconds
Started Aug 09 07:22:15 PM PDT 24
Finished Aug 09 07:25:38 PM PDT 24
Peak memory 200008 kb
Host smart-f4fa2b4c-15a2-4415-859c-9e89bc05e975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561079423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1561079423
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1095655920
Short name T33
Test name
Test status
Simulation time 157163996098 ps
CPU time 377.62 seconds
Started Aug 09 07:23:07 PM PDT 24
Finished Aug 09 07:29:25 PM PDT 24
Peak memory 216496 kb
Host smart-50159e92-3b3e-41d5-bfaa-958e72690d5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095655920 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1095655920
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_stress_all.2685946167
Short name T3
Test name
Test status
Simulation time 276171574310 ps
CPU time 104.25 seconds
Started Aug 09 07:21:07 PM PDT 24
Finished Aug 09 07:22:52 PM PDT 24
Peak memory 199948 kb
Host smart-934de21b-4c1d-4806-8342-3d31d9a396a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685946167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2685946167
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1111733510
Short name T26
Test name
Test status
Simulation time 37664548 ps
CPU time 0.78 seconds
Started Aug 09 07:18:34 PM PDT 24
Finished Aug 09 07:18:35 PM PDT 24
Peak memory 218388 kb
Host smart-2087691b-1a83-4fad-8cfb-bb0fa1ec9404
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111733510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1111733510
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/11.uart_alert_test.588376591
Short name T339
Test name
Test status
Simulation time 39573429 ps
CPU time 0.57 seconds
Started Aug 09 07:19:12 PM PDT 24
Finished Aug 09 07:19:13 PM PDT 24
Peak memory 195336 kb
Host smart-2e0b3c66-037d-4612-8587-f21d0c706862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588376591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.588376591
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_stress_all.2504366338
Short name T16
Test name
Test status
Simulation time 100234246539 ps
CPU time 735.67 seconds
Started Aug 09 07:21:50 PM PDT 24
Finished Aug 09 07:34:06 PM PDT 24
Peak memory 200000 kb
Host smart-ddac9876-4c0a-4907-b901-1f9459eada13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504366338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2504366338
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all.4224544066
Short name T275
Test name
Test status
Simulation time 267890139373 ps
CPU time 400.53 seconds
Started Aug 09 07:22:36 PM PDT 24
Finished Aug 09 07:29:16 PM PDT 24
Peak memory 208252 kb
Host smart-220a1eea-d585-4b8e-8e98-bb84248c97e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224544066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.4224544066
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all.167737500
Short name T256
Test name
Test status
Simulation time 625456982994 ps
CPU time 140.67 seconds
Started Aug 09 07:21:34 PM PDT 24
Finished Aug 09 07:23:55 PM PDT 24
Peak memory 208296 kb
Host smart-e3194c09-7ba1-46ee-beff-b6fca91058c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167737500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.167737500
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.970431444
Short name T121
Test name
Test status
Simulation time 335000512719 ps
CPU time 1106.07 seconds
Started Aug 09 07:20:52 PM PDT 24
Finished Aug 09 07:39:18 PM PDT 24
Peak memory 224752 kb
Host smart-d1804823-ca8d-429e-849e-a5c2de37ac3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970431444 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.970431444
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.4100576358
Short name T136
Test name
Test status
Simulation time 117405420924 ps
CPU time 89.85 seconds
Started Aug 09 07:22:51 PM PDT 24
Finished Aug 09 07:24:21 PM PDT 24
Peak memory 199960 kb
Host smart-fa588b01-3a2a-4ed3-beaa-4ab408f2d5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100576358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.4100576358
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2564994546
Short name T127
Test name
Test status
Simulation time 40208589147 ps
CPU time 36.27 seconds
Started Aug 09 07:24:53 PM PDT 24
Finished Aug 09 07:25:29 PM PDT 24
Peak memory 199920 kb
Host smart-dbfa5283-7d03-4e84-a954-af8660f779a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564994546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2564994546
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.330401579
Short name T82
Test name
Test status
Simulation time 209236815 ps
CPU time 1.26 seconds
Started Aug 09 07:15:11 PM PDT 24
Finished Aug 09 07:15:13 PM PDT 24
Peak memory 199680 kb
Host smart-0f6d17df-58cd-4dba-9845-0629db376b25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330401579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.330401579
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2563711892
Short name T55
Test name
Test status
Simulation time 132058696 ps
CPU time 0.75 seconds
Started Aug 09 07:14:55 PM PDT 24
Finished Aug 09 07:14:55 PM PDT 24
Peak memory 196612 kb
Host smart-91c74ed8-af97-4ae6-a018-0300d61350e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563711892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2563711892
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.566709687
Short name T135
Test name
Test status
Simulation time 155563466537 ps
CPU time 198.58 seconds
Started Aug 09 07:25:11 PM PDT 24
Finished Aug 09 07:28:29 PM PDT 24
Peak memory 199916 kb
Host smart-e93bb602-6f21-4bdc-8f56-9d4c092c471a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566709687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.566709687
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.675076607
Short name T189
Test name
Test status
Simulation time 189883430332 ps
CPU time 410.32 seconds
Started Aug 09 07:23:18 PM PDT 24
Finished Aug 09 07:30:09 PM PDT 24
Peak memory 199728 kb
Host smart-50a43c46-d51d-4e12-ab4c-cff471f2c73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675076607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.675076607
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.106304201
Short name T11
Test name
Test status
Simulation time 131790131778 ps
CPU time 1464.12 seconds
Started Aug 09 07:20:26 PM PDT 24
Finished Aug 09 07:44:50 PM PDT 24
Peak memory 199900 kb
Host smart-52826a9a-fda2-430f-a0af-9b77eaf84c24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106304201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.106304201
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3506214120
Short name T23
Test name
Test status
Simulation time 151419221407 ps
CPU time 60.2 seconds
Started Aug 09 07:19:28 PM PDT 24
Finished Aug 09 07:20:28 PM PDT 24
Peak memory 199796 kb
Host smart-1026ee83-2ea2-404d-8a51-69b5364e9bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506214120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3506214120
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1537400509
Short name T119
Test name
Test status
Simulation time 573879075633 ps
CPU time 727.21 seconds
Started Aug 09 07:23:37 PM PDT 24
Finished Aug 09 07:35:44 PM PDT 24
Peak memory 224836 kb
Host smart-0dfde06e-956d-4a2b-ac67-af31486be639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537400509 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1537400509
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2213675854
Short name T72
Test name
Test status
Simulation time 149358512 ps
CPU time 0.61 seconds
Started Aug 09 07:15:05 PM PDT 24
Finished Aug 09 07:15:06 PM PDT 24
Peak memory 195860 kb
Host smart-a567c85e-458c-4384-830c-4460f8efbfc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213675854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2213675854
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/default/10.uart_stress_all.2774653879
Short name T130
Test name
Test status
Simulation time 136245940945 ps
CPU time 85.15 seconds
Started Aug 09 07:19:16 PM PDT 24
Finished Aug 09 07:20:41 PM PDT 24
Peak memory 199684 kb
Host smart-53e31928-8c5c-48e9-a09e-d1c96b80f3d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774653879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2774653879
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all.1748605924
Short name T165
Test name
Test status
Simulation time 102017970417 ps
CPU time 569.23 seconds
Started Aug 09 07:21:36 PM PDT 24
Finished Aug 09 07:31:05 PM PDT 24
Peak memory 216432 kb
Host smart-a3af0490-0c49-42ef-b408-6ca7dd6d9dae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748605924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1748605924
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.2143171572
Short name T49
Test name
Test status
Simulation time 602572418590 ps
CPU time 863.5 seconds
Started Aug 09 07:19:03 PM PDT 24
Finished Aug 09 07:33:27 PM PDT 24
Peak memory 224748 kb
Host smart-f7b62424-5d37-46ef-a729-4c40d343a9a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143171572 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2143171572
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1512314946
Short name T209
Test name
Test status
Simulation time 307902294863 ps
CPU time 1015.29 seconds
Started Aug 09 07:21:31 PM PDT 24
Finished Aug 09 07:38:27 PM PDT 24
Peak memory 224736 kb
Host smart-3e819ac6-e117-4862-b8b5-93ecbc23f6e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512314946 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1512314946
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1776317925
Short name T30
Test name
Test status
Simulation time 20717279994 ps
CPU time 223.95 seconds
Started Aug 09 07:22:37 PM PDT 24
Finished Aug 09 07:26:21 PM PDT 24
Peak memory 216448 kb
Host smart-ff415760-b18c-42e1-95f1-edd3a6b7a583
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776317925 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1776317925
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2805065547
Short name T154
Test name
Test status
Simulation time 191757980350 ps
CPU time 555.62 seconds
Started Aug 09 07:19:45 PM PDT 24
Finished Aug 09 07:29:01 PM PDT 24
Peak memory 224820 kb
Host smart-fbc7d77c-43a8-4d58-9196-6052482a824d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805065547 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2805065547
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.4016783111
Short name T183
Test name
Test status
Simulation time 106754740993 ps
CPU time 187.72 seconds
Started Aug 09 07:23:48 PM PDT 24
Finished Aug 09 07:26:56 PM PDT 24
Peak memory 199876 kb
Host smart-be7aa46a-e5cd-484a-afd8-b08360f12ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016783111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.4016783111
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.4212477334
Short name T9
Test name
Test status
Simulation time 30888410396 ps
CPU time 17.9 seconds
Started Aug 09 07:25:00 PM PDT 24
Finished Aug 09 07:25:18 PM PDT 24
Peak memory 199916 kb
Host smart-0e56f914-9239-48b0-9223-cf63158f52a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212477334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.4212477334
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all.3684519984
Short name T148
Test name
Test status
Simulation time 230920589569 ps
CPU time 860.7 seconds
Started Aug 09 07:21:32 PM PDT 24
Finished Aug 09 07:35:53 PM PDT 24
Peak memory 199912 kb
Host smart-1984aa4b-e7f4-4b6d-b04f-a16a3f54c63c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684519984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3684519984
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2038640961
Short name T186
Test name
Test status
Simulation time 594470699113 ps
CPU time 381.05 seconds
Started Aug 09 07:23:14 PM PDT 24
Finished Aug 09 07:29:35 PM PDT 24
Peak memory 224824 kb
Host smart-04539285-9bb3-4173-8489-164c62f8ffa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038640961 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2038640961
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3157111118
Short name T1285
Test name
Test status
Simulation time 271454651 ps
CPU time 1.25 seconds
Started Aug 09 07:15:04 PM PDT 24
Finished Aug 09 07:15:06 PM PDT 24
Peak memory 199788 kb
Host smart-9a80c78e-4765-4c7b-93b6-356bdd79b47c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157111118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3157111118
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3175440532
Short name T146
Test name
Test status
Simulation time 291395162052 ps
CPU time 191.93 seconds
Started Aug 09 07:24:28 PM PDT 24
Finished Aug 09 07:27:40 PM PDT 24
Peak memory 199908 kb
Host smart-fcf18487-b437-45cc-936f-8155436f5a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175440532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3175440532
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.834820756
Short name T94
Test name
Test status
Simulation time 43748968506 ps
CPU time 32.89 seconds
Started Aug 09 07:24:44 PM PDT 24
Finished Aug 09 07:25:17 PM PDT 24
Peak memory 199796 kb
Host smart-d098f508-9c7e-45cc-a0ad-a81bcca5ea7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834820756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.834820756
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.846248772
Short name T84
Test name
Test status
Simulation time 338890983 ps
CPU time 1.4 seconds
Started Aug 09 07:14:49 PM PDT 24
Finished Aug 09 07:14:51 PM PDT 24
Peak memory 199628 kb
Host smart-fdd3b276-1f08-4eb4-bd0f-28fba5f5e1a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846248772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.846248772
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2734665721
Short name T160
Test name
Test status
Simulation time 51830275014 ps
CPU time 22.55 seconds
Started Aug 09 07:19:13 PM PDT 24
Finished Aug 09 07:19:36 PM PDT 24
Peak memory 199968 kb
Host smart-ba44e732-22a5-4f60-8ac7-d3cb153ede04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734665721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2734665721
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2702024985
Short name T15
Test name
Test status
Simulation time 18548324774 ps
CPU time 30.99 seconds
Started Aug 09 07:25:18 PM PDT 24
Finished Aug 09 07:25:49 PM PDT 24
Peak memory 199912 kb
Host smart-ebb5719d-ab1a-4387-8332-c7df86c4975c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702024985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2702024985
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3168273448
Short name T92
Test name
Test status
Simulation time 365555845469 ps
CPU time 333.15 seconds
Started Aug 09 07:21:50 PM PDT 24
Finished Aug 09 07:27:24 PM PDT 24
Peak memory 216560 kb
Host smart-5759764a-698a-44d9-9ac8-30c585540632
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168273448 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3168273448
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.408413121
Short name T234
Test name
Test status
Simulation time 28284951707 ps
CPU time 59.43 seconds
Started Aug 09 07:23:39 PM PDT 24
Finished Aug 09 07:24:39 PM PDT 24
Peak memory 199892 kb
Host smart-22f3e3e4-9f36-4b88-b075-183e52dd4700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408413121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.408413121
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all.558902851
Short name T195
Test name
Test status
Simulation time 934773129572 ps
CPU time 341.8 seconds
Started Aug 09 07:18:58 PM PDT 24
Finished Aug 09 07:24:40 PM PDT 24
Peak memory 199968 kb
Host smart-bb3bbe89-15e6-4f40-a364-1a71bf4ed977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558902851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.558902851
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.4074807142
Short name T170
Test name
Test status
Simulation time 91782474887 ps
CPU time 647.8 seconds
Started Aug 09 07:23:08 PM PDT 24
Finished Aug 09 07:33:56 PM PDT 24
Peak memory 224804 kb
Host smart-5e915e95-e028-4282-8c83-e04d9bd8d3a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074807142 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.4074807142
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2625570984
Short name T151
Test name
Test status
Simulation time 24709339023 ps
CPU time 39.93 seconds
Started Aug 09 07:18:31 PM PDT 24
Finished Aug 09 07:19:11 PM PDT 24
Peak memory 199996 kb
Host smart-82c7cbf4-7ddb-4197-8c51-df4da153f586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625570984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2625570984
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_stress_all.3294617884
Short name T208
Test name
Test status
Simulation time 59860294318 ps
CPU time 671.03 seconds
Started Aug 09 07:18:41 PM PDT 24
Finished Aug 09 07:29:52 PM PDT 24
Peak memory 199992 kb
Host smart-2736941c-8dc9-43c6-b906-7652acfcc79e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294617884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3294617884
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1133874349
Short name T277
Test name
Test status
Simulation time 280150765477 ps
CPU time 65.29 seconds
Started Aug 09 07:25:01 PM PDT 24
Finished Aug 09 07:26:07 PM PDT 24
Peak memory 199972 kb
Host smart-1dfd02f0-ef95-41b5-b3ec-708353ede733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133874349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1133874349
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3056855251
Short name T145
Test name
Test status
Simulation time 149968792883 ps
CPU time 130.32 seconds
Started Aug 09 07:21:33 PM PDT 24
Finished Aug 09 07:23:44 PM PDT 24
Peak memory 199952 kb
Host smart-3d77a572-50ce-48ab-a0e5-04e1db2cac54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056855251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3056855251
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.4044413348
Short name T246
Test name
Test status
Simulation time 97360842035 ps
CPU time 83.76 seconds
Started Aug 09 07:23:26 PM PDT 24
Finished Aug 09 07:24:50 PM PDT 24
Peak memory 199960 kb
Host smart-539f4cba-f993-45d0-88e0-def1077cea89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044413348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.4044413348
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1835316865
Short name T226
Test name
Test status
Simulation time 136397531623 ps
CPU time 139.19 seconds
Started Aug 09 07:23:47 PM PDT 24
Finished Aug 09 07:26:06 PM PDT 24
Peak memory 199880 kb
Host smart-df1d0574-4492-48d0-8463-590f302d6cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835316865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1835316865
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all.2907245746
Short name T173
Test name
Test status
Simulation time 60255894814 ps
CPU time 95.98 seconds
Started Aug 09 07:19:29 PM PDT 24
Finished Aug 09 07:21:05 PM PDT 24
Peak memory 199980 kb
Host smart-f29b2cd6-78d4-4b07-8d0b-fdfb8070c03a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907245746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2907245746
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.226540420
Short name T367
Test name
Test status
Simulation time 219339011763 ps
CPU time 113.07 seconds
Started Aug 09 07:19:35 PM PDT 24
Finished Aug 09 07:21:28 PM PDT 24
Peak memory 199940 kb
Host smart-607fae60-99c7-4c68-b80c-bb35681598a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226540420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.226540420
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2854077115
Short name T230
Test name
Test status
Simulation time 33645218656 ps
CPU time 47.41 seconds
Started Aug 09 07:19:53 PM PDT 24
Finished Aug 09 07:20:40 PM PDT 24
Peak memory 199884 kb
Host smart-b6c2cb6e-a954-4e72-98a8-990810bc194e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854077115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2854077115
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.956090674
Short name T133
Test name
Test status
Simulation time 15703180516 ps
CPU time 5.88 seconds
Started Aug 09 07:19:10 PM PDT 24
Finished Aug 09 07:19:16 PM PDT 24
Peak memory 199216 kb
Host smart-a186ee0f-8ce0-4584-9d4f-c43e132549d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956090674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.956090674
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3476459593
Short name T235
Test name
Test status
Simulation time 145940184398 ps
CPU time 54.7 seconds
Started Aug 09 07:23:36 PM PDT 24
Finished Aug 09 07:24:31 PM PDT 24
Peak memory 199992 kb
Host smart-c0fb3c58-dac9-40c7-9e97-5c0073727b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476459593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3476459593
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.660554672
Short name T228
Test name
Test status
Simulation time 169621249909 ps
CPU time 256.41 seconds
Started Aug 09 07:23:55 PM PDT 24
Finished Aug 09 07:28:12 PM PDT 24
Peak memory 199332 kb
Host smart-a92c505a-5d7b-45e4-b2ce-3485cf77c965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660554672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.660554672
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3568144557
Short name T237
Test name
Test status
Simulation time 117617293973 ps
CPU time 45.22 seconds
Started Aug 09 07:23:55 PM PDT 24
Finished Aug 09 07:24:40 PM PDT 24
Peak memory 199684 kb
Host smart-35b2c936-e885-4eff-b160-d3354601edba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568144557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3568144557
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1840915131
Short name T245
Test name
Test status
Simulation time 59877984907 ps
CPU time 88.75 seconds
Started Aug 09 07:23:56 PM PDT 24
Finished Aug 09 07:25:25 PM PDT 24
Peak memory 199948 kb
Host smart-258f2a43-08c0-4e67-81be-b7532c7953c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840915131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1840915131
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3677330635
Short name T128
Test name
Test status
Simulation time 88462323253 ps
CPU time 139.47 seconds
Started Aug 09 07:23:55 PM PDT 24
Finished Aug 09 07:26:15 PM PDT 24
Peak memory 199864 kb
Host smart-480deb1c-363a-497e-b305-914bf5b8a5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677330635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3677330635
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.4045960533
Short name T202
Test name
Test status
Simulation time 96879531356 ps
CPU time 30.88 seconds
Started Aug 09 07:24:03 PM PDT 24
Finished Aug 09 07:24:34 PM PDT 24
Peak memory 199704 kb
Host smart-b9d59f45-71b7-4160-8c8c-cb9465af4459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045960533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.4045960533
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.4110405177
Short name T212
Test name
Test status
Simulation time 18980603786 ps
CPU time 53.02 seconds
Started Aug 09 07:24:05 PM PDT 24
Finished Aug 09 07:24:58 PM PDT 24
Peak memory 199928 kb
Host smart-da15bd84-8516-4b27-af94-dfbf06681ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110405177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.4110405177
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2607982376
Short name T244
Test name
Test status
Simulation time 245792153578 ps
CPU time 76.84 seconds
Started Aug 09 07:24:03 PM PDT 24
Finished Aug 09 07:25:20 PM PDT 24
Peak memory 199980 kb
Host smart-317784e5-3622-4109-b1b3-6296326a6428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607982376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2607982376
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.121765631
Short name T231
Test name
Test status
Simulation time 26001936541 ps
CPU time 43.21 seconds
Started Aug 09 07:24:10 PM PDT 24
Finished Aug 09 07:24:53 PM PDT 24
Peak memory 199952 kb
Host smart-62d5c230-0fea-4311-aab3-8a1028151c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121765631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.121765631
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3966799151
Short name T217
Test name
Test status
Simulation time 19376163137 ps
CPU time 16.5 seconds
Started Aug 09 07:24:21 PM PDT 24
Finished Aug 09 07:24:37 PM PDT 24
Peak memory 199860 kb
Host smart-214dd4da-fa19-4888-9bab-875aeb3c1f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966799151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3966799151
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1476810021
Short name T404
Test name
Test status
Simulation time 58951943483 ps
CPU time 76.53 seconds
Started Aug 09 07:19:45 PM PDT 24
Finished Aug 09 07:21:02 PM PDT 24
Peak memory 199980 kb
Host smart-669b7118-2c41-4f5d-bc0e-8d3a394ab215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476810021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1476810021
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2026577260
Short name T225
Test name
Test status
Simulation time 92731904714 ps
CPU time 70.67 seconds
Started Aug 09 07:24:26 PM PDT 24
Finished Aug 09 07:25:37 PM PDT 24
Peak memory 199900 kb
Host smart-487583a7-6597-4adc-813d-c97ed37e6b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026577260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2026577260
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3496061931
Short name T200
Test name
Test status
Simulation time 114677351086 ps
CPU time 653.28 seconds
Started Aug 09 07:18:41 PM PDT 24
Finished Aug 09 07:29:35 PM PDT 24
Peak memory 214312 kb
Host smart-65634e54-fb5d-4ee0-a971-a816f0dc7cc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496061931 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3496061931
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.7540573
Short name T215
Test name
Test status
Simulation time 185718960531 ps
CPU time 61.23 seconds
Started Aug 09 07:24:28 PM PDT 24
Finished Aug 09 07:25:29 PM PDT 24
Peak memory 199964 kb
Host smart-57b51aa7-b3cd-4277-ac03-1c34f1db2ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7540573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.7540573
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1721702406
Short name T223
Test name
Test status
Simulation time 9429737470 ps
CPU time 17.28 seconds
Started Aug 09 07:24:42 PM PDT 24
Finished Aug 09 07:24:59 PM PDT 24
Peak memory 199876 kb
Host smart-1359b939-f0ea-49c2-9f95-5958c4a425f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721702406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1721702406
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2013155970
Short name T238
Test name
Test status
Simulation time 22677789597 ps
CPU time 40.09 seconds
Started Aug 09 07:25:01 PM PDT 24
Finished Aug 09 07:25:41 PM PDT 24
Peak memory 199892 kb
Host smart-e5e89c53-a2bf-4786-bf8d-addd5f6c9a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013155970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2013155970
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3832384566
Short name T167
Test name
Test status
Simulation time 189583108375 ps
CPU time 31.97 seconds
Started Aug 09 07:25:11 PM PDT 24
Finished Aug 09 07:25:43 PM PDT 24
Peak memory 199900 kb
Host smart-e1610f3c-c587-4858-b118-dba534e6459d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832384566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3832384566
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all.3356534177
Short name T243
Test name
Test status
Simulation time 412141535504 ps
CPU time 621.96 seconds
Started Aug 09 07:21:09 PM PDT 24
Finished Aug 09 07:31:31 PM PDT 24
Peak memory 199968 kb
Host smart-551aaed3-abf5-4a4e-a0a5-4b323372e407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356534177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3356534177
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2064962632
Short name T213
Test name
Test status
Simulation time 171081313336 ps
CPU time 1190.45 seconds
Started Aug 09 07:21:49 PM PDT 24
Finished Aug 09 07:41:40 PM PDT 24
Peak memory 216468 kb
Host smart-c5842360-83aa-4cb5-acd3-6d71131a2e0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064962632 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2064962632
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3305935252
Short name T229
Test name
Test status
Simulation time 78797821529 ps
CPU time 914.06 seconds
Started Aug 09 07:22:23 PM PDT 24
Finished Aug 09 07:37:37 PM PDT 24
Peak memory 224756 kb
Host smart-ae7810c4-76bb-4fd5-8c4e-6deb285366e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305935252 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3305935252
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3752520604
Short name T241
Test name
Test status
Simulation time 35211122694 ps
CPU time 44.05 seconds
Started Aug 09 07:23:00 PM PDT 24
Finished Aug 09 07:23:44 PM PDT 24
Peak memory 199960 kb
Host smart-36253aa5-076a-44aa-b003-b3ef8ccec661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752520604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3752520604
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.500883356
Short name T233
Test name
Test status
Simulation time 61454111817 ps
CPU time 25.96 seconds
Started Aug 09 07:23:10 PM PDT 24
Finished Aug 09 07:23:36 PM PDT 24
Peak memory 199900 kb
Host smart-b9efdf10-ae4b-46db-bed9-45c983acc6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500883356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.500883356
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.2720771869
Short name T242
Test name
Test status
Simulation time 11951441199 ps
CPU time 9.16 seconds
Started Aug 09 07:23:16 PM PDT 24
Finished Aug 09 07:23:26 PM PDT 24
Peak memory 199976 kb
Host smart-4020a1e2-24ac-410b-974b-0335607297b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720771869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2720771869
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.409174727
Short name T240
Test name
Test status
Simulation time 57733892447 ps
CPU time 37.13 seconds
Started Aug 09 07:23:17 PM PDT 24
Finished Aug 09 07:23:54 PM PDT 24
Peak memory 199916 kb
Host smart-9952507b-c063-49f3-8680-2f43f82898c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409174727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.409174727
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.731020537
Short name T1245
Test name
Test status
Simulation time 27670545 ps
CPU time 0.81 seconds
Started Aug 09 07:15:09 PM PDT 24
Finished Aug 09 07:15:10 PM PDT 24
Peak memory 196820 kb
Host smart-efe024e2-3d6d-45d5-8ecb-b1e09dd014eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731020537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.731020537
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1787712370
Short name T1203
Test name
Test status
Simulation time 626367343 ps
CPU time 2.45 seconds
Started Aug 09 07:14:54 PM PDT 24
Finished Aug 09 07:14:56 PM PDT 24
Peak memory 197964 kb
Host smart-ddb553d4-9a41-4a2d-9cf8-607304f9b9b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787712370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1787712370
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2033532594
Short name T1227
Test name
Test status
Simulation time 12359196 ps
CPU time 0.58 seconds
Started Aug 09 07:14:51 PM PDT 24
Finished Aug 09 07:14:52 PM PDT 24
Peak memory 195772 kb
Host smart-9c08ba21-7e51-4ebf-8898-f345db85cf54
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033532594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2033532594
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1256564226
Short name T1318
Test name
Test status
Simulation time 97708887 ps
CPU time 0.77 seconds
Started Aug 09 07:14:50 PM PDT 24
Finished Aug 09 07:14:51 PM PDT 24
Peak memory 198436 kb
Host smart-b19fbe2c-ca37-4deb-9e69-f7c87673a91d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256564226 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1256564226
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.35163714
Short name T66
Test name
Test status
Simulation time 35855448 ps
CPU time 0.58 seconds
Started Aug 09 07:14:54 PM PDT 24
Finished Aug 09 07:14:54 PM PDT 24
Peak memory 195760 kb
Host smart-3e373526-59ac-4d78-989a-eae2cd6c53ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35163714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.35163714
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.416464208
Short name T1197
Test name
Test status
Simulation time 50725598 ps
CPU time 0.56 seconds
Started Aug 09 07:15:03 PM PDT 24
Finished Aug 09 07:15:04 PM PDT 24
Peak memory 194780 kb
Host smart-f298488f-ad78-441b-91c1-9244ee503b59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416464208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.416464208
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.607351928
Short name T1258
Test name
Test status
Simulation time 30750479 ps
CPU time 0.72 seconds
Started Aug 09 07:14:56 PM PDT 24
Finished Aug 09 07:14:57 PM PDT 24
Peak memory 197448 kb
Host smart-29f5d1b0-eac2-446a-a0ff-c1e8799fa476
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607351928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.607351928
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1935225132
Short name T1230
Test name
Test status
Simulation time 108430390 ps
CPU time 1.57 seconds
Started Aug 09 07:14:54 PM PDT 24
Finished Aug 09 07:14:55 PM PDT 24
Peak memory 200468 kb
Host smart-f6ed52a9-ce5e-41c0-95fd-3c0572e46530
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935225132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1935225132
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2642927877
Short name T1186
Test name
Test status
Simulation time 375154836 ps
CPU time 0.78 seconds
Started Aug 09 07:15:00 PM PDT 24
Finished Aug 09 07:15:01 PM PDT 24
Peak memory 196492 kb
Host smart-90413c0c-8e76-4878-95ce-5d7519e03539
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642927877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2642927877
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1566816500
Short name T1212
Test name
Test status
Simulation time 38732700 ps
CPU time 1.37 seconds
Started Aug 09 07:14:45 PM PDT 24
Finished Aug 09 07:14:46 PM PDT 24
Peak memory 197688 kb
Host smart-288ce45d-b3cd-4248-a18e-e3fb70ea55f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566816500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1566816500
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3362418620
Short name T1188
Test name
Test status
Simulation time 18343383 ps
CPU time 0.59 seconds
Started Aug 09 07:15:03 PM PDT 24
Finished Aug 09 07:15:04 PM PDT 24
Peak memory 195792 kb
Host smart-875a75aa-eadc-4d1f-a7e4-f8740fdfb8bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362418620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3362418620
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.4015195249
Short name T1278
Test name
Test status
Simulation time 31301192 ps
CPU time 0.68 seconds
Started Aug 09 07:14:54 PM PDT 24
Finished Aug 09 07:14:54 PM PDT 24
Peak memory 198536 kb
Host smart-d6300296-c2f8-4a38-99ea-89353404da09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015195249 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.4015195249
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2587768137
Short name T1198
Test name
Test status
Simulation time 19598703 ps
CPU time 0.56 seconds
Started Aug 09 07:14:55 PM PDT 24
Finished Aug 09 07:14:56 PM PDT 24
Peak memory 194764 kb
Host smart-ec622782-2721-43f4-bb72-0f89d2deb0ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587768137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2587768137
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.475073736
Short name T71
Test name
Test status
Simulation time 48696685 ps
CPU time 0.74 seconds
Started Aug 09 07:14:53 PM PDT 24
Finished Aug 09 07:14:54 PM PDT 24
Peak memory 197864 kb
Host smart-fd25bfe7-8e98-447b-b4c3-fd9bb9dd29d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475073736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_
outstanding.475073736
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1671338381
Short name T1289
Test name
Test status
Simulation time 219455104 ps
CPU time 1.32 seconds
Started Aug 09 07:14:46 PM PDT 24
Finished Aug 09 07:14:48 PM PDT 24
Peak memory 200484 kb
Host smart-5039d982-08cb-41c6-b195-e4f11215de83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671338381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1671338381
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.148705632
Short name T1237
Test name
Test status
Simulation time 90907499 ps
CPU time 0.75 seconds
Started Aug 09 07:15:11 PM PDT 24
Finished Aug 09 07:15:12 PM PDT 24
Peak memory 198812 kb
Host smart-619b97b0-15fe-41ff-b65d-d6cb4d639782
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148705632 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.148705632
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.509293254
Short name T1261
Test name
Test status
Simulation time 44892191 ps
CPU time 0.56 seconds
Started Aug 09 07:14:56 PM PDT 24
Finished Aug 09 07:14:57 PM PDT 24
Peak memory 195808 kb
Host smart-8555acff-aaba-4bf0-9fe0-1bfa179ff2dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509293254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.509293254
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3878784729
Short name T1244
Test name
Test status
Simulation time 162516793 ps
CPU time 0.59 seconds
Started Aug 09 07:15:17 PM PDT 24
Finished Aug 09 07:15:18 PM PDT 24
Peak memory 194816 kb
Host smart-1bede027-c27b-417d-9ecb-48809981abac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878784729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3878784729
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2918988411
Short name T1253
Test name
Test status
Simulation time 20460397 ps
CPU time 0.63 seconds
Started Aug 09 07:15:02 PM PDT 24
Finished Aug 09 07:15:03 PM PDT 24
Peak memory 195956 kb
Host smart-b401b9bd-42a9-4de3-9c97-99d5c82554e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918988411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2918988411
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.143721461
Short name T1303
Test name
Test status
Simulation time 344623830 ps
CPU time 1.87 seconds
Started Aug 09 07:15:12 PM PDT 24
Finished Aug 09 07:15:14 PM PDT 24
Peak memory 200424 kb
Host smart-0ff86136-7e83-4152-94a8-9d7a538326ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143721461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.143721461
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.847377277
Short name T1280
Test name
Test status
Simulation time 49769461 ps
CPU time 0.96 seconds
Started Aug 09 07:15:12 PM PDT 24
Finished Aug 09 07:15:13 PM PDT 24
Peak memory 199148 kb
Host smart-b655e5a4-7e0b-4ef0-9687-a7b347ba3fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847377277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.847377277
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.193268775
Short name T1270
Test name
Test status
Simulation time 37201903 ps
CPU time 0.83 seconds
Started Aug 09 07:15:07 PM PDT 24
Finished Aug 09 07:15:13 PM PDT 24
Peak memory 200424 kb
Host smart-504e7029-2e8d-44b1-b101-0883c67d88bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193268775 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.193268775
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2305632596
Short name T1314
Test name
Test status
Simulation time 14073513 ps
CPU time 0.6 seconds
Started Aug 09 07:15:14 PM PDT 24
Finished Aug 09 07:15:14 PM PDT 24
Peak memory 195764 kb
Host smart-97d6eb7f-6f12-40e4-96c8-981a46a9fdad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305632596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2305632596
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1851032652
Short name T1194
Test name
Test status
Simulation time 21884363 ps
CPU time 0.58 seconds
Started Aug 09 07:15:02 PM PDT 24
Finished Aug 09 07:15:03 PM PDT 24
Peak memory 194724 kb
Host smart-0c875651-ee51-42dc-b138-a338b3a0b88a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851032652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1851032652
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1139901133
Short name T70
Test name
Test status
Simulation time 19495277 ps
CPU time 0.63 seconds
Started Aug 09 07:15:06 PM PDT 24
Finished Aug 09 07:15:06 PM PDT 24
Peak memory 196892 kb
Host smart-376395d5-4525-467b-80ad-599487cff7ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139901133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1139901133
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.667704620
Short name T1222
Test name
Test status
Simulation time 98961712 ps
CPU time 1.16 seconds
Started Aug 09 07:15:11 PM PDT 24
Finished Aug 09 07:15:12 PM PDT 24
Peak memory 200468 kb
Host smart-5cb38b93-fd4f-4a27-a1d0-706b2b1d2d3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667704620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.667704620
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1069559011
Short name T1256
Test name
Test status
Simulation time 77905543 ps
CPU time 0.96 seconds
Started Aug 09 07:15:09 PM PDT 24
Finished Aug 09 07:15:10 PM PDT 24
Peak memory 199312 kb
Host smart-aa30ef80-1eac-4afd-abdc-51f68cf3f33a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069559011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1069559011
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3079387053
Short name T1263
Test name
Test status
Simulation time 16609504 ps
CPU time 0.69 seconds
Started Aug 09 07:15:10 PM PDT 24
Finished Aug 09 07:15:11 PM PDT 24
Peak memory 199216 kb
Host smart-48c9eee0-2b74-4afd-b9e0-5235467db20a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079387053 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3079387053
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1573449891
Short name T1305
Test name
Test status
Simulation time 16245810 ps
CPU time 0.6 seconds
Started Aug 09 07:15:10 PM PDT 24
Finished Aug 09 07:15:11 PM PDT 24
Peak memory 195768 kb
Host smart-1c030672-809a-4ac1-8783-4bd0a17f4f97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573449891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1573449891
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3993307565
Short name T1190
Test name
Test status
Simulation time 12434075 ps
CPU time 0.58 seconds
Started Aug 09 07:15:01 PM PDT 24
Finished Aug 09 07:15:01 PM PDT 24
Peak memory 194660 kb
Host smart-22a2e4a4-b5b0-4632-a83f-87be25a2dfbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993307565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3993307565
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3027655889
Short name T1240
Test name
Test status
Simulation time 213370603 ps
CPU time 0.71 seconds
Started Aug 09 07:15:17 PM PDT 24
Finished Aug 09 07:15:18 PM PDT 24
Peak memory 197304 kb
Host smart-cf4eef44-3c1b-4f60-9c48-01d17a10a5c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027655889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3027655889
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.654358157
Short name T1267
Test name
Test status
Simulation time 701080938 ps
CPU time 2.35 seconds
Started Aug 09 07:15:12 PM PDT 24
Finished Aug 09 07:15:14 PM PDT 24
Peak memory 200448 kb
Host smart-d787727d-5644-421c-b2ac-7710b0c7d648
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654358157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.654358157
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3219705714
Short name T81
Test name
Test status
Simulation time 89603232 ps
CPU time 0.93 seconds
Started Aug 09 07:15:05 PM PDT 24
Finished Aug 09 07:15:06 PM PDT 24
Peak memory 199368 kb
Host smart-8b42ec1d-fdb6-4261-a067-863abba3e77f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219705714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3219705714
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2690245929
Short name T1191
Test name
Test status
Simulation time 87461411 ps
CPU time 0.74 seconds
Started Aug 09 07:15:06 PM PDT 24
Finished Aug 09 07:15:06 PM PDT 24
Peak memory 198744 kb
Host smart-543da78f-d6a0-40a0-856d-18036860d0fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690245929 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2690245929
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3721882696
Short name T74
Test name
Test status
Simulation time 24034925 ps
CPU time 0.59 seconds
Started Aug 09 07:15:11 PM PDT 24
Finished Aug 09 07:15:12 PM PDT 24
Peak memory 195764 kb
Host smart-9e924941-2c04-405b-928e-e1e8eb4b514e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721882696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3721882696
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.78438067
Short name T1312
Test name
Test status
Simulation time 48880781 ps
CPU time 0.57 seconds
Started Aug 09 07:15:04 PM PDT 24
Finished Aug 09 07:15:05 PM PDT 24
Peak memory 194812 kb
Host smart-0d936510-5a87-4850-a4f8-a04ed9a34d43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78438067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.78438067
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.211216135
Short name T1233
Test name
Test status
Simulation time 37302296 ps
CPU time 0.68 seconds
Started Aug 09 07:15:06 PM PDT 24
Finished Aug 09 07:15:06 PM PDT 24
Peak memory 195864 kb
Host smart-6d520fd4-7bd4-47b5-9430-e93c36a312b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211216135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.211216135
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3965692633
Short name T1205
Test name
Test status
Simulation time 50811569 ps
CPU time 1.37 seconds
Started Aug 09 07:15:23 PM PDT 24
Finished Aug 09 07:15:25 PM PDT 24
Peak memory 200468 kb
Host smart-95bd871c-b95b-4f92-bdd7-2057fb215512
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965692633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3965692633
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1619589992
Short name T1274
Test name
Test status
Simulation time 95503075 ps
CPU time 1.14 seconds
Started Aug 09 07:14:58 PM PDT 24
Finished Aug 09 07:14:59 PM PDT 24
Peak memory 200492 kb
Host smart-805ac80a-ce95-48fb-9d36-eb4a6507bb1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619589992 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1619589992
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.726507288
Short name T1239
Test name
Test status
Simulation time 39152327 ps
CPU time 0.55 seconds
Started Aug 09 07:15:03 PM PDT 24
Finished Aug 09 07:15:03 PM PDT 24
Peak memory 195800 kb
Host smart-fde4d90a-0549-4e5a-8621-694327352d82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726507288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.726507288
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1630756349
Short name T1221
Test name
Test status
Simulation time 26839074 ps
CPU time 0.58 seconds
Started Aug 09 07:14:59 PM PDT 24
Finished Aug 09 07:15:00 PM PDT 24
Peak memory 194852 kb
Host smart-c56ee2e7-8c1f-41ed-a948-afa3772eccb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630756349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1630756349
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2372372883
Short name T1226
Test name
Test status
Simulation time 114612499 ps
CPU time 0.72 seconds
Started Aug 09 07:15:06 PM PDT 24
Finished Aug 09 07:15:06 PM PDT 24
Peak memory 197324 kb
Host smart-e1644673-4693-4313-bde2-2be4a5a2ee58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372372883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2372372883
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2850107413
Short name T1219
Test name
Test status
Simulation time 263438525 ps
CPU time 1.52 seconds
Started Aug 09 07:15:12 PM PDT 24
Finished Aug 09 07:15:14 PM PDT 24
Peak memory 200372 kb
Host smart-a8684a51-0b4f-4801-a0f9-7cfc381be1ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850107413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2850107413
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3791550988
Short name T80
Test name
Test status
Simulation time 133835205 ps
CPU time 1.31 seconds
Started Aug 09 07:15:09 PM PDT 24
Finished Aug 09 07:15:11 PM PDT 24
Peak memory 199564 kb
Host smart-bddcf39f-05e5-43c1-b7f0-43356233c2ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791550988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3791550988
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1371771779
Short name T1196
Test name
Test status
Simulation time 50869864 ps
CPU time 0.65 seconds
Started Aug 09 07:15:03 PM PDT 24
Finished Aug 09 07:15:03 PM PDT 24
Peak memory 198032 kb
Host smart-92b17840-05e7-47dc-b300-07d5760a1755
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371771779 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1371771779
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.684728517
Short name T1229
Test name
Test status
Simulation time 17243153 ps
CPU time 0.62 seconds
Started Aug 09 07:15:04 PM PDT 24
Finished Aug 09 07:15:05 PM PDT 24
Peak memory 195884 kb
Host smart-f2124975-d2c5-4b2f-939b-1f9720e0d00c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684728517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.684728517
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.235612409
Short name T1259
Test name
Test status
Simulation time 17024795 ps
CPU time 0.56 seconds
Started Aug 09 07:15:05 PM PDT 24
Finished Aug 09 07:15:05 PM PDT 24
Peak memory 194716 kb
Host smart-9ff30dd7-35d2-46a5-990a-72a15f636b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235612409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.235612409
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1457404185
Short name T1307
Test name
Test status
Simulation time 19857066 ps
CPU time 0.67 seconds
Started Aug 09 07:15:25 PM PDT 24
Finished Aug 09 07:15:25 PM PDT 24
Peak memory 197152 kb
Host smart-285d2dcc-09a7-4031-b329-a934334e5d89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457404185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1457404185
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1404204009
Short name T1193
Test name
Test status
Simulation time 147125046 ps
CPU time 1.61 seconds
Started Aug 09 07:15:09 PM PDT 24
Finished Aug 09 07:15:11 PM PDT 24
Peak memory 200416 kb
Host smart-7f4e99c5-b87d-481a-b745-2d7295fbe223
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404204009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1404204009
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1292880204
Short name T1313
Test name
Test status
Simulation time 306983004 ps
CPU time 1.45 seconds
Started Aug 09 07:15:07 PM PDT 24
Finished Aug 09 07:15:09 PM PDT 24
Peak memory 199676 kb
Host smart-761311e5-644a-4938-b8ad-8eadfffb8a5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292880204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1292880204
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3827601183
Short name T1195
Test name
Test status
Simulation time 47821047 ps
CPU time 0.69 seconds
Started Aug 09 07:15:13 PM PDT 24
Finished Aug 09 07:15:14 PM PDT 24
Peak memory 198460 kb
Host smart-e4fc89d9-c931-4686-b431-71c28133fa0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827601183 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3827601183
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.927938457
Short name T1251
Test name
Test status
Simulation time 57120393 ps
CPU time 0.62 seconds
Started Aug 09 07:15:12 PM PDT 24
Finished Aug 09 07:15:13 PM PDT 24
Peak memory 195988 kb
Host smart-29e4277e-a2fa-4545-bb84-0b21d593a6f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927938457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.927938457
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.477667813
Short name T1296
Test name
Test status
Simulation time 13309128 ps
CPU time 0.57 seconds
Started Aug 09 07:15:05 PM PDT 24
Finished Aug 09 07:15:05 PM PDT 24
Peak memory 194824 kb
Host smart-533e6125-2421-499b-9060-5bd733a5cf01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477667813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.477667813
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3300020169
Short name T1241
Test name
Test status
Simulation time 61002083 ps
CPU time 0.73 seconds
Started Aug 09 07:15:10 PM PDT 24
Finished Aug 09 07:15:11 PM PDT 24
Peak memory 196404 kb
Host smart-64e9eebd-326c-4040-a7c1-78b54b10dd75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300020169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3300020169
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3685172654
Short name T1295
Test name
Test status
Simulation time 83626521 ps
CPU time 1.15 seconds
Started Aug 09 07:15:03 PM PDT 24
Finished Aug 09 07:15:04 PM PDT 24
Peak memory 200412 kb
Host smart-3207e93e-b546-4d73-a5a5-5097c50114ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685172654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3685172654
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1135682380
Short name T89
Test name
Test status
Simulation time 54363835 ps
CPU time 0.93 seconds
Started Aug 09 07:15:05 PM PDT 24
Finished Aug 09 07:15:06 PM PDT 24
Peak memory 199576 kb
Host smart-015003d9-fa78-4fa8-8bb1-8abddce05339
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135682380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1135682380
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1391652580
Short name T1299
Test name
Test status
Simulation time 201627532 ps
CPU time 0.77 seconds
Started Aug 09 07:15:05 PM PDT 24
Finished Aug 09 07:15:05 PM PDT 24
Peak memory 200148 kb
Host smart-31928352-03bd-4f47-8d29-c1af5bd52a23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391652580 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1391652580
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.233430724
Short name T75
Test name
Test status
Simulation time 150052340 ps
CPU time 0.62 seconds
Started Aug 09 07:15:10 PM PDT 24
Finished Aug 09 07:15:11 PM PDT 24
Peak memory 196244 kb
Host smart-a6aacaca-b1a3-4875-a615-2a5d529dab95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233430724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.233430724
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.1087983650
Short name T1206
Test name
Test status
Simulation time 45599551 ps
CPU time 0.6 seconds
Started Aug 09 07:15:31 PM PDT 24
Finished Aug 09 07:15:32 PM PDT 24
Peak memory 194788 kb
Host smart-1c5ed0c8-a8c6-43e3-9b5e-7298faedb795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087983650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1087983650
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2746563486
Short name T1272
Test name
Test status
Simulation time 60810161 ps
CPU time 0.63 seconds
Started Aug 09 07:15:12 PM PDT 24
Finished Aug 09 07:15:13 PM PDT 24
Peak memory 196064 kb
Host smart-dbc69066-407f-4ab3-893a-763e5b49c428
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746563486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2746563486
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3695931836
Short name T1199
Test name
Test status
Simulation time 104261497 ps
CPU time 1.58 seconds
Started Aug 09 07:15:13 PM PDT 24
Finished Aug 09 07:15:15 PM PDT 24
Peak memory 200464 kb
Host smart-113fd87b-e7ae-4026-94af-b410999bc49a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695931836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3695931836
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.957062411
Short name T83
Test name
Test status
Simulation time 141655751 ps
CPU time 0.97 seconds
Started Aug 09 07:15:04 PM PDT 24
Finished Aug 09 07:15:05 PM PDT 24
Peak memory 199348 kb
Host smart-4dfb92ce-4e47-4ddb-9f6b-39965b963cba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957062411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.957062411
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3409770828
Short name T1308
Test name
Test status
Simulation time 103724143 ps
CPU time 0.77 seconds
Started Aug 09 07:15:09 PM PDT 24
Finished Aug 09 07:15:10 PM PDT 24
Peak memory 199684 kb
Host smart-f45d8c43-a9cd-4c7b-92bf-ae557884205f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409770828 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3409770828
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3193593108
Short name T67
Test name
Test status
Simulation time 55199468 ps
CPU time 0.6 seconds
Started Aug 09 07:15:12 PM PDT 24
Finished Aug 09 07:15:13 PM PDT 24
Peak memory 195972 kb
Host smart-f535f0a0-a196-4c55-88c4-bfbf12f6f3b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193593108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3193593108
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3568372624
Short name T1294
Test name
Test status
Simulation time 39543367 ps
CPU time 0.58 seconds
Started Aug 09 07:15:10 PM PDT 24
Finished Aug 09 07:15:11 PM PDT 24
Peak memory 194772 kb
Host smart-4d84b21d-a55b-458a-80dc-a5568ef3cf42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568372624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3568372624
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2385166781
Short name T1269
Test name
Test status
Simulation time 51317132 ps
CPU time 0.72 seconds
Started Aug 09 07:15:14 PM PDT 24
Finished Aug 09 07:15:15 PM PDT 24
Peak memory 198136 kb
Host smart-7a24dd4d-9a45-41d0-98dc-f7f80ae442b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385166781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2385166781
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.346368814
Short name T1209
Test name
Test status
Simulation time 112214483 ps
CPU time 1.6 seconds
Started Aug 09 07:15:07 PM PDT 24
Finished Aug 09 07:15:09 PM PDT 24
Peak memory 200444 kb
Host smart-d4ec4213-6aeb-4695-82b0-81272f5f589a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346368814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.346368814
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2181093234
Short name T78
Test name
Test status
Simulation time 134290113 ps
CPU time 0.92 seconds
Started Aug 09 07:15:11 PM PDT 24
Finished Aug 09 07:15:17 PM PDT 24
Peak memory 199316 kb
Host smart-99cd162c-3d6b-452f-bcac-4c94d206aa23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181093234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2181093234
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1551457751
Short name T1275
Test name
Test status
Simulation time 158708967 ps
CPU time 0.76 seconds
Started Aug 09 07:15:08 PM PDT 24
Finished Aug 09 07:15:09 PM PDT 24
Peak memory 200200 kb
Host smart-9d264a26-33ed-4888-a216-63aef84cafcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551457751 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1551457751
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.654238185
Short name T1309
Test name
Test status
Simulation time 11134920 ps
CPU time 0.58 seconds
Started Aug 09 07:15:07 PM PDT 24
Finished Aug 09 07:15:07 PM PDT 24
Peak memory 195904 kb
Host smart-10c6af2b-5357-40a8-9cc9-5f44119015ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654238185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.654238185
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3958134181
Short name T1225
Test name
Test status
Simulation time 14683465 ps
CPU time 0.6 seconds
Started Aug 09 07:15:08 PM PDT 24
Finished Aug 09 07:15:09 PM PDT 24
Peak memory 194704 kb
Host smart-9dccf851-c736-4342-a3b6-14a823a5fb3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958134181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3958134181
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3502066147
Short name T1310
Test name
Test status
Simulation time 107430458 ps
CPU time 0.75 seconds
Started Aug 09 07:15:10 PM PDT 24
Finished Aug 09 07:15:11 PM PDT 24
Peak memory 196396 kb
Host smart-1f871cf3-2986-4053-9440-72b2ecefa3af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502066147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3502066147
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3209896434
Short name T1304
Test name
Test status
Simulation time 49854989 ps
CPU time 1.41 seconds
Started Aug 09 07:15:12 PM PDT 24
Finished Aug 09 07:15:14 PM PDT 24
Peak memory 200440 kb
Host smart-3b03692d-dec0-4236-aaa0-5be7c059e4f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209896434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3209896434
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.879766811
Short name T87
Test name
Test status
Simulation time 57240999 ps
CPU time 0.98 seconds
Started Aug 09 07:15:07 PM PDT 24
Finished Aug 09 07:15:08 PM PDT 24
Peak memory 199296 kb
Host smart-d86d2e9d-6ebe-483f-9aa9-36be2fd89e03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879766811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.879766811
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3795874823
Short name T1284
Test name
Test status
Simulation time 49829116 ps
CPU time 0.78 seconds
Started Aug 09 07:15:05 PM PDT 24
Finished Aug 09 07:15:05 PM PDT 24
Peak memory 196652 kb
Host smart-635631c7-0cfe-4be6-966f-a22b90aaebe9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795874823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3795874823
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2379859609
Short name T1262
Test name
Test status
Simulation time 197761525 ps
CPU time 2.24 seconds
Started Aug 09 07:14:54 PM PDT 24
Finished Aug 09 07:14:56 PM PDT 24
Peak memory 198476 kb
Host smart-3b2d034a-eb6e-4eb3-bd67-440971985949
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379859609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2379859609
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.175402717
Short name T1200
Test name
Test status
Simulation time 1053391234 ps
CPU time 1.09 seconds
Started Aug 09 07:15:09 PM PDT 24
Finished Aug 09 07:15:11 PM PDT 24
Peak memory 195764 kb
Host smart-2286f4d0-d20a-4904-af54-ab35a47a654e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175402717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.175402717
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3255637476
Short name T1264
Test name
Test status
Simulation time 65411145 ps
CPU time 0.67 seconds
Started Aug 09 07:15:03 PM PDT 24
Finished Aug 09 07:15:04 PM PDT 24
Peak memory 198364 kb
Host smart-1352fe34-b546-4401-89d4-277360f15b7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255637476 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3255637476
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.642241381
Short name T56
Test name
Test status
Simulation time 12340371 ps
CPU time 0.6 seconds
Started Aug 09 07:14:46 PM PDT 24
Finished Aug 09 07:14:47 PM PDT 24
Peak memory 195884 kb
Host smart-7b7ec92f-80a6-4b52-b2c2-f352137876a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642241381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.642241381
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.380035597
Short name T1202
Test name
Test status
Simulation time 32139674 ps
CPU time 0.55 seconds
Started Aug 09 07:15:11 PM PDT 24
Finished Aug 09 07:15:12 PM PDT 24
Peak memory 194752 kb
Host smart-a306b121-f3bb-482d-8dc0-563b0f131dbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380035597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.380035597
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2445976577
Short name T1300
Test name
Test status
Simulation time 31464748 ps
CPU time 0.74 seconds
Started Aug 09 07:14:58 PM PDT 24
Finished Aug 09 07:14:59 PM PDT 24
Peak memory 197460 kb
Host smart-7c89f2fd-481a-4082-8f74-aac047ed52bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445976577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2445976577
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.619291316
Short name T1255
Test name
Test status
Simulation time 70575214 ps
CPU time 1.02 seconds
Started Aug 09 07:14:50 PM PDT 24
Finished Aug 09 07:14:51 PM PDT 24
Peak memory 200248 kb
Host smart-9802ff05-0815-41e3-9272-ab241af689c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619291316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.619291316
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1298691126
Short name T122
Test name
Test status
Simulation time 177647857 ps
CPU time 1.4 seconds
Started Aug 09 07:14:55 PM PDT 24
Finished Aug 09 07:14:56 PM PDT 24
Peak memory 199812 kb
Host smart-afb95fb5-73b2-4c81-9291-84afe0ea0306
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298691126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1298691126
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2543902029
Short name T1319
Test name
Test status
Simulation time 35896021 ps
CPU time 0.59 seconds
Started Aug 09 07:15:10 PM PDT 24
Finished Aug 09 07:15:11 PM PDT 24
Peak memory 194672 kb
Host smart-bab094d4-3ec1-472c-aa62-8402f7c5924f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543902029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2543902029
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2710868962
Short name T1288
Test name
Test status
Simulation time 194615140 ps
CPU time 0.57 seconds
Started Aug 09 07:15:11 PM PDT 24
Finished Aug 09 07:15:12 PM PDT 24
Peak memory 194684 kb
Host smart-2a93548a-38bc-4137-9b86-c63c82da3d05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710868962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2710868962
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.3913649048
Short name T1279
Test name
Test status
Simulation time 19998110 ps
CPU time 0.56 seconds
Started Aug 09 07:15:17 PM PDT 24
Finished Aug 09 07:15:18 PM PDT 24
Peak memory 194736 kb
Host smart-f7f52376-3f0e-46e7-86a3-b37228aa01eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913649048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3913649048
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.127492059
Short name T1207
Test name
Test status
Simulation time 48568834 ps
CPU time 0.55 seconds
Started Aug 09 07:15:01 PM PDT 24
Finished Aug 09 07:15:02 PM PDT 24
Peak memory 194800 kb
Host smart-ef4cf69c-2d6b-497c-a201-a9192ac5dee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127492059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.127492059
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1677601389
Short name T1185
Test name
Test status
Simulation time 13686222 ps
CPU time 0.58 seconds
Started Aug 09 07:15:18 PM PDT 24
Finished Aug 09 07:15:19 PM PDT 24
Peak memory 194804 kb
Host smart-cd6e1867-6a91-425e-9631-f7b40286c6ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677601389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1677601389
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1308436511
Short name T1293
Test name
Test status
Simulation time 156442465 ps
CPU time 0.57 seconds
Started Aug 09 07:15:18 PM PDT 24
Finished Aug 09 07:15:19 PM PDT 24
Peak memory 194764 kb
Host smart-3126492d-3c23-4e01-adab-3505cbc709fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308436511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1308436511
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.822484593
Short name T1247
Test name
Test status
Simulation time 17489146 ps
CPU time 0.58 seconds
Started Aug 09 07:15:10 PM PDT 24
Finished Aug 09 07:15:11 PM PDT 24
Peak memory 194788 kb
Host smart-38288d82-9bfa-40de-b433-adc33cb142f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822484593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.822484593
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2400694018
Short name T1297
Test name
Test status
Simulation time 25021748 ps
CPU time 0.56 seconds
Started Aug 09 07:15:26 PM PDT 24
Finished Aug 09 07:15:26 PM PDT 24
Peak memory 194744 kb
Host smart-af9a172e-ac4c-441f-a42c-89c028804304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400694018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2400694018
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.741373764
Short name T1201
Test name
Test status
Simulation time 15002086 ps
CPU time 0.57 seconds
Started Aug 09 07:15:12 PM PDT 24
Finished Aug 09 07:15:13 PM PDT 24
Peak memory 194760 kb
Host smart-43583ef7-2d5c-4d1f-b141-badb786a241c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741373764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.741373764
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3166286950
Short name T1273
Test name
Test status
Simulation time 23949106 ps
CPU time 0.57 seconds
Started Aug 09 07:15:09 PM PDT 24
Finished Aug 09 07:15:10 PM PDT 24
Peak memory 194752 kb
Host smart-c4262829-31a2-48a8-a916-bc4c11294554
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166286950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3166286950
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3048552926
Short name T1252
Test name
Test status
Simulation time 63042668 ps
CPU time 1.35 seconds
Started Aug 09 07:14:55 PM PDT 24
Finished Aug 09 07:14:56 PM PDT 24
Peak memory 198332 kb
Host smart-f10abe76-b431-41dd-8dec-f4084a420fe0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048552926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3048552926
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3127803615
Short name T1211
Test name
Test status
Simulation time 14277070 ps
CPU time 0.61 seconds
Started Aug 09 07:14:59 PM PDT 24
Finished Aug 09 07:15:00 PM PDT 24
Peak memory 195808 kb
Host smart-a0106115-d040-4ccd-a314-d9e3de82de0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127803615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3127803615
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1846530189
Short name T1214
Test name
Test status
Simulation time 80663798 ps
CPU time 0.88 seconds
Started Aug 09 07:15:03 PM PDT 24
Finished Aug 09 07:15:04 PM PDT 24
Peak memory 200240 kb
Host smart-da6b5619-e25b-4e93-bb7d-6076bebc46eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846530189 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1846530189
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.419775068
Short name T1316
Test name
Test status
Simulation time 77957766 ps
CPU time 0.56 seconds
Started Aug 09 07:15:10 PM PDT 24
Finished Aug 09 07:15:11 PM PDT 24
Peak memory 195780 kb
Host smart-7ebbd3b2-db1d-415f-b57d-b1ae78697957
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419775068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.419775068
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.872378058
Short name T1306
Test name
Test status
Simulation time 13327996 ps
CPU time 0.58 seconds
Started Aug 09 07:14:58 PM PDT 24
Finished Aug 09 07:14:59 PM PDT 24
Peak memory 194832 kb
Host smart-3d86ffe0-003e-40be-bacd-b1a03019097f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872378058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.872378058
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3230316424
Short name T76
Test name
Test status
Simulation time 26695124 ps
CPU time 0.74 seconds
Started Aug 09 07:15:11 PM PDT 24
Finished Aug 09 07:15:12 PM PDT 24
Peak memory 197432 kb
Host smart-19ce6740-3f1a-453e-8d58-ec5a176c7eb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230316424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3230316424
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2788770901
Short name T1192
Test name
Test status
Simulation time 58065306 ps
CPU time 1.24 seconds
Started Aug 09 07:15:03 PM PDT 24
Finished Aug 09 07:15:05 PM PDT 24
Peak memory 200400 kb
Host smart-8a6220a8-43a5-492b-aae5-a67c455019c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788770901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2788770901
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.440881303
Short name T1234
Test name
Test status
Simulation time 249717764 ps
CPU time 1.28 seconds
Started Aug 09 07:14:46 PM PDT 24
Finished Aug 09 07:14:47 PM PDT 24
Peak memory 199636 kb
Host smart-8bec94bf-df15-42b2-a4db-b5851b3648ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440881303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.440881303
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2817403072
Short name T1183
Test name
Test status
Simulation time 17333308 ps
CPU time 0.54 seconds
Started Aug 09 07:15:12 PM PDT 24
Finished Aug 09 07:15:13 PM PDT 24
Peak memory 194748 kb
Host smart-1bcabc29-fef8-46fb-8034-4faa93e714d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817403072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2817403072
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2351063206
Short name T1216
Test name
Test status
Simulation time 14349258 ps
CPU time 0.56 seconds
Started Aug 09 07:15:07 PM PDT 24
Finished Aug 09 07:15:07 PM PDT 24
Peak memory 194768 kb
Host smart-93d399e6-cf69-427c-9045-b34917258fd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351063206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2351063206
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2253732958
Short name T1231
Test name
Test status
Simulation time 64484056 ps
CPU time 0.57 seconds
Started Aug 09 07:15:11 PM PDT 24
Finished Aug 09 07:15:12 PM PDT 24
Peak memory 194768 kb
Host smart-726ff2e8-8065-40e1-b1c0-3cfc1ad786c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253732958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2253732958
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2413423249
Short name T1215
Test name
Test status
Simulation time 142537587 ps
CPU time 0.58 seconds
Started Aug 09 07:15:24 PM PDT 24
Finished Aug 09 07:15:25 PM PDT 24
Peak memory 194776 kb
Host smart-73149a26-b3a0-40dc-b654-59590d5fe1b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413423249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2413423249
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.592984680
Short name T1257
Test name
Test status
Simulation time 43558315 ps
CPU time 0.56 seconds
Started Aug 09 07:15:09 PM PDT 24
Finished Aug 09 07:15:10 PM PDT 24
Peak memory 194828 kb
Host smart-63690045-2a0c-4aec-87fe-54674a013e9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592984680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.592984680
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3997293870
Short name T1276
Test name
Test status
Simulation time 15876247 ps
CPU time 0.57 seconds
Started Aug 09 07:15:12 PM PDT 24
Finished Aug 09 07:15:13 PM PDT 24
Peak memory 194756 kb
Host smart-39b7579a-e937-4eab-9362-abfcacc0849b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997293870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3997293870
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1301151466
Short name T1286
Test name
Test status
Simulation time 60517793 ps
CPU time 0.54 seconds
Started Aug 09 07:15:10 PM PDT 24
Finished Aug 09 07:15:11 PM PDT 24
Peak memory 194720 kb
Host smart-c6875d3d-6a20-45b3-bd43-3fff54914911
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301151466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1301151466
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2925754729
Short name T1302
Test name
Test status
Simulation time 14833465 ps
CPU time 0.55 seconds
Started Aug 09 07:15:09 PM PDT 24
Finished Aug 09 07:15:10 PM PDT 24
Peak memory 194796 kb
Host smart-841fbb25-8263-4f5f-8d65-da2d8f5a7501
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925754729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2925754729
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1584777714
Short name T1265
Test name
Test status
Simulation time 10942048 ps
CPU time 0.56 seconds
Started Aug 09 07:15:30 PM PDT 24
Finished Aug 09 07:15:31 PM PDT 24
Peak memory 194804 kb
Host smart-4bf3d2c0-2d96-46e9-a5d2-a826a6db5bfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584777714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1584777714
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1118262182
Short name T1249
Test name
Test status
Simulation time 12807321 ps
CPU time 0.55 seconds
Started Aug 09 07:15:11 PM PDT 24
Finished Aug 09 07:15:12 PM PDT 24
Peak memory 194780 kb
Host smart-fc19508a-f158-4eb2-a0a6-65c8b6b4d21c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118262182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1118262182
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1955615420
Short name T1210
Test name
Test status
Simulation time 50047189 ps
CPU time 0.77 seconds
Started Aug 09 07:15:11 PM PDT 24
Finished Aug 09 07:15:12 PM PDT 24
Peak memory 196808 kb
Host smart-80735c94-8949-4f4e-a642-219b37c00dc5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955615420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1955615420
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1034939364
Short name T1317
Test name
Test status
Simulation time 96413334 ps
CPU time 1.51 seconds
Started Aug 09 07:14:55 PM PDT 24
Finished Aug 09 07:14:57 PM PDT 24
Peak memory 198068 kb
Host smart-7dbe53c1-4e4f-468d-8f40-601872d324bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034939364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1034939364
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2338259037
Short name T65
Test name
Test status
Simulation time 35639596 ps
CPU time 0.58 seconds
Started Aug 09 07:14:49 PM PDT 24
Finished Aug 09 07:14:49 PM PDT 24
Peak memory 195768 kb
Host smart-97f7ed63-8e4c-43fd-8170-4968762357bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338259037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2338259037
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3860525656
Short name T1291
Test name
Test status
Simulation time 74361344 ps
CPU time 0.65 seconds
Started Aug 09 07:15:00 PM PDT 24
Finished Aug 09 07:15:05 PM PDT 24
Peak memory 198068 kb
Host smart-a813cf5d-bd7b-492d-a7cc-e015d13b1dda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860525656 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3860525656
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.860555423
Short name T69
Test name
Test status
Simulation time 23065713 ps
CPU time 0.65 seconds
Started Aug 09 07:14:48 PM PDT 24
Finished Aug 09 07:14:49 PM PDT 24
Peak memory 195868 kb
Host smart-a113d3f2-a307-4280-bf35-c20e6ef95dbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860555423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.860555423
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2852982689
Short name T1228
Test name
Test status
Simulation time 14534223 ps
CPU time 0.64 seconds
Started Aug 09 07:15:04 PM PDT 24
Finished Aug 09 07:15:05 PM PDT 24
Peak memory 194772 kb
Host smart-afa92e2c-6a48-44e7-a360-8fcbbd001eae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852982689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2852982689
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3051555166
Short name T1292
Test name
Test status
Simulation time 24671721 ps
CPU time 0.67 seconds
Started Aug 09 07:14:58 PM PDT 24
Finished Aug 09 07:14:59 PM PDT 24
Peak memory 195132 kb
Host smart-dfe68180-e89e-4cf2-b07d-a6f854366b51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051555166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3051555166
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1658496740
Short name T1271
Test name
Test status
Simulation time 91217648 ps
CPU time 1.47 seconds
Started Aug 09 07:14:59 PM PDT 24
Finished Aug 09 07:15:00 PM PDT 24
Peak memory 200428 kb
Host smart-ff1e506b-ea50-4ad9-8857-b1fdc576b7c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658496740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1658496740
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3884032446
Short name T79
Test name
Test status
Simulation time 56938571 ps
CPU time 0.97 seconds
Started Aug 09 07:14:58 PM PDT 24
Finished Aug 09 07:14:59 PM PDT 24
Peak memory 199492 kb
Host smart-a8e98ca3-4d63-4409-8b53-4efbbeb50144
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884032446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3884032446
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3397462611
Short name T1208
Test name
Test status
Simulation time 13085477 ps
CPU time 0.55 seconds
Started Aug 09 07:15:08 PM PDT 24
Finished Aug 09 07:15:09 PM PDT 24
Peak memory 194748 kb
Host smart-a0f566b8-8f7d-4854-a021-abab0223d878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397462611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3397462611
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3065344864
Short name T1223
Test name
Test status
Simulation time 22320314 ps
CPU time 0.57 seconds
Started Aug 09 07:15:31 PM PDT 24
Finished Aug 09 07:15:32 PM PDT 24
Peak memory 194800 kb
Host smart-6c55e690-1619-4e11-b6dc-6fbf55e32e63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065344864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3065344864
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3670176156
Short name T1224
Test name
Test status
Simulation time 19722818 ps
CPU time 0.55 seconds
Started Aug 09 07:15:11 PM PDT 24
Finished Aug 09 07:15:12 PM PDT 24
Peak memory 194792 kb
Host smart-3a0e568c-d926-4091-80f7-730eadf38eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670176156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3670176156
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2345522223
Short name T1182
Test name
Test status
Simulation time 38861685 ps
CPU time 0.59 seconds
Started Aug 09 07:15:23 PM PDT 24
Finished Aug 09 07:15:23 PM PDT 24
Peak memory 194732 kb
Host smart-5451b518-d080-4e25-b21a-b4f31bce8f81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345522223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2345522223
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.50778978
Short name T1250
Test name
Test status
Simulation time 30054993 ps
CPU time 0.55 seconds
Started Aug 09 07:15:11 PM PDT 24
Finished Aug 09 07:15:12 PM PDT 24
Peak memory 194760 kb
Host smart-cdf59c1a-2e35-4713-b880-a496c65506df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50778978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.50778978
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3006040005
Short name T1246
Test name
Test status
Simulation time 16602730 ps
CPU time 0.54 seconds
Started Aug 09 07:15:15 PM PDT 24
Finished Aug 09 07:15:16 PM PDT 24
Peak memory 194792 kb
Host smart-0caba7b1-a68d-4dc3-837b-4b0fc28e3cff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006040005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3006040005
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.704150062
Short name T1235
Test name
Test status
Simulation time 61023496 ps
CPU time 0.56 seconds
Started Aug 09 07:15:10 PM PDT 24
Finished Aug 09 07:15:11 PM PDT 24
Peak memory 194760 kb
Host smart-62612542-9175-4cea-82c3-0f8182027110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704150062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.704150062
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.661622955
Short name T1281
Test name
Test status
Simulation time 12619507 ps
CPU time 0.57 seconds
Started Aug 09 07:15:31 PM PDT 24
Finished Aug 09 07:15:32 PM PDT 24
Peak memory 194740 kb
Host smart-a4369e9a-47e2-440a-bced-aeef67c43a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661622955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.661622955
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2220131174
Short name T1268
Test name
Test status
Simulation time 83578661 ps
CPU time 0.59 seconds
Started Aug 09 07:15:12 PM PDT 24
Finished Aug 09 07:15:12 PM PDT 24
Peak memory 194752 kb
Host smart-634019b7-5fa4-470d-9c66-f2c17bcb3ca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220131174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2220131174
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1475440505
Short name T1204
Test name
Test status
Simulation time 22939218 ps
CPU time 0.56 seconds
Started Aug 09 07:15:16 PM PDT 24
Finished Aug 09 07:15:17 PM PDT 24
Peak memory 194772 kb
Host smart-a73da442-2dc1-48d5-a660-a89df1fea483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475440505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1475440505
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1295100748
Short name T1213
Test name
Test status
Simulation time 22404435 ps
CPU time 0.73 seconds
Started Aug 09 07:14:48 PM PDT 24
Finished Aug 09 07:14:49 PM PDT 24
Peak memory 198988 kb
Host smart-cd849539-830f-4d39-81ce-6e9ddc5d47f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295100748 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1295100748
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3685125096
Short name T1220
Test name
Test status
Simulation time 36758496 ps
CPU time 0.61 seconds
Started Aug 09 07:14:56 PM PDT 24
Finished Aug 09 07:14:57 PM PDT 24
Peak memory 195832 kb
Host smart-f3075120-3cf3-48e0-b504-cc35a50b4bff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685125096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3685125096
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3533312593
Short name T1187
Test name
Test status
Simulation time 23700501 ps
CPU time 0.57 seconds
Started Aug 09 07:14:56 PM PDT 24
Finished Aug 09 07:14:57 PM PDT 24
Peak memory 194760 kb
Host smart-929c5c73-a5df-425d-b9e9-e70bb410940e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533312593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3533312593
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.426090485
Short name T1248
Test name
Test status
Simulation time 95275950 ps
CPU time 0.72 seconds
Started Aug 09 07:15:13 PM PDT 24
Finished Aug 09 07:15:14 PM PDT 24
Peak memory 197284 kb
Host smart-c0ac79ec-d0fe-4254-8302-dc264aefa3ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426090485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.426090485
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3205799387
Short name T1189
Test name
Test status
Simulation time 707511939 ps
CPU time 2.14 seconds
Started Aug 09 07:14:55 PM PDT 24
Finished Aug 09 07:14:57 PM PDT 24
Peak memory 200480 kb
Host smart-ae977dd5-98ff-41aa-a33c-8cb7958e3121
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205799387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3205799387
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1373853250
Short name T1290
Test name
Test status
Simulation time 52811573 ps
CPU time 0.96 seconds
Started Aug 09 07:15:05 PM PDT 24
Finished Aug 09 07:15:06 PM PDT 24
Peak memory 199432 kb
Host smart-757d3eac-b96a-4d2f-b9d6-b998e5531f27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373853250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1373853250
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3950418914
Short name T1260
Test name
Test status
Simulation time 20079994 ps
CPU time 0.94 seconds
Started Aug 09 07:14:58 PM PDT 24
Finished Aug 09 07:14:59 PM PDT 24
Peak memory 200196 kb
Host smart-142f8303-091d-4c28-8577-4e8467969291
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950418914 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3950418914
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1997220869
Short name T1301
Test name
Test status
Simulation time 12464186 ps
CPU time 0.58 seconds
Started Aug 09 07:15:06 PM PDT 24
Finished Aug 09 07:15:07 PM PDT 24
Peak memory 195768 kb
Host smart-7e1f8987-a844-4570-b205-306e84dcd581
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997220869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1997220869
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.570815280
Short name T1238
Test name
Test status
Simulation time 26000169 ps
CPU time 0.59 seconds
Started Aug 09 07:14:58 PM PDT 24
Finished Aug 09 07:14:59 PM PDT 24
Peak memory 194756 kb
Host smart-b07f0904-6e58-4ffb-be0e-eb4044f68c3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570815280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.570815280
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3096688499
Short name T1311
Test name
Test status
Simulation time 72539674 ps
CPU time 0.6 seconds
Started Aug 09 07:14:55 PM PDT 24
Finished Aug 09 07:14:56 PM PDT 24
Peak memory 196040 kb
Host smart-db7d196a-372b-4721-9e93-772b37762961
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096688499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3096688499
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1489464459
Short name T1282
Test name
Test status
Simulation time 212930255 ps
CPU time 2.08 seconds
Started Aug 09 07:14:54 PM PDT 24
Finished Aug 09 07:14:56 PM PDT 24
Peak memory 200472 kb
Host smart-7e86cc80-50c9-49c6-9abf-a15c5eac915c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489464459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1489464459
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1698394553
Short name T1298
Test name
Test status
Simulation time 137764382 ps
CPU time 0.92 seconds
Started Aug 09 07:14:58 PM PDT 24
Finished Aug 09 07:14:59 PM PDT 24
Peak memory 199368 kb
Host smart-8f241e52-395c-42f4-bba4-48337933ebc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698394553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1698394553
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.218146931
Short name T1232
Test name
Test status
Simulation time 35422891 ps
CPU time 0.65 seconds
Started Aug 09 07:15:15 PM PDT 24
Finished Aug 09 07:15:15 PM PDT 24
Peak memory 198224 kb
Host smart-0af34482-ec6c-498f-a837-8851f51413f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218146931 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.218146931
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.562507058
Short name T1243
Test name
Test status
Simulation time 12653124 ps
CPU time 0.59 seconds
Started Aug 09 07:14:58 PM PDT 24
Finished Aug 09 07:14:59 PM PDT 24
Peak memory 195768 kb
Host smart-db66b02a-06b6-4993-aa5c-265f4a96f823
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562507058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.562507058
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3351216145
Short name T1283
Test name
Test status
Simulation time 24244397 ps
CPU time 0.59 seconds
Started Aug 09 07:14:46 PM PDT 24
Finished Aug 09 07:14:47 PM PDT 24
Peak memory 194796 kb
Host smart-221ac067-46bd-4fc2-b00d-c6e3f45889cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351216145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3351216145
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.538033055
Short name T68
Test name
Test status
Simulation time 17731242 ps
CPU time 0.65 seconds
Started Aug 09 07:15:04 PM PDT 24
Finished Aug 09 07:15:04 PM PDT 24
Peak memory 196264 kb
Host smart-fcc57cc7-0f77-472d-bd1a-124549187aaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538033055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_
outstanding.538033055
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.9909301
Short name T1277
Test name
Test status
Simulation time 417292977 ps
CPU time 2.01 seconds
Started Aug 09 07:14:53 PM PDT 24
Finished Aug 09 07:14:55 PM PDT 24
Peak memory 200360 kb
Host smart-32a9753f-8835-4970-a0fe-fe8a30b1d3eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9909301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.9909301
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.640636827
Short name T88
Test name
Test status
Simulation time 1320892482 ps
CPU time 1.64 seconds
Started Aug 09 07:14:58 PM PDT 24
Finished Aug 09 07:14:59 PM PDT 24
Peak memory 199692 kb
Host smart-b8b0e40a-5dcb-4158-9df2-2140c004cccf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640636827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.640636827
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3858693068
Short name T1184
Test name
Test status
Simulation time 70988049 ps
CPU time 0.73 seconds
Started Aug 09 07:15:06 PM PDT 24
Finished Aug 09 07:15:07 PM PDT 24
Peak memory 199156 kb
Host smart-0ed71fba-1d03-424f-96a5-19e63249abe5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858693068 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3858693068
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.252891409
Short name T1236
Test name
Test status
Simulation time 14483086 ps
CPU time 0.6 seconds
Started Aug 09 07:15:09 PM PDT 24
Finished Aug 09 07:15:10 PM PDT 24
Peak memory 195864 kb
Host smart-a500a3d1-9893-4708-b92d-749a80f03ba4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252891409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.252891409
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2882539129
Short name T1254
Test name
Test status
Simulation time 25204038 ps
CPU time 0.58 seconds
Started Aug 09 07:15:03 PM PDT 24
Finished Aug 09 07:15:04 PM PDT 24
Peak memory 194808 kb
Host smart-2ee36adb-abdd-4183-8eae-80434faf393e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882539129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2882539129
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1129265609
Short name T1242
Test name
Test status
Simulation time 30971026 ps
CPU time 0.78 seconds
Started Aug 09 07:15:27 PM PDT 24
Finished Aug 09 07:15:28 PM PDT 24
Peak memory 197112 kb
Host smart-48e22b95-e900-475d-825d-dd213d0595e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129265609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1129265609
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3648618358
Short name T1287
Test name
Test status
Simulation time 204240611 ps
CPU time 1.35 seconds
Started Aug 09 07:15:01 PM PDT 24
Finished Aug 09 07:15:02 PM PDT 24
Peak memory 200440 kb
Host smart-e50951e2-8403-4225-94c5-521c45183ce0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648618358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3648618358
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1584830149
Short name T85
Test name
Test status
Simulation time 74528903 ps
CPU time 0.95 seconds
Started Aug 09 07:15:06 PM PDT 24
Finished Aug 09 07:15:08 PM PDT 24
Peak memory 199216 kb
Host smart-e01a24ed-53d7-4736-8ed7-9eeb199e5b75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584830149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1584830149
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2927956240
Short name T1217
Test name
Test status
Simulation time 46079955 ps
CPU time 0.8 seconds
Started Aug 09 07:15:19 PM PDT 24
Finished Aug 09 07:15:20 PM PDT 24
Peak memory 199792 kb
Host smart-c993b0c6-1f4e-4b8a-8c3c-9a66f6e57717
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927956240 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2927956240
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.595028568
Short name T73
Test name
Test status
Simulation time 15392753 ps
CPU time 0.62 seconds
Started Aug 09 07:15:15 PM PDT 24
Finished Aug 09 07:15:16 PM PDT 24
Peak memory 195848 kb
Host smart-ff6fe4d8-aa87-44a0-bcc4-0410426295e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595028568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.595028568
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3345969169
Short name T1266
Test name
Test status
Simulation time 62689949 ps
CPU time 0.56 seconds
Started Aug 09 07:14:59 PM PDT 24
Finished Aug 09 07:15:00 PM PDT 24
Peak memory 194792 kb
Host smart-69319c0a-e9a6-4118-8281-8c82d384312c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345969169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3345969169
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.292632753
Short name T1315
Test name
Test status
Simulation time 40672279 ps
CPU time 0.65 seconds
Started Aug 09 07:15:21 PM PDT 24
Finished Aug 09 07:15:22 PM PDT 24
Peak memory 196184 kb
Host smart-a5b4d068-2012-4508-80ab-e1fe2264a65b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292632753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.292632753
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3942388941
Short name T1218
Test name
Test status
Simulation time 86046793 ps
CPU time 1.88 seconds
Started Aug 09 07:15:06 PM PDT 24
Finished Aug 09 07:15:08 PM PDT 24
Peak memory 200400 kb
Host smart-038ab0ce-cb70-4f5c-9bac-c573bcdf5780
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942388941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3942388941
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2502951845
Short name T86
Test name
Test status
Simulation time 128248518 ps
CPU time 0.95 seconds
Started Aug 09 07:15:26 PM PDT 24
Finished Aug 09 07:15:28 PM PDT 24
Peak memory 199012 kb
Host smart-30d161c0-75cc-47e9-a846-83abcd2b54b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502951845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2502951845
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.3981773022
Short name T452
Test name
Test status
Simulation time 14574875 ps
CPU time 0.57 seconds
Started Aug 09 07:18:34 PM PDT 24
Finished Aug 09 07:18:35 PM PDT 24
Peak memory 195348 kb
Host smart-682b57f1-e5f5-4361-9c55-50b26b69da83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981773022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3981773022
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.887086941
Short name T1090
Test name
Test status
Simulation time 34665277715 ps
CPU time 21.3 seconds
Started Aug 09 07:18:29 PM PDT 24
Finished Aug 09 07:18:51 PM PDT 24
Peak memory 199880 kb
Host smart-7646b1d2-b00e-48f4-9012-9bce2b48372e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887086941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.887086941
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.259966009
Short name T574
Test name
Test status
Simulation time 22005864403 ps
CPU time 29.74 seconds
Started Aug 09 07:18:30 PM PDT 24
Finished Aug 09 07:19:00 PM PDT 24
Peak memory 199820 kb
Host smart-7b283a54-c913-42d2-8bc2-884ea48ca670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259966009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.259966009
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.604015519
Short name T495
Test name
Test status
Simulation time 20201755184 ps
CPU time 56.1 seconds
Started Aug 09 07:18:29 PM PDT 24
Finished Aug 09 07:19:25 PM PDT 24
Peak memory 199908 kb
Host smart-bc3f1867-a169-4620-aa61-882fceb32c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604015519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.604015519
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.4277766210
Short name T627
Test name
Test status
Simulation time 31948569106 ps
CPU time 14.06 seconds
Started Aug 09 07:18:29 PM PDT 24
Finished Aug 09 07:18:43 PM PDT 24
Peak memory 198596 kb
Host smart-0bad5fe8-2aff-444d-b8bc-be0882753de9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277766210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.4277766210
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.593302621
Short name T982
Test name
Test status
Simulation time 265740218114 ps
CPU time 313.61 seconds
Started Aug 09 07:18:33 PM PDT 24
Finished Aug 09 07:23:47 PM PDT 24
Peak memory 199844 kb
Host smart-8d9921f2-1447-4965-8917-1969203679ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=593302621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.593302621
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.4250764419
Short name T593
Test name
Test status
Simulation time 5843825137 ps
CPU time 2.31 seconds
Started Aug 09 07:18:33 PM PDT 24
Finished Aug 09 07:18:36 PM PDT 24
Peak memory 199936 kb
Host smart-ac7fe31e-8f8b-4535-91a5-911f30482c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250764419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.4250764419
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.2511653228
Short name T846
Test name
Test status
Simulation time 109799251270 ps
CPU time 93.05 seconds
Started Aug 09 07:18:35 PM PDT 24
Finished Aug 09 07:20:08 PM PDT 24
Peak memory 209500 kb
Host smart-5e115ea7-0c7c-403e-b74b-636ad3872765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511653228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2511653228
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2172075220
Short name T39
Test name
Test status
Simulation time 15710481573 ps
CPU time 933.48 seconds
Started Aug 09 07:18:33 PM PDT 24
Finished Aug 09 07:34:07 PM PDT 24
Peak memory 199928 kb
Host smart-cb364eeb-3ae3-4b70-8402-fe5048619177
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2172075220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2172075220
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3748058990
Short name T439
Test name
Test status
Simulation time 4531523940 ps
CPU time 20.01 seconds
Started Aug 09 07:18:27 PM PDT 24
Finished Aug 09 07:18:47 PM PDT 24
Peak memory 198900 kb
Host smart-c40e4734-01e5-4461-9a42-8a860d63eaec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748058990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3748058990
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.1180446299
Short name T565
Test name
Test status
Simulation time 51859807862 ps
CPU time 79.33 seconds
Started Aug 09 07:18:33 PM PDT 24
Finished Aug 09 07:19:53 PM PDT 24
Peak memory 199872 kb
Host smart-25f3e2ad-2345-4949-bada-59ec5012f4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180446299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1180446299
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3743509117
Short name T917
Test name
Test status
Simulation time 2701169090 ps
CPU time 4.77 seconds
Started Aug 09 07:18:34 PM PDT 24
Finished Aug 09 07:18:39 PM PDT 24
Peak memory 196768 kb
Host smart-bdf27c47-fdef-4547-ab8b-856941763358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743509117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3743509117
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.1360434043
Short name T691
Test name
Test status
Simulation time 6208564139 ps
CPU time 3.46 seconds
Started Aug 09 07:18:27 PM PDT 24
Finished Aug 09 07:18:30 PM PDT 24
Peak memory 199052 kb
Host smart-b350c309-0129-4a77-97d7-462f57750f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360434043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1360434043
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.1590407590
Short name T894
Test name
Test status
Simulation time 190874213803 ps
CPU time 305.85 seconds
Started Aug 09 07:18:36 PM PDT 24
Finished Aug 09 07:23:42 PM PDT 24
Peak memory 208892 kb
Host smart-ce6899fc-60e5-44fd-a49a-5fae43c9797b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590407590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1590407590
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.389399933
Short name T722
Test name
Test status
Simulation time 120282446021 ps
CPU time 872.23 seconds
Started Aug 09 07:18:34 PM PDT 24
Finished Aug 09 07:33:07 PM PDT 24
Peak memory 216452 kb
Host smart-d7362eb1-9990-4aee-b410-2dd9e02397a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389399933 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.389399933
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1511851207
Short name T1008
Test name
Test status
Simulation time 729757362 ps
CPU time 3.27 seconds
Started Aug 09 07:18:34 PM PDT 24
Finished Aug 09 07:18:37 PM PDT 24
Peak memory 198252 kb
Host smart-a1b1b7b8-d7a5-4483-a2fb-6b8b74e3da9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511851207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1511851207
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1467283170
Short name T1045
Test name
Test status
Simulation time 22843266050 ps
CPU time 35.3 seconds
Started Aug 09 07:18:29 PM PDT 24
Finished Aug 09 07:19:05 PM PDT 24
Peak memory 199944 kb
Host smart-26a33cbb-8097-4fb8-a959-8c9edd0ce559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467283170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1467283170
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.38916946
Short name T833
Test name
Test status
Simulation time 42474773 ps
CPU time 0.57 seconds
Started Aug 09 07:18:41 PM PDT 24
Finished Aug 09 07:18:42 PM PDT 24
Peak memory 195164 kb
Host smart-350e364d-eb1f-4683-a06f-b1c9f378dc73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38916946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.38916946
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1018573958
Short name T821
Test name
Test status
Simulation time 13015448764 ps
CPU time 22.02 seconds
Started Aug 09 07:18:36 PM PDT 24
Finished Aug 09 07:18:58 PM PDT 24
Peak memory 199964 kb
Host smart-76081424-cb71-44bb-9969-56d30e357cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018573958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1018573958
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.762760582
Short name T169
Test name
Test status
Simulation time 86248726291 ps
CPU time 159.96 seconds
Started Aug 09 07:18:42 PM PDT 24
Finished Aug 09 07:21:22 PM PDT 24
Peak memory 199884 kb
Host smart-d1fd17d5-fbc9-4797-9172-0aa92155f42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762760582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.762760582
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.893481599
Short name T526
Test name
Test status
Simulation time 5944339067 ps
CPU time 4.45 seconds
Started Aug 09 07:18:40 PM PDT 24
Finished Aug 09 07:18:44 PM PDT 24
Peak memory 196188 kb
Host smart-3eed939e-0d24-4834-87ac-24c160045913
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893481599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.893481599
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.355502393
Short name T891
Test name
Test status
Simulation time 270604922555 ps
CPU time 477.94 seconds
Started Aug 09 07:18:41 PM PDT 24
Finished Aug 09 07:26:40 PM PDT 24
Peak memory 199840 kb
Host smart-ada9cd8a-f60b-498f-a4de-f1892dffbb0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=355502393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.355502393
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1081667618
Short name T344
Test name
Test status
Simulation time 7641432070 ps
CPU time 5.25 seconds
Started Aug 09 07:18:40 PM PDT 24
Finished Aug 09 07:18:46 PM PDT 24
Peak memory 199544 kb
Host smart-ce1cc272-5d75-4d29-8f75-587fb7b6e498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081667618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1081667618
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2103717502
Short name T1073
Test name
Test status
Simulation time 66164100498 ps
CPU time 27.68 seconds
Started Aug 09 07:18:41 PM PDT 24
Finished Aug 09 07:19:09 PM PDT 24
Peak memory 196828 kb
Host smart-850a7dcf-6fcd-4305-8586-7517793a79a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103717502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2103717502
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.654076127
Short name T1144
Test name
Test status
Simulation time 16644621120 ps
CPU time 432.3 seconds
Started Aug 09 07:18:41 PM PDT 24
Finished Aug 09 07:25:54 PM PDT 24
Peak memory 199756 kb
Host smart-9ca495a7-ac96-4d5d-abf5-0b3238cacc67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=654076127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.654076127
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2749580733
Short name T720
Test name
Test status
Simulation time 2022745860 ps
CPU time 6.18 seconds
Started Aug 09 07:18:41 PM PDT 24
Finished Aug 09 07:18:48 PM PDT 24
Peak memory 199072 kb
Host smart-1950ad56-9ade-449c-a1cb-29207fb31c5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2749580733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2749580733
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3903236050
Short name T661
Test name
Test status
Simulation time 164968448018 ps
CPU time 343.25 seconds
Started Aug 09 07:18:41 PM PDT 24
Finished Aug 09 07:24:24 PM PDT 24
Peak memory 200056 kb
Host smart-f05bb24a-4e11-4f5b-906a-3a95a7d1320d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903236050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3903236050
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2328185835
Short name T860
Test name
Test status
Simulation time 6297229759 ps
CPU time 3.33 seconds
Started Aug 09 07:18:41 PM PDT 24
Finished Aug 09 07:18:45 PM PDT 24
Peak memory 196044 kb
Host smart-013a7d00-4de4-41e6-a018-008d0e0e1da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328185835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2328185835
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.4293523256
Short name T28
Test name
Test status
Simulation time 42986044 ps
CPU time 0.79 seconds
Started Aug 09 07:18:42 PM PDT 24
Finished Aug 09 07:18:43 PM PDT 24
Peak memory 218332 kb
Host smart-1057ddcb-f044-4f4f-bde3-67a150644202
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293523256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.4293523256
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1233740633
Short name T486
Test name
Test status
Simulation time 459531644 ps
CPU time 2.12 seconds
Started Aug 09 07:18:32 PM PDT 24
Finished Aug 09 07:18:35 PM PDT 24
Peak memory 198704 kb
Host smart-43188b9d-6e2d-43ba-b0b9-aa5338afae63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233740633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1233740633
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3414444480
Short name T330
Test name
Test status
Simulation time 114913960660 ps
CPU time 160.94 seconds
Started Aug 09 07:18:41 PM PDT 24
Finished Aug 09 07:21:22 PM PDT 24
Peak memory 216412 kb
Host smart-64bc6743-472c-4e6e-871b-5253b95b3cef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414444480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3414444480
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.297087984
Short name T616
Test name
Test status
Simulation time 12616242126 ps
CPU time 62.31 seconds
Started Aug 09 07:18:43 PM PDT 24
Finished Aug 09 07:19:45 PM PDT 24
Peak memory 199872 kb
Host smart-ae5e7c8f-3fca-4171-9d15-ef8d0ed9393f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297087984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.297087984
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1245904499
Short name T97
Test name
Test status
Simulation time 182779697564 ps
CPU time 106.05 seconds
Started Aug 09 07:18:34 PM PDT 24
Finished Aug 09 07:20:21 PM PDT 24
Peak memory 199948 kb
Host smart-aebd2212-734b-4490-9703-c2fa9475fe69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245904499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1245904499
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3371163131
Short name T412
Test name
Test status
Simulation time 11595184 ps
CPU time 0.55 seconds
Started Aug 09 07:19:16 PM PDT 24
Finished Aug 09 07:19:17 PM PDT 24
Peak memory 194628 kb
Host smart-8132b686-bcbd-496b-b340-8b44a2eff67c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371163131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3371163131
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3715694117
Short name T152
Test name
Test status
Simulation time 25258737997 ps
CPU time 46.23 seconds
Started Aug 09 07:19:13 PM PDT 24
Finished Aug 09 07:20:00 PM PDT 24
Peak memory 199948 kb
Host smart-2bc5fc24-757f-4295-847b-db29a3d67511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715694117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3715694117
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.301276121
Short name T400
Test name
Test status
Simulation time 106039687073 ps
CPU time 135.97 seconds
Started Aug 09 07:19:10 PM PDT 24
Finished Aug 09 07:21:26 PM PDT 24
Peak memory 199952 kb
Host smart-e6be9b52-0784-4d3c-99ba-ade5c6b924b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301276121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.301276121
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.1355233814
Short name T825
Test name
Test status
Simulation time 51065114365 ps
CPU time 76.06 seconds
Started Aug 09 07:19:16 PM PDT 24
Finished Aug 09 07:20:32 PM PDT 24
Peak memory 199740 kb
Host smart-0e2c4e05-61eb-4a3f-9229-5a11296b1f9f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355233814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1355233814
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1884507287
Short name T272
Test name
Test status
Simulation time 131238081234 ps
CPU time 802.49 seconds
Started Aug 09 07:19:12 PM PDT 24
Finished Aug 09 07:32:34 PM PDT 24
Peak memory 199844 kb
Host smart-5f39be2b-05c8-4b3f-83cb-3c704f31e272
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1884507287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1884507287
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2789644735
Short name T641
Test name
Test status
Simulation time 3674201890 ps
CPU time 5.91 seconds
Started Aug 09 07:19:11 PM PDT 24
Finished Aug 09 07:19:17 PM PDT 24
Peak memory 196396 kb
Host smart-588fe6e6-bb9a-49d0-bb60-1bc436e8547e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789644735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2789644735
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.108575976
Short name T466
Test name
Test status
Simulation time 27722181584 ps
CPU time 26.35 seconds
Started Aug 09 07:19:11 PM PDT 24
Finished Aug 09 07:19:37 PM PDT 24
Peak memory 200004 kb
Host smart-61299667-b18b-4427-b120-dbcab32c6e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108575976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.108575976
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.86410276
Short name T413
Test name
Test status
Simulation time 1917083388 ps
CPU time 110.63 seconds
Started Aug 09 07:19:12 PM PDT 24
Finished Aug 09 07:21:02 PM PDT 24
Peak memory 199768 kb
Host smart-e9cda856-ee80-42ad-9a7f-b72026392b2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=86410276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.86410276
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2789670791
Short name T470
Test name
Test status
Simulation time 7301528674 ps
CPU time 16.61 seconds
Started Aug 09 07:19:11 PM PDT 24
Finished Aug 09 07:19:28 PM PDT 24
Peak memory 198052 kb
Host smart-3e22e356-d20c-46a9-b46b-919c083b3d45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2789670791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2789670791
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1438956165
Short name T1153
Test name
Test status
Simulation time 33108489432 ps
CPU time 24.17 seconds
Started Aug 09 07:19:11 PM PDT 24
Finished Aug 09 07:19:36 PM PDT 24
Peak memory 199964 kb
Host smart-16d56e41-ad22-4d7a-b319-4530bab40cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438956165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1438956165
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1541765226
Short name T63
Test name
Test status
Simulation time 537640688 ps
CPU time 1.56 seconds
Started Aug 09 07:19:09 PM PDT 24
Finished Aug 09 07:19:10 PM PDT 24
Peak memory 195636 kb
Host smart-b8fa8fa9-434c-4504-8d52-b2575594dd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541765226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1541765226
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.201254921
Short name T582
Test name
Test status
Simulation time 511437976 ps
CPU time 2.04 seconds
Started Aug 09 07:19:12 PM PDT 24
Finished Aug 09 07:19:14 PM PDT 24
Peak memory 198240 kb
Host smart-f51e11bf-50d7-4e44-bb24-d1240bd737ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201254921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.201254921
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.488228433
Short name T175
Test name
Test status
Simulation time 227543589049 ps
CPU time 542.83 seconds
Started Aug 09 07:19:09 PM PDT 24
Finished Aug 09 07:28:12 PM PDT 24
Peak memory 216380 kb
Host smart-f49260b0-bd9c-4572-bc22-f749238ad64e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488228433 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.488228433
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1900988354
Short name T352
Test name
Test status
Simulation time 7768718598 ps
CPU time 11.75 seconds
Started Aug 09 07:19:10 PM PDT 24
Finished Aug 09 07:19:22 PM PDT 24
Peak memory 199900 kb
Host smart-1f3cc7bf-0692-4404-8a19-7bf5972d2491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900988354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1900988354
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3014967646
Short name T487
Test name
Test status
Simulation time 91465831742 ps
CPU time 35.54 seconds
Started Aug 09 07:19:11 PM PDT 24
Finished Aug 09 07:19:47 PM PDT 24
Peak memory 199956 kb
Host smart-9e7eb338-3b53-4c53-97d0-9c0504051524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014967646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3014967646
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1970305842
Short name T577
Test name
Test status
Simulation time 118462013656 ps
CPU time 57.83 seconds
Started Aug 09 07:23:38 PM PDT 24
Finished Aug 09 07:24:36 PM PDT 24
Peak memory 199940 kb
Host smart-d880357e-fac1-4bd8-aad6-32cabd504c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970305842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1970305842
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3019682178
Short name T647
Test name
Test status
Simulation time 109219791131 ps
CPU time 49.88 seconds
Started Aug 09 07:23:37 PM PDT 24
Finished Aug 09 07:24:27 PM PDT 24
Peak memory 199920 kb
Host smart-f95f44d9-b2da-4da0-9c47-124d14b826d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019682178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3019682178
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3342533609
Short name T458
Test name
Test status
Simulation time 24945051248 ps
CPU time 51.78 seconds
Started Aug 09 07:23:37 PM PDT 24
Finished Aug 09 07:24:29 PM PDT 24
Peak memory 199944 kb
Host smart-a47318dc-c5b9-47e8-adb9-ca77f52ec51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342533609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3342533609
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3833826100
Short name T955
Test name
Test status
Simulation time 28738114425 ps
CPU time 33.34 seconds
Started Aug 09 07:23:37 PM PDT 24
Finished Aug 09 07:24:11 PM PDT 24
Peak memory 199888 kb
Host smart-07516f09-053b-4eca-8317-b325d50d804c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833826100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3833826100
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.736578220
Short name T411
Test name
Test status
Simulation time 114770602929 ps
CPU time 59.48 seconds
Started Aug 09 07:23:35 PM PDT 24
Finished Aug 09 07:24:35 PM PDT 24
Peak memory 199984 kb
Host smart-bc43059a-3f09-47c2-83cb-eb07d6abf39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736578220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.736578220
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.250042636
Short name T583
Test name
Test status
Simulation time 71242965252 ps
CPU time 98.39 seconds
Started Aug 09 07:23:37 PM PDT 24
Finished Aug 09 07:25:16 PM PDT 24
Peak memory 199920 kb
Host smart-a0ecd39e-4e5d-4c79-bcca-6dfdea78e53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250042636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.250042636
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2114151521
Short name T334
Test name
Test status
Simulation time 15052345603 ps
CPU time 22.06 seconds
Started Aug 09 07:23:40 PM PDT 24
Finished Aug 09 07:24:02 PM PDT 24
Peak memory 199012 kb
Host smart-da2aa269-83e7-4162-a79c-83a0fb0eea1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114151521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2114151521
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1226465815
Short name T398
Test name
Test status
Simulation time 118021335080 ps
CPU time 50.54 seconds
Started Aug 09 07:23:38 PM PDT 24
Finished Aug 09 07:24:28 PM PDT 24
Peak memory 199876 kb
Host smart-50a62b05-d685-4d3a-87f4-a8f97c2f7cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226465815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1226465815
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3426087840
Short name T603
Test name
Test status
Simulation time 224449862247 ps
CPU time 102.54 seconds
Started Aug 09 07:23:36 PM PDT 24
Finished Aug 09 07:25:19 PM PDT 24
Peak memory 199928 kb
Host smart-43e68fc3-8863-429a-8aba-d90a751b37ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426087840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3426087840
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1019505057
Short name T530
Test name
Test status
Simulation time 94906584633 ps
CPU time 40.23 seconds
Started Aug 09 07:19:10 PM PDT 24
Finished Aug 09 07:19:50 PM PDT 24
Peak memory 200152 kb
Host smart-43ca44c8-32d7-4149-8c13-d9335af73ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019505057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1019505057
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2611491265
Short name T1039
Test name
Test status
Simulation time 163784468683 ps
CPU time 120.18 seconds
Started Aug 09 07:19:11 PM PDT 24
Finished Aug 09 07:21:11 PM PDT 24
Peak memory 199956 kb
Host smart-1680596c-ae5a-458f-9bb5-aafd4dee09a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611491265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2611491265
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1557122806
Short name T942
Test name
Test status
Simulation time 289891790074 ps
CPU time 228.23 seconds
Started Aug 09 07:19:10 PM PDT 24
Finished Aug 09 07:22:58 PM PDT 24
Peak memory 199960 kb
Host smart-0798573a-634e-4820-b185-1863c869de90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557122806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1557122806
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.2271570779
Short name T707
Test name
Test status
Simulation time 8753529134 ps
CPU time 3.37 seconds
Started Aug 09 07:19:11 PM PDT 24
Finished Aug 09 07:19:15 PM PDT 24
Peak memory 196704 kb
Host smart-c043b74c-d3af-44e8-98eb-402dbbab4149
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271570779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2271570779
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.4146380372
Short name T721
Test name
Test status
Simulation time 109636614147 ps
CPU time 719.25 seconds
Started Aug 09 07:19:10 PM PDT 24
Finished Aug 09 07:31:10 PM PDT 24
Peak memory 200028 kb
Host smart-1ac1644b-f041-455f-9d38-76704f676928
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4146380372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.4146380372
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.726103636
Short name T22
Test name
Test status
Simulation time 797071216 ps
CPU time 1.96 seconds
Started Aug 09 07:19:15 PM PDT 24
Finished Aug 09 07:19:17 PM PDT 24
Peak memory 196120 kb
Host smart-99da7ecb-80d5-42d3-bdf9-ed2cf5c40114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726103636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.726103636
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2097458598
Short name T354
Test name
Test status
Simulation time 41001800889 ps
CPU time 65.58 seconds
Started Aug 09 07:19:12 PM PDT 24
Finished Aug 09 07:20:17 PM PDT 24
Peak memory 198784 kb
Host smart-3b9ca16f-c945-4cdd-959b-26f3cca0e7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097458598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2097458598
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.304960541
Short name T732
Test name
Test status
Simulation time 15539711038 ps
CPU time 858.47 seconds
Started Aug 09 07:19:12 PM PDT 24
Finished Aug 09 07:33:31 PM PDT 24
Peak memory 199840 kb
Host smart-79d63382-e367-4e54-a4ae-de88c54b5e35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=304960541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.304960541
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.399134005
Short name T491
Test name
Test status
Simulation time 1914028659 ps
CPU time 14.8 seconds
Started Aug 09 07:19:12 PM PDT 24
Finished Aug 09 07:19:26 PM PDT 24
Peak memory 197716 kb
Host smart-23599271-a679-4483-b4f6-63c175f7233a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=399134005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.399134005
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.362535304
Short name T1162
Test name
Test status
Simulation time 120265671024 ps
CPU time 37.25 seconds
Started Aug 09 07:19:11 PM PDT 24
Finished Aug 09 07:19:49 PM PDT 24
Peak memory 199952 kb
Host smart-0bfda4c1-4472-431a-9ea6-7301a4d0f9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362535304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.362535304
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1292592966
Short name T713
Test name
Test status
Simulation time 39539361446 ps
CPU time 54.94 seconds
Started Aug 09 07:19:11 PM PDT 24
Finished Aug 09 07:20:06 PM PDT 24
Peak memory 196080 kb
Host smart-2d703791-f1b6-4b2f-836a-a117526a56b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292592966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1292592966
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1493117706
Short name T1172
Test name
Test status
Simulation time 250303061 ps
CPU time 1.48 seconds
Started Aug 09 07:19:08 PM PDT 24
Finished Aug 09 07:19:09 PM PDT 24
Peak memory 199456 kb
Host smart-8e1efbf3-2e61-4e25-9585-ad6775215598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493117706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1493117706
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1260813317
Short name T524
Test name
Test status
Simulation time 135719819836 ps
CPU time 67.54 seconds
Started Aug 09 07:19:10 PM PDT 24
Finished Aug 09 07:20:17 PM PDT 24
Peak memory 199996 kb
Host smart-8ae6c473-9b6a-4306-811b-835593f30f39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260813317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1260813317
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3412408521
Short name T482
Test name
Test status
Simulation time 84827221657 ps
CPU time 815.25 seconds
Started Aug 09 07:19:14 PM PDT 24
Finished Aug 09 07:32:50 PM PDT 24
Peak memory 224808 kb
Host smart-65a3449a-2de7-4d5d-b4e5-2d5706b858e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412408521 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3412408521
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.556715391
Short name T918
Test name
Test status
Simulation time 2275212479 ps
CPU time 2.63 seconds
Started Aug 09 07:19:09 PM PDT 24
Finished Aug 09 07:19:12 PM PDT 24
Peak memory 198780 kb
Host smart-7bf57ed2-2a4f-46f9-aaa0-5fc0f57b175f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556715391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.556715391
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.934343539
Short name T1150
Test name
Test status
Simulation time 6256391916 ps
CPU time 5.16 seconds
Started Aug 09 07:19:12 PM PDT 24
Finished Aug 09 07:19:18 PM PDT 24
Peak memory 199772 kb
Host smart-28b10390-dd46-4828-a8a3-2e3a677177d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934343539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.934343539
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3156987945
Short name T329
Test name
Test status
Simulation time 59518764853 ps
CPU time 47.63 seconds
Started Aug 09 07:23:39 PM PDT 24
Finished Aug 09 07:24:27 PM PDT 24
Peak memory 199968 kb
Host smart-3cbc03d5-a223-4a19-858b-4f42aecb01ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156987945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3156987945
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3077013249
Short name T198
Test name
Test status
Simulation time 45596496473 ps
CPU time 64.54 seconds
Started Aug 09 07:23:47 PM PDT 24
Finished Aug 09 07:24:52 PM PDT 24
Peak memory 199940 kb
Host smart-158419ba-9ce9-407a-889f-e99d6c2b3c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077013249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3077013249
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2606850081
Short name T863
Test name
Test status
Simulation time 9460748438 ps
CPU time 17.31 seconds
Started Aug 09 07:23:48 PM PDT 24
Finished Aug 09 07:24:05 PM PDT 24
Peak memory 199896 kb
Host smart-b82bdea0-fceb-44b0-8971-17c284332621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606850081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2606850081
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.3464924605
Short name T871
Test name
Test status
Simulation time 220346256537 ps
CPU time 37.95 seconds
Started Aug 09 07:23:48 PM PDT 24
Finished Aug 09 07:24:26 PM PDT 24
Peak memory 199988 kb
Host smart-6ed0741e-8728-47f5-930e-f21466625564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464924605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3464924605
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3364032091
Short name T810
Test name
Test status
Simulation time 61727381754 ps
CPU time 11.2 seconds
Started Aug 09 07:23:48 PM PDT 24
Finished Aug 09 07:23:59 PM PDT 24
Peak memory 199764 kb
Host smart-559e2d7a-1f05-4384-becc-8d56f166cd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364032091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3364032091
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1270530798
Short name T1130
Test name
Test status
Simulation time 38388495202 ps
CPU time 56.45 seconds
Started Aug 09 07:23:55 PM PDT 24
Finished Aug 09 07:24:52 PM PDT 24
Peak memory 199928 kb
Host smart-283f0a99-0120-4229-ab7b-a00ceccafcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270530798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1270530798
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.4170066127
Short name T1091
Test name
Test status
Simulation time 23784156 ps
CPU time 0.6 seconds
Started Aug 09 07:19:13 PM PDT 24
Finished Aug 09 07:19:14 PM PDT 24
Peak memory 195348 kb
Host smart-08d764a3-766e-4970-ad66-0a8c191370e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170066127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.4170066127
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1348157335
Short name T114
Test name
Test status
Simulation time 121823904471 ps
CPU time 160.69 seconds
Started Aug 09 07:19:13 PM PDT 24
Finished Aug 09 07:21:54 PM PDT 24
Peak memory 199820 kb
Host smart-c93d3585-122e-41b9-8600-c287b543f4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348157335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1348157335
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1824646040
Short name T465
Test name
Test status
Simulation time 94252553600 ps
CPU time 127.31 seconds
Started Aug 09 07:19:12 PM PDT 24
Finished Aug 09 07:21:19 PM PDT 24
Peak memory 199996 kb
Host smart-8a7bf22d-8078-487a-b9e3-69f11a5acf96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824646040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1824646040
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.145986055
Short name T901
Test name
Test status
Simulation time 13666801831 ps
CPU time 75.59 seconds
Started Aug 09 07:19:12 PM PDT 24
Finished Aug 09 07:20:28 PM PDT 24
Peak memory 199992 kb
Host smart-7dbd2825-1d7f-4ae9-813d-74898ece6823
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145986055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.145986055
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2490821789
Short name T377
Test name
Test status
Simulation time 61071698833 ps
CPU time 115.47 seconds
Started Aug 09 07:19:13 PM PDT 24
Finished Aug 09 07:21:08 PM PDT 24
Peak memory 199904 kb
Host smart-0cf39095-ebcd-42f3-b9ff-145477e14fb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2490821789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2490821789
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3599578645
Short name T433
Test name
Test status
Simulation time 6295790425 ps
CPU time 13.9 seconds
Started Aug 09 07:19:11 PM PDT 24
Finished Aug 09 07:19:25 PM PDT 24
Peak memory 199948 kb
Host smart-6fa8b06c-4216-4af1-af57-11db7a456762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599578645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3599578645
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2629095897
Short name T310
Test name
Test status
Simulation time 5765958783 ps
CPU time 9.24 seconds
Started Aug 09 07:19:11 PM PDT 24
Finished Aug 09 07:19:20 PM PDT 24
Peak memory 196124 kb
Host smart-3cd57977-2eb6-4cc0-9336-6c5f4fffe227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629095897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2629095897
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.239040082
Short name T854
Test name
Test status
Simulation time 19813829904 ps
CPU time 1070.77 seconds
Started Aug 09 07:19:12 PM PDT 24
Finished Aug 09 07:37:03 PM PDT 24
Peak memory 199948 kb
Host smart-1eb12e64-df1c-471a-86a5-9db929d5b587
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=239040082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.239040082
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3088497137
Short name T77
Test name
Test status
Simulation time 4382251366 ps
CPU time 9.96 seconds
Started Aug 09 07:19:13 PM PDT 24
Finished Aug 09 07:19:23 PM PDT 24
Peak memory 198100 kb
Host smart-884a272c-1a9f-443f-8cb4-b13fba735cb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3088497137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3088497137
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1518801183
Short name T725
Test name
Test status
Simulation time 33285194822 ps
CPU time 17.13 seconds
Started Aug 09 07:19:12 PM PDT 24
Finished Aug 09 07:19:30 PM PDT 24
Peak memory 199848 kb
Host smart-535cfb6e-1814-4a5d-9133-8f4607769558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518801183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1518801183
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3809275950
Short name T954
Test name
Test status
Simulation time 42944347543 ps
CPU time 22.34 seconds
Started Aug 09 07:19:13 PM PDT 24
Finished Aug 09 07:19:35 PM PDT 24
Peak memory 195900 kb
Host smart-c083cddf-87e2-4480-a18e-478b5eb8ccd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809275950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3809275950
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1076704460
Short name T932
Test name
Test status
Simulation time 1006067144 ps
CPU time 2.62 seconds
Started Aug 09 07:19:13 PM PDT 24
Finished Aug 09 07:19:16 PM PDT 24
Peak memory 199780 kb
Host smart-2675f0be-f00e-4052-918a-f1489dc5f978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076704460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1076704460
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1621393616
Short name T405
Test name
Test status
Simulation time 177926655795 ps
CPU time 82.04 seconds
Started Aug 09 07:19:13 PM PDT 24
Finished Aug 09 07:20:35 PM PDT 24
Peak memory 199836 kb
Host smart-4002e273-99b4-4ab1-a873-513713dd9241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621393616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1621393616
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1629358453
Short name T31
Test name
Test status
Simulation time 78907145554 ps
CPU time 781.29 seconds
Started Aug 09 07:19:11 PM PDT 24
Finished Aug 09 07:32:12 PM PDT 24
Peak memory 216488 kb
Host smart-8e2b455f-b94e-47ba-9f55-ff40a9bae15c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629358453 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1629358453
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3864314463
Short name T525
Test name
Test status
Simulation time 7760554590 ps
CPU time 15.05 seconds
Started Aug 09 07:19:12 PM PDT 24
Finished Aug 09 07:19:27 PM PDT 24
Peak memory 199996 kb
Host smart-9be0cdff-11fb-4ff1-87af-c576a8bd740f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864314463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3864314463
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3169933219
Short name T636
Test name
Test status
Simulation time 53595812419 ps
CPU time 125.08 seconds
Started Aug 09 07:19:14 PM PDT 24
Finished Aug 09 07:21:19 PM PDT 24
Peak memory 199708 kb
Host smart-cd03d7d7-9448-4221-a4d0-222461fda1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169933219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3169933219
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.4116876091
Short name T477
Test name
Test status
Simulation time 9339365117 ps
CPU time 20.8 seconds
Started Aug 09 07:23:47 PM PDT 24
Finished Aug 09 07:24:08 PM PDT 24
Peak memory 199940 kb
Host smart-f5d87d50-ad70-4f72-9188-6effec959f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116876091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.4116876091
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3960446199
Short name T629
Test name
Test status
Simulation time 55808014711 ps
CPU time 46.9 seconds
Started Aug 09 07:23:49 PM PDT 24
Finished Aug 09 07:24:36 PM PDT 24
Peak memory 199252 kb
Host smart-51d32211-7dd6-48f4-8c1f-e473c45f1dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960446199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3960446199
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.516369488
Short name T116
Test name
Test status
Simulation time 28716833636 ps
CPU time 11.19 seconds
Started Aug 09 07:23:47 PM PDT 24
Finished Aug 09 07:23:59 PM PDT 24
Peak memory 199976 kb
Host smart-428a5117-c9c5-4516-b4c1-19293c9ad025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516369488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.516369488
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.737033646
Short name T946
Test name
Test status
Simulation time 121817303578 ps
CPU time 337.72 seconds
Started Aug 09 07:23:49 PM PDT 24
Finished Aug 09 07:29:26 PM PDT 24
Peak memory 199228 kb
Host smart-a243f863-ad42-44c5-ad59-d4e3cb7260cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737033646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.737033646
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3392681341
Short name T618
Test name
Test status
Simulation time 24018928435 ps
CPU time 41.57 seconds
Started Aug 09 07:23:55 PM PDT 24
Finished Aug 09 07:24:37 PM PDT 24
Peak memory 199368 kb
Host smart-135f139c-1f46-4fc2-b417-4beef4f10495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392681341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3392681341
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.2381679873
Short name T481
Test name
Test status
Simulation time 9827833713 ps
CPU time 4.72 seconds
Started Aug 09 07:23:46 PM PDT 24
Finished Aug 09 07:23:51 PM PDT 24
Peak memory 199968 kb
Host smart-293cb31b-e1ce-4e8d-9092-58790fb8c19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381679873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2381679873
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2013854780
Short name T708
Test name
Test status
Simulation time 21265582263 ps
CPU time 17.78 seconds
Started Aug 09 07:23:47 PM PDT 24
Finished Aug 09 07:24:05 PM PDT 24
Peak memory 199936 kb
Host smart-4f990350-291e-4a10-b52e-9991b93f3f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013854780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2013854780
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.368863474
Short name T490
Test name
Test status
Simulation time 24829630695 ps
CPU time 45.12 seconds
Started Aug 09 07:23:46 PM PDT 24
Finished Aug 09 07:24:32 PM PDT 24
Peak memory 198612 kb
Host smart-b29ce8ff-78a6-499c-bd10-24296c90f76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368863474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.368863474
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2337512713
Short name T885
Test name
Test status
Simulation time 234163615154 ps
CPU time 60 seconds
Started Aug 09 07:23:55 PM PDT 24
Finished Aug 09 07:24:55 PM PDT 24
Peak memory 199892 kb
Host smart-8b613d89-f170-48f0-9bc7-33df07880d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337512713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2337512713
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.55276718
Short name T926
Test name
Test status
Simulation time 14806914012 ps
CPU time 5.83 seconds
Started Aug 09 07:23:47 PM PDT 24
Finished Aug 09 07:23:53 PM PDT 24
Peak memory 197280 kb
Host smart-b55e5f99-e7ef-49e3-9cfb-e7c49401e83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55276718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.55276718
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.880914486
Short name T727
Test name
Test status
Simulation time 20926289 ps
CPU time 0.54 seconds
Started Aug 09 07:19:20 PM PDT 24
Finished Aug 09 07:19:21 PM PDT 24
Peak memory 195336 kb
Host smart-34c90b45-ec73-475b-a064-f944977dd2b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880914486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.880914486
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1112040710
Short name T335
Test name
Test status
Simulation time 150949276344 ps
CPU time 124.71 seconds
Started Aug 09 07:19:28 PM PDT 24
Finished Aug 09 07:21:33 PM PDT 24
Peak memory 199896 kb
Host smart-7545af85-d082-4015-880a-57d28435f065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112040710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1112040710
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2823114419
Short name T736
Test name
Test status
Simulation time 189194512147 ps
CPU time 510.57 seconds
Started Aug 09 07:19:20 PM PDT 24
Finished Aug 09 07:27:51 PM PDT 24
Peak memory 199868 kb
Host smart-1562ab30-7240-4b10-b26b-7a9f1c807d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823114419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2823114419
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1955658552
Short name T1178
Test name
Test status
Simulation time 31378504715 ps
CPU time 12.88 seconds
Started Aug 09 07:19:21 PM PDT 24
Finished Aug 09 07:19:34 PM PDT 24
Peak memory 199848 kb
Host smart-f2fe3ecc-ef66-4111-a84d-b4a9ebe3b0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955658552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1955658552
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3574419294
Short name T317
Test name
Test status
Simulation time 13127401537 ps
CPU time 5.96 seconds
Started Aug 09 07:19:18 PM PDT 24
Finished Aug 09 07:19:24 PM PDT 24
Peak memory 196760 kb
Host smart-de905117-0ae1-47de-aa8f-a34e10ab154e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574419294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3574419294
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.838146870
Short name T575
Test name
Test status
Simulation time 95193038588 ps
CPU time 202.41 seconds
Started Aug 09 07:19:29 PM PDT 24
Finished Aug 09 07:22:52 PM PDT 24
Peak memory 199916 kb
Host smart-7bea1373-0b78-4f67-9662-0a6e8e4bd590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=838146870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.838146870
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3042121660
Short name T984
Test name
Test status
Simulation time 7747544799 ps
CPU time 20.35 seconds
Started Aug 09 07:19:18 PM PDT 24
Finished Aug 09 07:19:39 PM PDT 24
Peak memory 198388 kb
Host smart-ab195004-54c2-45f0-9f3c-97f5de44bb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042121660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3042121660
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.987432223
Short name T1125
Test name
Test status
Simulation time 64768576241 ps
CPU time 26.3 seconds
Started Aug 09 07:19:21 PM PDT 24
Finished Aug 09 07:19:47 PM PDT 24
Peak memory 199732 kb
Host smart-b3aed606-31eb-456d-a635-b48afa71967e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987432223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.987432223
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.1117555482
Short name T289
Test name
Test status
Simulation time 13694572081 ps
CPU time 800.33 seconds
Started Aug 09 07:19:28 PM PDT 24
Finished Aug 09 07:32:49 PM PDT 24
Peak memory 199976 kb
Host smart-2b931255-0fbe-4b3d-8d0a-563cc8d5c6af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1117555482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1117555482
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2708712286
Short name T1116
Test name
Test status
Simulation time 4299394429 ps
CPU time 26.81 seconds
Started Aug 09 07:19:20 PM PDT 24
Finished Aug 09 07:19:46 PM PDT 24
Peak memory 198140 kb
Host smart-fb098942-9493-44e0-b383-ad6c773abd9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2708712286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2708712286
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1966289541
Short name T935
Test name
Test status
Simulation time 28637311388 ps
CPU time 11.84 seconds
Started Aug 09 07:19:23 PM PDT 24
Finished Aug 09 07:19:36 PM PDT 24
Peak memory 199940 kb
Host smart-b4541a3d-8cab-4654-8d31-1399e5c860ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966289541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1966289541
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2378001803
Short name T390
Test name
Test status
Simulation time 1843416444 ps
CPU time 1.12 seconds
Started Aug 09 07:19:28 PM PDT 24
Finished Aug 09 07:19:29 PM PDT 24
Peak memory 195648 kb
Host smart-8b277c62-7f4b-4518-ba75-9ff0d54e70bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378001803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2378001803
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.212521715
Short name T511
Test name
Test status
Simulation time 6253809422 ps
CPU time 7.4 seconds
Started Aug 09 07:19:24 PM PDT 24
Finished Aug 09 07:19:31 PM PDT 24
Peak memory 199808 kb
Host smart-3ff2650a-a310-4cbc-bc6f-1627c717f329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212521715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.212521715
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2585760681
Short name T802
Test name
Test status
Simulation time 39201056582 ps
CPU time 412.02 seconds
Started Aug 09 07:19:25 PM PDT 24
Finished Aug 09 07:26:17 PM PDT 24
Peak memory 216468 kb
Host smart-9f9f2c2b-211d-4da3-b8af-06aa7785fc15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585760681 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2585760681
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.608836593
Short name T1049
Test name
Test status
Simulation time 1526046662 ps
CPU time 1.85 seconds
Started Aug 09 07:19:24 PM PDT 24
Finished Aug 09 07:19:26 PM PDT 24
Peak memory 199736 kb
Host smart-08fe987a-6065-4ca7-8635-78ab18aa36bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608836593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.608836593
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.429520763
Short name T752
Test name
Test status
Simulation time 49178177423 ps
CPU time 28.51 seconds
Started Aug 09 07:19:20 PM PDT 24
Finished Aug 09 07:19:49 PM PDT 24
Peak memory 199952 kb
Host smart-2d52f20b-da98-44c2-baa5-b4f3b0261795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429520763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.429520763
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2438056872
Short name T738
Test name
Test status
Simulation time 14490089976 ps
CPU time 25.42 seconds
Started Aug 09 07:23:46 PM PDT 24
Finished Aug 09 07:24:11 PM PDT 24
Peak memory 199964 kb
Host smart-383c6dde-1730-4050-9c5c-7869365d3a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438056872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2438056872
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1045071985
Short name T996
Test name
Test status
Simulation time 101658369090 ps
CPU time 26.79 seconds
Started Aug 09 07:23:55 PM PDT 24
Finished Aug 09 07:24:22 PM PDT 24
Peak memory 199956 kb
Host smart-59c0d06f-84bf-455e-8a44-ccd65e53d27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045071985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1045071985
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1880420382
Short name T93
Test name
Test status
Simulation time 96084016276 ps
CPU time 44.55 seconds
Started Aug 09 07:23:47 PM PDT 24
Finished Aug 09 07:24:32 PM PDT 24
Peak memory 199528 kb
Host smart-d88fadc3-80b8-4bdb-adbb-1b7a3bde64aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880420382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1880420382
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3479395110
Short name T496
Test name
Test status
Simulation time 94147593853 ps
CPU time 64.34 seconds
Started Aug 09 07:23:56 PM PDT 24
Finished Aug 09 07:25:00 PM PDT 24
Peak memory 199848 kb
Host smart-dd19ccc9-652e-4d5f-90fb-a9a5111a1ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479395110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3479395110
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.949926553
Short name T980
Test name
Test status
Simulation time 16859117388 ps
CPU time 26.98 seconds
Started Aug 09 07:23:55 PM PDT 24
Finished Aug 09 07:24:22 PM PDT 24
Peak memory 198656 kb
Host smart-cfda69be-90ea-4183-8998-ee837df188b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949926553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.949926553
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.301234616
Short name T818
Test name
Test status
Simulation time 117657154369 ps
CPU time 185.92 seconds
Started Aug 09 07:23:58 PM PDT 24
Finished Aug 09 07:27:04 PM PDT 24
Peak memory 199960 kb
Host smart-ca253158-0443-45f0-90f6-aaa1e5b833f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301234616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.301234616
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1418420860
Short name T832
Test name
Test status
Simulation time 13139234482 ps
CPU time 22.09 seconds
Started Aug 09 07:23:56 PM PDT 24
Finished Aug 09 07:24:19 PM PDT 24
Peak memory 199800 kb
Host smart-8dfd5545-4dc7-440e-b675-71c6415d1797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418420860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1418420860
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.110448823
Short name T665
Test name
Test status
Simulation time 28346537594 ps
CPU time 25.3 seconds
Started Aug 09 07:23:58 PM PDT 24
Finished Aug 09 07:24:23 PM PDT 24
Peak memory 199900 kb
Host smart-1615af8b-7f05-42fa-ba39-69584fca1363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110448823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.110448823
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1423112126
Short name T948
Test name
Test status
Simulation time 45458225340 ps
CPU time 66.53 seconds
Started Aug 09 07:23:56 PM PDT 24
Finished Aug 09 07:25:03 PM PDT 24
Peak memory 198676 kb
Host smart-44508b45-a78a-4c05-95dd-7b40cdbdd97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423112126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1423112126
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1136142755
Short name T974
Test name
Test status
Simulation time 44946225 ps
CPU time 0.56 seconds
Started Aug 09 07:19:24 PM PDT 24
Finished Aug 09 07:19:24 PM PDT 24
Peak memory 194984 kb
Host smart-db57d813-8c3e-4b24-8f29-814182dd1aa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136142755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1136142755
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3999131426
Short name T429
Test name
Test status
Simulation time 81718911402 ps
CPU time 21.63 seconds
Started Aug 09 07:19:23 PM PDT 24
Finished Aug 09 07:19:45 PM PDT 24
Peak memory 199944 kb
Host smart-838cd0bf-d953-46f1-842c-efb14a7f725c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999131426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3999131426
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2010398117
Short name T520
Test name
Test status
Simulation time 96531599072 ps
CPU time 38.06 seconds
Started Aug 09 07:19:24 PM PDT 24
Finished Aug 09 07:20:02 PM PDT 24
Peak memory 199900 kb
Host smart-cd1e634f-e5cd-4097-b426-82f2bec57598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010398117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2010398117
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1128093669
Short name T248
Test name
Test status
Simulation time 23440537057 ps
CPU time 38.78 seconds
Started Aug 09 07:19:23 PM PDT 24
Finished Aug 09 07:20:02 PM PDT 24
Peak memory 199952 kb
Host smart-3d51d205-03d3-4ce4-ac2d-7bb8c7ca890c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128093669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1128093669
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1837123715
Short name T1110
Test name
Test status
Simulation time 20303275655 ps
CPU time 6.38 seconds
Started Aug 09 07:19:19 PM PDT 24
Finished Aug 09 07:19:25 PM PDT 24
Peak memory 198788 kb
Host smart-037e3a33-036f-41ab-ad26-64630fe5d233
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837123715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1837123715
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3777834103
Short name T1181
Test name
Test status
Simulation time 117199569668 ps
CPU time 213.1 seconds
Started Aug 09 07:19:18 PM PDT 24
Finished Aug 09 07:22:52 PM PDT 24
Peak memory 199960 kb
Host smart-aa112022-57fd-4f4f-bdb2-e2aa10d7d0df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3777834103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3777834103
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2241374228
Short name T517
Test name
Test status
Simulation time 10013796373 ps
CPU time 19.8 seconds
Started Aug 09 07:19:23 PM PDT 24
Finished Aug 09 07:19:43 PM PDT 24
Peak memory 199212 kb
Host smart-2981b086-0619-4e6e-a4c4-dbd0ba7fafed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241374228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2241374228
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3126749601
Short name T41
Test name
Test status
Simulation time 75657363006 ps
CPU time 32.02 seconds
Started Aug 09 07:19:17 PM PDT 24
Finished Aug 09 07:19:49 PM PDT 24
Peak memory 199800 kb
Host smart-92a2438b-3274-4790-a6ee-cfe6f5a4b10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126749601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3126749601
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.778795752
Short name T266
Test name
Test status
Simulation time 17359542717 ps
CPU time 696.41 seconds
Started Aug 09 07:19:18 PM PDT 24
Finished Aug 09 07:30:54 PM PDT 24
Peak memory 199912 kb
Host smart-80b3d5e8-7066-4458-ad68-3074ed305322
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=778795752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.778795752
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2556432177
Short name T968
Test name
Test status
Simulation time 2124832054 ps
CPU time 5.1 seconds
Started Aug 09 07:19:25 PM PDT 24
Finished Aug 09 07:19:30 PM PDT 24
Peak memory 197868 kb
Host smart-ed18b009-530c-48ad-a5ec-2b0c39dba972
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2556432177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2556432177
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2831273302
Short name T457
Test name
Test status
Simulation time 80839362207 ps
CPU time 115.06 seconds
Started Aug 09 07:19:21 PM PDT 24
Finished Aug 09 07:21:16 PM PDT 24
Peak memory 199948 kb
Host smart-444308c4-a051-43a6-9ec0-aba1d8459772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831273302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2831273302
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.2214987281
Short name T1079
Test name
Test status
Simulation time 734126235 ps
CPU time 1.22 seconds
Started Aug 09 07:19:19 PM PDT 24
Finished Aug 09 07:19:21 PM PDT 24
Peak memory 195448 kb
Host smart-3bbdc6de-8b74-4688-8ce4-dcb3c5849461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214987281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2214987281
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.2094411390
Short name T293
Test name
Test status
Simulation time 687631431 ps
CPU time 3.94 seconds
Started Aug 09 07:19:20 PM PDT 24
Finished Aug 09 07:19:24 PM PDT 24
Peak memory 199836 kb
Host smart-b999abfb-cc7a-40bc-9e26-984fd00eee35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094411390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2094411390
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2948284913
Short name T892
Test name
Test status
Simulation time 166258215022 ps
CPU time 93.4 seconds
Started Aug 09 07:19:23 PM PDT 24
Finished Aug 09 07:20:57 PM PDT 24
Peak memory 199948 kb
Host smart-1000885e-40ff-4a31-a8e5-bdbe2d72548b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948284913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2948284913
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.115879623
Short name T504
Test name
Test status
Simulation time 91890314040 ps
CPU time 1113.7 seconds
Started Aug 09 07:19:18 PM PDT 24
Finished Aug 09 07:37:52 PM PDT 24
Peak memory 227152 kb
Host smart-f1dae380-e46a-4656-bfd9-bc564140d330
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115879623 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.115879623
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1058395322
Short name T1107
Test name
Test status
Simulation time 7831130744 ps
CPU time 14.68 seconds
Started Aug 09 07:19:29 PM PDT 24
Finished Aug 09 07:19:44 PM PDT 24
Peak memory 199704 kb
Host smart-b3fec889-6210-4aca-ae99-f04cc0cf9c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058395322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1058395322
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1784487203
Short name T1117
Test name
Test status
Simulation time 25565915299 ps
CPU time 44.07 seconds
Started Aug 09 07:19:20 PM PDT 24
Finished Aug 09 07:20:05 PM PDT 24
Peak memory 199956 kb
Host smart-94955487-1c41-4eba-8305-c96c1838e076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784487203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1784487203
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.4138332331
Short name T322
Test name
Test status
Simulation time 47835126187 ps
CPU time 32.64 seconds
Started Aug 09 07:23:58 PM PDT 24
Finished Aug 09 07:24:31 PM PDT 24
Peak memory 199992 kb
Host smart-3fac5795-a0e4-48e0-80b1-6baf893a7ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138332331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.4138332331
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.964544596
Short name T850
Test name
Test status
Simulation time 28329676394 ps
CPU time 11.98 seconds
Started Aug 09 07:23:56 PM PDT 24
Finished Aug 09 07:24:08 PM PDT 24
Peak memory 199772 kb
Host smart-4b95a9b7-2ab2-427c-aa4c-bec78ad8564e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964544596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.964544596
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1071841121
Short name T500
Test name
Test status
Simulation time 24606983213 ps
CPU time 41.3 seconds
Started Aug 09 07:23:56 PM PDT 24
Finished Aug 09 07:24:37 PM PDT 24
Peak memory 199836 kb
Host smart-c1f74039-3ba9-4d10-a0d5-770c959fecc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071841121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1071841121
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2805207767
Short name T579
Test name
Test status
Simulation time 82113203108 ps
CPU time 24.81 seconds
Started Aug 09 07:23:55 PM PDT 24
Finished Aug 09 07:24:20 PM PDT 24
Peak memory 199856 kb
Host smart-56577595-e90d-4872-8fa7-a7db1458120b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805207767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2805207767
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2828767245
Short name T1007
Test name
Test status
Simulation time 96688146834 ps
CPU time 227.85 seconds
Started Aug 09 07:23:56 PM PDT 24
Finished Aug 09 07:27:44 PM PDT 24
Peak memory 199968 kb
Host smart-0d12f053-8358-4b9e-860d-35c30cd13e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828767245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2828767245
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3130872184
Short name T1065
Test name
Test status
Simulation time 30464810769 ps
CPU time 53.36 seconds
Started Aug 09 07:23:55 PM PDT 24
Finished Aug 09 07:24:49 PM PDT 24
Peak memory 199960 kb
Host smart-b4371b5a-1623-4ee6-ae0f-b73ab2be4a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130872184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3130872184
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.983056908
Short name T967
Test name
Test status
Simulation time 36913552909 ps
CPU time 59.07 seconds
Started Aug 09 07:23:56 PM PDT 24
Finished Aug 09 07:24:55 PM PDT 24
Peak memory 199924 kb
Host smart-056e17b4-f53f-4dcf-b7b5-38234ba9d8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983056908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.983056908
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2625612211
Short name T40
Test name
Test status
Simulation time 26756855041 ps
CPU time 14.05 seconds
Started Aug 09 07:23:57 PM PDT 24
Finished Aug 09 07:24:11 PM PDT 24
Peak memory 199972 kb
Host smart-7eebdaf8-581f-49c2-ade3-9f9f2962fe11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625612211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2625612211
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3471687270
Short name T437
Test name
Test status
Simulation time 32698057 ps
CPU time 0.57 seconds
Started Aug 09 07:19:27 PM PDT 24
Finished Aug 09 07:19:28 PM PDT 24
Peak memory 195356 kb
Host smart-4d14ec83-9355-4c6c-ab64-7202682efca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471687270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3471687270
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.805783553
Short name T973
Test name
Test status
Simulation time 53984600088 ps
CPU time 11.17 seconds
Started Aug 09 07:19:23 PM PDT 24
Finished Aug 09 07:19:34 PM PDT 24
Peak memory 199768 kb
Host smart-a2412ae1-23f4-4e50-bf3e-5299f85fa1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805783553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.805783553
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.208824511
Short name T131
Test name
Test status
Simulation time 98296940189 ps
CPU time 38.79 seconds
Started Aug 09 07:19:29 PM PDT 24
Finished Aug 09 07:20:08 PM PDT 24
Peak memory 199968 kb
Host smart-c6ddf2cd-12ae-463f-834f-a642c3f35447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208824511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.208824511
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2434282283
Short name T994
Test name
Test status
Simulation time 30821955713 ps
CPU time 40.89 seconds
Started Aug 09 07:19:23 PM PDT 24
Finished Aug 09 07:20:05 PM PDT 24
Peak memory 199892 kb
Host smart-5165d504-9037-42e8-a980-14445deb2b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434282283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2434282283
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.3054041586
Short name T381
Test name
Test status
Simulation time 89127098568 ps
CPU time 30.16 seconds
Started Aug 09 07:19:29 PM PDT 24
Finished Aug 09 07:19:59 PM PDT 24
Peak memory 199476 kb
Host smart-7a40b232-1a5a-474b-be6a-215ed6577f68
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054041586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3054041586
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3714050086
Short name T788
Test name
Test status
Simulation time 88826801379 ps
CPU time 268.31 seconds
Started Aug 09 07:19:27 PM PDT 24
Finished Aug 09 07:23:56 PM PDT 24
Peak memory 199924 kb
Host smart-d1606aa6-537c-4eac-b99e-61218cb757ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3714050086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3714050086
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2666249031
Short name T342
Test name
Test status
Simulation time 6599809433 ps
CPU time 11.22 seconds
Started Aug 09 07:19:34 PM PDT 24
Finished Aug 09 07:19:45 PM PDT 24
Peak memory 199876 kb
Host smart-8670392d-9540-45aa-b0e3-84bf0c2949cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666249031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2666249031
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.2648231116
Short name T1061
Test name
Test status
Simulation time 102372366069 ps
CPU time 23.68 seconds
Started Aug 09 07:19:27 PM PDT 24
Finished Aug 09 07:19:50 PM PDT 24
Peak memory 208224 kb
Host smart-71fedad2-bdb8-4582-af4d-1fc9ea192cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648231116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2648231116
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2795257979
Short name T1088
Test name
Test status
Simulation time 20263347981 ps
CPU time 281.93 seconds
Started Aug 09 07:19:27 PM PDT 24
Finished Aug 09 07:24:09 PM PDT 24
Peak memory 199948 kb
Host smart-25a48a0a-8395-4ca6-b63e-7ffe83749b93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2795257979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2795257979
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.405276217
Short name T109
Test name
Test status
Simulation time 2146314763 ps
CPU time 3.01 seconds
Started Aug 09 07:19:28 PM PDT 24
Finished Aug 09 07:19:31 PM PDT 24
Peak memory 198592 kb
Host smart-db21914c-9651-4fab-a73f-248e363c2051
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405276217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.405276217
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.1847841680
Short name T709
Test name
Test status
Simulation time 4788829120 ps
CPU time 2.52 seconds
Started Aug 09 07:19:27 PM PDT 24
Finished Aug 09 07:19:30 PM PDT 24
Peak memory 196740 kb
Host smart-4badfb61-4d92-482d-9da1-f35483bc0be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847841680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1847841680
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2187633842
Short name T1094
Test name
Test status
Simulation time 734974102 ps
CPU time 3 seconds
Started Aug 09 07:19:20 PM PDT 24
Finished Aug 09 07:19:23 PM PDT 24
Peak memory 199692 kb
Host smart-360fd5cd-653a-4b29-bef6-1da5ee58339d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187633842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2187633842
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.4128601088
Short name T981
Test name
Test status
Simulation time 347350002665 ps
CPU time 588.78 seconds
Started Aug 09 07:19:27 PM PDT 24
Finished Aug 09 07:29:16 PM PDT 24
Peak memory 199920 kb
Host smart-0a36a5d4-c2ea-4bd4-8ec8-53e461fdf98a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128601088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.4128601088
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.667537819
Short name T6
Test name
Test status
Simulation time 16559909903 ps
CPU time 641.5 seconds
Started Aug 09 07:19:29 PM PDT 24
Finished Aug 09 07:30:11 PM PDT 24
Peak memory 216172 kb
Host smart-162cde11-525d-497f-981b-08a3db6f1789
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667537819 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.667537819
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1081877539
Short name T448
Test name
Test status
Simulation time 328418142 ps
CPU time 1.53 seconds
Started Aug 09 07:19:29 PM PDT 24
Finished Aug 09 07:19:31 PM PDT 24
Peak memory 198604 kb
Host smart-ccf144a6-149f-43ba-b34f-b320f63427e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081877539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1081877539
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.4134456132
Short name T799
Test name
Test status
Simulation time 13872694304 ps
CPU time 10.67 seconds
Started Aug 09 07:19:20 PM PDT 24
Finished Aug 09 07:19:31 PM PDT 24
Peak memory 199988 kb
Host smart-93107258-8822-4f34-851c-673182647df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134456132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.4134456132
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.4157945719
Short name T1099
Test name
Test status
Simulation time 23058843518 ps
CPU time 16.04 seconds
Started Aug 09 07:23:56 PM PDT 24
Finished Aug 09 07:24:12 PM PDT 24
Peak memory 199552 kb
Host smart-d7608d15-89ac-40ba-ae4b-21c0a7ad8143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157945719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.4157945719
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1557615436
Short name T450
Test name
Test status
Simulation time 27659753154 ps
CPU time 27.7 seconds
Started Aug 09 07:24:06 PM PDT 24
Finished Aug 09 07:24:34 PM PDT 24
Peak memory 199920 kb
Host smart-8ebb07d1-2a2c-4892-accf-43f54bcf34af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557615436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1557615436
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.180750763
Short name T1078
Test name
Test status
Simulation time 109456387098 ps
CPU time 74.36 seconds
Started Aug 09 07:24:03 PM PDT 24
Finished Aug 09 07:25:17 PM PDT 24
Peak memory 199904 kb
Host smart-4b1d9cfb-2368-4020-b889-7413a25f8506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180750763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.180750763
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.1285074590
Short name T12
Test name
Test status
Simulation time 113352761509 ps
CPU time 85.94 seconds
Started Aug 09 07:24:05 PM PDT 24
Finished Aug 09 07:25:31 PM PDT 24
Peak memory 199924 kb
Host smart-ecda2761-422c-4089-b5fa-46ecad823c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285074590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1285074590
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1401850365
Short name T96
Test name
Test status
Simulation time 27886710232 ps
CPU time 43.84 seconds
Started Aug 09 07:24:05 PM PDT 24
Finished Aug 09 07:24:49 PM PDT 24
Peak memory 199924 kb
Host smart-39bbb693-783f-4013-81ab-4adadfab8dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401850365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1401850365
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2446942565
Short name T1005
Test name
Test status
Simulation time 130354942585 ps
CPU time 102.52 seconds
Started Aug 09 07:24:03 PM PDT 24
Finished Aug 09 07:25:45 PM PDT 24
Peak memory 199952 kb
Host smart-b250fd09-3ce0-41f3-a7b4-589376c7afd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446942565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2446942565
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3248086274
Short name T728
Test name
Test status
Simulation time 67003567212 ps
CPU time 13.86 seconds
Started Aug 09 07:24:02 PM PDT 24
Finished Aug 09 07:24:16 PM PDT 24
Peak memory 199952 kb
Host smart-ff605d4e-fff1-4525-9e96-986768509842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248086274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3248086274
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.4068113124
Short name T134
Test name
Test status
Simulation time 34612255766 ps
CPU time 28.13 seconds
Started Aug 09 07:24:05 PM PDT 24
Finished Aug 09 07:24:33 PM PDT 24
Peak memory 199628 kb
Host smart-69145443-1a4d-400c-8cf4-75f189613fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068113124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.4068113124
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3647375821
Short name T766
Test name
Test status
Simulation time 182622469 ps
CPU time 0.53 seconds
Started Aug 09 07:19:36 PM PDT 24
Finished Aug 09 07:19:36 PM PDT 24
Peak memory 195264 kb
Host smart-a497d49b-4441-47d6-abb7-33570c0eff50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647375821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3647375821
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.614177179
Short name T1000
Test name
Test status
Simulation time 89534578943 ps
CPU time 43.22 seconds
Started Aug 09 07:19:28 PM PDT 24
Finished Aug 09 07:20:11 PM PDT 24
Peak memory 199892 kb
Host smart-63aaf966-603c-44f7-979b-1c5dc98a0fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614177179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.614177179
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3145806340
Short name T927
Test name
Test status
Simulation time 89598508573 ps
CPU time 129.69 seconds
Started Aug 09 07:19:26 PM PDT 24
Finished Aug 09 07:21:36 PM PDT 24
Peak memory 199944 kb
Host smart-edf3af48-4235-4abf-b455-a10e1b60454a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145806340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3145806340
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1325684548
Short name T631
Test name
Test status
Simulation time 27262056974 ps
CPU time 42.58 seconds
Started Aug 09 07:19:28 PM PDT 24
Finished Aug 09 07:20:11 PM PDT 24
Peak memory 199936 kb
Host smart-4c9bb126-c902-4915-b161-a027f1fcd020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325684548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1325684548
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2349626308
Short name T325
Test name
Test status
Simulation time 37537903237 ps
CPU time 16.63 seconds
Started Aug 09 07:19:29 PM PDT 24
Finished Aug 09 07:19:45 PM PDT 24
Peak memory 199944 kb
Host smart-7d97ccaf-63cd-4fba-98bb-45de8e6714ed
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349626308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2349626308
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2215140129
Short name T389
Test name
Test status
Simulation time 120616242115 ps
CPU time 254.12 seconds
Started Aug 09 07:19:27 PM PDT 24
Finished Aug 09 07:23:41 PM PDT 24
Peak memory 199976 kb
Host smart-362ac9ea-4b95-43ac-9c02-71d02ff76eea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2215140129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2215140129
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3599060857
Short name T1120
Test name
Test status
Simulation time 7279222458 ps
CPU time 13.99 seconds
Started Aug 09 07:19:28 PM PDT 24
Finished Aug 09 07:19:43 PM PDT 24
Peak memory 199584 kb
Host smart-573049fa-1994-4786-9776-95a49c7aba0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599060857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3599060857
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.3927862179
Short name T662
Test name
Test status
Simulation time 85118507778 ps
CPU time 70.05 seconds
Started Aug 09 07:19:29 PM PDT 24
Finished Aug 09 07:20:39 PM PDT 24
Peak memory 200084 kb
Host smart-c60d5fb4-fe3c-475e-887b-891a384c0774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927862179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3927862179
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.351251203
Short name T972
Test name
Test status
Simulation time 5829236183 ps
CPU time 84.04 seconds
Started Aug 09 07:19:30 PM PDT 24
Finished Aug 09 07:20:54 PM PDT 24
Peak memory 199972 kb
Host smart-eb1248dd-2328-49ec-94a6-876cfe2ba82c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=351251203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.351251203
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2660250840
Short name T1044
Test name
Test status
Simulation time 6613618511 ps
CPU time 10.94 seconds
Started Aug 09 07:19:29 PM PDT 24
Finished Aug 09 07:19:40 PM PDT 24
Peak memory 198132 kb
Host smart-8e91d7f1-8df9-4ab4-9eff-00c76b545cca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2660250840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2660250840
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.4281941434
Short name T378
Test name
Test status
Simulation time 13340881905 ps
CPU time 21.93 seconds
Started Aug 09 07:19:29 PM PDT 24
Finished Aug 09 07:19:51 PM PDT 24
Peak memory 199836 kb
Host smart-f55681f8-0bd4-41e7-a3dd-e3af9d7c7115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281941434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.4281941434
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1987285472
Short name T794
Test name
Test status
Simulation time 27220967693 ps
CPU time 10.76 seconds
Started Aug 09 07:19:27 PM PDT 24
Finished Aug 09 07:19:38 PM PDT 24
Peak memory 195884 kb
Host smart-809459a3-1f03-481c-ad09-1a73268d476c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987285472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1987285472
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1750437011
Short name T933
Test name
Test status
Simulation time 547233508 ps
CPU time 2.27 seconds
Started Aug 09 07:19:30 PM PDT 24
Finished Aug 09 07:19:32 PM PDT 24
Peak memory 198856 kb
Host smart-52e4040b-32b1-431a-9e02-24d5fd12f008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750437011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1750437011
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.3029691627
Short name T943
Test name
Test status
Simulation time 236231763724 ps
CPU time 245.16 seconds
Started Aug 09 07:19:35 PM PDT 24
Finished Aug 09 07:23:40 PM PDT 24
Peak memory 199888 kb
Host smart-8f9cf1db-15d8-4f86-9280-38681bdfa8e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029691627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3029691627
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2782645299
Short name T1018
Test name
Test status
Simulation time 66721013307 ps
CPU time 1043.13 seconds
Started Aug 09 07:19:36 PM PDT 24
Finished Aug 09 07:36:59 PM PDT 24
Peak memory 216604 kb
Host smart-5c93102b-9920-4d39-9564-78af6499b930
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782645299 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2782645299
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1665676664
Short name T1020
Test name
Test status
Simulation time 7930765902 ps
CPU time 11.4 seconds
Started Aug 09 07:19:25 PM PDT 24
Finished Aug 09 07:19:37 PM PDT 24
Peak memory 199284 kb
Host smart-c86d2c9a-8361-413e-8dca-baaa5ed7f9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665676664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1665676664
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.4080144841
Short name T741
Test name
Test status
Simulation time 151680809633 ps
CPU time 100.21 seconds
Started Aug 09 07:19:30 PM PDT 24
Finished Aug 09 07:21:10 PM PDT 24
Peak memory 199976 kb
Host smart-23dcc1ac-c6c4-422d-801f-c4924603bab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080144841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.4080144841
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.4000840214
Short name T399
Test name
Test status
Simulation time 212493407390 ps
CPU time 52.96 seconds
Started Aug 09 07:24:03 PM PDT 24
Finished Aug 09 07:24:56 PM PDT 24
Peak memory 199888 kb
Host smart-ab9d23e1-0746-4e3a-9e3b-fc399eff3325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000840214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.4000840214
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3069374365
Short name T207
Test name
Test status
Simulation time 34816052674 ps
CPU time 53.97 seconds
Started Aug 09 07:24:04 PM PDT 24
Finished Aug 09 07:24:59 PM PDT 24
Peak memory 199896 kb
Host smart-08a2697e-8b85-442c-807e-600d0e8c401b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069374365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3069374365
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2983277417
Short name T666
Test name
Test status
Simulation time 175074035883 ps
CPU time 109.62 seconds
Started Aug 09 07:24:04 PM PDT 24
Finished Aug 09 07:25:54 PM PDT 24
Peak memory 199984 kb
Host smart-aba3849c-cec0-42b7-88f2-6bfdade86f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983277417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2983277417
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3903272160
Short name T1135
Test name
Test status
Simulation time 48387185307 ps
CPU time 46.55 seconds
Started Aug 09 07:24:05 PM PDT 24
Finished Aug 09 07:24:51 PM PDT 24
Peak memory 199988 kb
Host smart-88fa0975-ff20-42fb-a486-d06539aeeeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903272160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3903272160
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1555462259
Short name T548
Test name
Test status
Simulation time 21236029062 ps
CPU time 10.83 seconds
Started Aug 09 07:24:06 PM PDT 24
Finished Aug 09 07:24:17 PM PDT 24
Peak memory 199968 kb
Host smart-4e800fe9-54c2-4030-a82d-f13e28df0896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555462259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1555462259
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3844006293
Short name T979
Test name
Test status
Simulation time 69868774105 ps
CPU time 63.91 seconds
Started Aug 09 07:24:04 PM PDT 24
Finished Aug 09 07:25:08 PM PDT 24
Peak memory 199892 kb
Host smart-48ba9713-387e-4f5c-8853-dca39ef1b548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844006293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3844006293
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.578947365
Short name T302
Test name
Test status
Simulation time 190683593212 ps
CPU time 37.6 seconds
Started Aug 09 07:24:03 PM PDT 24
Finished Aug 09 07:24:41 PM PDT 24
Peak memory 199980 kb
Host smart-087b9901-ad9a-438b-a102-0c4e51cd9551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578947365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.578947365
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.100134633
Short name T906
Test name
Test status
Simulation time 44511546921 ps
CPU time 14.28 seconds
Started Aug 09 07:24:12 PM PDT 24
Finished Aug 09 07:24:26 PM PDT 24
Peak memory 199892 kb
Host smart-7a642e11-bb2b-43b0-954b-b418bec86535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100134633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.100134633
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.33754570
Short name T110
Test name
Test status
Simulation time 84569542320 ps
CPU time 115.29 seconds
Started Aug 09 07:24:10 PM PDT 24
Finished Aug 09 07:26:06 PM PDT 24
Peak memory 199896 kb
Host smart-655bcf20-6a61-4bb1-9cab-750af3cd4097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33754570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.33754570
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.4289158846
Short name T64
Test name
Test status
Simulation time 12983597 ps
CPU time 0.6 seconds
Started Aug 09 07:19:39 PM PDT 24
Finished Aug 09 07:19:40 PM PDT 24
Peak memory 194800 kb
Host smart-4bd9282d-c1c8-4ce7-91f2-7262f5027aac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289158846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.4289158846
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1998745474
Short name T124
Test name
Test status
Simulation time 23681425143 ps
CPU time 38.09 seconds
Started Aug 09 07:19:37 PM PDT 24
Finished Aug 09 07:20:15 PM PDT 24
Peak memory 199948 kb
Host smart-a0fc3b8e-d607-4ec5-a3b5-6432dd923fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998745474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1998745474
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1077061700
Short name T392
Test name
Test status
Simulation time 38601087225 ps
CPU time 29.85 seconds
Started Aug 09 07:19:41 PM PDT 24
Finished Aug 09 07:20:11 PM PDT 24
Peak memory 199508 kb
Host smart-3414c827-d8e3-4f3b-8d36-a7fa37e56a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077061700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1077061700
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.662089052
Short name T781
Test name
Test status
Simulation time 46609922851 ps
CPU time 62.89 seconds
Started Aug 09 07:19:38 PM PDT 24
Finished Aug 09 07:20:41 PM PDT 24
Peak memory 199632 kb
Host smart-a1c7bda9-30b2-41db-b0ab-2b7707db1336
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662089052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.662089052
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3534124523
Short name T453
Test name
Test status
Simulation time 84808545024 ps
CPU time 328.53 seconds
Started Aug 09 07:19:37 PM PDT 24
Finished Aug 09 07:25:05 PM PDT 24
Peak memory 199932 kb
Host smart-e7c19095-7518-441e-8a77-149bd53643e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3534124523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3534124523
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.905071638
Short name T835
Test name
Test status
Simulation time 7011351541 ps
CPU time 9.81 seconds
Started Aug 09 07:19:37 PM PDT 24
Finished Aug 09 07:19:47 PM PDT 24
Peak memory 199708 kb
Host smart-76d16c2f-7cb8-43f6-a7c5-654a4cffb649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905071638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.905071638
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3345862710
Short name T1038
Test name
Test status
Simulation time 37368747376 ps
CPU time 65.43 seconds
Started Aug 09 07:19:41 PM PDT 24
Finished Aug 09 07:20:47 PM PDT 24
Peak memory 207588 kb
Host smart-12cef23e-ad68-43a1-a103-439fa565bfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345862710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3345862710
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.3669142291
Short name T792
Test name
Test status
Simulation time 19278559905 ps
CPU time 1056.3 seconds
Started Aug 09 07:19:36 PM PDT 24
Finished Aug 09 07:37:12 PM PDT 24
Peak memory 199980 kb
Host smart-f25f9f5e-cc6c-4985-9788-8d2f1108eb03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3669142291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3669142291
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2980619203
Short name T776
Test name
Test status
Simulation time 4210640596 ps
CPU time 9.29 seconds
Started Aug 09 07:19:35 PM PDT 24
Finished Aug 09 07:19:45 PM PDT 24
Peak memory 199100 kb
Host smart-c3f15856-2774-4e15-ae38-f4baef783078
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2980619203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2980619203
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2407199846
Short name T550
Test name
Test status
Simulation time 163152627398 ps
CPU time 259.39 seconds
Started Aug 09 07:19:38 PM PDT 24
Finished Aug 09 07:23:58 PM PDT 24
Peak memory 199884 kb
Host smart-5af1b5fb-25b7-4edf-b3ae-4c570b4ef4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407199846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2407199846
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2928680377
Short name T8
Test name
Test status
Simulation time 4724668585 ps
CPU time 2.56 seconds
Started Aug 09 07:19:39 PM PDT 24
Finished Aug 09 07:19:41 PM PDT 24
Peak memory 196108 kb
Host smart-a9b66cff-bfd2-4da0-86b8-ccf4a129efd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928680377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2928680377
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.243063062
Short name T805
Test name
Test status
Simulation time 6221396583 ps
CPU time 9.58 seconds
Started Aug 09 07:19:41 PM PDT 24
Finished Aug 09 07:19:51 PM PDT 24
Peak memory 199296 kb
Host smart-43017740-ef42-4463-967a-732a83e0c20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243063062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.243063062
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.3822783936
Short name T187
Test name
Test status
Simulation time 295210769880 ps
CPU time 417.45 seconds
Started Aug 09 07:19:35 PM PDT 24
Finished Aug 09 07:26:33 PM PDT 24
Peak memory 199992 kb
Host smart-a855bd62-0e7c-4883-b1f5-01906a72d7e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822783936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3822783936
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.3450865134
Short name T650
Test name
Test status
Simulation time 8634107983 ps
CPU time 112.35 seconds
Started Aug 09 07:19:36 PM PDT 24
Finished Aug 09 07:21:28 PM PDT 24
Peak memory 208304 kb
Host smart-c94a83bc-6b06-4f54-a6a0-859b437ea085
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450865134 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.3450865134
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.4258068170
Short name T768
Test name
Test status
Simulation time 6727000618 ps
CPU time 25.37 seconds
Started Aug 09 07:19:35 PM PDT 24
Finished Aug 09 07:20:01 PM PDT 24
Peak memory 199984 kb
Host smart-0d133c87-b927-4d5a-8719-c8a382429954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258068170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.4258068170
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.4209024673
Short name T936
Test name
Test status
Simulation time 98625627236 ps
CPU time 35.98 seconds
Started Aug 09 07:19:40 PM PDT 24
Finished Aug 09 07:20:16 PM PDT 24
Peak memory 199964 kb
Host smart-82225f21-fc7b-424b-9413-0f6a2b36b870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209024673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.4209024673
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.394545723
Short name T688
Test name
Test status
Simulation time 89220020677 ps
CPU time 99.65 seconds
Started Aug 09 07:24:14 PM PDT 24
Finished Aug 09 07:25:54 PM PDT 24
Peak memory 200028 kb
Host smart-a333b21f-d2c8-4049-b72b-c0db20b99344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394545723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.394545723
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.319019090
Short name T1092
Test name
Test status
Simulation time 151906994252 ps
CPU time 68.84 seconds
Started Aug 09 07:24:10 PM PDT 24
Finished Aug 09 07:25:19 PM PDT 24
Peak memory 199900 kb
Host smart-84f32a4f-a5d3-44f8-8ba7-6392aadc0e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319019090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.319019090
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1231616077
Short name T480
Test name
Test status
Simulation time 133737361202 ps
CPU time 52.54 seconds
Started Aug 09 07:24:10 PM PDT 24
Finished Aug 09 07:25:03 PM PDT 24
Peak memory 199940 kb
Host smart-1d45272d-d8a9-4c8b-8156-a46f9586de6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231616077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1231616077
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1355383272
Short name T44
Test name
Test status
Simulation time 122546345580 ps
CPU time 55.27 seconds
Started Aug 09 07:24:11 PM PDT 24
Finished Aug 09 07:25:07 PM PDT 24
Peak memory 199908 kb
Host smart-03d2ee72-2cb6-4c2c-a5d8-865450317ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355383272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1355383272
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2477561872
Short name T1166
Test name
Test status
Simulation time 342711599417 ps
CPU time 191.18 seconds
Started Aug 09 07:24:13 PM PDT 24
Finished Aug 09 07:27:25 PM PDT 24
Peak memory 200028 kb
Host smart-361f7bfc-7cbc-4f9d-b339-e62f028c108b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477561872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2477561872
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.2955408393
Short name T803
Test name
Test status
Simulation time 75017842554 ps
CPU time 28.09 seconds
Started Aug 09 07:24:10 PM PDT 24
Finished Aug 09 07:24:38 PM PDT 24
Peak memory 199968 kb
Host smart-eb9d19dc-0051-405a-84d3-bc70cf88b941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955408393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2955408393
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3013475468
Short name T791
Test name
Test status
Simulation time 8582903504 ps
CPU time 13.71 seconds
Started Aug 09 07:24:10 PM PDT 24
Finished Aug 09 07:24:24 PM PDT 24
Peak memory 199952 kb
Host smart-11c1b529-27cb-4cf1-bc5a-44188668a088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013475468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3013475468
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.803600431
Short name T606
Test name
Test status
Simulation time 141366170453 ps
CPU time 105.58 seconds
Started Aug 09 07:24:18 PM PDT 24
Finished Aug 09 07:26:04 PM PDT 24
Peak memory 199932 kb
Host smart-13933eaf-c2f8-4d53-aea1-8f22f4105255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803600431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.803600431
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2480413954
Short name T545
Test name
Test status
Simulation time 120559436677 ps
CPU time 89.38 seconds
Started Aug 09 07:24:19 PM PDT 24
Finished Aug 09 07:25:48 PM PDT 24
Peak memory 199960 kb
Host smart-8a41ebed-5edf-4d92-a024-85cc96ae1e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480413954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2480413954
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.620890898
Short name T362
Test name
Test status
Simulation time 16420067 ps
CPU time 0.59 seconds
Started Aug 09 07:19:45 PM PDT 24
Finished Aug 09 07:19:46 PM PDT 24
Peak memory 195544 kb
Host smart-346f6cef-fa0e-4c15-83c9-2a51a220365a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620890898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.620890898
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2192761712
Short name T764
Test name
Test status
Simulation time 34080614104 ps
CPU time 34.03 seconds
Started Aug 09 07:19:49 PM PDT 24
Finished Aug 09 07:20:23 PM PDT 24
Peak memory 199752 kb
Host smart-b2fbe779-aa58-4273-b557-be73507d3ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192761712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2192761712
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2696647598
Short name T592
Test name
Test status
Simulation time 44487566069 ps
CPU time 30.29 seconds
Started Aug 09 07:19:48 PM PDT 24
Finished Aug 09 07:20:19 PM PDT 24
Peak memory 199492 kb
Host smart-d23e5ca7-c5dd-4260-809d-2937e444adb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696647598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2696647598
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3284318752
Short name T912
Test name
Test status
Simulation time 15766732415 ps
CPU time 26.24 seconds
Started Aug 09 07:19:46 PM PDT 24
Finished Aug 09 07:20:12 PM PDT 24
Peak memory 199888 kb
Host smart-7c819924-c529-4274-b47f-304eda725c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284318752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3284318752
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.237154604
Short name T988
Test name
Test status
Simulation time 176224575361 ps
CPU time 60.41 seconds
Started Aug 09 07:19:46 PM PDT 24
Finished Aug 09 07:20:46 PM PDT 24
Peak memory 198128 kb
Host smart-b2ceeb69-aa75-41bd-bac8-a48789958e29
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237154604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.237154604
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3420453430
Short name T375
Test name
Test status
Simulation time 93046504521 ps
CPU time 100.74 seconds
Started Aug 09 07:19:44 PM PDT 24
Finished Aug 09 07:21:25 PM PDT 24
Peak memory 199940 kb
Host smart-4cf5b530-1117-4187-9a9a-f06fe92023e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3420453430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3420453430
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1167992103
Short name T340
Test name
Test status
Simulation time 2536466399 ps
CPU time 6.6 seconds
Started Aug 09 07:19:46 PM PDT 24
Finished Aug 09 07:19:52 PM PDT 24
Peak memory 198696 kb
Host smart-a271b3f7-9ba3-4bd3-8283-3218a3225ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167992103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1167992103
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3663977468
Short name T276
Test name
Test status
Simulation time 120202827046 ps
CPU time 66.68 seconds
Started Aug 09 07:19:47 PM PDT 24
Finished Aug 09 07:20:54 PM PDT 24
Peak memory 200076 kb
Host smart-5ca91ab0-6670-4f49-9876-47540eaf6429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663977468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3663977468
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.4050555347
Short name T359
Test name
Test status
Simulation time 7525062994 ps
CPU time 284.3 seconds
Started Aug 09 07:19:46 PM PDT 24
Finished Aug 09 07:24:31 PM PDT 24
Peak memory 199892 kb
Host smart-6350849b-e0ba-451a-8118-8051785ae645
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4050555347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.4050555347
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3256083930
Short name T1140
Test name
Test status
Simulation time 7510705985 ps
CPU time 29 seconds
Started Aug 09 07:19:48 PM PDT 24
Finished Aug 09 07:20:17 PM PDT 24
Peak memory 198660 kb
Host smart-8137ff1b-91e7-4c9c-9fed-6486f27ab366
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3256083930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3256083930
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.517717938
Short name T567
Test name
Test status
Simulation time 16650613272 ps
CPU time 24.98 seconds
Started Aug 09 07:19:45 PM PDT 24
Finished Aug 09 07:20:10 PM PDT 24
Peak memory 199840 kb
Host smart-503b35ee-0e64-4f61-a320-6c322564fa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517717938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.517717938
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2201280346
Short name T783
Test name
Test status
Simulation time 35116557829 ps
CPU time 25.95 seconds
Started Aug 09 07:19:50 PM PDT 24
Finished Aug 09 07:20:16 PM PDT 24
Peak memory 196320 kb
Host smart-edcd2697-bf70-4024-b7fd-f38d1ad8a8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201280346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2201280346
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2605411468
Short name T584
Test name
Test status
Simulation time 935034891 ps
CPU time 2.13 seconds
Started Aug 09 07:19:36 PM PDT 24
Finished Aug 09 07:19:38 PM PDT 24
Peak memory 198300 kb
Host smart-7320bf31-c116-4224-92a0-33793aab2c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605411468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2605411468
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.188009381
Short name T779
Test name
Test status
Simulation time 152078135150 ps
CPU time 118.74 seconds
Started Aug 09 07:19:47 PM PDT 24
Finished Aug 09 07:21:46 PM PDT 24
Peak memory 199912 kb
Host smart-40fe992c-a471-43c6-b0c9-d334dc9ad721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188009381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.188009381
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.91755131
Short name T509
Test name
Test status
Simulation time 6990238692 ps
CPU time 26.05 seconds
Started Aug 09 07:19:45 PM PDT 24
Finished Aug 09 07:20:11 PM PDT 24
Peak memory 199936 kb
Host smart-8c2ed95d-2cb7-4d12-ba98-bcef5347bfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91755131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.91755131
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1324205697
Short name T1009
Test name
Test status
Simulation time 223711685637 ps
CPU time 98.8 seconds
Started Aug 09 07:19:50 PM PDT 24
Finished Aug 09 07:21:29 PM PDT 24
Peak memory 199988 kb
Host smart-a0f3f5e4-9bda-45c3-9fb7-95ce4234e0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324205697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1324205697
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.513469314
Short name T220
Test name
Test status
Simulation time 106451340014 ps
CPU time 57.74 seconds
Started Aug 09 07:24:19 PM PDT 24
Finished Aug 09 07:25:17 PM PDT 24
Peak memory 199896 kb
Host smart-41a1bb42-9990-4593-a951-68ab3e4bb043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513469314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.513469314
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1634958453
Short name T519
Test name
Test status
Simulation time 34751663459 ps
CPU time 15.01 seconds
Started Aug 09 07:24:21 PM PDT 24
Finished Aug 09 07:24:36 PM PDT 24
Peak memory 200004 kb
Host smart-b0e7c276-7693-4cf6-9f2f-b6e03be0436a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634958453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1634958453
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3850637912
Short name T156
Test name
Test status
Simulation time 189029486520 ps
CPU time 27.38 seconds
Started Aug 09 07:24:19 PM PDT 24
Finished Aug 09 07:24:47 PM PDT 24
Peak memory 199876 kb
Host smart-941f4ca7-1384-47b4-8cad-0a5facf7ca51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850637912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3850637912
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.606833140
Short name T839
Test name
Test status
Simulation time 74331017454 ps
CPU time 134.93 seconds
Started Aug 09 07:24:19 PM PDT 24
Finished Aug 09 07:26:34 PM PDT 24
Peak memory 199980 kb
Host smart-f8d79dbe-c7d2-42c4-900a-84b9b1eb2453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606833140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.606833140
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.4176075358
Short name T191
Test name
Test status
Simulation time 13523985141 ps
CPU time 20 seconds
Started Aug 09 07:24:18 PM PDT 24
Finished Aug 09 07:24:38 PM PDT 24
Peak memory 199968 kb
Host smart-beb851bd-6df1-4b49-93e2-cce62fdaf1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176075358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.4176075358
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2537970931
Short name T733
Test name
Test status
Simulation time 191487097750 ps
CPU time 401.89 seconds
Started Aug 09 07:24:18 PM PDT 24
Finished Aug 09 07:31:00 PM PDT 24
Peak memory 199960 kb
Host smart-ac4af3e5-2f0f-4602-b077-8fec190eab0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537970931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2537970931
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1688066779
Short name T206
Test name
Test status
Simulation time 51144036232 ps
CPU time 68.04 seconds
Started Aug 09 07:24:19 PM PDT 24
Finished Aug 09 07:25:27 PM PDT 24
Peak memory 199984 kb
Host smart-b77c36b7-11e8-4ff2-8e14-aed5ecf83bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688066779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1688066779
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3091132425
Short name T1111
Test name
Test status
Simulation time 36733778312 ps
CPU time 61.08 seconds
Started Aug 09 07:24:20 PM PDT 24
Finished Aug 09 07:25:21 PM PDT 24
Peak memory 199940 kb
Host smart-bff6a096-dcad-43bc-b81d-0fd420a938a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091132425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3091132425
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3018257339
Short name T798
Test name
Test status
Simulation time 55131957338 ps
CPU time 42.03 seconds
Started Aug 09 07:24:18 PM PDT 24
Finished Aug 09 07:25:00 PM PDT 24
Peak memory 199984 kb
Host smart-98948899-5c08-4eba-9608-d2eb1e227678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018257339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3018257339
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1654310060
Short name T343
Test name
Test status
Simulation time 12745103 ps
CPU time 0.58 seconds
Started Aug 09 07:19:50 PM PDT 24
Finished Aug 09 07:19:51 PM PDT 24
Peak memory 195636 kb
Host smart-65686dbc-7133-4f52-b23e-c561ff7ab0bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654310060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1654310060
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1762883830
Short name T970
Test name
Test status
Simulation time 26256177275 ps
CPU time 41.91 seconds
Started Aug 09 07:19:46 PM PDT 24
Finished Aug 09 07:20:27 PM PDT 24
Peak memory 199944 kb
Host smart-47578e0a-b6a7-40ee-a92c-e49160ba16b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762883830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1762883830
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3108696751
Short name T268
Test name
Test status
Simulation time 31161951788 ps
CPU time 13.73 seconds
Started Aug 09 07:19:46 PM PDT 24
Finished Aug 09 07:20:00 PM PDT 24
Peak memory 199496 kb
Host smart-8a29e07b-6bce-4f26-a946-dbce97546b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108696751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3108696751
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2202639855
Short name T1141
Test name
Test status
Simulation time 57491907983 ps
CPU time 75.01 seconds
Started Aug 09 07:19:46 PM PDT 24
Finished Aug 09 07:21:01 PM PDT 24
Peak memory 199988 kb
Host smart-cde21d98-f8ef-43d2-8cb7-5a85c9c1ff32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202639855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2202639855
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.437073916
Short name T547
Test name
Test status
Simulation time 49279965716 ps
CPU time 21.72 seconds
Started Aug 09 07:19:46 PM PDT 24
Finished Aug 09 07:20:08 PM PDT 24
Peak memory 199976 kb
Host smart-2c0d99e3-e3e2-46c6-a9e2-089d4ff663b2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437073916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.437073916
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.512533169
Short name T817
Test name
Test status
Simulation time 56055555033 ps
CPU time 422.69 seconds
Started Aug 09 07:19:49 PM PDT 24
Finished Aug 09 07:26:52 PM PDT 24
Peak memory 199904 kb
Host smart-58ce223b-9834-4013-9de6-48a7c969d755
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=512533169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.512533169
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1555791645
Short name T21
Test name
Test status
Simulation time 2037073167 ps
CPU time 2.22 seconds
Started Aug 09 07:19:44 PM PDT 24
Finished Aug 09 07:19:47 PM PDT 24
Peak memory 196088 kb
Host smart-34d4aa59-7ae5-4a2b-816a-baa8a3dc23a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555791645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1555791645
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1668103252
Short name T852
Test name
Test status
Simulation time 42115861630 ps
CPU time 70.99 seconds
Started Aug 09 07:19:44 PM PDT 24
Finished Aug 09 07:20:55 PM PDT 24
Peak memory 200068 kb
Host smart-1ffcd347-9dfe-4f6a-8c05-9c2af2454a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668103252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1668103252
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.319383065
Short name T369
Test name
Test status
Simulation time 2827541375 ps
CPU time 155.14 seconds
Started Aug 09 07:19:51 PM PDT 24
Finished Aug 09 07:22:26 PM PDT 24
Peak memory 200004 kb
Host smart-8a1e9902-a4d8-4134-a45d-0f427da7dc6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=319383065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.319383065
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2423279404
Short name T384
Test name
Test status
Simulation time 4004414196 ps
CPU time 6.84 seconds
Started Aug 09 07:19:44 PM PDT 24
Finished Aug 09 07:19:51 PM PDT 24
Peak memory 199028 kb
Host smart-0a95c5e5-95b6-4fc5-b1b0-8903188b7cda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2423279404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2423279404
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.840090040
Short name T637
Test name
Test status
Simulation time 91912827798 ps
CPU time 34.18 seconds
Started Aug 09 07:19:46 PM PDT 24
Finished Aug 09 07:20:21 PM PDT 24
Peak memory 195836 kb
Host smart-3bee0319-0a64-4087-9a07-ec2b54f714cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840090040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.840090040
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2772036923
Short name T1122
Test name
Test status
Simulation time 624072820 ps
CPU time 2.44 seconds
Started Aug 09 07:19:50 PM PDT 24
Finished Aug 09 07:19:52 PM PDT 24
Peak memory 199860 kb
Host smart-2ab3790b-ce86-4e21-9ca6-440fc5cb611a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772036923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2772036923
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1155312908
Short name T710
Test name
Test status
Simulation time 522249134961 ps
CPU time 239.45 seconds
Started Aug 09 07:19:51 PM PDT 24
Finished Aug 09 07:23:50 PM PDT 24
Peak memory 216400 kb
Host smart-e2d2afec-6bb6-4c36-9f8e-4f448d288b74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155312908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1155312908
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1761185131
Short name T1133
Test name
Test status
Simulation time 172188035816 ps
CPU time 398.11 seconds
Started Aug 09 07:19:53 PM PDT 24
Finished Aug 09 07:26:31 PM PDT 24
Peak memory 210624 kb
Host smart-28d3b7bc-4e3c-440d-89c6-92693aab5307
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761185131 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1761185131
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.550326639
Short name T306
Test name
Test status
Simulation time 6630817437 ps
CPU time 12.76 seconds
Started Aug 09 07:19:46 PM PDT 24
Finished Aug 09 07:19:59 PM PDT 24
Peak memory 199824 kb
Host smart-d29fe998-c72f-4155-a2de-64af9a457949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550326639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.550326639
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3101936000
Short name T475
Test name
Test status
Simulation time 18290210935 ps
CPU time 6.6 seconds
Started Aug 09 07:19:46 PM PDT 24
Finished Aug 09 07:19:53 PM PDT 24
Peak memory 197160 kb
Host smart-118e2bc9-72b5-49b4-b284-07298ef1d3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101936000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3101936000
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2730011497
Short name T753
Test name
Test status
Simulation time 46354748164 ps
CPU time 35.63 seconds
Started Aug 09 07:24:19 PM PDT 24
Finished Aug 09 07:24:54 PM PDT 24
Peak memory 199940 kb
Host smart-9016d9c5-501e-4e20-bd21-b6665d754ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730011497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2730011497
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3919256922
Short name T61
Test name
Test status
Simulation time 53611506179 ps
CPU time 22.06 seconds
Started Aug 09 07:24:20 PM PDT 24
Finished Aug 09 07:24:42 PM PDT 24
Peak memory 200028 kb
Host smart-8950c239-dacc-404b-bb51-33f58451302f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919256922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3919256922
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2872456410
Short name T1087
Test name
Test status
Simulation time 137017754881 ps
CPU time 157.31 seconds
Started Aug 09 07:24:27 PM PDT 24
Finished Aug 09 07:27:04 PM PDT 24
Peak memory 199816 kb
Host smart-bd2584c8-ec73-4806-ac61-ed009c0f9b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872456410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2872456410
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3251365214
Short name T566
Test name
Test status
Simulation time 21746062444 ps
CPU time 16.69 seconds
Started Aug 09 07:24:26 PM PDT 24
Finished Aug 09 07:24:43 PM PDT 24
Peak memory 199916 kb
Host smart-7ee8e2f8-5a53-44a1-83ae-4c097b192b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251365214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3251365214
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3712485472
Short name T158
Test name
Test status
Simulation time 69810298891 ps
CPU time 74.66 seconds
Started Aug 09 07:24:27 PM PDT 24
Finished Aug 09 07:25:42 PM PDT 24
Peak memory 200024 kb
Host smart-9cd402be-d61e-4444-99ce-a26614d136ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712485472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3712485472
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.476243853
Short name T808
Test name
Test status
Simulation time 20325264406 ps
CPU time 29.08 seconds
Started Aug 09 07:24:28 PM PDT 24
Finished Aug 09 07:24:57 PM PDT 24
Peak memory 199976 kb
Host smart-20fd0533-505a-41b6-9d47-0f1f2a837681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476243853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.476243853
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.1598030986
Short name T196
Test name
Test status
Simulation time 27082900329 ps
CPU time 16.42 seconds
Started Aug 09 07:24:26 PM PDT 24
Finished Aug 09 07:24:43 PM PDT 24
Peak memory 199936 kb
Host smart-81142c68-385e-4a6f-a802-a92dac24efd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598030986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1598030986
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.3307569097
Short name T153
Test name
Test status
Simulation time 502237030110 ps
CPU time 49.7 seconds
Started Aug 09 07:24:28 PM PDT 24
Finished Aug 09 07:25:18 PM PDT 24
Peak memory 199852 kb
Host smart-db64550d-ba16-4364-9a1e-b0e1007b361f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307569097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3307569097
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3700039293
Short name T95
Test name
Test status
Simulation time 15353836 ps
CPU time 0.55 seconds
Started Aug 09 07:18:39 PM PDT 24
Finished Aug 09 07:18:40 PM PDT 24
Peak memory 195352 kb
Host smart-bc779f64-29be-4ca4-965e-7c19c0b9806b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700039293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3700039293
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3095901999
Short name T772
Test name
Test status
Simulation time 23837426668 ps
CPU time 55.99 seconds
Started Aug 09 07:18:43 PM PDT 24
Finished Aug 09 07:19:39 PM PDT 24
Peak memory 199960 kb
Host smart-f2a780a0-6527-4fdd-83b6-e516603ef5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095901999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3095901999
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3229449305
Short name T408
Test name
Test status
Simulation time 32942587403 ps
CPU time 59.86 seconds
Started Aug 09 07:18:45 PM PDT 24
Finished Aug 09 07:19:45 PM PDT 24
Peak memory 199884 kb
Host smart-88801481-7bc2-44b8-bfdd-ea5fce073695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229449305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3229449305
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.304404992
Short name T759
Test name
Test status
Simulation time 61237466165 ps
CPU time 551.05 seconds
Started Aug 09 07:18:40 PM PDT 24
Finished Aug 09 07:27:51 PM PDT 24
Peak memory 199936 kb
Host smart-5be7ff16-aaa8-48ee-8f59-56d9d6d5e3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304404992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.304404992
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2601015255
Short name T814
Test name
Test status
Simulation time 7756509282 ps
CPU time 5.54 seconds
Started Aug 09 07:18:42 PM PDT 24
Finished Aug 09 07:18:48 PM PDT 24
Peak memory 196780 kb
Host smart-d9c84556-a1f5-43b1-9b17-d376a7c0a3db
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601015255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2601015255
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2251488374
Short name T568
Test name
Test status
Simulation time 211141026825 ps
CPU time 289.37 seconds
Started Aug 09 07:18:42 PM PDT 24
Finished Aug 09 07:23:31 PM PDT 24
Peak memory 199892 kb
Host smart-c68e8a01-3c8e-4de4-a7cc-81de6ca34df0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2251488374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2251488374
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3787610599
Short name T771
Test name
Test status
Simulation time 6694432558 ps
CPU time 5.41 seconds
Started Aug 09 07:18:43 PM PDT 24
Finished Aug 09 07:18:49 PM PDT 24
Peak memory 199924 kb
Host smart-04b34bab-d63c-4aee-a72f-6673675b34d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787610599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3787610599
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3887928026
Short name T279
Test name
Test status
Simulation time 86291116708 ps
CPU time 192.88 seconds
Started Aug 09 07:18:41 PM PDT 24
Finished Aug 09 07:21:55 PM PDT 24
Peak memory 200032 kb
Host smart-15545bbd-f7a0-49d3-b0e4-5b065fb2f077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887928026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3887928026
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.1108839778
Short name T625
Test name
Test status
Simulation time 15340310514 ps
CPU time 314.33 seconds
Started Aug 09 07:18:41 PM PDT 24
Finished Aug 09 07:23:56 PM PDT 24
Peak memory 199916 kb
Host smart-5617be55-3848-497c-abe6-174d9436c1e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1108839778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1108839778
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1597268168
Short name T623
Test name
Test status
Simulation time 4523599101 ps
CPU time 7.62 seconds
Started Aug 09 07:18:42 PM PDT 24
Finished Aug 09 07:18:50 PM PDT 24
Peak memory 199172 kb
Host smart-158ec34f-ffd0-4341-9894-efdec6955ddf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1597268168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1597268168
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.4184436167
Short name T820
Test name
Test status
Simulation time 97023739867 ps
CPU time 78.32 seconds
Started Aug 09 07:18:42 PM PDT 24
Finished Aug 09 07:20:00 PM PDT 24
Peak memory 199944 kb
Host smart-5f86f9fe-8a2a-486b-a8cf-9eebf2a07f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184436167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.4184436167
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.958293518
Short name T364
Test name
Test status
Simulation time 37785442273 ps
CPU time 62.92 seconds
Started Aug 09 07:18:41 PM PDT 24
Finished Aug 09 07:19:44 PM PDT 24
Peak memory 195772 kb
Host smart-67a69dec-79a3-4351-bc25-e333ddf2cb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958293518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.958293518
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2620583423
Short name T91
Test name
Test status
Simulation time 127825537 ps
CPU time 0.8 seconds
Started Aug 09 07:18:42 PM PDT 24
Finished Aug 09 07:18:43 PM PDT 24
Peak memory 218368 kb
Host smart-8e28e0a5-d8b1-4888-b0d7-a555a6622122
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620583423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2620583423
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.3174671264
Short name T305
Test name
Test status
Simulation time 467650796 ps
CPU time 2.9 seconds
Started Aug 09 07:18:41 PM PDT 24
Finished Aug 09 07:18:44 PM PDT 24
Peak memory 198824 kb
Host smart-071723ca-2edb-4422-b3fe-256a8b92cf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174671264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3174671264
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.912414398
Short name T415
Test name
Test status
Simulation time 835030584 ps
CPU time 1.76 seconds
Started Aug 09 07:18:45 PM PDT 24
Finished Aug 09 07:18:47 PM PDT 24
Peak memory 199888 kb
Host smart-f0d512d9-fe45-45d2-9373-79452d0356a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912414398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.912414398
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3763114161
Short name T544
Test name
Test status
Simulation time 84229826436 ps
CPU time 116.25 seconds
Started Aug 09 07:18:42 PM PDT 24
Finished Aug 09 07:20:38 PM PDT 24
Peak memory 199900 kb
Host smart-1d9ebdc0-5bf2-4138-80b2-4c402516d2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763114161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3763114161
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1254118540
Short name T337
Test name
Test status
Simulation time 35137145 ps
CPU time 0.55 seconds
Started Aug 09 07:19:50 PM PDT 24
Finished Aug 09 07:19:50 PM PDT 24
Peak memory 195624 kb
Host smart-2ce6ba95-3ea9-4cff-96d2-5a0a32b3a9c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254118540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1254118540
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2566442856
Short name T826
Test name
Test status
Simulation time 79376244504 ps
CPU time 71.51 seconds
Started Aug 09 07:19:50 PM PDT 24
Finished Aug 09 07:21:02 PM PDT 24
Peak memory 199948 kb
Host smart-5582187e-652a-4cac-be85-158297c2a184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566442856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2566442856
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3078332575
Short name T323
Test name
Test status
Simulation time 9952598880 ps
CPU time 9.01 seconds
Started Aug 09 07:19:51 PM PDT 24
Finished Aug 09 07:20:00 PM PDT 24
Peak memory 199912 kb
Host smart-22d9391e-1121-4b23-b1a7-4d2bb34763d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078332575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3078332575
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_intr.2667871353
Short name T287
Test name
Test status
Simulation time 49045407764 ps
CPU time 78.39 seconds
Started Aug 09 07:19:51 PM PDT 24
Finished Aug 09 07:21:10 PM PDT 24
Peak memory 199984 kb
Host smart-754b7779-5096-4927-a66b-14b28c07c283
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667871353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2667871353
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.160641911
Short name T338
Test name
Test status
Simulation time 95564333506 ps
CPU time 138.27 seconds
Started Aug 09 07:19:54 PM PDT 24
Finished Aug 09 07:22:12 PM PDT 24
Peak memory 199964 kb
Host smart-b0764161-404f-421b-a405-0891ebb67b45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=160641911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.160641911
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2940091821
Short name T922
Test name
Test status
Simulation time 2059941978 ps
CPU time 4.19 seconds
Started Aug 09 07:19:54 PM PDT 24
Finished Aug 09 07:19:58 PM PDT 24
Peak memory 199808 kb
Host smart-1c2a4450-fc73-4555-82b0-492eea890d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940091821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2940091821
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.1569043517
Short name T703
Test name
Test status
Simulation time 168843066803 ps
CPU time 255.71 seconds
Started Aug 09 07:19:54 PM PDT 24
Finished Aug 09 07:24:10 PM PDT 24
Peak memory 199968 kb
Host smart-bb7a53f7-9997-46f6-a20e-501770b34626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569043517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1569043517
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.248320887
Short name T391
Test name
Test status
Simulation time 3476246706 ps
CPU time 202.47 seconds
Started Aug 09 07:19:53 PM PDT 24
Finished Aug 09 07:23:15 PM PDT 24
Peak memory 199948 kb
Host smart-83b908bb-0500-4fa8-81c3-69918ddeca42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=248320887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.248320887
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1542618655
Short name T498
Test name
Test status
Simulation time 3192280496 ps
CPU time 7.03 seconds
Started Aug 09 07:19:51 PM PDT 24
Finished Aug 09 07:19:58 PM PDT 24
Peak memory 199104 kb
Host smart-bceae129-11ba-4604-a624-67d07e94963b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1542618655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1542618655
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1223563599
Short name T281
Test name
Test status
Simulation time 140480269668 ps
CPU time 72.3 seconds
Started Aug 09 07:19:53 PM PDT 24
Finished Aug 09 07:21:05 PM PDT 24
Peak memory 199908 kb
Host smart-04214694-9a80-42f8-9beb-67a8e344e83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223563599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1223563599
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3103981698
Short name T758
Test name
Test status
Simulation time 7196930582 ps
CPU time 2.64 seconds
Started Aug 09 07:19:55 PM PDT 24
Finished Aug 09 07:19:58 PM PDT 24
Peak memory 196808 kb
Host smart-f60c11ea-bd96-4918-a155-1ae3c8949920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103981698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3103981698
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3480710146
Short name T1083
Test name
Test status
Simulation time 5718202923 ps
CPU time 13.36 seconds
Started Aug 09 07:19:51 PM PDT 24
Finished Aug 09 07:20:04 PM PDT 24
Peak memory 199744 kb
Host smart-84571c9f-d0bc-449c-a915-25af4ce3c03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480710146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3480710146
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.1705673235
Short name T654
Test name
Test status
Simulation time 194340517158 ps
CPU time 95.51 seconds
Started Aug 09 07:19:50 PM PDT 24
Finished Aug 09 07:21:26 PM PDT 24
Peak memory 199916 kb
Host smart-30b7cbe4-8f33-4c58-993e-44a67447c38a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705673235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1705673235
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1576429300
Short name T726
Test name
Test status
Simulation time 123470562945 ps
CPU time 499.95 seconds
Started Aug 09 07:19:52 PM PDT 24
Finished Aug 09 07:28:13 PM PDT 24
Peak memory 216492 kb
Host smart-cdd8612a-cb5c-4273-8b87-c39c34e1d93a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576429300 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1576429300
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1062150935
Short name T924
Test name
Test status
Simulation time 1007649991 ps
CPU time 2.07 seconds
Started Aug 09 07:19:53 PM PDT 24
Finished Aug 09 07:19:55 PM PDT 24
Peak memory 199456 kb
Host smart-46389a34-1f2d-4797-8920-cd83f3f23941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062150935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1062150935
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1854628113
Short name T290
Test name
Test status
Simulation time 78087788412 ps
CPU time 141.94 seconds
Started Aug 09 07:19:52 PM PDT 24
Finished Aug 09 07:22:14 PM PDT 24
Peak memory 199920 kb
Host smart-31ac5be9-656d-4985-8fe1-928bd8c28160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854628113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1854628113
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3274484741
Short name T193
Test name
Test status
Simulation time 156312885957 ps
CPU time 106.94 seconds
Started Aug 09 07:24:27 PM PDT 24
Finished Aug 09 07:26:14 PM PDT 24
Peak memory 199920 kb
Host smart-6725b6ef-821d-4ad5-a662-d72478ab2025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274484741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3274484741
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3796035915
Short name T263
Test name
Test status
Simulation time 53564638592 ps
CPU time 90.75 seconds
Started Aug 09 07:24:45 PM PDT 24
Finished Aug 09 07:26:16 PM PDT 24
Peak memory 199884 kb
Host smart-d61580de-5c11-4575-b6e9-6f13356883f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796035915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3796035915
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.4016517407
Short name T751
Test name
Test status
Simulation time 60015232916 ps
CPU time 23.48 seconds
Started Aug 09 07:24:44 PM PDT 24
Finished Aug 09 07:25:07 PM PDT 24
Peak memory 199912 kb
Host smart-cdb6f4ca-a7c9-4cef-92d4-58aa1ad58ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016517407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.4016517407
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3344922347
Short name T512
Test name
Test status
Simulation time 40493626995 ps
CPU time 16.5 seconds
Started Aug 09 07:24:42 PM PDT 24
Finished Aug 09 07:24:58 PM PDT 24
Peak memory 199756 kb
Host smart-9141808b-957d-4cf9-9731-c55ff67d07c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344922347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3344922347
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2918814597
Short name T149
Test name
Test status
Simulation time 49009565690 ps
CPU time 49.28 seconds
Started Aug 09 07:24:40 PM PDT 24
Finished Aug 09 07:25:29 PM PDT 24
Peak memory 199948 kb
Host smart-e8d85657-c234-48ba-88e4-5f3727e041ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918814597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2918814597
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.3453236465
Short name T851
Test name
Test status
Simulation time 129683563446 ps
CPU time 20.22 seconds
Started Aug 09 07:24:42 PM PDT 24
Finished Aug 09 07:25:02 PM PDT 24
Peak memory 199916 kb
Host smart-a5dcc39a-0b90-43b4-973b-8faa3296bc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453236465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3453236465
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2791600834
Short name T1032
Test name
Test status
Simulation time 18220267108 ps
CPU time 13.52 seconds
Started Aug 09 07:24:41 PM PDT 24
Finished Aug 09 07:24:54 PM PDT 24
Peak memory 199880 kb
Host smart-1d332cad-c76f-4246-9707-5938fb3973ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791600834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2791600834
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1394721842
Short name T38
Test name
Test status
Simulation time 72342758621 ps
CPU time 162.4 seconds
Started Aug 09 07:24:45 PM PDT 24
Finished Aug 09 07:27:28 PM PDT 24
Peak memory 199892 kb
Host smart-0ec80b75-635a-4338-814c-79033349bdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394721842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1394721842
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.4214586568
Short name T564
Test name
Test status
Simulation time 29013671 ps
CPU time 0.52 seconds
Started Aug 09 07:20:00 PM PDT 24
Finished Aug 09 07:20:01 PM PDT 24
Peak memory 194448 kb
Host smart-e336ddef-ab3d-4f00-8b88-10fecfc5a0f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214586568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.4214586568
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.1816774079
Short name T1096
Test name
Test status
Simulation time 43999715044 ps
CPU time 68.16 seconds
Started Aug 09 07:19:57 PM PDT 24
Finished Aug 09 07:21:05 PM PDT 24
Peak memory 199820 kb
Host smart-c75b3e3d-61f9-4823-88e7-eb8fc90a9ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816774079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1816774079
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2872214115
Short name T162
Test name
Test status
Simulation time 131380769420 ps
CPU time 64.27 seconds
Started Aug 09 07:19:59 PM PDT 24
Finished Aug 09 07:21:03 PM PDT 24
Peak memory 199964 kb
Host smart-df344a4c-a7fc-4205-91dd-58e8beefcadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872214115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2872214115
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.49625208
Short name T849
Test name
Test status
Simulation time 52248753152 ps
CPU time 61.16 seconds
Started Aug 09 07:19:58 PM PDT 24
Finished Aug 09 07:20:59 PM PDT 24
Peak memory 199956 kb
Host smart-9374223e-2fb6-464f-b912-51c0d9b02b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49625208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.49625208
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1788716869
Short name T586
Test name
Test status
Simulation time 41218198833 ps
CPU time 18.8 seconds
Started Aug 09 07:19:57 PM PDT 24
Finished Aug 09 07:20:16 PM PDT 24
Peak memory 199968 kb
Host smart-726bb27e-eace-4af3-a49c-5eb102fae6b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788716869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1788716869
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.752341647
Short name T372
Test name
Test status
Simulation time 163317626137 ps
CPU time 167.03 seconds
Started Aug 09 07:19:58 PM PDT 24
Finished Aug 09 07:22:45 PM PDT 24
Peak memory 199936 kb
Host smart-a337f5e6-5681-4bd4-9dee-052a2f10855f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=752341647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.752341647
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1167218775
Short name T443
Test name
Test status
Simulation time 9790728390 ps
CPU time 14.88 seconds
Started Aug 09 07:19:59 PM PDT 24
Finished Aug 09 07:20:14 PM PDT 24
Peak memory 198584 kb
Host smart-59b69222-85db-4c13-899c-72f652d6ee99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167218775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1167218775
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3235491528
Short name T447
Test name
Test status
Simulation time 31093884001 ps
CPU time 20.34 seconds
Started Aug 09 07:19:59 PM PDT 24
Finished Aug 09 07:20:20 PM PDT 24
Peak memory 199864 kb
Host smart-f6b1650a-dd0e-4c40-b168-f3d3c13487b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235491528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3235491528
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3232990044
Short name T1173
Test name
Test status
Simulation time 5735964029 ps
CPU time 87.99 seconds
Started Aug 09 07:19:58 PM PDT 24
Finished Aug 09 07:21:26 PM PDT 24
Peak memory 199908 kb
Host smart-493bbdc9-f140-4edb-ac6a-238508e7e555
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3232990044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3232990044
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.657914279
Short name T425
Test name
Test status
Simulation time 6865057642 ps
CPU time 33.55 seconds
Started Aug 09 07:19:59 PM PDT 24
Finished Aug 09 07:20:33 PM PDT 24
Peak memory 198924 kb
Host smart-895e8856-a711-4c2b-a7b3-f71267444d8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=657914279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.657914279
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2928792775
Short name T578
Test name
Test status
Simulation time 19996029467 ps
CPU time 29.15 seconds
Started Aug 09 07:19:57 PM PDT 24
Finished Aug 09 07:20:27 PM PDT 24
Peak memory 199980 kb
Host smart-96bc449e-176c-4644-97e6-749431929ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928792775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2928792775
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2562287472
Short name T831
Test name
Test status
Simulation time 4058705948 ps
CPU time 3.48 seconds
Started Aug 09 07:19:58 PM PDT 24
Finished Aug 09 07:20:02 PM PDT 24
Peak memory 196852 kb
Host smart-cba34d05-a222-4565-a044-c4cb0992dd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562287472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2562287472
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1323235891
Short name T634
Test name
Test status
Simulation time 481095409 ps
CPU time 2.03 seconds
Started Aug 09 07:19:57 PM PDT 24
Finished Aug 09 07:20:00 PM PDT 24
Peak memory 198160 kb
Host smart-c222822e-0fd5-4e30-9f5e-ca8175234002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323235891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1323235891
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2901298193
Short name T308
Test name
Test status
Simulation time 41762101281 ps
CPU time 57.73 seconds
Started Aug 09 07:19:58 PM PDT 24
Finished Aug 09 07:20:56 PM PDT 24
Peak memory 199912 kb
Host smart-bf5e7dc7-7244-4717-b993-8d64f266d63e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901298193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2901298193
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2959170215
Short name T1060
Test name
Test status
Simulation time 30909932276 ps
CPU time 833.59 seconds
Started Aug 09 07:19:59 PM PDT 24
Finished Aug 09 07:33:53 PM PDT 24
Peak memory 209068 kb
Host smart-4ee0dc30-844c-49f6-963d-1dfb941ef9eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959170215 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2959170215
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2702050346
Short name T515
Test name
Test status
Simulation time 1175964549 ps
CPU time 1.65 seconds
Started Aug 09 07:19:57 PM PDT 24
Finished Aug 09 07:20:00 PM PDT 24
Peak memory 198412 kb
Host smart-40461e5f-f744-41aa-b547-6040152fdfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702050346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2702050346
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3715322027
Short name T992
Test name
Test status
Simulation time 54475341489 ps
CPU time 41.61 seconds
Started Aug 09 07:19:59 PM PDT 24
Finished Aug 09 07:20:41 PM PDT 24
Peak memory 199976 kb
Host smart-37796ac7-a354-4277-982f-101e9a1309d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715322027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3715322027
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1648969353
Short name T591
Test name
Test status
Simulation time 25205876532 ps
CPU time 37.61 seconds
Started Aug 09 07:24:42 PM PDT 24
Finished Aug 09 07:25:20 PM PDT 24
Peak memory 199908 kb
Host smart-e4dfb708-be3f-43cb-8e0b-e4e8db873bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648969353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1648969353
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3749468278
Short name T540
Test name
Test status
Simulation time 17523582138 ps
CPU time 14.61 seconds
Started Aug 09 07:24:41 PM PDT 24
Finished Aug 09 07:24:56 PM PDT 24
Peak memory 199896 kb
Host smart-3c90c3da-3e95-470f-9aa7-650b204eb657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749468278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3749468278
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.1462105097
Short name T197
Test name
Test status
Simulation time 98708812894 ps
CPU time 60.65 seconds
Started Aug 09 07:24:41 PM PDT 24
Finished Aug 09 07:25:42 PM PDT 24
Peak memory 199808 kb
Host smart-4b482750-f0b7-4641-b597-f0ce3dadee7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462105097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1462105097
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.688111998
Short name T1085
Test name
Test status
Simulation time 39301666206 ps
CPU time 16.5 seconds
Started Aug 09 07:24:42 PM PDT 24
Finished Aug 09 07:24:58 PM PDT 24
Peak memory 199976 kb
Host smart-abef13c0-c54a-4b04-833a-97ea79c13563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688111998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.688111998
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3179098638
Short name T581
Test name
Test status
Simulation time 18435595624 ps
CPU time 11.21 seconds
Started Aug 09 07:24:42 PM PDT 24
Finished Aug 09 07:24:53 PM PDT 24
Peak memory 199936 kb
Host smart-7f941206-719a-45b7-8f9a-55b7cc7c7952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179098638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3179098638
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3187933280
Short name T1154
Test name
Test status
Simulation time 150592939801 ps
CPU time 223 seconds
Started Aug 09 07:24:42 PM PDT 24
Finished Aug 09 07:28:25 PM PDT 24
Peak memory 199936 kb
Host smart-c3a9ceba-e9db-4d8e-a0d6-7a07e5ab203b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187933280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3187933280
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3604038475
Short name T1041
Test name
Test status
Simulation time 38401815295 ps
CPU time 16.88 seconds
Started Aug 09 07:24:41 PM PDT 24
Finished Aug 09 07:24:58 PM PDT 24
Peak memory 199864 kb
Host smart-3332c1a8-3b6a-402a-8990-f0ddfaf5dc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604038475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3604038475
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.388222983
Short name T147
Test name
Test status
Simulation time 79993281398 ps
CPU time 46.83 seconds
Started Aug 09 07:24:42 PM PDT 24
Finished Aug 09 07:25:29 PM PDT 24
Peak memory 199976 kb
Host smart-8cd77624-e077-41af-896a-706f496f49eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388222983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.388222983
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.800364801
Short name T823
Test name
Test status
Simulation time 6288426208 ps
CPU time 9.2 seconds
Started Aug 09 07:24:42 PM PDT 24
Finished Aug 09 07:24:51 PM PDT 24
Peak memory 199324 kb
Host smart-d58fb8f0-90d4-401a-9bc3-232a2dcb53b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800364801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.800364801
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1797508432
Short name T304
Test name
Test status
Simulation time 168701416213 ps
CPU time 173.36 seconds
Started Aug 09 07:24:43 PM PDT 24
Finished Aug 09 07:27:36 PM PDT 24
Peak memory 200152 kb
Host smart-be0baee2-1e75-4dde-b928-e760cf8eb540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797508432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1797508432
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2557838989
Short name T1115
Test name
Test status
Simulation time 11643237 ps
CPU time 0.53 seconds
Started Aug 09 07:20:07 PM PDT 24
Finished Aug 09 07:20:08 PM PDT 24
Peak memory 194324 kb
Host smart-58d01fe1-fdc9-4077-a40c-294fff4ac284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557838989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2557838989
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2279448248
Short name T371
Test name
Test status
Simulation time 120195879533 ps
CPU time 196.26 seconds
Started Aug 09 07:19:59 PM PDT 24
Finished Aug 09 07:23:15 PM PDT 24
Peak memory 199952 kb
Host smart-8f691b9d-95cf-444d-bd3b-d60a9c1484ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279448248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2279448248
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2739200729
Short name T777
Test name
Test status
Simulation time 96871932961 ps
CPU time 140.27 seconds
Started Aug 09 07:19:58 PM PDT 24
Finished Aug 09 07:22:18 PM PDT 24
Peak memory 199956 kb
Host smart-7fd13fb0-8a37-4a75-9127-66c9e4368b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739200729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2739200729
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3420799515
Short name T706
Test name
Test status
Simulation time 9529637582 ps
CPU time 16.6 seconds
Started Aug 09 07:19:59 PM PDT 24
Finished Aug 09 07:20:16 PM PDT 24
Peak memory 199700 kb
Host smart-57559cbb-c2d5-4bff-924c-fb1b3359cc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420799515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3420799515
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3199887508
Short name T393
Test name
Test status
Simulation time 32744965060 ps
CPU time 52.3 seconds
Started Aug 09 07:20:07 PM PDT 24
Finished Aug 09 07:21:00 PM PDT 24
Peak memory 199940 kb
Host smart-b116ac1f-7fb6-4c95-b290-1545e351b830
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199887508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3199887508
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3335294799
Short name T1139
Test name
Test status
Simulation time 118043433870 ps
CPU time 309.55 seconds
Started Aug 09 07:20:07 PM PDT 24
Finished Aug 09 07:25:17 PM PDT 24
Peak memory 199984 kb
Host smart-9636a760-1e0a-4b21-8ee9-deb25190bc4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3335294799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3335294799
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2218405683
Short name T347
Test name
Test status
Simulation time 6355903936 ps
CPU time 11.37 seconds
Started Aug 09 07:20:06 PM PDT 24
Finished Aug 09 07:20:17 PM PDT 24
Peak memory 199400 kb
Host smart-1dee3e98-4651-4ec3-a8c1-7608ae5f034b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218405683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2218405683
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3019811160
Short name T1053
Test name
Test status
Simulation time 122397980489 ps
CPU time 108.18 seconds
Started Aug 09 07:20:11 PM PDT 24
Finished Aug 09 07:21:59 PM PDT 24
Peak memory 198384 kb
Host smart-b5a5c004-55fa-4bb5-8e65-a45ae7e2ad3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019811160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3019811160
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.3206655219
Short name T507
Test name
Test status
Simulation time 7986169647 ps
CPU time 432.15 seconds
Started Aug 09 07:20:08 PM PDT 24
Finished Aug 09 07:27:21 PM PDT 24
Peak memory 199884 kb
Host smart-45fae93e-f295-4fda-b2f9-72acfee9a95c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3206655219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3206655219
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3276350
Short name T474
Test name
Test status
Simulation time 6409854367 ps
CPU time 3.82 seconds
Started Aug 09 07:19:59 PM PDT 24
Finished Aug 09 07:20:03 PM PDT 24
Peak memory 199380 kb
Host smart-2eb26d08-3718-4f57-9c7b-4031da07d92c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3276350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3276350
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.545238395
Short name T253
Test name
Test status
Simulation time 100573768201 ps
CPU time 42.02 seconds
Started Aug 09 07:20:07 PM PDT 24
Finished Aug 09 07:20:49 PM PDT 24
Peak memory 199864 kb
Host smart-21e28b33-d781-4d44-bd99-2fe03f224cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545238395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.545238395
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2982192079
Short name T977
Test name
Test status
Simulation time 3575784830 ps
CPU time 5.49 seconds
Started Aug 09 07:20:10 PM PDT 24
Finished Aug 09 07:20:16 PM PDT 24
Peak memory 196032 kb
Host smart-388719cb-24bf-4a62-a164-06707ea389c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982192079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2982192079
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1597125634
Short name T502
Test name
Test status
Simulation time 141865543 ps
CPU time 0.78 seconds
Started Aug 09 07:19:57 PM PDT 24
Finished Aug 09 07:19:58 PM PDT 24
Peak memory 197756 kb
Host smart-aa6f99f9-0764-406b-9aa8-ad369419c63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597125634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1597125634
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3175880883
Short name T461
Test name
Test status
Simulation time 497946820855 ps
CPU time 380.88 seconds
Started Aug 09 07:20:08 PM PDT 24
Finished Aug 09 07:26:29 PM PDT 24
Peak memory 199944 kb
Host smart-d2c7fc54-002a-4081-9dc8-aa53c9656d58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175880883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3175880883
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1235719223
Short name T819
Test name
Test status
Simulation time 64805367982 ps
CPU time 693.46 seconds
Started Aug 09 07:20:08 PM PDT 24
Finished Aug 09 07:31:41 PM PDT 24
Peak memory 224796 kb
Host smart-f8b4b900-0a25-4a4b-af38-dfca0b53e6fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235719223 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1235719223
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2056570743
Short name T790
Test name
Test status
Simulation time 911819830 ps
CPU time 2.86 seconds
Started Aug 09 07:20:11 PM PDT 24
Finished Aug 09 07:20:14 PM PDT 24
Peak memory 198652 kb
Host smart-709b486a-8573-4684-a8df-388ae192fb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056570743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2056570743
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.290441555
Short name T260
Test name
Test status
Simulation time 111128677278 ps
CPU time 173.78 seconds
Started Aug 09 07:20:00 PM PDT 24
Finished Aug 09 07:22:54 PM PDT 24
Peak memory 199824 kb
Host smart-7fe032cc-2648-4613-929f-496483f01f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290441555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.290441555
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3078892408
Short name T734
Test name
Test status
Simulation time 96965495965 ps
CPU time 60.56 seconds
Started Aug 09 07:24:43 PM PDT 24
Finished Aug 09 07:25:43 PM PDT 24
Peak memory 199968 kb
Host smart-497d92ed-f3af-4ec2-9ca3-13435b3c3fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078892408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3078892408
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.4010201327
Short name T737
Test name
Test status
Simulation time 47030829801 ps
CPU time 14.57 seconds
Started Aug 09 07:24:45 PM PDT 24
Finished Aug 09 07:24:59 PM PDT 24
Peak memory 200028 kb
Host smart-325f2f73-3203-4478-8f34-2066f6a81abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010201327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.4010201327
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.754231973
Short name T719
Test name
Test status
Simulation time 52541915865 ps
CPU time 102.52 seconds
Started Aug 09 07:24:44 PM PDT 24
Finished Aug 09 07:26:26 PM PDT 24
Peak memory 199956 kb
Host smart-ddbc46eb-39e3-45a1-b177-e5d7ab451555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754231973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.754231973
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2327387574
Short name T597
Test name
Test status
Simulation time 50876603346 ps
CPU time 81.71 seconds
Started Aug 09 07:24:42 PM PDT 24
Finished Aug 09 07:26:04 PM PDT 24
Peak memory 199960 kb
Host smart-d23e414e-186c-4ed2-9b08-a3dfcab2b685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327387574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2327387574
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1566369969
Short name T1014
Test name
Test status
Simulation time 40320280493 ps
CPU time 23.74 seconds
Started Aug 09 07:24:44 PM PDT 24
Finished Aug 09 07:25:08 PM PDT 24
Peak memory 199856 kb
Host smart-f19ddbe8-462d-45c1-8f41-505195a817a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566369969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1566369969
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3492218952
Short name T285
Test name
Test status
Simulation time 77025466910 ps
CPU time 25.31 seconds
Started Aug 09 07:24:44 PM PDT 24
Finished Aug 09 07:25:10 PM PDT 24
Peak memory 199396 kb
Host smart-d51a1bc1-6543-486d-947b-03d7f20e61cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492218952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3492218952
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.577381376
Short name T441
Test name
Test status
Simulation time 32679137534 ps
CPU time 16.24 seconds
Started Aug 09 07:24:44 PM PDT 24
Finished Aug 09 07:25:00 PM PDT 24
Peak memory 199988 kb
Host smart-d5d3f4fb-2056-4c48-89dc-9f806702b1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577381376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.577381376
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.4002325675
Short name T1013
Test name
Test status
Simulation time 16529437428 ps
CPU time 31.78 seconds
Started Aug 09 07:24:51 PM PDT 24
Finished Aug 09 07:25:23 PM PDT 24
Peak memory 199976 kb
Host smart-f8506e99-26ab-4e98-9c67-ea7bee43b11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002325675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.4002325675
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.408767568
Short name T227
Test name
Test status
Simulation time 192334217269 ps
CPU time 37.9 seconds
Started Aug 09 07:24:53 PM PDT 24
Finished Aug 09 07:25:30 PM PDT 24
Peak memory 199992 kb
Host smart-e37bffc5-884e-4589-b17e-1a8a1da7312f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408767568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.408767568
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1225650671
Short name T653
Test name
Test status
Simulation time 36297275 ps
CPU time 0.56 seconds
Started Aug 09 07:20:14 PM PDT 24
Finished Aug 09 07:20:15 PM PDT 24
Peak memory 195324 kb
Host smart-ee3fee8f-9dd2-4cd9-8915-99372c553331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225650671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1225650671
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3371851875
Short name T904
Test name
Test status
Simulation time 134993219560 ps
CPU time 77.61 seconds
Started Aug 09 07:20:06 PM PDT 24
Finished Aug 09 07:21:24 PM PDT 24
Peak memory 199940 kb
Host smart-8aa7590e-4d5f-4774-85ed-37bd2deffb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371851875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3371851875
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.689081993
Short name T880
Test name
Test status
Simulation time 77470757060 ps
CPU time 32.27 seconds
Started Aug 09 07:20:10 PM PDT 24
Finished Aug 09 07:20:42 PM PDT 24
Peak memory 199872 kb
Host smart-254901ad-1375-43f2-9b5a-cdd5f00cb8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689081993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.689081993
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.927378836
Short name T190
Test name
Test status
Simulation time 218784504612 ps
CPU time 582.34 seconds
Started Aug 09 07:20:11 PM PDT 24
Finished Aug 09 07:29:53 PM PDT 24
Peak memory 199884 kb
Host smart-b7beabf3-c062-4677-9d37-0461ff79b438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927378836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.927378836
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.823692899
Short name T395
Test name
Test status
Simulation time 11654809599 ps
CPU time 5.16 seconds
Started Aug 09 07:20:06 PM PDT 24
Finished Aug 09 07:20:11 PM PDT 24
Peak memory 197360 kb
Host smart-a00d99ce-1b4e-4b77-829c-ed369cfe78e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823692899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.823692899
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1267548220
Short name T560
Test name
Test status
Simulation time 150700680364 ps
CPU time 138.15 seconds
Started Aug 09 07:20:09 PM PDT 24
Finished Aug 09 07:22:28 PM PDT 24
Peak memory 200120 kb
Host smart-74478518-a56a-4bc6-becf-48bda633e9c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1267548220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1267548220
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.876509845
Short name T615
Test name
Test status
Simulation time 6914647400 ps
CPU time 11.74 seconds
Started Aug 09 07:20:08 PM PDT 24
Finished Aug 09 07:20:20 PM PDT 24
Peak memory 198204 kb
Host smart-2c3c137a-5209-49f2-a076-1595304b1b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876509845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.876509845
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.4247289841
Short name T410
Test name
Test status
Simulation time 16590106629 ps
CPU time 31.72 seconds
Started Aug 09 07:20:07 PM PDT 24
Finished Aug 09 07:20:39 PM PDT 24
Peak memory 199228 kb
Host smart-85496499-8512-417f-bb77-b06a6a176fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247289841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.4247289841
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.336445211
Short name T315
Test name
Test status
Simulation time 12634148260 ps
CPU time 169.81 seconds
Started Aug 09 07:20:06 PM PDT 24
Finished Aug 09 07:22:56 PM PDT 24
Peak memory 199880 kb
Host smart-9250b24f-6783-4467-81c4-fe29eedc3c96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=336445211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.336445211
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3131051318
Short name T379
Test name
Test status
Simulation time 5077959460 ps
CPU time 41.95 seconds
Started Aug 09 07:20:07 PM PDT 24
Finished Aug 09 07:20:49 PM PDT 24
Peak memory 199388 kb
Host smart-d521def6-2fe5-45d0-8d3d-335ff721a087
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3131051318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3131051318
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2083864750
Short name T957
Test name
Test status
Simulation time 79537476322 ps
CPU time 38.03 seconds
Started Aug 09 07:20:11 PM PDT 24
Finished Aug 09 07:20:49 PM PDT 24
Peak memory 199884 kb
Host smart-8d2d3f6d-f1ec-4066-ac34-f2f39a2dd494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083864750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2083864750
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.4132195493
Short name T1112
Test name
Test status
Simulation time 5113609787 ps
CPU time 1.27 seconds
Started Aug 09 07:20:10 PM PDT 24
Finished Aug 09 07:20:11 PM PDT 24
Peak memory 196260 kb
Host smart-f1a1b0f0-21aa-4319-a26b-8957eee0595f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132195493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.4132195493
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.320339439
Short name T311
Test name
Test status
Simulation time 852774829 ps
CPU time 2.63 seconds
Started Aug 09 07:20:08 PM PDT 24
Finished Aug 09 07:20:11 PM PDT 24
Peak memory 198648 kb
Host smart-931c90be-edfe-40c1-b9c1-9e43df39df80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320339439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.320339439
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1266611683
Short name T749
Test name
Test status
Simulation time 230356744877 ps
CPU time 140.35 seconds
Started Aug 09 07:20:09 PM PDT 24
Finished Aug 09 07:22:29 PM PDT 24
Peak memory 199860 kb
Host smart-13dcc29f-c10e-4fb2-a31e-68bac2ed247f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266611683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1266611683
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.666468529
Short name T1129
Test name
Test status
Simulation time 48048120194 ps
CPU time 146.91 seconds
Started Aug 09 07:20:06 PM PDT 24
Finished Aug 09 07:22:33 PM PDT 24
Peak memory 216320 kb
Host smart-ff989a6c-d921-4246-96a5-6631715b23a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666468529 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.666468529
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1290806802
Short name T859
Test name
Test status
Simulation time 568359729 ps
CPU time 1.57 seconds
Started Aug 09 07:20:08 PM PDT 24
Finished Aug 09 07:20:09 PM PDT 24
Peak memory 197192 kb
Host smart-334ba861-8ac6-4e80-9898-b5ad3f982dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290806802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1290806802
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.2325402286
Short name T652
Test name
Test status
Simulation time 73653463061 ps
CPU time 34.45 seconds
Started Aug 09 07:20:05 PM PDT 24
Finished Aug 09 07:20:39 PM PDT 24
Peak memory 199884 kb
Host smart-d397eb5d-ef97-45ba-96c9-cfae4cf34ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325402286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2325402286
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2236455190
Short name T1127
Test name
Test status
Simulation time 36229280293 ps
CPU time 13.58 seconds
Started Aug 09 07:24:55 PM PDT 24
Finished Aug 09 07:25:09 PM PDT 24
Peak memory 199828 kb
Host smart-2dde65c3-0f1e-4c48-a511-672b59accfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236455190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2236455190
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3341941803
Short name T157
Test name
Test status
Simulation time 56683789104 ps
CPU time 50.82 seconds
Started Aug 09 07:24:52 PM PDT 24
Finished Aug 09 07:25:43 PM PDT 24
Peak memory 200028 kb
Host smart-0b528066-e770-41b1-ab95-4e8d79e1c482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341941803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3341941803
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3794630125
Short name T570
Test name
Test status
Simulation time 19749984328 ps
CPU time 20.31 seconds
Started Aug 09 07:24:52 PM PDT 24
Finished Aug 09 07:25:13 PM PDT 24
Peak memory 199928 kb
Host smart-c197b74f-56b9-43af-a04c-cbf25120ebcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794630125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3794630125
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.575292143
Short name T1
Test name
Test status
Simulation time 55482016567 ps
CPU time 23.5 seconds
Started Aug 09 07:24:51 PM PDT 24
Finished Aug 09 07:25:15 PM PDT 24
Peak memory 199952 kb
Host smart-1d8da74b-929e-40f2-ba63-5286d01edbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575292143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.575292143
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.811169695
Short name T58
Test name
Test status
Simulation time 102921433846 ps
CPU time 168.47 seconds
Started Aug 09 07:24:52 PM PDT 24
Finished Aug 09 07:27:41 PM PDT 24
Peak memory 199916 kb
Host smart-15c9bd64-54b8-4d43-a035-ec4820a0c409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811169695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.811169695
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1136663716
Short name T762
Test name
Test status
Simulation time 66321663582 ps
CPU time 102.94 seconds
Started Aug 09 07:24:52 PM PDT 24
Finished Aug 09 07:26:35 PM PDT 24
Peak memory 199876 kb
Host smart-001465d0-f015-4ac7-a6ba-054ca82ff93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136663716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1136663716
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1552684185
Short name T897
Test name
Test status
Simulation time 174662899899 ps
CPU time 73.47 seconds
Started Aug 09 07:24:53 PM PDT 24
Finished Aug 09 07:26:06 PM PDT 24
Peak memory 199964 kb
Host smart-8611a20e-8c93-470d-be47-4bddfcd0a273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552684185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1552684185
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1449840388
Short name T847
Test name
Test status
Simulation time 29222990560 ps
CPU time 22.76 seconds
Started Aug 09 07:24:52 PM PDT 24
Finished Aug 09 07:25:15 PM PDT 24
Peak memory 199948 kb
Host smart-3118a24a-8017-44a2-8b64-9c26c1df5e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449840388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1449840388
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3333369220
Short name T255
Test name
Test status
Simulation time 21996043632 ps
CPU time 15.56 seconds
Started Aug 09 07:24:53 PM PDT 24
Finished Aug 09 07:25:08 PM PDT 24
Peak memory 199952 kb
Host smart-c20ae496-6617-4e33-b2fa-5a38c265fc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333369220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3333369220
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.345563736
Short name T2
Test name
Test status
Simulation time 13992152 ps
CPU time 0.58 seconds
Started Aug 09 07:20:14 PM PDT 24
Finished Aug 09 07:20:15 PM PDT 24
Peak memory 195340 kb
Host smart-2277a25a-880b-4768-951b-5cff9dfd80f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345563736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.345563736
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.750905566
Short name T267
Test name
Test status
Simulation time 116048398364 ps
CPU time 141.93 seconds
Started Aug 09 07:20:16 PM PDT 24
Finished Aug 09 07:22:38 PM PDT 24
Peak memory 199892 kb
Host smart-62c89648-673a-45c6-a7e9-1184a756eb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750905566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.750905566
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.818444275
Short name T176
Test name
Test status
Simulation time 24061942925 ps
CPU time 18.11 seconds
Started Aug 09 07:20:15 PM PDT 24
Finished Aug 09 07:20:34 PM PDT 24
Peak memory 199908 kb
Host smart-d7d76ff1-1aab-425c-9586-87aa7c88d9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818444275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.818444275
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2050298726
Short name T834
Test name
Test status
Simulation time 9670666348 ps
CPU time 15.66 seconds
Started Aug 09 07:20:15 PM PDT 24
Finished Aug 09 07:20:31 PM PDT 24
Peak memory 199700 kb
Host smart-d3b8f34e-24ab-40bd-b6b7-fc1e767d5c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050298726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2050298726
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.2579308101
Short name T610
Test name
Test status
Simulation time 27349920642 ps
CPU time 43.72 seconds
Started Aug 09 07:20:14 PM PDT 24
Finished Aug 09 07:20:58 PM PDT 24
Peak memory 198528 kb
Host smart-b11d69a4-60e5-448e-8904-a22c009c80c0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579308101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2579308101
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.691365184
Short name T459
Test name
Test status
Simulation time 240330688384 ps
CPU time 268.36 seconds
Started Aug 09 07:20:16 PM PDT 24
Finished Aug 09 07:24:44 PM PDT 24
Peak memory 199824 kb
Host smart-1be1d9db-f373-446a-8154-4a25e7c4c1ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=691365184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.691365184
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3240935218
Short name T655
Test name
Test status
Simulation time 7815692913 ps
CPU time 8.33 seconds
Started Aug 09 07:20:17 PM PDT 24
Finished Aug 09 07:20:25 PM PDT 24
Peak memory 199244 kb
Host smart-0d9b89d1-0981-4a81-a606-b767973c5042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240935218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3240935218
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.1158374353
Short name T572
Test name
Test status
Simulation time 162132675153 ps
CPU time 85.17 seconds
Started Aug 09 07:20:16 PM PDT 24
Finished Aug 09 07:21:41 PM PDT 24
Peak memory 199304 kb
Host smart-fb803d8e-bf02-41da-813c-8f277b00100b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158374353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1158374353
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.337383529
Short name T1123
Test name
Test status
Simulation time 5534507919 ps
CPU time 190.99 seconds
Started Aug 09 07:20:16 PM PDT 24
Finished Aug 09 07:23:27 PM PDT 24
Peak memory 199940 kb
Host smart-891025a5-491e-4a0b-b289-60caa5c76cbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=337383529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.337383529
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.2652056584
Short name T432
Test name
Test status
Simulation time 4305135821 ps
CPU time 16.45 seconds
Started Aug 09 07:20:16 PM PDT 24
Finished Aug 09 07:20:33 PM PDT 24
Peak memory 199340 kb
Host smart-072384f7-4853-43d5-97ba-8e65ea102a99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2652056584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2652056584
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.4176826717
Short name T848
Test name
Test status
Simulation time 352885246197 ps
CPU time 136.2 seconds
Started Aug 09 07:20:15 PM PDT 24
Finished Aug 09 07:22:31 PM PDT 24
Peak memory 199964 kb
Host smart-76296ef5-de25-4788-a54c-9d90538b0aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176826717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.4176826717
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.4107111748
Short name T45
Test name
Test status
Simulation time 45223837944 ps
CPU time 73.4 seconds
Started Aug 09 07:20:16 PM PDT 24
Finished Aug 09 07:21:30 PM PDT 24
Peak memory 195820 kb
Host smart-e6b0358b-e6f6-4ccf-8310-2cb1a74b435d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107111748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.4107111748
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1512380149
Short name T488
Test name
Test status
Simulation time 328775319 ps
CPU time 1.31 seconds
Started Aug 09 07:20:17 PM PDT 24
Finished Aug 09 07:20:18 PM PDT 24
Peak memory 199404 kb
Host smart-96f545bb-ca77-411f-b49e-19076b504600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512380149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1512380149
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.2578892992
Short name T858
Test name
Test status
Simulation time 43252038577 ps
CPU time 36.61 seconds
Started Aug 09 07:20:13 PM PDT 24
Finished Aug 09 07:20:50 PM PDT 24
Peak memory 199932 kb
Host smart-36b250e7-ee06-41ef-94ac-2868f7b93d21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578892992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2578892992
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.507526953
Short name T663
Test name
Test status
Simulation time 27220890574 ps
CPU time 641.25 seconds
Started Aug 09 07:20:15 PM PDT 24
Finished Aug 09 07:30:56 PM PDT 24
Peak memory 208080 kb
Host smart-e1208eb0-77ce-47a7-b78b-da48059f550a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507526953 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.507526953
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.884354964
Short name T366
Test name
Test status
Simulation time 1090371243 ps
CPU time 2 seconds
Started Aug 09 07:20:16 PM PDT 24
Finished Aug 09 07:20:18 PM PDT 24
Peak memory 198264 kb
Host smart-9e95f117-8660-48ba-b2ea-690a2f0a4f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884354964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.884354964
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.4226838722
Short name T573
Test name
Test status
Simulation time 101143161190 ps
CPU time 36.82 seconds
Started Aug 09 07:20:14 PM PDT 24
Finished Aug 09 07:20:51 PM PDT 24
Peak memory 199960 kb
Host smart-638e2356-dd58-49c7-a6d8-7741a2b7c017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226838722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.4226838722
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.193803288
Short name T1119
Test name
Test status
Simulation time 7248544865 ps
CPU time 11.41 seconds
Started Aug 09 07:24:52 PM PDT 24
Finished Aug 09 07:25:04 PM PDT 24
Peak memory 198312 kb
Host smart-5392b2e0-a422-405a-954a-e31c132e7bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193803288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.193803288
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2558503577
Short name T100
Test name
Test status
Simulation time 108719680690 ps
CPU time 216.45 seconds
Started Aug 09 07:24:55 PM PDT 24
Finished Aug 09 07:28:31 PM PDT 24
Peak memory 199952 kb
Host smart-f57de580-7792-4a89-a331-9c3e0550121c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558503577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2558503577
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3772763719
Short name T1059
Test name
Test status
Simulation time 85540537075 ps
CPU time 195.48 seconds
Started Aug 09 07:24:53 PM PDT 24
Finished Aug 09 07:28:08 PM PDT 24
Peak memory 199896 kb
Host smart-b8120052-1224-4d45-810d-465243083dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772763719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3772763719
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.199334648
Short name T115
Test name
Test status
Simulation time 28564456632 ps
CPU time 43.48 seconds
Started Aug 09 07:24:55 PM PDT 24
Finished Aug 09 07:25:38 PM PDT 24
Peak memory 199488 kb
Host smart-e357d05a-33e7-486d-8c8e-19c92f900504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199334648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.199334648
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.906031636
Short name T471
Test name
Test status
Simulation time 33446470692 ps
CPU time 26.55 seconds
Started Aug 09 07:24:53 PM PDT 24
Finished Aug 09 07:25:20 PM PDT 24
Peak memory 199976 kb
Host smart-7738201e-aa55-4171-a2f4-46911a1b75d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906031636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.906031636
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.351003322
Short name T1151
Test name
Test status
Simulation time 73640268398 ps
CPU time 107.91 seconds
Started Aug 09 07:24:53 PM PDT 24
Finished Aug 09 07:26:41 PM PDT 24
Peak memory 199672 kb
Host smart-58f71a76-bb49-47d8-9fdc-7a0bdddfdac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351003322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.351003322
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.230196050
Short name T748
Test name
Test status
Simulation time 78119070845 ps
CPU time 389.39 seconds
Started Aug 09 07:24:54 PM PDT 24
Finished Aug 09 07:31:23 PM PDT 24
Peak memory 199908 kb
Host smart-1926cf1b-171c-4e66-b2a0-8747eec9af37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230196050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.230196050
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1815357175
Short name T42
Test name
Test status
Simulation time 42694727913 ps
CPU time 22.46 seconds
Started Aug 09 07:25:01 PM PDT 24
Finished Aug 09 07:25:23 PM PDT 24
Peak memory 199920 kb
Host smart-45ed0c64-ff79-4ffe-8b86-172986b8b7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815357175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1815357175
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.485025852
Short name T965
Test name
Test status
Simulation time 17968372 ps
CPU time 0.54 seconds
Started Aug 09 07:20:25 PM PDT 24
Finished Aug 09 07:20:25 PM PDT 24
Peak memory 195320 kb
Host smart-20f34529-9f48-412f-a807-1efa4e5b8ec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485025852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.485025852
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1083168026
Short name T680
Test name
Test status
Simulation time 27458867764 ps
CPU time 60.78 seconds
Started Aug 09 07:20:15 PM PDT 24
Finished Aug 09 07:21:16 PM PDT 24
Peak memory 199944 kb
Host smart-d0337602-738c-45ac-8f55-082b199ba619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083168026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1083168026
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.483598227
Short name T1070
Test name
Test status
Simulation time 113747770636 ps
CPU time 115.3 seconds
Started Aug 09 07:20:17 PM PDT 24
Finished Aug 09 07:22:12 PM PDT 24
Peak memory 199924 kb
Host smart-4b1e8ec4-c915-4a02-8b49-b4fd918b2567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483598227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.483598227
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3650088590
Short name T905
Test name
Test status
Simulation time 61484119390 ps
CPU time 90.87 seconds
Started Aug 09 07:20:14 PM PDT 24
Finished Aug 09 07:21:45 PM PDT 24
Peak memory 199944 kb
Host smart-7439e139-5916-4074-93fc-146e3338affc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650088590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3650088590
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.1842126918
Short name T828
Test name
Test status
Simulation time 101218174456 ps
CPU time 49.21 seconds
Started Aug 09 07:20:26 PM PDT 24
Finished Aug 09 07:21:15 PM PDT 24
Peak memory 199872 kb
Host smart-8a335b1c-1c88-480a-a7f4-08eb459088b8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842126918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1842126918
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.3494254334
Short name T934
Test name
Test status
Simulation time 83858668786 ps
CPU time 426.36 seconds
Started Aug 09 07:20:25 PM PDT 24
Finished Aug 09 07:27:31 PM PDT 24
Peak memory 199968 kb
Host smart-5774deb4-67c4-4638-93b8-0c3760f97413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3494254334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3494254334
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1829700201
Short name T902
Test name
Test status
Simulation time 8454426217 ps
CPU time 5.96 seconds
Started Aug 09 07:20:25 PM PDT 24
Finished Aug 09 07:20:31 PM PDT 24
Peak memory 199844 kb
Host smart-0757559c-1985-409e-adca-1d26d283c4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829700201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1829700201
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3745918623
Short name T536
Test name
Test status
Simulation time 10224238180 ps
CPU time 18.58 seconds
Started Aug 09 07:20:24 PM PDT 24
Finished Aug 09 07:20:43 PM PDT 24
Peak memory 198872 kb
Host smart-3bf9e7ae-c528-4025-829d-db087dc4244a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745918623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3745918623
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.2540401133
Short name T903
Test name
Test status
Simulation time 16844362963 ps
CPU time 90.33 seconds
Started Aug 09 07:20:24 PM PDT 24
Finished Aug 09 07:21:54 PM PDT 24
Peak memory 199884 kb
Host smart-0a585d23-d1db-4c27-9705-1a1be4d53ea4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2540401133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2540401133
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.984410926
Short name T365
Test name
Test status
Simulation time 5935868835 ps
CPU time 12 seconds
Started Aug 09 07:20:14 PM PDT 24
Finished Aug 09 07:20:26 PM PDT 24
Peak memory 197916 kb
Host smart-08d64786-596f-4c4d-8422-a914125c4aa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=984410926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.984410926
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1954297098
Short name T416
Test name
Test status
Simulation time 21605953777 ps
CPU time 44.54 seconds
Started Aug 09 07:20:25 PM PDT 24
Finished Aug 09 07:21:10 PM PDT 24
Peak memory 199668 kb
Host smart-3760181d-99a8-4aec-83f7-ccfddd9b578e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954297098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1954297098
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1147380886
Short name T300
Test name
Test status
Simulation time 5039174014 ps
CPU time 2.02 seconds
Started Aug 09 07:20:26 PM PDT 24
Finished Aug 09 07:20:28 PM PDT 24
Peak memory 196532 kb
Host smart-54db1619-e212-4b28-9e75-0f18a7c9ed3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147380886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1147380886
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3164831646
Short name T431
Test name
Test status
Simulation time 5476060966 ps
CPU time 10.89 seconds
Started Aug 09 07:20:15 PM PDT 24
Finished Aug 09 07:20:26 PM PDT 24
Peak memory 199900 kb
Host smart-579eb000-787d-4514-98f9-d44e4452effb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164831646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3164831646
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2384716948
Short name T523
Test name
Test status
Simulation time 210020571341 ps
CPU time 703.92 seconds
Started Aug 09 07:20:27 PM PDT 24
Finished Aug 09 07:32:11 PM PDT 24
Peak memory 199992 kb
Host smart-d64dd90c-049f-488a-8a24-27631528e4b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384716948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2384716948
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.449396370
Short name T34
Test name
Test status
Simulation time 150489024273 ps
CPU time 479.58 seconds
Started Aug 09 07:20:25 PM PDT 24
Finished Aug 09 07:28:24 PM PDT 24
Peak memory 226960 kb
Host smart-3fbad0c1-e9cf-4f55-a9be-375fca85b29d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449396370 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.449396370
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.4270892833
Short name T986
Test name
Test status
Simulation time 408306789 ps
CPU time 1.75 seconds
Started Aug 09 07:20:24 PM PDT 24
Finished Aug 09 07:20:26 PM PDT 24
Peak memory 199576 kb
Host smart-31d8c399-86da-4290-a4d1-4f8a1d83e2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270892833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.4270892833
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3641169631
Short name T1042
Test name
Test status
Simulation time 77787753674 ps
CPU time 37.21 seconds
Started Aug 09 07:20:17 PM PDT 24
Finished Aug 09 07:20:54 PM PDT 24
Peak memory 199960 kb
Host smart-f3bd5613-d282-41d1-8cd5-9003b431d71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641169631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3641169631
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1208311625
Short name T224
Test name
Test status
Simulation time 80888923499 ps
CPU time 212.84 seconds
Started Aug 09 07:25:04 PM PDT 24
Finished Aug 09 07:28:37 PM PDT 24
Peak memory 199964 kb
Host smart-f8cd759d-c6ca-4e8c-94e7-3d79e3066968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208311625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1208311625
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.4170319682
Short name T608
Test name
Test status
Simulation time 87743265513 ps
CPU time 43.21 seconds
Started Aug 09 07:25:01 PM PDT 24
Finished Aug 09 07:25:44 PM PDT 24
Peak memory 199956 kb
Host smart-6cf1e3f5-6507-40e7-b987-95634568f237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170319682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.4170319682
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3481210570
Short name T921
Test name
Test status
Simulation time 21751746231 ps
CPU time 36.16 seconds
Started Aug 09 07:25:01 PM PDT 24
Finished Aug 09 07:25:37 PM PDT 24
Peak memory 199964 kb
Host smart-1c98be57-6023-457c-bf10-3afd0546366c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481210570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3481210570
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.650615630
Short name T219
Test name
Test status
Simulation time 35434708137 ps
CPU time 15.8 seconds
Started Aug 09 07:25:03 PM PDT 24
Finished Aug 09 07:25:19 PM PDT 24
Peak memory 199960 kb
Host smart-40137a65-6cf3-4e35-a2af-8f298cd0ad8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650615630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.650615630
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3138811922
Short name T1093
Test name
Test status
Simulation time 108367890923 ps
CPU time 165.28 seconds
Started Aug 09 07:25:02 PM PDT 24
Finished Aug 09 07:27:47 PM PDT 24
Peak memory 199852 kb
Host smart-2366792f-f983-42e0-ad9f-bba205de5dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138811922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3138811922
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1655539396
Short name T714
Test name
Test status
Simulation time 63106678769 ps
CPU time 98.64 seconds
Started Aug 09 07:25:04 PM PDT 24
Finished Aug 09 07:26:42 PM PDT 24
Peak memory 199640 kb
Host smart-3d0df3f5-ef1c-4730-9a89-016920acd59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655539396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1655539396
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1254972409
Short name T188
Test name
Test status
Simulation time 147079220696 ps
CPU time 77.27 seconds
Started Aug 09 07:25:01 PM PDT 24
Finished Aug 09 07:26:18 PM PDT 24
Peak memory 199824 kb
Host smart-c93a1624-c306-4e3f-9b6c-c95ea2d92729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254972409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1254972409
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1137446841
Short name T205
Test name
Test status
Simulation time 186013804323 ps
CPU time 67.43 seconds
Started Aug 09 07:25:01 PM PDT 24
Finished Aug 09 07:26:08 PM PDT 24
Peak memory 199896 kb
Host smart-1df776f3-87c2-4cf5-8e06-7bac4856ed9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137446841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1137446841
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.236421023
Short name T875
Test name
Test status
Simulation time 315105983659 ps
CPU time 33.45 seconds
Started Aug 09 07:25:03 PM PDT 24
Finished Aug 09 07:25:36 PM PDT 24
Peak memory 199900 kb
Host smart-fc9b5960-6ed2-47b9-b881-ec6cd2882246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236421023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.236421023
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.358751006
Short name T588
Test name
Test status
Simulation time 13878179 ps
CPU time 0.56 seconds
Started Aug 09 07:20:27 PM PDT 24
Finished Aug 09 07:20:28 PM PDT 24
Peak memory 195356 kb
Host smart-b3059195-315a-440e-a014-d562241dcb9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358751006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.358751006
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.828226515
Short name T1036
Test name
Test status
Simulation time 13394744970 ps
CPU time 7.21 seconds
Started Aug 09 07:20:27 PM PDT 24
Finished Aug 09 07:20:34 PM PDT 24
Peak memory 199912 kb
Host smart-70103d3d-8e86-4fc1-92bd-5e6ec8e43486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828226515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.828226515
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2088240644
Short name T656
Test name
Test status
Simulation time 26771468569 ps
CPU time 20.61 seconds
Started Aug 09 07:20:24 PM PDT 24
Finished Aug 09 07:20:45 PM PDT 24
Peak memory 199720 kb
Host smart-eaee6df2-c7e4-4841-bf41-b8fe9e74802e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088240644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2088240644
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.92760507
Short name T884
Test name
Test status
Simulation time 157628383842 ps
CPU time 43.76 seconds
Started Aug 09 07:20:25 PM PDT 24
Finished Aug 09 07:21:09 PM PDT 24
Peak memory 199972 kb
Host smart-fef1bcdd-168f-40a1-a8f9-04f711932699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92760507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.92760507
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.2961347786
Short name T914
Test name
Test status
Simulation time 255324336533 ps
CPU time 359.84 seconds
Started Aug 09 07:20:25 PM PDT 24
Finished Aug 09 07:26:25 PM PDT 24
Peak memory 199808 kb
Host smart-7821a9a5-ca99-479c-8037-00b770ed5044
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961347786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2961347786
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_loopback.197897844
Short name T537
Test name
Test status
Simulation time 12987559887 ps
CPU time 14.45 seconds
Started Aug 09 07:20:23 PM PDT 24
Finished Aug 09 07:20:38 PM PDT 24
Peak memory 199904 kb
Host smart-ce951f45-976f-41c1-b5ce-b32eb44a3c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197897844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.197897844
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.2893989374
Short name T428
Test name
Test status
Simulation time 28524991811 ps
CPU time 45.18 seconds
Started Aug 09 07:20:23 PM PDT 24
Finished Aug 09 07:21:09 PM PDT 24
Peak memory 199104 kb
Host smart-e03eb389-c0fc-48d7-85f1-654308cbe42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893989374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2893989374
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3297643682
Short name T397
Test name
Test status
Simulation time 14585071655 ps
CPU time 146.78 seconds
Started Aug 09 07:20:25 PM PDT 24
Finished Aug 09 07:22:52 PM PDT 24
Peak memory 199956 kb
Host smart-6f069c84-007d-4125-8096-bdfbac72fa1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3297643682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3297643682
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3725146492
Short name T501
Test name
Test status
Simulation time 3879208087 ps
CPU time 8.25 seconds
Started Aug 09 07:20:27 PM PDT 24
Finished Aug 09 07:20:35 PM PDT 24
Peak memory 198980 kb
Host smart-845034d1-34ea-4f10-b58e-1155f2aafe20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3725146492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3725146492
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2368986206
Short name T896
Test name
Test status
Simulation time 124524593291 ps
CPU time 88.97 seconds
Started Aug 09 07:20:25 PM PDT 24
Finished Aug 09 07:21:54 PM PDT 24
Peak memory 199944 kb
Host smart-a33a7949-0e24-4afd-857f-6ea59ee46da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368986206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2368986206
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3499234953
Short name T472
Test name
Test status
Simulation time 36521044105 ps
CPU time 20.64 seconds
Started Aug 09 07:20:27 PM PDT 24
Finished Aug 09 07:20:48 PM PDT 24
Peak memory 196284 kb
Host smart-823c8e79-def8-44ce-b83f-6955755846de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499234953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3499234953
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3740167665
Short name T62
Test name
Test status
Simulation time 5335198155 ps
CPU time 8.51 seconds
Started Aug 09 07:20:27 PM PDT 24
Finished Aug 09 07:20:35 PM PDT 24
Peak memory 199972 kb
Host smart-9b0516a3-ef52-4a21-8326-e9cac4ede80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740167665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3740167665
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.4260629096
Short name T1160
Test name
Test status
Simulation time 586284231010 ps
CPU time 1749.49 seconds
Started Aug 09 07:20:27 PM PDT 24
Finished Aug 09 07:49:37 PM PDT 24
Peak memory 199972 kb
Host smart-012ae0e4-087a-491e-b260-49601f9681ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260629096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.4260629096
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3171359641
Short name T1169
Test name
Test status
Simulation time 36614376081 ps
CPU time 255.6 seconds
Started Aug 09 07:20:25 PM PDT 24
Finished Aug 09 07:24:41 PM PDT 24
Peak memory 213656 kb
Host smart-a26b52f1-8bb6-4365-86e2-4eedafc7fe07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171359641 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3171359641
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1949040436
Short name T1084
Test name
Test status
Simulation time 17059803832 ps
CPU time 11.06 seconds
Started Aug 09 07:20:27 PM PDT 24
Finished Aug 09 07:20:38 PM PDT 24
Peak memory 199972 kb
Host smart-dca8ce26-53a0-4d3d-aa85-ce9ad9069059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949040436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1949040436
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.86591291
Short name T111
Test name
Test status
Simulation time 16591397505 ps
CPU time 26.22 seconds
Started Aug 09 07:20:25 PM PDT 24
Finished Aug 09 07:20:51 PM PDT 24
Peak memory 199940 kb
Host smart-ff969f4a-3bb8-49cc-b1cc-87d9d1b199e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86591291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.86591291
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3577825840
Short name T669
Test name
Test status
Simulation time 150375790924 ps
CPU time 100.86 seconds
Started Aug 09 07:25:02 PM PDT 24
Finished Aug 09 07:26:43 PM PDT 24
Peak memory 199968 kb
Host smart-40301ea8-817e-41c0-bc88-647e20b7cc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577825840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3577825840
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1886032206
Short name T913
Test name
Test status
Simulation time 13435171714 ps
CPU time 12.37 seconds
Started Aug 09 07:25:01 PM PDT 24
Finished Aug 09 07:25:13 PM PDT 24
Peak memory 199940 kb
Host smart-e425a9c1-dc21-4a1f-a07b-c8dd88429cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886032206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1886032206
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3716649888
Short name T426
Test name
Test status
Simulation time 94187416548 ps
CPU time 91.43 seconds
Started Aug 09 07:25:00 PM PDT 24
Finished Aug 09 07:26:32 PM PDT 24
Peak memory 199936 kb
Host smart-cb785b71-cd04-4cbe-a2aa-f097999a2591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716649888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3716649888
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3048085201
Short name T1082
Test name
Test status
Simulation time 131496449292 ps
CPU time 29.28 seconds
Started Aug 09 07:25:11 PM PDT 24
Finished Aug 09 07:25:40 PM PDT 24
Peak memory 199836 kb
Host smart-d2be7b24-047a-40a6-90b3-10747b6c69ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048085201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3048085201
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3614896981
Short name T1055
Test name
Test status
Simulation time 66972842051 ps
CPU time 131.9 seconds
Started Aug 09 07:25:11 PM PDT 24
Finished Aug 09 07:27:23 PM PDT 24
Peak memory 199992 kb
Host smart-07b6e6e3-3104-4c78-911d-d0a44aa93889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614896981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3614896981
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2950935190
Short name T950
Test name
Test status
Simulation time 125724153049 ps
CPU time 66.17 seconds
Started Aug 09 07:25:10 PM PDT 24
Finished Aug 09 07:26:16 PM PDT 24
Peak memory 199892 kb
Host smart-02d2d62b-48f9-414e-a5d3-edf94c9fccdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950935190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2950935190
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3258287900
Short name T194
Test name
Test status
Simulation time 24899539983 ps
CPU time 43.74 seconds
Started Aug 09 07:25:10 PM PDT 24
Finished Aug 09 07:25:53 PM PDT 24
Peak memory 199912 kb
Host smart-f4f7d9d0-8935-4b9c-8711-99fe588db7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258287900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3258287900
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.640730515
Short name T743
Test name
Test status
Simulation time 11673514770 ps
CPU time 16.32 seconds
Started Aug 09 07:25:11 PM PDT 24
Finished Aug 09 07:25:27 PM PDT 24
Peak memory 199988 kb
Host smart-4f7b662b-8fad-43cd-b6e2-af097c1ab8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640730515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.640730515
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3429796438
Short name T222
Test name
Test status
Simulation time 86372568485 ps
CPU time 222.77 seconds
Started Aug 09 07:25:10 PM PDT 24
Finished Aug 09 07:28:53 PM PDT 24
Peak memory 199984 kb
Host smart-13fe7c1b-a1fa-41ff-b9f0-b815ad3031be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429796438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3429796438
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3928023160
Short name T210
Test name
Test status
Simulation time 18483224860 ps
CPU time 19.22 seconds
Started Aug 09 07:25:12 PM PDT 24
Finished Aug 09 07:25:31 PM PDT 24
Peak memory 199956 kb
Host smart-5e42d31e-c4c6-4122-9fb1-e395582acc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928023160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3928023160
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.112725903
Short name T775
Test name
Test status
Simulation time 108667636 ps
CPU time 0.57 seconds
Started Aug 09 07:20:38 PM PDT 24
Finished Aug 09 07:20:39 PM PDT 24
Peak memory 195360 kb
Host smart-5637ac00-1641-4fb5-b0c3-281e65e58600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112725903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.112725903
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3343833391
Short name T1062
Test name
Test status
Simulation time 103205902132 ps
CPU time 213.09 seconds
Started Aug 09 07:20:26 PM PDT 24
Finished Aug 09 07:23:59 PM PDT 24
Peak memory 199956 kb
Host smart-b25e9d7c-f978-4bc4-af26-9589dc1e6775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343833391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3343833391
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.4163107830
Short name T370
Test name
Test status
Simulation time 20428385535 ps
CPU time 31.25 seconds
Started Aug 09 07:20:25 PM PDT 24
Finished Aug 09 07:20:57 PM PDT 24
Peak memory 199564 kb
Host smart-f068b400-3d53-40ca-9745-1338686b8408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163107830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.4163107830
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2329418498
Short name T221
Test name
Test status
Simulation time 37639612254 ps
CPU time 58.44 seconds
Started Aug 09 07:20:26 PM PDT 24
Finished Aug 09 07:21:25 PM PDT 24
Peak memory 199900 kb
Host smart-55db4660-368a-4ae2-ab87-5fc3700694a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329418498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2329418498
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.2697280029
Short name T742
Test name
Test status
Simulation time 61869754209 ps
CPU time 52.89 seconds
Started Aug 09 07:20:37 PM PDT 24
Finished Aug 09 07:21:30 PM PDT 24
Peak memory 199820 kb
Host smart-b620eca1-f310-4fa7-9028-1f58e8af27ac
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697280029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2697280029
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3510190825
Short name T36
Test name
Test status
Simulation time 117530913064 ps
CPU time 330.5 seconds
Started Aug 09 07:20:37 PM PDT 24
Finished Aug 09 07:26:08 PM PDT 24
Peak memory 199972 kb
Host smart-8d914487-f67b-4c10-908b-b027906810d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3510190825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3510190825
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2608201656
Short name T684
Test name
Test status
Simulation time 227401885 ps
CPU time 0.81 seconds
Started Aug 09 07:20:39 PM PDT 24
Finished Aug 09 07:20:39 PM PDT 24
Peak memory 195844 kb
Host smart-e2813b08-7328-4b4d-9bcb-fc97f2ccc1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608201656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2608201656
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.4105210814
Short name T514
Test name
Test status
Simulation time 19435660272 ps
CPU time 26.53 seconds
Started Aug 09 07:20:35 PM PDT 24
Finished Aug 09 07:21:01 PM PDT 24
Peak memory 200064 kb
Host smart-6247b793-ff41-44d9-90eb-04e5a1ffb63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105210814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.4105210814
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2867514513
Short name T1102
Test name
Test status
Simulation time 7529358949 ps
CPU time 125.18 seconds
Started Aug 09 07:20:37 PM PDT 24
Finished Aug 09 07:22:42 PM PDT 24
Peak memory 199956 kb
Host smart-82e1800a-e227-45c6-9928-f151ee178d86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2867514513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2867514513
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1164268994
Short name T542
Test name
Test status
Simulation time 4831077508 ps
CPU time 10.81 seconds
Started Aug 09 07:20:38 PM PDT 24
Finished Aug 09 07:20:49 PM PDT 24
Peak memory 199208 kb
Host smart-558d5c70-000c-4edd-90f9-73f3906addc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1164268994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1164268994
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2096490004
Short name T724
Test name
Test status
Simulation time 156954204845 ps
CPU time 217.73 seconds
Started Aug 09 07:20:37 PM PDT 24
Finished Aug 09 07:24:15 PM PDT 24
Peak memory 199892 kb
Host smart-b36810af-3cc9-40ed-bf92-439d0554afa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096490004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2096490004
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1809360566
Short name T643
Test name
Test status
Simulation time 35763408704 ps
CPU time 15.5 seconds
Started Aug 09 07:20:41 PM PDT 24
Finished Aug 09 07:20:57 PM PDT 24
Peak memory 195920 kb
Host smart-774ed200-e7b5-43dc-a179-2ed3576d2abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809360566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1809360566
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1264638651
Short name T558
Test name
Test status
Simulation time 6123271128 ps
CPU time 4.97 seconds
Started Aug 09 07:20:27 PM PDT 24
Finished Aug 09 07:20:32 PM PDT 24
Peak memory 199896 kb
Host smart-1a3dcdb3-38d4-48a5-a7ca-bfff5ce9c92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264638651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1264638651
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1283554477
Short name T1161
Test name
Test status
Simulation time 181865026110 ps
CPU time 73.08 seconds
Started Aug 09 07:20:37 PM PDT 24
Finished Aug 09 07:21:50 PM PDT 24
Peak memory 200104 kb
Host smart-fc27d5fd-f848-4d9c-9953-0fa7a25f80fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283554477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1283554477
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1471251656
Short name T1054
Test name
Test status
Simulation time 1633649043 ps
CPU time 1.98 seconds
Started Aug 09 07:20:35 PM PDT 24
Finished Aug 09 07:20:37 PM PDT 24
Peak memory 199636 kb
Host smart-f28cb680-0ae3-495a-8ff7-4287a8059972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471251656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1471251656
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3631681175
Short name T503
Test name
Test status
Simulation time 168239012166 ps
CPU time 42.36 seconds
Started Aug 09 07:20:25 PM PDT 24
Finished Aug 09 07:21:08 PM PDT 24
Peak memory 200104 kb
Host smart-668b0695-0011-4321-8219-03e2e76531e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631681175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3631681175
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.132920792
Short name T1157
Test name
Test status
Simulation time 39223428006 ps
CPU time 56.64 seconds
Started Aug 09 07:25:11 PM PDT 24
Finished Aug 09 07:26:08 PM PDT 24
Peak memory 199952 kb
Host smart-47e0c26b-c9c9-4c3c-80ef-08e624f2b563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132920792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.132920792
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1862892912
Short name T182
Test name
Test status
Simulation time 12465195739 ps
CPU time 18.83 seconds
Started Aug 09 07:25:12 PM PDT 24
Finished Aug 09 07:25:31 PM PDT 24
Peak memory 200112 kb
Host smart-e1013799-8f9c-4b3c-9690-308d9c4aec95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862892912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1862892912
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2425582356
Short name T332
Test name
Test status
Simulation time 63263992771 ps
CPU time 41.86 seconds
Started Aug 09 07:25:13 PM PDT 24
Finished Aug 09 07:25:54 PM PDT 24
Peak memory 199932 kb
Host smart-f7ca4dfb-2b60-433a-8f70-caa0a715a01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425582356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2425582356
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1713443118
Short name T1168
Test name
Test status
Simulation time 27483511361 ps
CPU time 51.14 seconds
Started Aug 09 07:25:10 PM PDT 24
Finished Aug 09 07:26:01 PM PDT 24
Peak memory 199884 kb
Host smart-6333337a-2ffb-4f42-8ac6-3f5dc3976dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713443118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1713443118
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.556130460
Short name T773
Test name
Test status
Simulation time 108096046834 ps
CPU time 242.6 seconds
Started Aug 09 07:25:10 PM PDT 24
Finished Aug 09 07:29:13 PM PDT 24
Peak memory 199900 kb
Host smart-d01ebcbe-dbbe-463e-91cf-b3d1769f347f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556130460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.556130460
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.953806545
Short name T177
Test name
Test status
Simulation time 11172132562 ps
CPU time 18.77 seconds
Started Aug 09 07:25:10 PM PDT 24
Finished Aug 09 07:25:29 PM PDT 24
Peak memory 199848 kb
Host smart-9388677b-b2d2-481a-a381-78641304bab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953806545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.953806545
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1353739464
Short name T780
Test name
Test status
Simulation time 105276030909 ps
CPU time 149.74 seconds
Started Aug 09 07:25:11 PM PDT 24
Finished Aug 09 07:27:41 PM PDT 24
Peak memory 200168 kb
Host smart-77e11424-a8d1-4001-a42e-92b8f0989e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353739464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1353739464
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3113390241
Short name T1143
Test name
Test status
Simulation time 95215027452 ps
CPU time 22.27 seconds
Started Aug 09 07:25:10 PM PDT 24
Finished Aug 09 07:25:32 PM PDT 24
Peak memory 199832 kb
Host smart-0d7bd1f1-c9e8-4f93-a611-c30f0030aa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113390241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3113390241
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3615087283
Short name T966
Test name
Test status
Simulation time 14069433 ps
CPU time 0.57 seconds
Started Aug 09 07:20:37 PM PDT 24
Finished Aug 09 07:20:38 PM PDT 24
Peak memory 194328 kb
Host smart-81fa52e9-25cf-4390-a068-c915deb7c6ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615087283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3615087283
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.467893210
Short name T336
Test name
Test status
Simulation time 160454813914 ps
CPU time 246.67 seconds
Started Aug 09 07:20:38 PM PDT 24
Finished Aug 09 07:24:45 PM PDT 24
Peak memory 199984 kb
Host smart-1002b49f-6b3d-4fbf-90ea-03d67af01c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467893210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.467893210
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.4061899950
Short name T541
Test name
Test status
Simulation time 16282878407 ps
CPU time 23.51 seconds
Started Aug 09 07:20:36 PM PDT 24
Finished Aug 09 07:21:00 PM PDT 24
Peak memory 200000 kb
Host smart-09ff26a7-7cd9-495e-b53f-e1ed2b25be56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061899950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.4061899950
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1466745975
Short name T239
Test name
Test status
Simulation time 26441830544 ps
CPU time 38.19 seconds
Started Aug 09 07:20:37 PM PDT 24
Finished Aug 09 07:21:15 PM PDT 24
Peak memory 199908 kb
Host smart-bb7e44d1-6a10-4681-8f45-1e23e243b27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466745975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1466745975
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.2985412422
Short name T532
Test name
Test status
Simulation time 63126877604 ps
CPU time 136.54 seconds
Started Aug 09 07:20:37 PM PDT 24
Finished Aug 09 07:22:54 PM PDT 24
Peak memory 199940 kb
Host smart-905ed4e1-3ed5-4411-b22d-296703142bda
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985412422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2985412422
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3016789091
Short name T270
Test name
Test status
Simulation time 71008100629 ps
CPU time 288.47 seconds
Started Aug 09 07:20:39 PM PDT 24
Finished Aug 09 07:25:27 PM PDT 24
Peak memory 199908 kb
Host smart-66e911bf-c57d-4d0e-88ec-77ab49fd517f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3016789091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3016789091
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2073066475
Short name T590
Test name
Test status
Simulation time 775963442 ps
CPU time 1.36 seconds
Started Aug 09 07:20:38 PM PDT 24
Finished Aug 09 07:20:39 PM PDT 24
Peak memory 197608 kb
Host smart-565d2b91-8723-4e12-8a33-f3cca5477b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073066475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2073066475
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.905269731
Short name T735
Test name
Test status
Simulation time 153027087093 ps
CPU time 233.51 seconds
Started Aug 09 07:20:37 PM PDT 24
Finished Aug 09 07:24:31 PM PDT 24
Peak memory 200256 kb
Host smart-6ced2b77-84f3-4067-8b5c-0b8c02a99703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905269731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.905269731
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.450789805
Short name T1164
Test name
Test status
Simulation time 8267686264 ps
CPU time 243.85 seconds
Started Aug 09 07:20:37 PM PDT 24
Finished Aug 09 07:24:41 PM PDT 24
Peak memory 199964 kb
Host smart-6fcffd8e-98c4-449e-8287-fc1b78489648
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=450789805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.450789805
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1621181470
Short name T729
Test name
Test status
Simulation time 3962408227 ps
CPU time 15.73 seconds
Started Aug 09 07:20:38 PM PDT 24
Finished Aug 09 07:20:54 PM PDT 24
Peak memory 198320 kb
Host smart-1e4b9a3d-53e3-48c6-9790-82adb558e3dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1621181470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1621181470
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.4042723481
Short name T809
Test name
Test status
Simulation time 60529374391 ps
CPU time 132.18 seconds
Started Aug 09 07:20:37 PM PDT 24
Finished Aug 09 07:22:49 PM PDT 24
Peak memory 199904 kb
Host smart-3d2c5074-5bfc-4e17-b53b-78e5718c9a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042723481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.4042723481
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1724117542
Short name T1067
Test name
Test status
Simulation time 91133280754 ps
CPU time 79.4 seconds
Started Aug 09 07:20:36 PM PDT 24
Finished Aug 09 07:21:55 PM PDT 24
Peak memory 196000 kb
Host smart-3aaa8076-abf7-4735-8bd5-5fc2055629fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724117542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1724117542
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1072267875
Short name T1001
Test name
Test status
Simulation time 486957720 ps
CPU time 2.41 seconds
Started Aug 09 07:20:36 PM PDT 24
Finished Aug 09 07:20:39 PM PDT 24
Peak memory 198440 kb
Host smart-b8c44d44-5f8c-4ac7-96e7-8cd4c076d6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072267875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1072267875
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.788126927
Short name T886
Test name
Test status
Simulation time 223217057564 ps
CPU time 1261.6 seconds
Started Aug 09 07:20:37 PM PDT 24
Finished Aug 09 07:41:38 PM PDT 24
Peak memory 208264 kb
Host smart-a9e82039-22f6-4031-beb2-12b2f199ab09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788126927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.788126927
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1118797639
Short name T52
Test name
Test status
Simulation time 127270116268 ps
CPU time 643.23 seconds
Started Aug 09 07:20:38 PM PDT 24
Finished Aug 09 07:31:21 PM PDT 24
Peak memory 224724 kb
Host smart-fb9d46e8-69dc-40e2-8340-9d301123362a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118797639 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1118797639
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.4023830050
Short name T350
Test name
Test status
Simulation time 461282817 ps
CPU time 1.46 seconds
Started Aug 09 07:20:37 PM PDT 24
Finished Aug 09 07:20:39 PM PDT 24
Peak memory 198700 kb
Host smart-c7b8aa4b-1d05-42ff-b749-1024c996f5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023830050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.4023830050
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.695906156
Short name T796
Test name
Test status
Simulation time 11493957453 ps
CPU time 8.49 seconds
Started Aug 09 07:20:38 PM PDT 24
Finished Aug 09 07:20:47 PM PDT 24
Peak memory 199756 kb
Host smart-513977f5-bf01-48a3-9b5c-5bad28b04d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695906156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.695906156
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2886207642
Short name T784
Test name
Test status
Simulation time 24546992625 ps
CPU time 33.03 seconds
Started Aug 09 07:25:11 PM PDT 24
Finished Aug 09 07:25:44 PM PDT 24
Peak memory 199944 kb
Host smart-9a5d73e0-4945-4c90-997f-53067fc5ef07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886207642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2886207642
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1282372161
Short name T925
Test name
Test status
Simulation time 14628829736 ps
CPU time 7.52 seconds
Started Aug 09 07:25:17 PM PDT 24
Finished Aug 09 07:25:24 PM PDT 24
Peak memory 199880 kb
Host smart-f8c9c9ee-d098-4004-ab01-53f6b8a99a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282372161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1282372161
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2758411648
Short name T1024
Test name
Test status
Simulation time 26067264613 ps
CPU time 66.63 seconds
Started Aug 09 07:25:20 PM PDT 24
Finished Aug 09 07:26:26 PM PDT 24
Peak memory 199900 kb
Host smart-6693dacf-4299-4733-b70f-383c021ec7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758411648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2758411648
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2128404136
Short name T873
Test name
Test status
Simulation time 45938455963 ps
CPU time 36.52 seconds
Started Aug 09 07:25:18 PM PDT 24
Finished Aug 09 07:25:55 PM PDT 24
Peak memory 199892 kb
Host smart-335956da-2f7d-490f-8af8-02da2b42d18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128404136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2128404136
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2212653883
Short name T888
Test name
Test status
Simulation time 21095110490 ps
CPU time 35.41 seconds
Started Aug 09 07:25:18 PM PDT 24
Finished Aug 09 07:25:54 PM PDT 24
Peak memory 199836 kb
Host smart-027f4ab7-44b5-47d2-b2b7-6ff7298f942b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212653883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2212653883
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.4173709913
Short name T312
Test name
Test status
Simulation time 41575606112 ps
CPU time 65.92 seconds
Started Aug 09 07:25:19 PM PDT 24
Finished Aug 09 07:26:25 PM PDT 24
Peak memory 199944 kb
Host smart-84087c69-7ae0-4003-a281-d59ddf4ad368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173709913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.4173709913
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3959657711
Short name T387
Test name
Test status
Simulation time 45204117812 ps
CPU time 19.5 seconds
Started Aug 09 07:25:18 PM PDT 24
Finished Aug 09 07:25:37 PM PDT 24
Peak memory 199696 kb
Host smart-b81d7661-c8a6-4d1c-a7bd-f48648effd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959657711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3959657711
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3800464472
Short name T755
Test name
Test status
Simulation time 82260347085 ps
CPU time 28.8 seconds
Started Aug 09 07:25:17 PM PDT 24
Finished Aug 09 07:25:47 PM PDT 24
Peak memory 199964 kb
Host smart-dda60363-3a02-4fbf-880a-daaf59e334fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800464472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3800464472
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2237736877
Short name T1126
Test name
Test status
Simulation time 72780214230 ps
CPU time 22.84 seconds
Started Aug 09 07:25:19 PM PDT 24
Finished Aug 09 07:25:42 PM PDT 24
Peak memory 199964 kb
Host smart-b41a621f-7804-4720-bf59-366612ab7c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237736877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2237736877
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2460095408
Short name T633
Test name
Test status
Simulation time 134696754379 ps
CPU time 205.26 seconds
Started Aug 09 07:25:18 PM PDT 24
Finished Aug 09 07:28:44 PM PDT 24
Peak memory 199904 kb
Host smart-9798c6ac-2fbf-449f-82b5-af36f60b106f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460095408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2460095408
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2620931777
Short name T1175
Test name
Test status
Simulation time 12510156 ps
CPU time 0.56 seconds
Started Aug 09 07:20:51 PM PDT 24
Finished Aug 09 07:20:52 PM PDT 24
Peak memory 194332 kb
Host smart-958e7351-89df-4012-bf64-c89f8c519428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620931777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2620931777
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.89268276
Short name T887
Test name
Test status
Simulation time 267093636558 ps
CPU time 214.27 seconds
Started Aug 09 07:20:39 PM PDT 24
Finished Aug 09 07:24:13 PM PDT 24
Peak memory 199908 kb
Host smart-a05390e7-fa19-4dae-8664-6afa4c901766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89268276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.89268276
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3505225464
Short name T958
Test name
Test status
Simulation time 154672778421 ps
CPU time 182.34 seconds
Started Aug 09 07:20:50 PM PDT 24
Finished Aug 09 07:23:53 PM PDT 24
Peak memory 199908 kb
Host smart-edb68a39-b0dd-41d7-8e4c-6c673e47e6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505225464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3505225464
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2887324224
Short name T1103
Test name
Test status
Simulation time 42943867810 ps
CPU time 122.9 seconds
Started Aug 09 07:20:50 PM PDT 24
Finished Aug 09 07:22:53 PM PDT 24
Peak memory 199988 kb
Host smart-175f1c07-cf7f-4667-b619-c584ad4f6a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887324224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2887324224
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.6449847
Short name T120
Test name
Test status
Simulation time 23568410875 ps
CPU time 17.78 seconds
Started Aug 09 07:20:51 PM PDT 24
Finished Aug 09 07:21:09 PM PDT 24
Peak memory 199460 kb
Host smart-d267ddc7-8f27-4334-9078-376eb685e736
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6449847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.6449847
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.264241575
Short name T601
Test name
Test status
Simulation time 150862239867 ps
CPU time 973.61 seconds
Started Aug 09 07:20:52 PM PDT 24
Finished Aug 09 07:37:06 PM PDT 24
Peak memory 199876 kb
Host smart-abe042d0-4578-4fe0-a1f0-3a0cacb49def
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=264241575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.264241575
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.246859092
Short name T1149
Test name
Test status
Simulation time 1733972851 ps
CPU time 3.07 seconds
Started Aug 09 07:20:49 PM PDT 24
Finished Aug 09 07:20:53 PM PDT 24
Peak memory 197420 kb
Host smart-cab755e3-f7b4-48d1-af18-3d8bc6e9877a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246859092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.246859092
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.791368406
Short name T840
Test name
Test status
Simulation time 179199054203 ps
CPU time 56.77 seconds
Started Aug 09 07:20:52 PM PDT 24
Finished Aug 09 07:21:49 PM PDT 24
Peak memory 208272 kb
Host smart-db35dcea-70d8-47d2-89a1-b64485231955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791368406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.791368406
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2928526471
Short name T555
Test name
Test status
Simulation time 5038041439 ps
CPU time 53.28 seconds
Started Aug 09 07:20:51 PM PDT 24
Finished Aug 09 07:21:44 PM PDT 24
Peak memory 200004 kb
Host smart-706a7ef8-2299-400b-b3ca-83eb1f0365f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2928526471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2928526471
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.886018565
Short name T402
Test name
Test status
Simulation time 6243626855 ps
CPU time 5.76 seconds
Started Aug 09 07:20:50 PM PDT 24
Finished Aug 09 07:20:56 PM PDT 24
Peak memory 198992 kb
Host smart-25965a9d-629d-42ef-8794-25c1a0926a92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=886018565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.886018565
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3706311112
Short name T731
Test name
Test status
Simulation time 41489406567 ps
CPU time 16.59 seconds
Started Aug 09 07:20:52 PM PDT 24
Finished Aug 09 07:21:09 PM PDT 24
Peak memory 199840 kb
Host smart-f20e420c-afc2-4a93-9071-0691b86d792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706311112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3706311112
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2809999539
Short name T1029
Test name
Test status
Simulation time 585410794 ps
CPU time 1.05 seconds
Started Aug 09 07:20:51 PM PDT 24
Finished Aug 09 07:20:52 PM PDT 24
Peak memory 195476 kb
Host smart-ea4c0d21-6193-4bfa-a1eb-cc80a29488ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809999539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2809999539
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3705848193
Short name T418
Test name
Test status
Simulation time 580113315 ps
CPU time 1.67 seconds
Started Aug 09 07:20:37 PM PDT 24
Finished Aug 09 07:20:39 PM PDT 24
Peak memory 199056 kb
Host smart-1a6c9a39-8219-4af1-a185-e6f3303edec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705848193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3705848193
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1869962261
Short name T962
Test name
Test status
Simulation time 603178744 ps
CPU time 1.16 seconds
Started Aug 09 07:20:50 PM PDT 24
Finished Aug 09 07:20:52 PM PDT 24
Peak memory 198340 kb
Host smart-78973804-2c86-4421-a6d2-91b40cd7771b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869962261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1869962261
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.4002548385
Short name T318
Test name
Test status
Simulation time 6728571588 ps
CPU time 10 seconds
Started Aug 09 07:20:38 PM PDT 24
Finished Aug 09 07:20:48 PM PDT 24
Peak memory 198884 kb
Host smart-9df2f84a-587a-4334-a423-0fc3eec9feaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002548385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.4002548385
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.3199996427
Short name T870
Test name
Test status
Simulation time 35249121014 ps
CPU time 15.34 seconds
Started Aug 09 07:25:18 PM PDT 24
Finished Aug 09 07:25:33 PM PDT 24
Peak memory 199268 kb
Host smart-81f5d5ce-4540-4b44-838c-79510685cc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199996427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3199996427
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1418764634
Short name T546
Test name
Test status
Simulation time 19088472015 ps
CPU time 32.29 seconds
Started Aug 09 07:25:17 PM PDT 24
Finished Aug 09 07:25:49 PM PDT 24
Peak memory 199940 kb
Host smart-63f7c5df-73b9-4d0e-aab5-73c89a8a0cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418764634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1418764634
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1523602187
Short name T274
Test name
Test status
Simulation time 8577006057 ps
CPU time 14.05 seconds
Started Aug 09 07:25:20 PM PDT 24
Finished Aug 09 07:25:34 PM PDT 24
Peak memory 199960 kb
Host smart-8a65f12f-dd3e-4242-8596-b50ef995712f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523602187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1523602187
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.620793410
Short name T144
Test name
Test status
Simulation time 124598838783 ps
CPU time 174.62 seconds
Started Aug 09 07:25:19 PM PDT 24
Finished Aug 09 07:28:14 PM PDT 24
Peak memory 199900 kb
Host smart-5680d82d-429e-4783-9696-8fa9da12d89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620793410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.620793410
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2843074618
Short name T630
Test name
Test status
Simulation time 10906889090 ps
CPU time 11.69 seconds
Started Aug 09 07:25:18 PM PDT 24
Finished Aug 09 07:25:30 PM PDT 24
Peak memory 199976 kb
Host smart-86560017-3ab9-4654-89e0-071c9ef328e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843074618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2843074618
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.4003671686
Short name T649
Test name
Test status
Simulation time 20363170375 ps
CPU time 34.39 seconds
Started Aug 09 07:25:18 PM PDT 24
Finished Aug 09 07:25:53 PM PDT 24
Peak memory 199980 kb
Host smart-4af04300-bff4-413f-af55-81092e445b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003671686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.4003671686
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1846408534
Short name T1100
Test name
Test status
Simulation time 314550674870 ps
CPU time 77.82 seconds
Started Aug 09 07:25:18 PM PDT 24
Finished Aug 09 07:26:36 PM PDT 24
Peak memory 199904 kb
Host smart-a6ad44e7-a46d-4abb-80d5-d42df3a887e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846408534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1846408534
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1048687341
Short name T216
Test name
Test status
Simulation time 37624731318 ps
CPU time 92.24 seconds
Started Aug 09 07:25:18 PM PDT 24
Finished Aug 09 07:26:51 PM PDT 24
Peak memory 199864 kb
Host smart-e89bbf97-81d6-4c4d-84b2-7811b5b87d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048687341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1048687341
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.1449397010
Short name T201
Test name
Test status
Simulation time 112754325080 ps
CPU time 160.61 seconds
Started Aug 09 07:25:16 PM PDT 24
Finished Aug 09 07:27:57 PM PDT 24
Peak memory 199896 kb
Host smart-bf8ea47f-6bff-4bc6-a5a3-2619761379a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449397010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1449397010
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1303349847
Short name T427
Test name
Test status
Simulation time 23904665 ps
CPU time 0.57 seconds
Started Aug 09 07:18:52 PM PDT 24
Finished Aug 09 07:18:52 PM PDT 24
Peak memory 195332 kb
Host smart-ff1fae88-1191-44ad-9319-79ccf363fc9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303349847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1303349847
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.4088262268
Short name T704
Test name
Test status
Simulation time 37410511797 ps
CPU time 62.36 seconds
Started Aug 09 07:18:42 PM PDT 24
Finished Aug 09 07:19:44 PM PDT 24
Peak memory 199908 kb
Host smart-bfb7fb99-7430-434b-b568-9df64d185dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088262268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.4088262268
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.776675196
Short name T993
Test name
Test status
Simulation time 24599961763 ps
CPU time 39.39 seconds
Started Aug 09 07:18:40 PM PDT 24
Finished Aug 09 07:19:20 PM PDT 24
Peak memory 199984 kb
Host smart-354b511e-e63d-4907-afe9-e9cd019bff5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776675196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.776675196
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.3554619421
Short name T673
Test name
Test status
Simulation time 22370121294 ps
CPU time 37.08 seconds
Started Aug 09 07:18:42 PM PDT 24
Finished Aug 09 07:19:19 PM PDT 24
Peak memory 199956 kb
Host smart-62e02614-8386-491e-a6c0-f3f54695f4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554619421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3554619421
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2472464062
Short name T1145
Test name
Test status
Simulation time 26548107993 ps
CPU time 54.15 seconds
Started Aug 09 07:18:41 PM PDT 24
Finished Aug 09 07:19:35 PM PDT 24
Peak memory 199928 kb
Host smart-1deabaf1-afa8-4be7-994d-cd2a7b5c011e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472464062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2472464062
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.323459269
Short name T602
Test name
Test status
Simulation time 122645617251 ps
CPU time 666.74 seconds
Started Aug 09 07:18:51 PM PDT 24
Finished Aug 09 07:29:58 PM PDT 24
Peak memory 199972 kb
Host smart-f05dfee8-a067-4486-8361-6cec68ddb08f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=323459269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.323459269
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.36905884
Short name T675
Test name
Test status
Simulation time 6370412816 ps
CPU time 3.34 seconds
Started Aug 09 07:18:41 PM PDT 24
Finished Aug 09 07:18:45 PM PDT 24
Peak memory 199960 kb
Host smart-5462cac6-0b04-4b30-8e1b-55057c79c4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36905884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.36905884
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.2741796279
Short name T485
Test name
Test status
Simulation time 492277500307 ps
CPU time 60.56 seconds
Started Aug 09 07:18:43 PM PDT 24
Finished Aug 09 07:19:44 PM PDT 24
Peak memory 199996 kb
Host smart-834b84f3-25b8-473e-a9c6-f4bb8105d564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741796279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2741796279
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1018806386
Short name T376
Test name
Test status
Simulation time 18481832105 ps
CPU time 876.41 seconds
Started Aug 09 07:18:51 PM PDT 24
Finished Aug 09 07:33:27 PM PDT 24
Peak memory 199940 kb
Host smart-2d001371-f28e-4a8b-b281-78137ca16851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018806386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1018806386
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1030072193
Short name T1138
Test name
Test status
Simulation time 3092434416 ps
CPU time 5.37 seconds
Started Aug 09 07:18:43 PM PDT 24
Finished Aug 09 07:18:49 PM PDT 24
Peak memory 198504 kb
Host smart-948b1b00-20c7-42bf-ba0b-f99294b6c72a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1030072193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1030072193
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1252786176
Short name T273
Test name
Test status
Simulation time 35790622064 ps
CPU time 54.88 seconds
Started Aug 09 07:18:43 PM PDT 24
Finished Aug 09 07:19:38 PM PDT 24
Peak memory 199872 kb
Host smart-0a4551e8-2ddb-4759-ad1b-28708a4eb949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252786176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1252786176
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.119304813
Short name T303
Test name
Test status
Simulation time 33602719577 ps
CPU time 4.85 seconds
Started Aug 09 07:18:41 PM PDT 24
Finished Aug 09 07:18:46 PM PDT 24
Peak memory 196124 kb
Host smart-17f51493-15f7-4a30-8388-5944d15e7597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119304813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.119304813
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3467928818
Short name T90
Test name
Test status
Simulation time 246076093 ps
CPU time 0.84 seconds
Started Aug 09 07:18:51 PM PDT 24
Finished Aug 09 07:18:52 PM PDT 24
Peak memory 218372 kb
Host smart-cdb8979e-6b9b-46f4-84f5-c1d99f764123
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467928818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3467928818
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.83206867
Short name T363
Test name
Test status
Simulation time 532592787 ps
CPU time 1.61 seconds
Started Aug 09 07:18:42 PM PDT 24
Finished Aug 09 07:18:44 PM PDT 24
Peak memory 198652 kb
Host smart-e857f82b-fbc4-4a13-8f46-bf548471ce19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83206867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.83206867
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.3773423692
Short name T327
Test name
Test status
Simulation time 119115412059 ps
CPU time 562.2 seconds
Started Aug 09 07:18:53 PM PDT 24
Finished Aug 09 07:28:15 PM PDT 24
Peak memory 199992 kb
Host smart-25e1c736-c58d-4c5c-b51a-e0cea873b5c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773423692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3773423692
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1849663117
Short name T29
Test name
Test status
Simulation time 7743250177 ps
CPU time 156.32 seconds
Started Aug 09 07:18:49 PM PDT 24
Finished Aug 09 07:21:25 PM PDT 24
Peak memory 200424 kb
Host smart-52904aeb-6c06-45d3-8ab8-10177e304e0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849663117 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1849663117
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2747540581
Short name T492
Test name
Test status
Simulation time 1355234937 ps
CPU time 2.6 seconds
Started Aug 09 07:18:40 PM PDT 24
Finished Aug 09 07:18:42 PM PDT 24
Peak memory 198776 kb
Host smart-666cc1d7-beda-49fe-a663-80789b21728e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747540581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2747540581
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.923054025
Short name T1142
Test name
Test status
Simulation time 45504906106 ps
CPU time 19.67 seconds
Started Aug 09 07:18:43 PM PDT 24
Finished Aug 09 07:19:02 PM PDT 24
Peak memory 199948 kb
Host smart-b37f8b69-afd1-4edf-b429-ba12f96d6717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923054025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.923054025
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2128464684
Short name T626
Test name
Test status
Simulation time 73099944 ps
CPU time 0.54 seconds
Started Aug 09 07:20:50 PM PDT 24
Finished Aug 09 07:20:51 PM PDT 24
Peak memory 194984 kb
Host smart-98fd0ec4-433c-47c7-90a0-38e057f7b998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128464684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2128464684
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2334592272
Short name T451
Test name
Test status
Simulation time 81015044439 ps
CPU time 61.76 seconds
Started Aug 09 07:20:50 PM PDT 24
Finished Aug 09 07:21:51 PM PDT 24
Peak memory 199964 kb
Host smart-b8a985ec-15f6-48ff-9ed9-4a90878c30bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334592272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2334592272
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1846969192
Short name T159
Test name
Test status
Simulation time 33729325983 ps
CPU time 57.47 seconds
Started Aug 09 07:20:52 PM PDT 24
Finished Aug 09 07:21:50 PM PDT 24
Peak memory 199888 kb
Host smart-2c1d5880-2baa-4cb7-9859-71c115a50cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846969192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1846969192
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2391088837
Short name T937
Test name
Test status
Simulation time 73986837432 ps
CPU time 234.21 seconds
Started Aug 09 07:20:51 PM PDT 24
Finished Aug 09 07:24:45 PM PDT 24
Peak memory 199900 kb
Host smart-fa8f259f-6600-4055-bac5-f065a5a6e836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391088837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2391088837
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.2683501719
Short name T640
Test name
Test status
Simulation time 56019877641 ps
CPU time 108.71 seconds
Started Aug 09 07:20:49 PM PDT 24
Finished Aug 09 07:22:38 PM PDT 24
Peak memory 199976 kb
Host smart-f8567cad-582f-4d98-817a-d4a4b6680b5b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683501719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2683501719
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3634468147
Short name T990
Test name
Test status
Simulation time 47971344973 ps
CPU time 244.14 seconds
Started Aug 09 07:20:51 PM PDT 24
Finished Aug 09 07:24:55 PM PDT 24
Peak memory 199940 kb
Host smart-d67bdd59-1653-4cbc-8383-99fa4c691364
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3634468147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3634468147
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2836715164
Short name T1057
Test name
Test status
Simulation time 9833699141 ps
CPU time 21.67 seconds
Started Aug 09 07:20:51 PM PDT 24
Finished Aug 09 07:21:13 PM PDT 24
Peak memory 199604 kb
Host smart-c7e46c1d-6629-4675-b8e3-b49d6bb2dd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836715164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2836715164
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3424518418
Short name T535
Test name
Test status
Simulation time 8633832778 ps
CPU time 14.18 seconds
Started Aug 09 07:20:50 PM PDT 24
Finished Aug 09 07:21:04 PM PDT 24
Peak memory 197980 kb
Host smart-96b1721c-6754-45f4-b15d-4a6f35671b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424518418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3424518418
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.145133365
Short name T284
Test name
Test status
Simulation time 5404891741 ps
CPU time 61.2 seconds
Started Aug 09 07:20:50 PM PDT 24
Finished Aug 09 07:21:51 PM PDT 24
Peak memory 199932 kb
Host smart-fa267507-cf04-40d1-bec2-d7971f56b9af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=145133365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.145133365
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2412612622
Short name T527
Test name
Test status
Simulation time 6963815986 ps
CPU time 15.02 seconds
Started Aug 09 07:20:50 PM PDT 24
Finished Aug 09 07:21:05 PM PDT 24
Peak memory 197996 kb
Host smart-1a7d0973-2a6e-4a7c-b2fd-d40bd29e1291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2412612622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2412612622
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1643791977
Short name T899
Test name
Test status
Simulation time 35844168655 ps
CPU time 55.09 seconds
Started Aug 09 07:20:50 PM PDT 24
Finished Aug 09 07:21:46 PM PDT 24
Peak memory 199904 kb
Host smart-42971242-66ea-423b-8555-9f6d790992de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643791977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1643791977
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1416780773
Short name T463
Test name
Test status
Simulation time 41113876508 ps
CPU time 62.43 seconds
Started Aug 09 07:20:51 PM PDT 24
Finished Aug 09 07:21:53 PM PDT 24
Peak memory 195812 kb
Host smart-6ee869ed-0233-4318-aad3-4250de3c4b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416780773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1416780773
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.146397622
Short name T1025
Test name
Test status
Simulation time 334908196 ps
CPU time 1.07 seconds
Started Aug 09 07:20:50 PM PDT 24
Finished Aug 09 07:20:51 PM PDT 24
Peak memory 198504 kb
Host smart-c7bcb78a-4bbb-44d8-adb4-65912aa3fe0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146397622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.146397622
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1198145518
Short name T744
Test name
Test status
Simulation time 24493916664 ps
CPU time 24.3 seconds
Started Aug 09 07:20:50 PM PDT 24
Finished Aug 09 07:21:15 PM PDT 24
Peak memory 200092 kb
Host smart-8224a7e8-f788-40a0-b998-2af40430e095
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198145518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1198145518
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.823733197
Short name T1071
Test name
Test status
Simulation time 113496329508 ps
CPU time 823.6 seconds
Started Aug 09 07:20:52 PM PDT 24
Finished Aug 09 07:34:36 PM PDT 24
Peak memory 216612 kb
Host smart-9063ab7a-c6f8-48a4-a4c9-490eff864757
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823733197 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.823733197
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.908609639
Short name T521
Test name
Test status
Simulation time 1490955000 ps
CPU time 4.93 seconds
Started Aug 09 07:20:50 PM PDT 24
Finished Aug 09 07:20:56 PM PDT 24
Peak memory 199512 kb
Host smart-def8b491-0310-405f-bdb4-90d0f3436c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908609639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.908609639
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1667952625
Short name T806
Test name
Test status
Simulation time 85605676469 ps
CPU time 22.62 seconds
Started Aug 09 07:20:50 PM PDT 24
Finished Aug 09 07:21:13 PM PDT 24
Peak memory 199888 kb
Host smart-841adc86-ae80-4cc7-98c9-f4b4f521b3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667952625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1667952625
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1167549449
Short name T685
Test name
Test status
Simulation time 14101617 ps
CPU time 0.55 seconds
Started Aug 09 07:21:02 PM PDT 24
Finished Aug 09 07:21:02 PM PDT 24
Peak memory 195472 kb
Host smart-49b15eda-de4d-4c68-8182-df27f0beeac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167549449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1167549449
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2398330448
Short name T604
Test name
Test status
Simulation time 177798326087 ps
CPU time 36.63 seconds
Started Aug 09 07:20:52 PM PDT 24
Finished Aug 09 07:21:29 PM PDT 24
Peak memory 199892 kb
Host smart-2506ab05-eda4-4e2f-b97c-198d092f4461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398330448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2398330448
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2212850923
Short name T434
Test name
Test status
Simulation time 184857811954 ps
CPU time 343.12 seconds
Started Aug 09 07:20:52 PM PDT 24
Finished Aug 09 07:26:35 PM PDT 24
Peak memory 199864 kb
Host smart-8c7eefea-751a-4144-bf8d-b237beb1fbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212850923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2212850923
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2197699934
Short name T991
Test name
Test status
Simulation time 100741017422 ps
CPU time 171.49 seconds
Started Aug 09 07:20:50 PM PDT 24
Finished Aug 09 07:23:42 PM PDT 24
Peak memory 199880 kb
Host smart-7168496c-a388-49aa-be41-2236c33a5dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197699934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2197699934
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2184075681
Short name T250
Test name
Test status
Simulation time 41575755684 ps
CPU time 78.69 seconds
Started Aug 09 07:20:59 PM PDT 24
Finished Aug 09 07:22:18 PM PDT 24
Peak memory 199932 kb
Host smart-92c51674-008d-42df-bb25-b1adebba4ef7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184075681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2184075681
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.231041486
Short name T518
Test name
Test status
Simulation time 112411498724 ps
CPU time 273.96 seconds
Started Aug 09 07:21:01 PM PDT 24
Finished Aug 09 07:25:35 PM PDT 24
Peak memory 199956 kb
Host smart-4a1b2a0c-8254-401e-a769-834fb923f1f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=231041486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.231041486
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2507126073
Short name T355
Test name
Test status
Simulation time 881466481 ps
CPU time 2.02 seconds
Started Aug 09 07:21:03 PM PDT 24
Finished Aug 09 07:21:05 PM PDT 24
Peak memory 196200 kb
Host smart-bc52186d-dc35-4ae6-a3d0-67ecd9deece1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507126073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2507126073
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3957249218
Short name T767
Test name
Test status
Simulation time 119341620658 ps
CPU time 460.09 seconds
Started Aug 09 07:21:00 PM PDT 24
Finished Aug 09 07:28:40 PM PDT 24
Peak memory 208344 kb
Host smart-aebe0fd2-00f5-4988-92e8-5a1d5d2fd630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957249218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3957249218
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.55527731
Short name T1069
Test name
Test status
Simulation time 20577847427 ps
CPU time 1157.87 seconds
Started Aug 09 07:21:02 PM PDT 24
Finished Aug 09 07:40:20 PM PDT 24
Peak memory 199976 kb
Host smart-71ad247d-77a8-4a49-97e9-35787d57ba0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=55527731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.55527731
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.4175990425
Short name T910
Test name
Test status
Simulation time 2675035897 ps
CPU time 3.38 seconds
Started Aug 09 07:20:59 PM PDT 24
Finished Aug 09 07:21:03 PM PDT 24
Peak memory 198120 kb
Host smart-9d9d1b3f-70b2-41c7-87b7-9a4c7d2adede
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4175990425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.4175990425
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.687134195
Short name T1072
Test name
Test status
Simulation time 190043355465 ps
CPU time 70.01 seconds
Started Aug 09 07:21:01 PM PDT 24
Finished Aug 09 07:22:11 PM PDT 24
Peak memory 199732 kb
Host smart-91de67e9-0661-49b1-be4a-5ae0e0dc40c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687134195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.687134195
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3502624488
Short name T1101
Test name
Test status
Simulation time 2987030974 ps
CPU time 2.8 seconds
Started Aug 09 07:21:08 PM PDT 24
Finished Aug 09 07:21:10 PM PDT 24
Peak memory 196484 kb
Host smart-a7ed9aa3-9344-468a-9641-0281f6a9e0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502624488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3502624488
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.4216809324
Short name T1132
Test name
Test status
Simulation time 448478361 ps
CPU time 1.43 seconds
Started Aug 09 07:20:51 PM PDT 24
Finished Aug 09 07:20:53 PM PDT 24
Peak memory 198908 kb
Host smart-fb364ab0-84b7-43c6-8a70-b49a27f62b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216809324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.4216809324
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.110732715
Short name T35
Test name
Test status
Simulation time 98499867703 ps
CPU time 223.03 seconds
Started Aug 09 07:21:00 PM PDT 24
Finished Aug 09 07:24:43 PM PDT 24
Peak memory 209340 kb
Host smart-9a7a7fbf-61d3-4f1b-a493-fd1b7d38ec5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110732715 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.110732715
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2037713839
Short name T607
Test name
Test status
Simulation time 6298630804 ps
CPU time 25.88 seconds
Started Aug 09 07:21:00 PM PDT 24
Finished Aug 09 07:21:26 PM PDT 24
Peak memory 199472 kb
Host smart-38af000f-f0ac-4cfe-81cd-d7910cc84b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037713839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2037713839
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.4024898885
Short name T333
Test name
Test status
Simulation time 76811796885 ps
CPU time 73.49 seconds
Started Aug 09 07:20:50 PM PDT 24
Finished Aug 09 07:22:04 PM PDT 24
Peak memory 199944 kb
Host smart-773602cb-2464-4bf8-8802-58298b2be0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024898885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.4024898885
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.4010190307
Short name T971
Test name
Test status
Simulation time 12137013 ps
CPU time 0.57 seconds
Started Aug 09 07:21:00 PM PDT 24
Finished Aug 09 07:21:00 PM PDT 24
Peak memory 194316 kb
Host smart-885dfbb0-5177-4a51-81c4-f78caf08e847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010190307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.4010190307
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.165742714
Short name T137
Test name
Test status
Simulation time 322885068495 ps
CPU time 28.18 seconds
Started Aug 09 07:21:08 PM PDT 24
Finished Aug 09 07:21:36 PM PDT 24
Peak memory 199884 kb
Host smart-58af057a-5f29-418b-896f-70b2a5d60135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165742714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.165742714
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2475469340
Short name T930
Test name
Test status
Simulation time 91083137589 ps
CPU time 130.85 seconds
Started Aug 09 07:21:00 PM PDT 24
Finished Aug 09 07:23:11 PM PDT 24
Peak memory 199868 kb
Host smart-04ca3dce-f004-4aa8-8acd-98b561edfad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475469340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2475469340
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.782356146
Short name T108
Test name
Test status
Simulation time 33989055256 ps
CPU time 27.88 seconds
Started Aug 09 07:21:00 PM PDT 24
Finished Aug 09 07:21:28 PM PDT 24
Peak memory 199928 kb
Host smart-0ce4dbad-fda4-4a4c-9ec3-3f57738e8ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782356146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.782356146
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3850943010
Short name T843
Test name
Test status
Simulation time 24198087880 ps
CPU time 22.94 seconds
Started Aug 09 07:21:00 PM PDT 24
Finished Aug 09 07:21:23 PM PDT 24
Peak memory 199924 kb
Host smart-3d1dd1aa-9cb7-44a6-95f3-2dbefab4ed00
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850943010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3850943010
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2295897681
Short name T1048
Test name
Test status
Simulation time 118472795497 ps
CPU time 299.71 seconds
Started Aug 09 07:21:03 PM PDT 24
Finished Aug 09 07:26:03 PM PDT 24
Peak memory 199976 kb
Host smart-71fcc34d-6386-4b6c-ba0d-463398b3c243
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2295897681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2295897681
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3166111458
Short name T508
Test name
Test status
Simulation time 4763637661 ps
CPU time 3.89 seconds
Started Aug 09 07:21:08 PM PDT 24
Finished Aug 09 07:21:12 PM PDT 24
Peak memory 196172 kb
Host smart-58879fce-7136-4dee-b7f4-8b882236ab37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166111458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3166111458
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3265968692
Short name T659
Test name
Test status
Simulation time 34406101950 ps
CPU time 33.4 seconds
Started Aug 09 07:20:59 PM PDT 24
Finished Aug 09 07:21:32 PM PDT 24
Peak memory 200028 kb
Host smart-37d5278a-7b3c-4aea-b767-9cdc62b333ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265968692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3265968692
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1261179584
Short name T493
Test name
Test status
Simulation time 6856088056 ps
CPU time 339.35 seconds
Started Aug 09 07:21:03 PM PDT 24
Finished Aug 09 07:26:43 PM PDT 24
Peak memory 199916 kb
Host smart-6460a7d1-cf31-49b8-af3d-8b76e0738c86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1261179584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1261179584
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1554901088
Short name T374
Test name
Test status
Simulation time 4235316404 ps
CPU time 38.66 seconds
Started Aug 09 07:20:59 PM PDT 24
Finished Aug 09 07:21:38 PM PDT 24
Peak memory 197924 kb
Host smart-716279a5-b57f-40cf-9c61-bd516706258b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1554901088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1554901088
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3850409996
Short name T717
Test name
Test status
Simulation time 68352433222 ps
CPU time 96.63 seconds
Started Aug 09 07:21:01 PM PDT 24
Finished Aug 09 07:22:38 PM PDT 24
Peak memory 199744 kb
Host smart-512ce57a-f53b-48f6-8aee-3812b99e0993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850409996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3850409996
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.4177661183
Short name T5
Test name
Test status
Simulation time 1716833450 ps
CPU time 1.99 seconds
Started Aug 09 07:21:07 PM PDT 24
Finished Aug 09 07:21:09 PM PDT 24
Peak memory 195464 kb
Host smart-06c08594-d958-4e9f-825d-cb4b807093d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177661183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.4177661183
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3060476738
Short name T660
Test name
Test status
Simulation time 11579341306 ps
CPU time 31.29 seconds
Started Aug 09 07:21:02 PM PDT 24
Finished Aug 09 07:21:33 PM PDT 24
Peak memory 199564 kb
Host smart-9d799648-15ee-4b20-bfcd-9f8247546508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060476738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3060476738
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.584270426
Short name T406
Test name
Test status
Simulation time 48628599642 ps
CPU time 600.57 seconds
Started Aug 09 07:20:59 PM PDT 24
Finished Aug 09 07:31:00 PM PDT 24
Peak memory 216484 kb
Host smart-ec91e04a-a717-4b5c-a604-a4109fbd81d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584270426 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.584270426
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.685362136
Short name T106
Test name
Test status
Simulation time 1109907504 ps
CPU time 3.32 seconds
Started Aug 09 07:21:03 PM PDT 24
Finished Aug 09 07:21:07 PM PDT 24
Peak memory 198572 kb
Host smart-72fd3a01-5312-4b01-9006-92954508e94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685362136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.685362136
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.392643978
Short name T259
Test name
Test status
Simulation time 25138086486 ps
CPU time 11.19 seconds
Started Aug 09 07:21:01 PM PDT 24
Finished Aug 09 07:21:13 PM PDT 24
Peak memory 199776 kb
Host smart-a1cd9af8-b31b-463b-8d22-1d8c1791bf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392643978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.392643978
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3554636112
Short name T430
Test name
Test status
Simulation time 24951600 ps
CPU time 0.56 seconds
Started Aug 09 07:21:09 PM PDT 24
Finished Aug 09 07:21:10 PM PDT 24
Peak memory 195328 kb
Host smart-4d937b75-f144-4bb2-8b68-bef66e587188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554636112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3554636112
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.575972596
Short name T1063
Test name
Test status
Simulation time 101727440435 ps
CPU time 52.29 seconds
Started Aug 09 07:21:00 PM PDT 24
Finished Aug 09 07:21:52 PM PDT 24
Peak memory 199888 kb
Host smart-258f3423-06ad-4150-bc4b-bf6571615e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575972596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.575972596
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.990870442
Short name T648
Test name
Test status
Simulation time 23450964083 ps
CPU time 30.81 seconds
Started Aug 09 07:21:01 PM PDT 24
Finished Aug 09 07:21:32 PM PDT 24
Peak memory 199904 kb
Host smart-6d5dcc84-b09e-4825-8116-cb92e3c270ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990870442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.990870442
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3565274915
Short name T1015
Test name
Test status
Simulation time 107102974782 ps
CPU time 40.54 seconds
Started Aug 09 07:21:09 PM PDT 24
Finished Aug 09 07:21:50 PM PDT 24
Peak memory 199956 kb
Host smart-dbc8a9c1-f6c0-4b83-9d17-8fbcbdfe00bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565274915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3565274915
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1321758636
Short name T118
Test name
Test status
Simulation time 93469514937 ps
CPU time 81.06 seconds
Started Aug 09 07:21:08 PM PDT 24
Finished Aug 09 07:22:29 PM PDT 24
Peak memory 199896 kb
Host smart-0fba1173-9f34-4cf1-903c-f310f57810f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321758636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1321758636
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1751085137
Short name T357
Test name
Test status
Simulation time 140195146353 ps
CPU time 1257.73 seconds
Started Aug 09 07:21:08 PM PDT 24
Finished Aug 09 07:42:06 PM PDT 24
Peak memory 199960 kb
Host smart-fb8c863e-ef2f-490d-9fb2-66854f160a26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1751085137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1751085137
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2791319693
Short name T1167
Test name
Test status
Simulation time 121265437 ps
CPU time 0.68 seconds
Started Aug 09 07:21:07 PM PDT 24
Finished Aug 09 07:21:08 PM PDT 24
Peak memory 195956 kb
Host smart-2e2cdad2-89cf-4319-9ea2-2bccaa16f56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791319693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2791319693
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.1347438197
Short name T778
Test name
Test status
Simulation time 58035399489 ps
CPU time 47.89 seconds
Started Aug 09 07:21:08 PM PDT 24
Finished Aug 09 07:21:56 PM PDT 24
Peak memory 200056 kb
Host smart-a6dac971-47dc-47fa-8b8d-aad4f9de0c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347438197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1347438197
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3945547308
Short name T528
Test name
Test status
Simulation time 25857975316 ps
CPU time 1439.33 seconds
Started Aug 09 07:21:06 PM PDT 24
Finished Aug 09 07:45:06 PM PDT 24
Peak memory 199972 kb
Host smart-c5e38a00-be31-4286-b806-375c65a3ea74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3945547308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3945547308
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3058813492
Short name T561
Test name
Test status
Simulation time 5024947359 ps
CPU time 36.31 seconds
Started Aug 09 07:21:15 PM PDT 24
Finished Aug 09 07:21:51 PM PDT 24
Peak memory 199096 kb
Host smart-19b0f020-abb7-4bb2-8747-907ae2c3807b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3058813492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3058813492
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3213834399
Short name T280
Test name
Test status
Simulation time 78671144943 ps
CPU time 34.32 seconds
Started Aug 09 07:21:07 PM PDT 24
Finished Aug 09 07:21:41 PM PDT 24
Peak memory 199980 kb
Host smart-afaae0ba-fa1f-4b01-8781-12b7e0f9d86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213834399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3213834399
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2347685217
Short name T467
Test name
Test status
Simulation time 2604861795 ps
CPU time 4.31 seconds
Started Aug 09 07:21:08 PM PDT 24
Finished Aug 09 07:21:12 PM PDT 24
Peak memory 196528 kb
Host smart-1520f96a-bea4-473f-8cc1-509693c9d9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347685217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2347685217
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3392159514
Short name T489
Test name
Test status
Simulation time 632163578 ps
CPU time 1.85 seconds
Started Aug 09 07:21:02 PM PDT 24
Finished Aug 09 07:21:04 PM PDT 24
Peak memory 198504 kb
Host smart-ec6198dd-85a4-4266-8bcb-a9fa2afee0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392159514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3392159514
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.477596691
Short name T639
Test name
Test status
Simulation time 378976271364 ps
CPU time 797.94 seconds
Started Aug 09 07:21:08 PM PDT 24
Finished Aug 09 07:34:26 PM PDT 24
Peak memory 199968 kb
Host smart-040cf62e-a921-4274-854a-9f7d9a874e55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477596691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.477596691
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.2895424346
Short name T321
Test name
Test status
Simulation time 19152376185 ps
CPU time 217.57 seconds
Started Aug 09 07:21:08 PM PDT 24
Finished Aug 09 07:24:46 PM PDT 24
Peak memory 216300 kb
Host smart-a995b53c-6030-488c-b179-0704543e8bda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895424346 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.2895424346
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.221269083
Short name T867
Test name
Test status
Simulation time 878175221 ps
CPU time 2.46 seconds
Started Aug 09 07:21:08 PM PDT 24
Finished Aug 09 07:21:10 PM PDT 24
Peak memory 198916 kb
Host smart-8bce08e8-7ecb-4e34-b45d-105006c6a533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221269083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.221269083
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.4040997922
Short name T782
Test name
Test status
Simulation time 88902577625 ps
CPU time 32.19 seconds
Started Aug 09 07:20:58 PM PDT 24
Finished Aug 09 07:21:31 PM PDT 24
Peak memory 199904 kb
Host smart-b0b5e624-6ad7-43dc-a314-1565c2fcd6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040997922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.4040997922
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3654085299
Short name T898
Test name
Test status
Simulation time 11051738 ps
CPU time 0.53 seconds
Started Aug 09 07:21:17 PM PDT 24
Finished Aug 09 07:21:17 PM PDT 24
Peak memory 195628 kb
Host smart-0c0528cc-a083-4f81-a9f5-a2dacfcc01a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654085299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3654085299
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1893117021
Short name T1035
Test name
Test status
Simulation time 233138785833 ps
CPU time 108.18 seconds
Started Aug 09 07:21:12 PM PDT 24
Finished Aug 09 07:23:00 PM PDT 24
Peak memory 199976 kb
Host smart-e9fe0b28-bb05-4967-9aa9-85a95fd5a115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893117021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1893117021
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1851194357
Short name T1052
Test name
Test status
Simulation time 107402162989 ps
CPU time 51.5 seconds
Started Aug 09 07:21:12 PM PDT 24
Finished Aug 09 07:22:04 PM PDT 24
Peak memory 199796 kb
Host smart-a19a712d-4f59-4339-b363-44efbbe6e9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851194357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1851194357
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.4042760341
Short name T247
Test name
Test status
Simulation time 13259812011 ps
CPU time 30.27 seconds
Started Aug 09 07:21:15 PM PDT 24
Finished Aug 09 07:21:46 PM PDT 24
Peak memory 199896 kb
Host smart-44760844-cc7e-4a19-af48-8c30f0704077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042760341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.4042760341
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.2707907348
Short name T18
Test name
Test status
Simulation time 12471888259 ps
CPU time 28.71 seconds
Started Aug 09 07:21:17 PM PDT 24
Finished Aug 09 07:21:46 PM PDT 24
Peak memory 199916 kb
Host smart-aab0ecf7-47cd-4e17-a3c0-3a24b5ac0e5f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707907348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2707907348
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1634997780
Short name T956
Test name
Test status
Simulation time 76535256253 ps
CPU time 281.71 seconds
Started Aug 09 07:21:15 PM PDT 24
Finished Aug 09 07:25:57 PM PDT 24
Peak memory 199976 kb
Host smart-c64f34fd-28c3-4d67-84be-5c95971b8d11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1634997780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1634997780
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3545498515
Short name T360
Test name
Test status
Simulation time 1119519867 ps
CPU time 1.18 seconds
Started Aug 09 07:21:16 PM PDT 24
Finished Aug 09 07:21:17 PM PDT 24
Peak memory 197068 kb
Host smart-0c59fea0-4ace-4468-b051-c1ca56e61a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545498515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3545498515
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.866071477
Short name T462
Test name
Test status
Simulation time 91838459627 ps
CPU time 37.29 seconds
Started Aug 09 07:21:17 PM PDT 24
Finished Aug 09 07:21:55 PM PDT 24
Peak memory 198644 kb
Host smart-4133f57b-e945-421f-8ce5-854785dc58b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866071477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.866071477
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1978742929
Short name T916
Test name
Test status
Simulation time 14903898572 ps
CPU time 797.96 seconds
Started Aug 09 07:21:16 PM PDT 24
Finished Aug 09 07:34:34 PM PDT 24
Peak memory 199948 kb
Host smart-8efda8f9-704b-4847-8a7a-6317b67858fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1978742929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1978742929
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.620787556
Short name T59
Test name
Test status
Simulation time 3270476299 ps
CPU time 12.35 seconds
Started Aug 09 07:21:18 PM PDT 24
Finished Aug 09 07:21:30 PM PDT 24
Peak memory 198264 kb
Host smart-6213b044-91e2-4dbd-bdc6-562218762ca1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=620787556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.620787556
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.3714925418
Short name T166
Test name
Test status
Simulation time 99330389031 ps
CPU time 32.78 seconds
Started Aug 09 07:21:16 PM PDT 24
Finished Aug 09 07:21:49 PM PDT 24
Peak memory 199972 kb
Host smart-e154b9ba-99e8-4b35-b298-765b7670b56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714925418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3714925418
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2162737745
Short name T361
Test name
Test status
Simulation time 5208456911 ps
CPU time 8.87 seconds
Started Aug 09 07:21:15 PM PDT 24
Finished Aug 09 07:21:24 PM PDT 24
Peak memory 196240 kb
Host smart-0dbd4cff-0a5e-4fda-909e-d66cae741b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162737745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2162737745
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.4086660676
Short name T478
Test name
Test status
Simulation time 11582645491 ps
CPU time 16.99 seconds
Started Aug 09 07:21:08 PM PDT 24
Finished Aug 09 07:21:25 PM PDT 24
Peak memory 199808 kb
Host smart-e4a42d72-b33e-42f8-92b4-a5bf4bbe5847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086660676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.4086660676
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2293252762
Short name T1108
Test name
Test status
Simulation time 274463041182 ps
CPU time 103.51 seconds
Started Aug 09 07:21:18 PM PDT 24
Finished Aug 09 07:23:02 PM PDT 24
Peak memory 199956 kb
Host smart-bcd21f40-2538-4568-a0bc-12b0013a04ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293252762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2293252762
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2764001522
Short name T895
Test name
Test status
Simulation time 55659070479 ps
CPU time 117.82 seconds
Started Aug 09 07:21:19 PM PDT 24
Finished Aug 09 07:23:17 PM PDT 24
Peak memory 215600 kb
Host smart-d5c048bc-76b9-4a83-8bb5-40e97735a546
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764001522 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2764001522
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2715708452
Short name T1098
Test name
Test status
Simulation time 6313999456 ps
CPU time 31.87 seconds
Started Aug 09 07:21:16 PM PDT 24
Finished Aug 09 07:21:48 PM PDT 24
Peak memory 199804 kb
Host smart-56f130de-cf93-432b-b104-641c9ef7ef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715708452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2715708452
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.222599786
Short name T907
Test name
Test status
Simulation time 70008762827 ps
CPU time 105.56 seconds
Started Aug 09 07:21:09 PM PDT 24
Finished Aug 09 07:22:54 PM PDT 24
Peak memory 199884 kb
Host smart-ef59181e-9e33-4d4b-9146-e95d952b3fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222599786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.222599786
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.628523703
Short name T373
Test name
Test status
Simulation time 11593911 ps
CPU time 0.55 seconds
Started Aug 09 07:21:36 PM PDT 24
Finished Aug 09 07:21:36 PM PDT 24
Peak memory 195304 kb
Host smart-7c0f7627-54ee-483b-80a9-519bea9a4431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628523703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.628523703
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1354721715
Short name T296
Test name
Test status
Simulation time 45768346367 ps
CPU time 59.76 seconds
Started Aug 09 07:21:15 PM PDT 24
Finished Aug 09 07:22:15 PM PDT 24
Peak memory 199880 kb
Host smart-3bcbc1a9-72f8-4043-99fe-28de432d964a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354721715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1354721715
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.442722650
Short name T464
Test name
Test status
Simulation time 8264043249 ps
CPU time 11.94 seconds
Started Aug 09 07:21:16 PM PDT 24
Finished Aug 09 07:21:28 PM PDT 24
Peak memory 199384 kb
Host smart-70507dcb-0b89-4eb1-a468-62dd7afcfe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442722650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.442722650
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2064239408
Short name T881
Test name
Test status
Simulation time 50854823372 ps
CPU time 37.96 seconds
Started Aug 09 07:21:17 PM PDT 24
Finished Aug 09 07:21:55 PM PDT 24
Peak memory 200180 kb
Host smart-0dcf7a00-cd7f-453b-b6ea-25b711a514a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064239408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2064239408
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.34863088
Short name T1021
Test name
Test status
Simulation time 60708374136 ps
CPU time 109.89 seconds
Started Aug 09 07:21:17 PM PDT 24
Finished Aug 09 07:23:07 PM PDT 24
Peak memory 199968 kb
Host smart-f227ffbc-967e-4469-85fb-eea89671a3f9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34863088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.34863088
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.1761108997
Short name T539
Test name
Test status
Simulation time 28606076994 ps
CPU time 214 seconds
Started Aug 09 07:21:18 PM PDT 24
Finished Aug 09 07:24:52 PM PDT 24
Peak memory 199944 kb
Host smart-c89382e5-b3c3-439f-9870-3815c18c88e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1761108997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1761108997
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2228230472
Short name T676
Test name
Test status
Simulation time 5491421571 ps
CPU time 3.75 seconds
Started Aug 09 07:21:17 PM PDT 24
Finished Aug 09 07:21:21 PM PDT 24
Peak memory 199928 kb
Host smart-57e35e74-146a-4746-913e-af60b744c2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228230472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2228230472
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1370422168
Short name T700
Test name
Test status
Simulation time 89814084933 ps
CPU time 186.95 seconds
Started Aug 09 07:21:16 PM PDT 24
Finished Aug 09 07:24:23 PM PDT 24
Peak memory 200124 kb
Host smart-a01bb7fc-cba3-465a-a105-5a1615e67eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370422168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1370422168
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1539430166
Short name T435
Test name
Test status
Simulation time 13630561224 ps
CPU time 583.8 seconds
Started Aug 09 07:21:19 PM PDT 24
Finished Aug 09 07:31:03 PM PDT 24
Peak memory 199992 kb
Host smart-9e360852-48da-4e90-b254-d94d2085d335
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1539430166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1539430166
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3114165814
Short name T1028
Test name
Test status
Simulation time 5893081332 ps
CPU time 51.78 seconds
Started Aug 09 07:21:19 PM PDT 24
Finished Aug 09 07:22:11 PM PDT 24
Peak memory 199076 kb
Host smart-f669cc8a-b3e8-4003-9f74-53dc29cfc54a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3114165814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3114165814
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1167524633
Short name T632
Test name
Test status
Simulation time 38521649138 ps
CPU time 15.67 seconds
Started Aug 09 07:21:17 PM PDT 24
Finished Aug 09 07:21:32 PM PDT 24
Peak memory 198652 kb
Host smart-cc39b0f6-f5c8-415e-b1cb-09d7323b3665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167524633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1167524633
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1518060088
Short name T351
Test name
Test status
Simulation time 3299226296 ps
CPU time 2.92 seconds
Started Aug 09 07:21:18 PM PDT 24
Finished Aug 09 07:21:21 PM PDT 24
Peak memory 196468 kb
Host smart-9fbbc26e-05a0-4455-973a-27e88c5a11f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518060088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1518060088
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1982707269
Short name T789
Test name
Test status
Simulation time 482307162 ps
CPU time 1.97 seconds
Started Aug 09 07:21:18 PM PDT 24
Finished Aug 09 07:21:20 PM PDT 24
Peak memory 199812 kb
Host smart-6394dddc-0318-4d5d-ba98-e4b8969cc931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982707269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1982707269
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2349740344
Short name T1026
Test name
Test status
Simulation time 7081010318 ps
CPU time 11.25 seconds
Started Aug 09 07:21:19 PM PDT 24
Finished Aug 09 07:21:30 PM PDT 24
Peak memory 199908 kb
Host smart-54f6cac7-b15f-4ff7-bea0-b337cde50e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349740344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2349740344
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1175987371
Short name T423
Test name
Test status
Simulation time 35969036619 ps
CPU time 61.94 seconds
Started Aug 09 07:21:17 PM PDT 24
Finished Aug 09 07:22:19 PM PDT 24
Peak memory 199936 kb
Host smart-fe53ad3e-eee7-4b27-922b-138558df2d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175987371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1175987371
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3154972276
Short name T444
Test name
Test status
Simulation time 45431136 ps
CPU time 0.57 seconds
Started Aug 09 07:21:34 PM PDT 24
Finished Aug 09 07:21:34 PM PDT 24
Peak memory 195300 kb
Host smart-61f3abfa-6f31-46b6-b0c7-6a65723ec338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154972276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3154972276
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.4058680897
Short name T37
Test name
Test status
Simulation time 37443060346 ps
CPU time 26.68 seconds
Started Aug 09 07:21:33 PM PDT 24
Finished Aug 09 07:22:00 PM PDT 24
Peak memory 199868 kb
Host smart-c8d51ad6-8dbe-4db0-b9cd-18a7f8e57f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058680897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.4058680897
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3025918288
Short name T695
Test name
Test status
Simulation time 33705777589 ps
CPU time 14.72 seconds
Started Aug 09 07:21:33 PM PDT 24
Finished Aug 09 07:21:48 PM PDT 24
Peak memory 199968 kb
Host smart-ce3ef6e8-9966-43e1-8bca-f22cb3fb1160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025918288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3025918288
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_intr.2419941517
Short name T964
Test name
Test status
Simulation time 349369007898 ps
CPU time 118.78 seconds
Started Aug 09 07:21:33 PM PDT 24
Finished Aug 09 07:23:32 PM PDT 24
Peak memory 199924 kb
Host smart-f380b9dc-0e28-4307-8383-8811aecd0192
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419941517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2419941517
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.526005331
Short name T712
Test name
Test status
Simulation time 42941367665 ps
CPU time 107.52 seconds
Started Aug 09 07:21:49 PM PDT 24
Finished Aug 09 07:23:36 PM PDT 24
Peak memory 199788 kb
Host smart-d791f2a0-ee85-49f8-b69b-8f42e4575b5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=526005331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.526005331
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.4258370092
Short name T420
Test name
Test status
Simulation time 889038049 ps
CPU time 1.77 seconds
Started Aug 09 07:21:36 PM PDT 24
Finished Aug 09 07:21:38 PM PDT 24
Peak memory 197988 kb
Host smart-470f2095-8d4b-4c55-b913-60108392a48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258370092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.4258370092
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2420532455
Short name T795
Test name
Test status
Simulation time 16443543663 ps
CPU time 30.87 seconds
Started Aug 09 07:21:34 PM PDT 24
Finished Aug 09 07:22:05 PM PDT 24
Peak memory 200060 kb
Host smart-f4ae25a7-2f2b-4ae7-bc2b-3ba68a9fab30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420532455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2420532455
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3175396458
Short name T1080
Test name
Test status
Simulation time 22522329287 ps
CPU time 1268.34 seconds
Started Aug 09 07:21:34 PM PDT 24
Finished Aug 09 07:42:43 PM PDT 24
Peak memory 199996 kb
Host smart-655a878f-7598-4eda-abf6-d2befa0565f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175396458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3175396458
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.764516587
Short name T562
Test name
Test status
Simulation time 6227792681 ps
CPU time 52.14 seconds
Started Aug 09 07:21:33 PM PDT 24
Finished Aug 09 07:22:25 PM PDT 24
Peak memory 199200 kb
Host smart-eb6050fa-4bba-4b86-99e8-3b5fb8fc2a32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=764516587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.764516587
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1966140921
Short name T140
Test name
Test status
Simulation time 187087727231 ps
CPU time 83.02 seconds
Started Aug 09 07:21:32 PM PDT 24
Finished Aug 09 07:22:55 PM PDT 24
Peak memory 199972 kb
Host smart-03f0bddf-42a8-44e2-aa56-c45bbe0b7ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966140921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1966140921
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.344547939
Short name T407
Test name
Test status
Simulation time 32447620415 ps
CPU time 50.75 seconds
Started Aug 09 07:21:33 PM PDT 24
Finished Aug 09 07:22:23 PM PDT 24
Peak memory 196264 kb
Host smart-21d7eb9c-2865-49da-a452-1c59807a0a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344547939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.344547939
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1484061991
Short name T699
Test name
Test status
Simulation time 292700298 ps
CPU time 1.45 seconds
Started Aug 09 07:21:32 PM PDT 24
Finished Aug 09 07:21:34 PM PDT 24
Peak memory 198612 kb
Host smart-91252a30-0311-4efc-a6cf-4f997063bcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484061991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1484061991
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3395873369
Short name T320
Test name
Test status
Simulation time 60403181509 ps
CPU time 779.64 seconds
Started Aug 09 07:21:35 PM PDT 24
Finished Aug 09 07:34:34 PM PDT 24
Peak memory 224776 kb
Host smart-d3dcc7eb-1df8-45d4-a01f-86ceeccbd773
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395873369 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3395873369
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3011811076
Short name T282
Test name
Test status
Simulation time 6266055287 ps
CPU time 15.94 seconds
Started Aug 09 07:21:33 PM PDT 24
Finished Aug 09 07:21:49 PM PDT 24
Peak memory 199792 kb
Host smart-8b583bd6-e7c0-447a-a339-51e077f18983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011811076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3011811076
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.3139416308
Short name T841
Test name
Test status
Simulation time 85238147619 ps
CPU time 105.96 seconds
Started Aug 09 07:21:35 PM PDT 24
Finished Aug 09 07:23:21 PM PDT 24
Peak memory 199980 kb
Host smart-31026c9c-8724-4cfc-83c8-955e5ffe5565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139416308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3139416308
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.2663352786
Short name T348
Test name
Test status
Simulation time 12533247 ps
CPU time 0.56 seconds
Started Aug 09 07:21:34 PM PDT 24
Finished Aug 09 07:21:35 PM PDT 24
Peak memory 194788 kb
Host smart-e62c80b0-b675-4f1f-b0e4-36f3864aba2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663352786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2663352786
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.1697949852
Short name T479
Test name
Test status
Simulation time 280179793753 ps
CPU time 107.85 seconds
Started Aug 09 07:21:34 PM PDT 24
Finished Aug 09 07:23:22 PM PDT 24
Peak memory 199980 kb
Host smart-bbac3613-f74d-42ac-8de3-68467ca67848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697949852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1697949852
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2959605995
Short name T1068
Test name
Test status
Simulation time 231894590800 ps
CPU time 108.02 seconds
Started Aug 09 07:21:40 PM PDT 24
Finished Aug 09 07:23:28 PM PDT 24
Peak memory 199840 kb
Host smart-c9e4cd56-40fd-4120-9694-00fbbfc899b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959605995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2959605995
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.357343560
Short name T1155
Test name
Test status
Simulation time 13770908282 ps
CPU time 22.2 seconds
Started Aug 09 07:21:34 PM PDT 24
Finished Aug 09 07:21:57 PM PDT 24
Peak memory 199896 kb
Host smart-37c41d12-6a19-424d-8386-74361eb6f585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357343560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.357343560
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1873882443
Short name T386
Test name
Test status
Simulation time 188710917343 ps
CPU time 73.82 seconds
Started Aug 09 07:21:35 PM PDT 24
Finished Aug 09 07:22:49 PM PDT 24
Peak memory 199812 kb
Host smart-a09f3bb3-e4b1-458f-826c-08ad4bcc0a83
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873882443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1873882443
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2606368870
Short name T931
Test name
Test status
Simulation time 116463331378 ps
CPU time 109.47 seconds
Started Aug 09 07:21:49 PM PDT 24
Finished Aug 09 07:23:38 PM PDT 24
Peak memory 199736 kb
Host smart-8bf8d95e-4c53-496c-9c41-eec7c7d9db8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2606368870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2606368870
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.232548109
Short name T929
Test name
Test status
Simulation time 9729785467 ps
CPU time 18.26 seconds
Started Aug 09 07:21:49 PM PDT 24
Finished Aug 09 07:22:07 PM PDT 24
Peak memory 198996 kb
Host smart-8362fd66-eac8-4adb-b9ae-712e0401d07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232548109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.232548109
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2345167498
Short name T678
Test name
Test status
Simulation time 45716532414 ps
CPU time 34.48 seconds
Started Aug 09 07:21:39 PM PDT 24
Finished Aug 09 07:22:13 PM PDT 24
Peak memory 199632 kb
Host smart-be33228e-960f-4e56-8942-85cc779df6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345167498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2345167498
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.561009575
Short name T671
Test name
Test status
Simulation time 14822328843 ps
CPU time 404.59 seconds
Started Aug 09 07:21:33 PM PDT 24
Finished Aug 09 07:28:18 PM PDT 24
Peak memory 199964 kb
Host smart-f34aa5ed-a937-457e-bf84-9577073b73da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=561009575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.561009575
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.113535144
Short name T598
Test name
Test status
Simulation time 6684352831 ps
CPU time 6.81 seconds
Started Aug 09 07:21:49 PM PDT 24
Finished Aug 09 07:21:56 PM PDT 24
Peak memory 197616 kb
Host smart-29075940-043d-4c36-b7ae-3a58ff9173a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=113535144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.113535144
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.602146521
Short name T838
Test name
Test status
Simulation time 195492203816 ps
CPU time 65.63 seconds
Started Aug 09 07:21:34 PM PDT 24
Finished Aug 09 07:22:40 PM PDT 24
Peak memory 199932 kb
Host smart-5ba486c4-ea09-4db1-9e6e-f3d6fa369e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602146521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.602146521
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3374768969
Short name T1046
Test name
Test status
Simulation time 703621735 ps
CPU time 1.65 seconds
Started Aug 09 07:21:33 PM PDT 24
Finished Aug 09 07:21:35 PM PDT 24
Peak memory 195384 kb
Host smart-32e03e52-a3bb-4392-9ba5-9f35155150c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374768969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3374768969
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3089709050
Short name T449
Test name
Test status
Simulation time 957322082 ps
CPU time 1.76 seconds
Started Aug 09 07:21:40 PM PDT 24
Finished Aug 09 07:21:42 PM PDT 24
Peak memory 198736 kb
Host smart-a18403da-d2ef-4c66-b7f5-0e3e62469eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089709050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3089709050
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1731829450
Short name T812
Test name
Test status
Simulation time 12545176497 ps
CPU time 96.77 seconds
Started Aug 09 07:21:46 PM PDT 24
Finished Aug 09 07:23:23 PM PDT 24
Peak memory 216200 kb
Host smart-cd0d57ed-bd86-46e3-9f36-7f2b65ef459a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731829450 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1731829450
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.2940327012
Short name T19
Test name
Test status
Simulation time 972500944 ps
CPU time 1.77 seconds
Started Aug 09 07:21:47 PM PDT 24
Finished Aug 09 07:21:49 PM PDT 24
Peak memory 199680 kb
Host smart-be1d9528-28e3-4abd-bb17-e9cf27dc8204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940327012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2940327012
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.898819451
Short name T1081
Test name
Test status
Simulation time 98947792434 ps
CPU time 121.74 seconds
Started Aug 09 07:21:36 PM PDT 24
Finished Aug 09 07:23:38 PM PDT 24
Peak memory 199912 kb
Host smart-039f5c4d-b7f3-438b-90f6-c24966940deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898819451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.898819451
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1779789218
Short name T585
Test name
Test status
Simulation time 65873521 ps
CPU time 0.57 seconds
Started Aug 09 07:21:49 PM PDT 24
Finished Aug 09 07:21:50 PM PDT 24
Peak memory 195188 kb
Host smart-f75d99cd-74c3-4408-bfbd-91659547f23a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779789218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1779789218
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.825194300
Short name T987
Test name
Test status
Simulation time 26903965255 ps
CPU time 16.9 seconds
Started Aug 09 07:21:41 PM PDT 24
Finished Aug 09 07:21:58 PM PDT 24
Peak memory 199920 kb
Host smart-5f309eb3-53cb-490b-98e6-f278aa3fb89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825194300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.825194300
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1679551988
Short name T718
Test name
Test status
Simulation time 57790582288 ps
CPU time 46.01 seconds
Started Aug 09 07:21:44 PM PDT 24
Finished Aug 09 07:22:30 PM PDT 24
Peak memory 199964 kb
Host smart-28643c55-b5a5-42ef-b832-d0b51cc1998a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679551988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1679551988
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.350993987
Short name T797
Test name
Test status
Simulation time 14558176982 ps
CPU time 19.13 seconds
Started Aug 09 07:21:41 PM PDT 24
Finished Aug 09 07:22:01 PM PDT 24
Peak memory 199900 kb
Host smart-d93afc4a-9cdb-4a6c-946f-2fcf13b57b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350993987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.350993987
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2318862437
Short name T455
Test name
Test status
Simulation time 27900333484 ps
CPU time 14.66 seconds
Started Aug 09 07:21:42 PM PDT 24
Finished Aug 09 07:21:56 PM PDT 24
Peak memory 199944 kb
Host smart-87b99752-bc48-457f-80f4-97270eb621a7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318862437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2318862437
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.874312548
Short name T383
Test name
Test status
Simulation time 123416840843 ps
CPU time 293.6 seconds
Started Aug 09 07:21:41 PM PDT 24
Finished Aug 09 07:26:35 PM PDT 24
Peak memory 199956 kb
Host smart-28e18083-3d64-4a12-beae-f87e38854e51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=874312548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.874312548
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.3700575354
Short name T353
Test name
Test status
Simulation time 5187604342 ps
CPU time 11.33 seconds
Started Aug 09 07:21:42 PM PDT 24
Finished Aug 09 07:21:53 PM PDT 24
Peak memory 199248 kb
Host smart-7e237ebb-0ebe-4299-88b3-85c114827518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700575354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3700575354
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.66034781
Short name T552
Test name
Test status
Simulation time 26037903759 ps
CPU time 41.4 seconds
Started Aug 09 07:21:43 PM PDT 24
Finished Aug 09 07:22:24 PM PDT 24
Peak memory 200012 kb
Host smart-e68084da-e596-4aab-9044-64efaaf381c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66034781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.66034781
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.636692165
Short name T254
Test name
Test status
Simulation time 16711002846 ps
CPU time 678.39 seconds
Started Aug 09 07:21:43 PM PDT 24
Finished Aug 09 07:33:02 PM PDT 24
Peak memory 199888 kb
Host smart-b395bf6d-0c5f-4d44-88a0-41a08ef486f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=636692165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.636692165
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.4084830998
Short name T1010
Test name
Test status
Simulation time 7477341795 ps
CPU time 65.72 seconds
Started Aug 09 07:21:42 PM PDT 24
Finished Aug 09 07:22:47 PM PDT 24
Peak memory 199912 kb
Host smart-32c8f293-b16b-4f81-8874-eb3de99cf517
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4084830998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.4084830998
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.4204266181
Short name T760
Test name
Test status
Simulation time 25306979259 ps
CPU time 11.01 seconds
Started Aug 09 07:21:40 PM PDT 24
Finished Aug 09 07:21:51 PM PDT 24
Peak memory 199904 kb
Host smart-6303056e-696b-4010-96be-955bf1163e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204266181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.4204266181
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2645582471
Short name T1114
Test name
Test status
Simulation time 494479351 ps
CPU time 0.82 seconds
Started Aug 09 07:21:42 PM PDT 24
Finished Aug 09 07:21:43 PM PDT 24
Peak memory 195440 kb
Host smart-f075c88e-8898-4f98-a53d-1642f7599f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645582471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2645582471
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2189842515
Short name T845
Test name
Test status
Simulation time 679799804 ps
CPU time 1.72 seconds
Started Aug 09 07:21:32 PM PDT 24
Finished Aug 09 07:21:34 PM PDT 24
Peak memory 198176 kb
Host smart-48bad4c8-a3f9-4ff1-b3ba-1069c75b5861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189842515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2189842515
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3379695943
Short name T908
Test name
Test status
Simulation time 204437501069 ps
CPU time 987.4 seconds
Started Aug 09 07:21:42 PM PDT 24
Finished Aug 09 07:38:09 PM PDT 24
Peak memory 208368 kb
Host smart-08154f57-4835-4f17-9f6d-299a9a3892ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379695943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3379695943
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1467609915
Short name T664
Test name
Test status
Simulation time 231306588564 ps
CPU time 484.95 seconds
Started Aug 09 07:21:42 PM PDT 24
Finished Aug 09 07:29:47 PM PDT 24
Peak memory 216444 kb
Host smart-fda0e4a9-38b3-4345-96f9-5050bcf5b3d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467609915 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1467609915
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2869569148
Short name T865
Test name
Test status
Simulation time 12579338576 ps
CPU time 41 seconds
Started Aug 09 07:21:42 PM PDT 24
Finished Aug 09 07:22:23 PM PDT 24
Peak memory 199792 kb
Host smart-1ca36875-28e0-43d1-86b3-870350019a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869569148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2869569148
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.460236685
Short name T43
Test name
Test status
Simulation time 93271279427 ps
CPU time 58.7 seconds
Started Aug 09 07:21:40 PM PDT 24
Finished Aug 09 07:22:39 PM PDT 24
Peak memory 199904 kb
Host smart-9117b5b6-c08f-4633-a128-31c8ec8c0040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460236685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.460236685
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.455824442
Short name T882
Test name
Test status
Simulation time 14782024 ps
CPU time 0.57 seconds
Started Aug 09 07:21:50 PM PDT 24
Finished Aug 09 07:21:51 PM PDT 24
Peak memory 194544 kb
Host smart-3d7d7686-7e18-4178-a775-565221ecb54d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455824442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.455824442
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.3845516698
Short name T1040
Test name
Test status
Simulation time 33869751707 ps
CPU time 28.73 seconds
Started Aug 09 07:21:43 PM PDT 24
Finished Aug 09 07:22:12 PM PDT 24
Peak memory 199980 kb
Host smart-b1f9bf96-6466-4a4c-aa4e-05393e8f8032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845516698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3845516698
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3155268240
Short name T123
Test name
Test status
Simulation time 112241038391 ps
CPU time 22.98 seconds
Started Aug 09 07:21:43 PM PDT 24
Finished Aug 09 07:22:06 PM PDT 24
Peak memory 199900 kb
Host smart-63272366-3bd5-49c0-ad64-a794af22ad96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155268240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3155268240
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2701481721
Short name T1158
Test name
Test status
Simulation time 134703972880 ps
CPU time 110.84 seconds
Started Aug 09 07:21:44 PM PDT 24
Finished Aug 09 07:23:35 PM PDT 24
Peak memory 199864 kb
Host smart-fe287a26-ab15-42d8-b778-a9416ea8a72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701481721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2701481721
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.607047069
Short name T1113
Test name
Test status
Simulation time 345223833338 ps
CPU time 617.63 seconds
Started Aug 09 07:21:42 PM PDT 24
Finished Aug 09 07:32:00 PM PDT 24
Peak memory 199984 kb
Host smart-0c2ff6ef-7529-4f84-b54d-adfa1015d605
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607047069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.607047069
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2683298924
Short name T774
Test name
Test status
Simulation time 127285058937 ps
CPU time 865.76 seconds
Started Aug 09 07:21:51 PM PDT 24
Finished Aug 09 07:36:17 PM PDT 24
Peak memory 199868 kb
Host smart-587bd21d-cff8-4c7b-af6d-57f4826d1805
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2683298924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2683298924
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.640355154
Short name T696
Test name
Test status
Simulation time 12254625744 ps
CPU time 15.72 seconds
Started Aug 09 07:21:49 PM PDT 24
Finished Aug 09 07:22:05 PM PDT 24
Peak memory 199836 kb
Host smart-b356d786-9cee-4b83-ab31-72a7d3416bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640355154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.640355154
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3992741808
Short name T1134
Test name
Test status
Simulation time 93225133647 ps
CPU time 48.06 seconds
Started Aug 09 07:21:45 PM PDT 24
Finished Aug 09 07:22:33 PM PDT 24
Peak memory 200044 kb
Host smart-9d4a8b5f-a644-42c3-8124-bfed08b8dce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992741808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3992741808
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.3163028607
Short name T324
Test name
Test status
Simulation time 4291919253 ps
CPU time 124.31 seconds
Started Aug 09 07:21:49 PM PDT 24
Finished Aug 09 07:23:53 PM PDT 24
Peak memory 199948 kb
Host smart-22c7b83b-5baf-44dd-a460-fa6627064f2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3163028607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3163028607
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.840598820
Short name T1128
Test name
Test status
Simulation time 4079217715 ps
CPU time 27.82 seconds
Started Aug 09 07:21:43 PM PDT 24
Finished Aug 09 07:22:11 PM PDT 24
Peak memory 198356 kb
Host smart-211ead09-38a9-4ce9-b35b-741fb5412fee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=840598820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.840598820
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1892543350
Short name T1180
Test name
Test status
Simulation time 85637190621 ps
CPU time 151.32 seconds
Started Aug 09 07:21:49 PM PDT 24
Finished Aug 09 07:24:20 PM PDT 24
Peak memory 199952 kb
Host smart-86ac81f2-0951-4a0e-98ec-180d15c61248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892543350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1892543350
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.755070176
Short name T438
Test name
Test status
Simulation time 843967265 ps
CPU time 1.28 seconds
Started Aug 09 07:21:49 PM PDT 24
Finished Aug 09 07:21:50 PM PDT 24
Peak memory 195660 kb
Host smart-56367482-9ac3-438d-9218-a0b53782d243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755070176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.755070176
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2878524391
Short name T844
Test name
Test status
Simulation time 471546096 ps
CPU time 1.39 seconds
Started Aug 09 07:21:43 PM PDT 24
Finished Aug 09 07:21:44 PM PDT 24
Peak memory 198976 kb
Host smart-27f848ab-935c-453a-b0a2-9a0917903eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878524391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2878524391
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3732577870
Short name T793
Test name
Test status
Simulation time 907494094 ps
CPU time 1.21 seconds
Started Aug 09 07:21:49 PM PDT 24
Finished Aug 09 07:21:50 PM PDT 24
Peak memory 199392 kb
Host smart-90a75c06-4764-45ca-b4e7-0d74fb3ccf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732577870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3732577870
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.923930820
Short name T689
Test name
Test status
Simulation time 114713637850 ps
CPU time 85.06 seconds
Started Aug 09 07:21:49 PM PDT 24
Finished Aug 09 07:23:14 PM PDT 24
Peak memory 199776 kb
Host smart-30f69b52-5409-4185-838b-6083286cc3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923930820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.923930820
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3632915600
Short name T658
Test name
Test status
Simulation time 21791378 ps
CPU time 0.56 seconds
Started Aug 09 07:18:52 PM PDT 24
Finished Aug 09 07:18:53 PM PDT 24
Peak memory 195348 kb
Host smart-4fdd8601-ad1c-42d7-9d11-421199bcb24a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632915600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3632915600
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3730373786
Short name T587
Test name
Test status
Simulation time 43927561000 ps
CPU time 69.04 seconds
Started Aug 09 07:18:48 PM PDT 24
Finished Aug 09 07:19:57 PM PDT 24
Peak memory 199928 kb
Host smart-e434ecff-3afd-47ed-b400-0f035cb6c120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730373786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3730373786
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1494487582
Short name T614
Test name
Test status
Simulation time 84545044392 ps
CPU time 162.63 seconds
Started Aug 09 07:18:51 PM PDT 24
Finished Aug 09 07:21:33 PM PDT 24
Peak memory 199944 kb
Host smart-023dfb89-fdbd-44f8-93a7-96268fdc7ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494487582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1494487582
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3567808610
Short name T199
Test name
Test status
Simulation time 180799707265 ps
CPU time 128.77 seconds
Started Aug 09 07:18:50 PM PDT 24
Finished Aug 09 07:20:59 PM PDT 24
Peak memory 199880 kb
Host smart-d284ba5d-ca89-472c-bbae-222d987d5f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567808610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3567808610
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2701418599
Short name T757
Test name
Test status
Simulation time 458385554627 ps
CPU time 839.88 seconds
Started Aug 09 07:18:54 PM PDT 24
Finished Aug 09 07:32:54 PM PDT 24
Peak memory 199212 kb
Host smart-558aa13c-77dc-44fa-84cc-1e35f3d62996
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701418599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2701418599
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1662340447
Short name T827
Test name
Test status
Simulation time 46412933248 ps
CPU time 167.46 seconds
Started Aug 09 07:18:51 PM PDT 24
Finished Aug 09 07:21:39 PM PDT 24
Peak memory 199880 kb
Host smart-62dc92b1-3f11-48e4-8514-eec3b96287e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1662340447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1662340447
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.4239834533
Short name T879
Test name
Test status
Simulation time 9618581997 ps
CPU time 19.42 seconds
Started Aug 09 07:18:56 PM PDT 24
Finished Aug 09 07:19:15 PM PDT 24
Peak memory 199880 kb
Host smart-d235b91f-e94e-400f-bb4b-db6d3132eab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239834533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.4239834533
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2851389421
Short name T770
Test name
Test status
Simulation time 6422412659 ps
CPU time 10.37 seconds
Started Aug 09 07:18:54 PM PDT 24
Finished Aug 09 07:19:05 PM PDT 24
Peak memory 194516 kb
Host smart-872b61bf-7053-486f-b523-6c28bf06edc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851389421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2851389421
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.4026548918
Short name T747
Test name
Test status
Simulation time 24577554656 ps
CPU time 740.98 seconds
Started Aug 09 07:18:49 PM PDT 24
Finished Aug 09 07:31:10 PM PDT 24
Peak memory 199940 kb
Host smart-4ad0c517-5aeb-46f7-a6a2-64b036b58c13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4026548918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.4026548918
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.724600199
Short name T628
Test name
Test status
Simulation time 4854945429 ps
CPU time 10.44 seconds
Started Aug 09 07:18:51 PM PDT 24
Finished Aug 09 07:19:01 PM PDT 24
Peak memory 199760 kb
Host smart-97c683d2-6510-4652-bd2e-8ab71eb28603
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=724600199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.724600199
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2115030084
Short name T460
Test name
Test status
Simulation time 206080929019 ps
CPU time 180.56 seconds
Started Aug 09 07:18:55 PM PDT 24
Finished Aug 09 07:21:56 PM PDT 24
Peak memory 199896 kb
Host smart-6734cc88-537a-482f-831a-f8d62840ef36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115030084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2115030084
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2816645752
Short name T419
Test name
Test status
Simulation time 4268079438 ps
CPU time 6.8 seconds
Started Aug 09 07:18:49 PM PDT 24
Finished Aug 09 07:18:56 PM PDT 24
Peak memory 196816 kb
Host smart-d4466aa7-263e-45d1-82cb-7ff2188057e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816645752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2816645752
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.879678679
Short name T27
Test name
Test status
Simulation time 523962029 ps
CPU time 0.92 seconds
Started Aug 09 07:18:50 PM PDT 24
Finished Aug 09 07:18:51 PM PDT 24
Peak memory 218348 kb
Host smart-9ca526b1-706e-4d5c-942e-840dd2d2b4b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879678679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.879678679
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.548398159
Short name T698
Test name
Test status
Simulation time 6210994861 ps
CPU time 17.12 seconds
Started Aug 09 07:18:50 PM PDT 24
Finished Aug 09 07:19:07 PM PDT 24
Peak memory 199416 kb
Host smart-e13efee1-9f35-4fa2-9953-c34ae6dbd3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548398159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.548398159
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1734453378
Short name T1051
Test name
Test status
Simulation time 180672308602 ps
CPU time 517 seconds
Started Aug 09 07:18:49 PM PDT 24
Finished Aug 09 07:27:26 PM PDT 24
Peak memory 216596 kb
Host smart-172ae802-0762-4360-9691-de4cbd3dfc2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734453378 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1734453378
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1358037749
Short name T388
Test name
Test status
Simulation time 1198049165 ps
CPU time 2.76 seconds
Started Aug 09 07:18:49 PM PDT 24
Finished Aug 09 07:18:52 PM PDT 24
Peak memory 198916 kb
Host smart-c101c93e-fa0a-4b36-b8ea-2fc8e7a1e667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358037749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1358037749
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.194343103
Short name T940
Test name
Test status
Simulation time 29280107301 ps
CPU time 43.96 seconds
Started Aug 09 07:18:50 PM PDT 24
Finished Aug 09 07:19:34 PM PDT 24
Peak memory 199876 kb
Host smart-9fdd55c9-c8f3-4d22-94d1-b74c51c1b975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194343103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.194343103
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1110054116
Short name T25
Test name
Test status
Simulation time 12634857 ps
CPU time 0.56 seconds
Started Aug 09 07:21:55 PM PDT 24
Finished Aug 09 07:21:56 PM PDT 24
Peak memory 195312 kb
Host smart-8d45b92a-51f6-4522-850f-de60e0e7ad68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110054116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1110054116
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1680641243
Short name T396
Test name
Test status
Simulation time 163504369289 ps
CPU time 419.75 seconds
Started Aug 09 07:21:50 PM PDT 24
Finished Aug 09 07:28:50 PM PDT 24
Peak memory 199976 kb
Host smart-6ace7bb9-598d-4ed2-ac09-90d6e3f4dc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680641243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1680641243
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2765510166
Short name T893
Test name
Test status
Simulation time 84858364076 ps
CPU time 12.47 seconds
Started Aug 09 07:21:49 PM PDT 24
Finished Aug 09 07:22:02 PM PDT 24
Peak memory 199904 kb
Host smart-79e39d96-a523-4fbd-8872-62bee61febec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765510166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2765510166
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1806392906
Short name T1179
Test name
Test status
Simulation time 60149180841 ps
CPU time 25.29 seconds
Started Aug 09 07:21:49 PM PDT 24
Finished Aug 09 07:22:15 PM PDT 24
Peak memory 199892 kb
Host smart-e53d6efc-d221-4b26-993b-bf4e0c865adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806392906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1806392906
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2235718038
Short name T589
Test name
Test status
Simulation time 56689063345 ps
CPU time 40.18 seconds
Started Aug 09 07:21:49 PM PDT 24
Finished Aug 09 07:22:29 PM PDT 24
Peak memory 199912 kb
Host smart-3082dbce-b1a6-42ff-99ec-2f6aa45848e1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235718038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2235718038
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.1812054821
Short name T394
Test name
Test status
Simulation time 51013619285 ps
CPU time 87.89 seconds
Started Aug 09 07:21:50 PM PDT 24
Finished Aug 09 07:23:18 PM PDT 24
Peak memory 199880 kb
Host smart-e40025ab-e094-4a71-afc8-87354a196d51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1812054821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1812054821
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2055692279
Short name T349
Test name
Test status
Simulation time 9115722138 ps
CPU time 18.77 seconds
Started Aug 09 07:21:53 PM PDT 24
Finished Aug 09 07:22:12 PM PDT 24
Peak memory 199836 kb
Host smart-be47cfb9-e50b-4adf-b726-f2a6f2e0608e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055692279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2055692279
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.3640446133
Short name T473
Test name
Test status
Simulation time 33166129886 ps
CPU time 13.39 seconds
Started Aug 09 07:21:53 PM PDT 24
Finished Aug 09 07:22:06 PM PDT 24
Peak memory 199852 kb
Host smart-7c0e88d7-33e8-4602-bd32-942d4901a39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640446133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.3640446133
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.2702092773
Short name T299
Test name
Test status
Simulation time 9655613805 ps
CPU time 143.03 seconds
Started Aug 09 07:21:50 PM PDT 24
Finished Aug 09 07:24:13 PM PDT 24
Peak memory 199876 kb
Host smart-c7ff79db-363e-4326-8df6-a283ba9bfb00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2702092773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2702092773
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3311021248
Short name T1165
Test name
Test status
Simulation time 6950089017 ps
CPU time 66.62 seconds
Started Aug 09 07:21:53 PM PDT 24
Finished Aug 09 07:23:00 PM PDT 24
Peak memory 198800 kb
Host smart-569a1c9b-428b-445b-b20b-cb915de0b3c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3311021248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3311021248
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.949165191
Short name T804
Test name
Test status
Simulation time 142877704164 ps
CPU time 42.48 seconds
Started Aug 09 07:21:50 PM PDT 24
Finished Aug 09 07:22:32 PM PDT 24
Peak memory 199912 kb
Host smart-4f2e560d-48c8-482b-8514-a82244ec8822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949165191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.949165191
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2982447722
Short name T580
Test name
Test status
Simulation time 564414525 ps
CPU time 0.82 seconds
Started Aug 09 07:21:50 PM PDT 24
Finished Aug 09 07:21:51 PM PDT 24
Peak memory 195392 kb
Host smart-89da725d-5498-4289-856a-56cb49d2162f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982447722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2982447722
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3533267911
Short name T4
Test name
Test status
Simulation time 660395268 ps
CPU time 1.43 seconds
Started Aug 09 07:21:51 PM PDT 24
Finished Aug 09 07:21:52 PM PDT 24
Peak memory 199588 kb
Host smart-02ec9250-a18f-4cef-9f44-f0a4f5f9288c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533267911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3533267911
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3974055802
Short name T401
Test name
Test status
Simulation time 189722485517 ps
CPU time 182.17 seconds
Started Aug 09 07:21:51 PM PDT 24
Finished Aug 09 07:24:53 PM PDT 24
Peak memory 199984 kb
Host smart-28361f11-02c7-4508-a848-4f2f3d452a15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974055802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3974055802
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2324628225
Short name T822
Test name
Test status
Simulation time 2094301818 ps
CPU time 1.64 seconds
Started Aug 09 07:21:52 PM PDT 24
Finished Aug 09 07:21:54 PM PDT 24
Peak memory 198276 kb
Host smart-4c96b7b9-c5bd-47f8-a455-9324e707c1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324628225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2324628225
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2900669686
Short name T556
Test name
Test status
Simulation time 28586688352 ps
CPU time 49.81 seconds
Started Aug 09 07:21:50 PM PDT 24
Finished Aug 09 07:22:40 PM PDT 24
Peak memory 199948 kb
Host smart-f1a14269-d8be-44c4-8d88-508f667f2616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900669686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2900669686
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1416667993
Short name T619
Test name
Test status
Simulation time 26226093 ps
CPU time 0.55 seconds
Started Aug 09 07:22:05 PM PDT 24
Finished Aug 09 07:22:06 PM PDT 24
Peak memory 195596 kb
Host smart-5cc04b52-a41a-4760-9507-aa90aad07bc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416667993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1416667993
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.901597988
Short name T883
Test name
Test status
Simulation time 148947608938 ps
CPU time 114.6 seconds
Started Aug 09 07:21:57 PM PDT 24
Finished Aug 09 07:23:51 PM PDT 24
Peak memory 199968 kb
Host smart-468d2881-6129-407e-8338-145af2ff80c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901597988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.901597988
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3022090599
Short name T421
Test name
Test status
Simulation time 22365015474 ps
CPU time 37.4 seconds
Started Aug 09 07:22:04 PM PDT 24
Finished Aug 09 07:22:41 PM PDT 24
Peak memory 199712 kb
Host smart-76f9c53f-245c-4e1e-bba2-0dcd1a5d1594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022090599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3022090599
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.219006385
Short name T969
Test name
Test status
Simulation time 24499970662 ps
CPU time 39.86 seconds
Started Aug 09 07:22:05 PM PDT 24
Finished Aug 09 07:22:44 PM PDT 24
Peak memory 199728 kb
Host smart-16e3f8ee-f341-454d-b4c0-4f5d1a989045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219006385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.219006385
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2189815383
Short name T1163
Test name
Test status
Simulation time 10392217313 ps
CPU time 1.79 seconds
Started Aug 09 07:21:57 PM PDT 24
Finished Aug 09 07:21:58 PM PDT 24
Peak memory 198656 kb
Host smart-514b65d1-2161-417d-b4a2-288f2ca9366e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189815383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2189815383
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.4227688103
Short name T510
Test name
Test status
Simulation time 79596613927 ps
CPU time 508.92 seconds
Started Aug 09 07:22:05 PM PDT 24
Finished Aug 09 07:30:34 PM PDT 24
Peak memory 199972 kb
Host smart-766de60a-dbf5-477f-aede-e9f20d9fe6b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4227688103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.4227688103
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1080938387
Short name T745
Test name
Test status
Simulation time 6598136369 ps
CPU time 5.36 seconds
Started Aug 09 07:21:58 PM PDT 24
Finished Aug 09 07:22:03 PM PDT 24
Peak memory 199704 kb
Host smart-80fb783c-0f33-45d9-9b93-a836d75e2b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080938387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1080938387
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1254709175
Short name T1131
Test name
Test status
Simulation time 74167262176 ps
CPU time 84.64 seconds
Started Aug 09 07:21:57 PM PDT 24
Finished Aug 09 07:23:22 PM PDT 24
Peak memory 200092 kb
Host smart-d20068fe-0b62-436b-96de-4475664661b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254709175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1254709175
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2302305719
Short name T533
Test name
Test status
Simulation time 2199508207 ps
CPU time 34.88 seconds
Started Aug 09 07:22:04 PM PDT 24
Finished Aug 09 07:22:39 PM PDT 24
Peak memory 199992 kb
Host smart-6f41c6af-ce9f-4f01-9df9-cb523810ad19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2302305719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2302305719
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2316811242
Short name T813
Test name
Test status
Simulation time 6210407137 ps
CPU time 28.13 seconds
Started Aug 09 07:21:59 PM PDT 24
Finished Aug 09 07:22:27 PM PDT 24
Peak memory 198048 kb
Host smart-43aa473f-32e2-4db3-a60e-ca9b5243f18c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2316811242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2316811242
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2873057212
Short name T185
Test name
Test status
Simulation time 45508653848 ps
CPU time 37.6 seconds
Started Aug 09 07:21:59 PM PDT 24
Finished Aug 09 07:22:36 PM PDT 24
Peak memory 199928 kb
Host smart-44020b42-2e16-4f01-bd11-b32649a9f63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873057212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2873057212
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3152553722
Short name T869
Test name
Test status
Simulation time 40985212580 ps
CPU time 61.01 seconds
Started Aug 09 07:21:56 PM PDT 24
Finished Aug 09 07:22:57 PM PDT 24
Peak memory 195800 kb
Host smart-be12772d-417e-4673-8000-82bab9e08237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152553722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3152553722
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2081833874
Short name T358
Test name
Test status
Simulation time 5312018190 ps
CPU time 17.22 seconds
Started Aug 09 07:21:57 PM PDT 24
Finished Aug 09 07:22:15 PM PDT 24
Peak memory 199796 kb
Host smart-2ee7aa1a-4917-4776-ac85-bfc213e010c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081833874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2081833874
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.907014760
Short name T878
Test name
Test status
Simulation time 143745715280 ps
CPU time 231.57 seconds
Started Aug 09 07:22:04 PM PDT 24
Finished Aug 09 07:25:56 PM PDT 24
Peak memory 199912 kb
Host smart-366bf93a-6a3e-447c-94b8-7afab3700f49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907014760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.907014760
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.777023566
Short name T750
Test name
Test status
Simulation time 51294091862 ps
CPU time 1284.15 seconds
Started Aug 09 07:22:05 PM PDT 24
Finished Aug 09 07:43:29 PM PDT 24
Peak memory 224800 kb
Host smart-dc7a1ab7-b0cc-44e9-8a90-7493e7209d31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777023566 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.777023566
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2019374538
Short name T1086
Test name
Test status
Simulation time 844348829 ps
CPU time 3.08 seconds
Started Aug 09 07:21:58 PM PDT 24
Finished Aug 09 07:22:01 PM PDT 24
Peak memory 198852 kb
Host smart-73699ea4-74c1-47c7-9648-95fa643049c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019374538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2019374538
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3771355934
Short name T999
Test name
Test status
Simulation time 956946807 ps
CPU time 1.22 seconds
Started Aug 09 07:21:59 PM PDT 24
Finished Aug 09 07:22:00 PM PDT 24
Peak memory 196668 kb
Host smart-9452efa5-e80f-47c7-9455-a2a3c1f4c4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771355934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3771355934
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1044988422
Short name T769
Test name
Test status
Simulation time 15888717 ps
CPU time 0.6 seconds
Started Aug 09 07:22:11 PM PDT 24
Finished Aug 09 07:22:12 PM PDT 24
Peak memory 195324 kb
Host smart-ed3d87a5-09e5-41b7-91e0-0927c1d194f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044988422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1044988422
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.616297389
Short name T368
Test name
Test status
Simulation time 46823118603 ps
CPU time 62.26 seconds
Started Aug 09 07:22:05 PM PDT 24
Finished Aug 09 07:23:07 PM PDT 24
Peak memory 199908 kb
Host smart-bc568c78-6401-4cb7-a28b-f7b8a08c5091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616297389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.616297389
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1310822807
Short name T174
Test name
Test status
Simulation time 15844625216 ps
CPU time 14.23 seconds
Started Aug 09 07:22:05 PM PDT 24
Finished Aug 09 07:22:19 PM PDT 24
Peak memory 199608 kb
Host smart-ea6d67cc-3b1d-42b7-bad5-64103ccd80ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310822807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1310822807
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2420326053
Short name T309
Test name
Test status
Simulation time 11883071230 ps
CPU time 18.81 seconds
Started Aug 09 07:22:05 PM PDT 24
Finished Aug 09 07:22:24 PM PDT 24
Peak memory 199896 kb
Host smart-9ec7041d-3ca0-44df-9c4c-49d26bb71581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420326053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2420326053
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2317921911
Short name T288
Test name
Test status
Simulation time 29823146124 ps
CPU time 27.6 seconds
Started Aug 09 07:22:06 PM PDT 24
Finished Aug 09 07:22:34 PM PDT 24
Peak memory 199844 kb
Host smart-ccbc8f5a-b145-4207-9e6e-a61700146325
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317921911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2317921911
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3168779145
Short name T811
Test name
Test status
Simulation time 160533215615 ps
CPU time 207.89 seconds
Started Aug 09 07:22:15 PM PDT 24
Finished Aug 09 07:25:43 PM PDT 24
Peak memory 199840 kb
Host smart-8f372e56-129a-43bf-aa13-1c1b52eb1ca0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3168779145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3168779145
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.160862187
Short name T1037
Test name
Test status
Simulation time 8873637031 ps
CPU time 11.32 seconds
Started Aug 09 07:22:04 PM PDT 24
Finished Aug 09 07:22:15 PM PDT 24
Peak memory 199928 kb
Host smart-8720864f-c5e8-41b7-9e5b-df504fe58811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160862187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.160862187
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1631178295
Short name T264
Test name
Test status
Simulation time 10302803925 ps
CPU time 19.45 seconds
Started Aug 09 07:22:11 PM PDT 24
Finished Aug 09 07:22:30 PM PDT 24
Peak memory 198212 kb
Host smart-75215c03-d556-41b8-ad47-2444d4984b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631178295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1631178295
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.301291970
Short name T316
Test name
Test status
Simulation time 10410459008 ps
CPU time 577.85 seconds
Started Aug 09 07:22:04 PM PDT 24
Finished Aug 09 07:31:42 PM PDT 24
Peak memory 200168 kb
Host smart-7d5cc638-d7ca-46e7-84b6-c5cf9f883b39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=301291970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.301291970
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3654220136
Short name T385
Test name
Test status
Simulation time 2119644930 ps
CPU time 9.66 seconds
Started Aug 09 07:22:05 PM PDT 24
Finished Aug 09 07:22:14 PM PDT 24
Peak memory 197980 kb
Host smart-dce7075c-862b-4ee6-b541-01dff3df0b31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3654220136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3654220136
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.4013308840
Short name T60
Test name
Test status
Simulation time 88034418613 ps
CPU time 25.34 seconds
Started Aug 09 07:22:05 PM PDT 24
Finished Aug 09 07:22:31 PM PDT 24
Peak memory 199900 kb
Host smart-3d9dafcb-2bbe-45b5-9585-43993ecd2b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013308840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.4013308840
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3472117890
Short name T382
Test name
Test status
Simulation time 40550076670 ps
CPU time 14.38 seconds
Started Aug 09 07:22:05 PM PDT 24
Finished Aug 09 07:22:19 PM PDT 24
Peak memory 195824 kb
Host smart-a25b7284-6701-4b95-8a3c-1b51c21d0f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472117890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3472117890
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1890102056
Short name T679
Test name
Test status
Simulation time 507288914 ps
CPU time 1.72 seconds
Started Aug 09 07:22:06 PM PDT 24
Finished Aug 09 07:22:07 PM PDT 24
Peak memory 198604 kb
Host smart-ad43f134-6a92-44dc-99f1-44505b02bb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890102056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1890102056
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2917583142
Short name T46
Test name
Test status
Simulation time 46091581657 ps
CPU time 253.89 seconds
Started Aug 09 07:22:13 PM PDT 24
Finished Aug 09 07:26:27 PM PDT 24
Peak memory 214376 kb
Host smart-29225b54-cb8d-43e8-96ba-97aef7977918
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917583142 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2917583142
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3590890918
Short name T670
Test name
Test status
Simulation time 12560924012 ps
CPU time 42.52 seconds
Started Aug 09 07:22:05 PM PDT 24
Finished Aug 09 07:22:48 PM PDT 24
Peak memory 199936 kb
Host smart-ccb8c768-cfdf-4e60-a4fd-c440da85514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590890918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3590890918
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.84665852
Short name T469
Test name
Test status
Simulation time 101314127593 ps
CPU time 34.36 seconds
Started Aug 09 07:22:05 PM PDT 24
Finished Aug 09 07:22:40 PM PDT 24
Peak memory 199964 kb
Host smart-3806785e-a382-4950-b942-3599d5426a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84665852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.84665852
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1283428050
Short name T961
Test name
Test status
Simulation time 20092222 ps
CPU time 0.57 seconds
Started Aug 09 07:22:13 PM PDT 24
Finished Aug 09 07:22:14 PM PDT 24
Peak memory 195592 kb
Host smart-dc8ce449-9ebf-434e-b1e7-8bfc8d4c711e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283428050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1283428050
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.456446449
Short name T139
Test name
Test status
Simulation time 126046240501 ps
CPU time 34.77 seconds
Started Aug 09 07:22:13 PM PDT 24
Finished Aug 09 07:22:48 PM PDT 24
Peak memory 199944 kb
Host smart-fa5bd7fa-6c8f-4d15-a2dd-142788c06e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456446449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.456446449
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3347188585
Short name T298
Test name
Test status
Simulation time 77092891699 ps
CPU time 19.75 seconds
Started Aug 09 07:22:12 PM PDT 24
Finished Aug 09 07:22:32 PM PDT 24
Peak memory 199828 kb
Host smart-3bd58784-43b1-4ab6-8261-aaee47f20e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347188585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3347188585
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2840931629
Short name T129
Test name
Test status
Simulation time 177232467610 ps
CPU time 46.18 seconds
Started Aug 09 07:22:13 PM PDT 24
Finished Aug 09 07:22:59 PM PDT 24
Peak memory 199892 kb
Host smart-f22e5fc2-4f83-42cf-9d62-12805782f057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840931629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2840931629
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.784516029
Short name T505
Test name
Test status
Simulation time 14226705822 ps
CPU time 5.38 seconds
Started Aug 09 07:22:14 PM PDT 24
Finished Aug 09 07:22:19 PM PDT 24
Peak memory 196948 kb
Host smart-2b738f59-093d-48af-bfce-9942108c7577
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784516029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.784516029
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1260678390
Short name T611
Test name
Test status
Simulation time 158882093243 ps
CPU time 322.59 seconds
Started Aug 09 07:22:14 PM PDT 24
Finished Aug 09 07:27:36 PM PDT 24
Peak memory 199884 kb
Host smart-0b04eaf6-6943-4adf-8e92-2b668e4248db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260678390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1260678390
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2749038873
Short name T1002
Test name
Test status
Simulation time 1881918365 ps
CPU time 3.47 seconds
Started Aug 09 07:22:13 PM PDT 24
Finished Aug 09 07:22:17 PM PDT 24
Peak memory 196000 kb
Host smart-a8a62bf0-2386-49b2-bf90-d3d35e5d2e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749038873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2749038873
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2812375025
Short name T99
Test name
Test status
Simulation time 35733223884 ps
CPU time 56.55 seconds
Started Aug 09 07:22:13 PM PDT 24
Finished Aug 09 07:23:10 PM PDT 24
Peak memory 199052 kb
Host smart-bcd37d70-d47d-4193-a45e-ad719e857c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812375025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2812375025
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.2606012799
Short name T801
Test name
Test status
Simulation time 18763465892 ps
CPU time 956.61 seconds
Started Aug 09 07:22:12 PM PDT 24
Finished Aug 09 07:38:09 PM PDT 24
Peak memory 199800 kb
Host smart-864ab6ae-efa1-4aca-a65d-cc00f66ee4ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2606012799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2606012799
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.577498326
Short name T938
Test name
Test status
Simulation time 3627825633 ps
CPU time 13.36 seconds
Started Aug 09 07:22:13 PM PDT 24
Finished Aug 09 07:22:26 PM PDT 24
Peak memory 199376 kb
Host smart-5e2f13f6-318d-430d-8101-a8bccea45fd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=577498326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.577498326
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1852314135
Short name T483
Test name
Test status
Simulation time 84621155656 ps
CPU time 145.95 seconds
Started Aug 09 07:22:13 PM PDT 24
Finished Aug 09 07:24:39 PM PDT 24
Peak memory 199904 kb
Host smart-d48256f9-de30-4a7b-9c55-d7155c3434ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852314135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1852314135
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.257232501
Short name T674
Test name
Test status
Simulation time 473352911 ps
CPU time 1 seconds
Started Aug 09 07:22:15 PM PDT 24
Finished Aug 09 07:22:16 PM PDT 24
Peak memory 195624 kb
Host smart-b0bc4988-c268-4970-b33f-3c073be80e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257232501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.257232501
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3365626074
Short name T1104
Test name
Test status
Simulation time 417927289 ps
CPU time 1.35 seconds
Started Aug 09 07:22:13 PM PDT 24
Finished Aug 09 07:22:15 PM PDT 24
Peak memory 198532 kb
Host smart-15373c28-328e-4f2d-b14f-adff5c91be7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365626074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3365626074
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2318658421
Short name T594
Test name
Test status
Simulation time 21068335855 ps
CPU time 52.4 seconds
Started Aug 09 07:22:13 PM PDT 24
Finished Aug 09 07:23:05 PM PDT 24
Peak memory 199952 kb
Host smart-69ea35ff-f1a7-4a76-a4ae-e0d04f9233b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318658421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2318658421
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2146349053
Short name T164
Test name
Test status
Simulation time 27545006932 ps
CPU time 330.24 seconds
Started Aug 09 07:22:13 PM PDT 24
Finished Aug 09 07:27:44 PM PDT 24
Peak memory 214532 kb
Host smart-409b7ff1-c49c-4d15-97e0-7193ce51e04b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146349053 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2146349053
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3311839506
Short name T667
Test name
Test status
Simulation time 1715031479 ps
CPU time 1.81 seconds
Started Aug 09 07:22:15 PM PDT 24
Finished Aug 09 07:22:17 PM PDT 24
Peak memory 198984 kb
Host smart-da223c04-a641-49e3-96f1-39a0dea82a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311839506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3311839506
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3324093326
Short name T1105
Test name
Test status
Simulation time 68299402804 ps
CPU time 22.34 seconds
Started Aug 09 07:22:12 PM PDT 24
Finished Aug 09 07:22:34 PM PDT 24
Peak memory 199892 kb
Host smart-64e04010-51c1-4c11-a3de-3003480abcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324093326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3324093326
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3971750130
Short name T1031
Test name
Test status
Simulation time 23987086 ps
CPU time 0.57 seconds
Started Aug 09 07:22:22 PM PDT 24
Finished Aug 09 07:22:22 PM PDT 24
Peak memory 195616 kb
Host smart-760ed77c-a1c7-4cfe-a55b-4267e13a94ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971750130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3971750130
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1126029911
Short name T549
Test name
Test status
Simulation time 97638072921 ps
CPU time 34.53 seconds
Started Aug 09 07:22:13 PM PDT 24
Finished Aug 09 07:22:48 PM PDT 24
Peak memory 199944 kb
Host smart-39e20d1d-ead3-48c5-80eb-43a1e3d131b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126029911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1126029911
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1100290586
Short name T1056
Test name
Test status
Simulation time 31452264213 ps
CPU time 18.13 seconds
Started Aug 09 07:22:13 PM PDT 24
Finished Aug 09 07:22:31 PM PDT 24
Peak memory 199976 kb
Host smart-f04954bd-1974-4101-af2d-9dcc33adcba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100290586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1100290586
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.4237537500
Short name T7
Test name
Test status
Simulation time 5742839857 ps
CPU time 5.19 seconds
Started Aug 09 07:22:15 PM PDT 24
Finished Aug 09 07:22:20 PM PDT 24
Peak memory 199964 kb
Host smart-a411a151-8ad9-440f-8918-0efe00ecd1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237537500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.4237537500
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.4204502253
Short name T292
Test name
Test status
Simulation time 25950181373 ps
CPU time 5.28 seconds
Started Aug 09 07:22:23 PM PDT 24
Finished Aug 09 07:22:28 PM PDT 24
Peak memory 199944 kb
Host smart-f0bb553b-7a69-46ef-ac7f-c8bcb873c36e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204502253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.4204502253
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1610099253
Short name T1176
Test name
Test status
Simulation time 75993312084 ps
CPU time 193.72 seconds
Started Aug 09 07:22:22 PM PDT 24
Finished Aug 09 07:25:36 PM PDT 24
Peak memory 199916 kb
Host smart-886da3e4-bc1a-4946-b3e0-e8f87e0613d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1610099253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1610099253
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.199332131
Short name T855
Test name
Test status
Simulation time 4999344855 ps
CPU time 8.19 seconds
Started Aug 09 07:22:24 PM PDT 24
Finished Aug 09 07:22:33 PM PDT 24
Peak memory 198504 kb
Host smart-2f270be3-a52d-4bca-9ab5-d7e21815a4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199332131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.199332131
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3091808211
Short name T403
Test name
Test status
Simulation time 96566276659 ps
CPU time 57.82 seconds
Started Aug 09 07:22:22 PM PDT 24
Finished Aug 09 07:23:19 PM PDT 24
Peak memory 199212 kb
Host smart-a4fb3d1c-ca69-4597-8af0-73cd6f732865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091808211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3091808211
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.1439129929
Short name T945
Test name
Test status
Simulation time 20947915592 ps
CPU time 222.3 seconds
Started Aug 09 07:22:21 PM PDT 24
Finished Aug 09 07:26:04 PM PDT 24
Peak memory 199944 kb
Host smart-ed7729a3-6d7f-474c-a6a9-cc6d889ec5da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1439129929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1439129929
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3536797049
Short name T1159
Test name
Test status
Simulation time 5631747227 ps
CPU time 12.6 seconds
Started Aug 09 07:22:15 PM PDT 24
Finished Aug 09 07:22:28 PM PDT 24
Peak memory 199132 kb
Host smart-693725bc-754d-4c87-a5d4-427f43e0a1ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3536797049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3536797049
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2056991472
Short name T117
Test name
Test status
Simulation time 148718661063 ps
CPU time 210.23 seconds
Started Aug 09 07:22:22 PM PDT 24
Finished Aug 09 07:25:52 PM PDT 24
Peak memory 199884 kb
Host smart-ad94c7c7-d2cf-4f72-ab89-ba66bf039738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056991472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2056991472
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1159127981
Short name T468
Test name
Test status
Simulation time 4833984806 ps
CPU time 1.64 seconds
Started Aug 09 07:22:20 PM PDT 24
Finished Aug 09 07:22:22 PM PDT 24
Peak memory 196268 kb
Host smart-a6e45401-ff2c-4df0-a738-5e1da3ad7cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159127981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1159127981
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.976103570
Short name T761
Test name
Test status
Simulation time 88801388 ps
CPU time 0.91 seconds
Started Aug 09 07:22:15 PM PDT 24
Finished Aug 09 07:22:16 PM PDT 24
Peak memory 197652 kb
Host smart-778434e8-c755-42b4-a1f4-abc877da81b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976103570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.976103570
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.895978525
Short name T866
Test name
Test status
Simulation time 447042895119 ps
CPU time 742.91 seconds
Started Aug 09 07:22:21 PM PDT 24
Finished Aug 09 07:34:44 PM PDT 24
Peak memory 199976 kb
Host smart-c7d88bf7-244c-4c1b-b21c-1288f202258b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895978525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.895978525
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.4129805597
Short name T978
Test name
Test status
Simulation time 559862057 ps
CPU time 1.18 seconds
Started Aug 09 07:22:23 PM PDT 24
Finished Aug 09 07:22:25 PM PDT 24
Peak memory 197200 kb
Host smart-ad46b2cd-3fc9-41f8-ae04-837495c21caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129805597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.4129805597
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1929842740
Short name T816
Test name
Test status
Simulation time 124204900486 ps
CPU time 239.05 seconds
Started Aug 09 07:22:14 PM PDT 24
Finished Aug 09 07:26:13 PM PDT 24
Peak memory 199888 kb
Host smart-8f1a6304-648a-46ff-aa9d-626623e47f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929842740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1929842740
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.271676086
Short name T693
Test name
Test status
Simulation time 19451964 ps
CPU time 0.58 seconds
Started Aug 09 07:22:31 PM PDT 24
Finished Aug 09 07:22:31 PM PDT 24
Peak memory 194604 kb
Host smart-f4dfe4a7-ff07-4994-bdd9-83c026dedbc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271676086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.271676086
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.2922233372
Short name T682
Test name
Test status
Simulation time 32459259041 ps
CPU time 33.38 seconds
Started Aug 09 07:22:22 PM PDT 24
Finished Aug 09 07:22:56 PM PDT 24
Peak memory 199932 kb
Host smart-ffa3598a-94f7-43bc-a65c-bd742d366619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922233372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2922233372
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.670831104
Short name T1174
Test name
Test status
Simulation time 176088119905 ps
CPU time 41.33 seconds
Started Aug 09 07:22:23 PM PDT 24
Finished Aug 09 07:23:05 PM PDT 24
Peak memory 199896 kb
Host smart-a14f0dac-f771-45b7-8a8e-32c9e168dbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670831104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.670831104
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.901069981
Short name T257
Test name
Test status
Simulation time 126300888314 ps
CPU time 234.74 seconds
Started Aug 09 07:22:23 PM PDT 24
Finished Aug 09 07:26:18 PM PDT 24
Peak memory 199944 kb
Host smart-edb1940b-ad12-4bd7-83f9-394a5882e9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901069981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.901069981
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2550955626
Short name T271
Test name
Test status
Simulation time 37473381453 ps
CPU time 104.9 seconds
Started Aug 09 07:22:30 PM PDT 24
Finished Aug 09 07:24:15 PM PDT 24
Peak memory 199968 kb
Host smart-f1707eee-771a-43fe-b09c-2f2d841e04e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550955626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2550955626
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.975746546
Short name T998
Test name
Test status
Simulation time 78441192932 ps
CPU time 448.46 seconds
Started Aug 09 07:22:31 PM PDT 24
Finished Aug 09 07:30:00 PM PDT 24
Peak memory 199832 kb
Host smart-7b2ae2f4-8b6c-4ad2-bf31-8027dfff26de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=975746546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.975746546
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2482933847
Short name T345
Test name
Test status
Simulation time 6623469031 ps
CPU time 14.57 seconds
Started Aug 09 07:22:31 PM PDT 24
Finished Aug 09 07:22:45 PM PDT 24
Peak memory 199968 kb
Host smart-f14f7c32-e6e1-45f0-80ac-df018e034eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482933847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2482933847
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.3737426262
Short name T785
Test name
Test status
Simulation time 187884503376 ps
CPU time 114.46 seconds
Started Aug 09 07:22:29 PM PDT 24
Finished Aug 09 07:24:24 PM PDT 24
Peak memory 199900 kb
Host smart-2fcc0e5f-ab32-4d1f-900c-999d525c0072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737426262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3737426262
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.368209643
Short name T947
Test name
Test status
Simulation time 4180376480 ps
CPU time 62.6 seconds
Started Aug 09 07:22:30 PM PDT 24
Finished Aug 09 07:23:33 PM PDT 24
Peak memory 199936 kb
Host smart-1857a59e-d556-42cc-bc88-e1cb2112c0ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=368209643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.368209643
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2725942167
Short name T356
Test name
Test status
Simulation time 1299524939 ps
CPU time 1.04 seconds
Started Aug 09 07:22:21 PM PDT 24
Finished Aug 09 07:22:22 PM PDT 24
Peak memory 195588 kb
Host smart-7b85ea8a-3a32-4d3e-ad55-aa1448c81455
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2725942167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2725942167
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.4088421673
Short name T807
Test name
Test status
Simulation time 28216417719 ps
CPU time 12.71 seconds
Started Aug 09 07:22:29 PM PDT 24
Finished Aug 09 07:22:42 PM PDT 24
Peak memory 199948 kb
Host smart-be1b34a8-1fcd-4e01-bb88-cb763604fc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088421673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.4088421673
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3042966766
Short name T701
Test name
Test status
Simulation time 1895635493 ps
CPU time 2.49 seconds
Started Aug 09 07:22:29 PM PDT 24
Finished Aug 09 07:22:31 PM PDT 24
Peak memory 195460 kb
Host smart-f1e81ceb-f640-4cd5-88cb-e72b00d5d16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042966766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3042966766
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1534247130
Short name T612
Test name
Test status
Simulation time 519790933 ps
CPU time 1.39 seconds
Started Aug 09 07:22:21 PM PDT 24
Finished Aug 09 07:22:22 PM PDT 24
Peak memory 198556 kb
Host smart-1d4e6629-9143-4c48-8e37-b8891453f13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534247130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1534247130
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.3116290046
Short name T620
Test name
Test status
Simulation time 63756320461 ps
CPU time 348.48 seconds
Started Aug 09 07:22:29 PM PDT 24
Finished Aug 09 07:28:18 PM PDT 24
Peak memory 208244 kb
Host smart-c43e071e-e844-46c8-9019-ebf3f2f97563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116290046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3116290046
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1750705638
Short name T1170
Test name
Test status
Simulation time 42960102333 ps
CPU time 375.45 seconds
Started Aug 09 07:22:31 PM PDT 24
Finished Aug 09 07:28:46 PM PDT 24
Peak memory 216472 kb
Host smart-1d38b79d-e3bf-4aa2-9535-f4828dc34e7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750705638 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1750705638
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.4018673865
Short name T494
Test name
Test status
Simulation time 1146519330 ps
CPU time 1.68 seconds
Started Aug 09 07:22:31 PM PDT 24
Finished Aug 09 07:22:33 PM PDT 24
Peak memory 199808 kb
Host smart-f86bcf6c-0c3f-4914-985d-bd29262bcf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018673865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.4018673865
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2449590044
Short name T319
Test name
Test status
Simulation time 48888072404 ps
CPU time 14.06 seconds
Started Aug 09 07:22:23 PM PDT 24
Finished Aug 09 07:22:37 PM PDT 24
Peak memory 198064 kb
Host smart-0e8559bf-f5f9-483f-96c3-0f72882a3cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449590044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2449590044
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2319099847
Short name T900
Test name
Test status
Simulation time 39831949 ps
CPU time 0.56 seconds
Started Aug 09 07:22:29 PM PDT 24
Finished Aug 09 07:22:30 PM PDT 24
Peak memory 194808 kb
Host smart-3d384856-8e9c-469d-82d2-e2488a608e9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319099847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2319099847
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.850274654
Short name T278
Test name
Test status
Simulation time 257401617734 ps
CPU time 115.07 seconds
Started Aug 09 07:22:28 PM PDT 24
Finished Aug 09 07:24:23 PM PDT 24
Peak memory 199848 kb
Host smart-0d40e3ba-135d-4070-9d2c-9ee296e39938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850274654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.850274654
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2582526072
Short name T181
Test name
Test status
Simulation time 105040554519 ps
CPU time 25.18 seconds
Started Aug 09 07:22:29 PM PDT 24
Finished Aug 09 07:22:54 PM PDT 24
Peak memory 199964 kb
Host smart-063d1397-fc5c-4ae3-8626-c2987520f0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582526072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2582526072
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3580411705
Short name T422
Test name
Test status
Simulation time 15953116835 ps
CPU time 13.39 seconds
Started Aug 09 07:22:29 PM PDT 24
Finished Aug 09 07:22:43 PM PDT 24
Peak memory 199952 kb
Host smart-113bcff9-bfa9-4c4d-ae29-4de2937b24bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580411705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3580411705
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.1612519752
Short name T262
Test name
Test status
Simulation time 24825272223 ps
CPU time 14.51 seconds
Started Aug 09 07:22:28 PM PDT 24
Finished Aug 09 07:22:43 PM PDT 24
Peak memory 199960 kb
Host smart-cca2d171-14cd-4e5b-b2d6-0fd5a7cb38ff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612519752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1612519752
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.876780107
Short name T694
Test name
Test status
Simulation time 72427923589 ps
CPU time 126.52 seconds
Started Aug 09 07:22:29 PM PDT 24
Finished Aug 09 07:24:35 PM PDT 24
Peak memory 199932 kb
Host smart-c3b4eb0c-9bfb-4d73-abfe-21d520f4ce28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=876780107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.876780107
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.330664950
Short name T554
Test name
Test status
Simulation time 147512717 ps
CPU time 0.89 seconds
Started Aug 09 07:22:29 PM PDT 24
Finished Aug 09 07:22:30 PM PDT 24
Peak memory 197192 kb
Host smart-eb726880-78d1-4ba6-9b57-2e390488e520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330664950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.330664950
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.610545142
Short name T1077
Test name
Test status
Simulation time 26207776168 ps
CPU time 75.92 seconds
Started Aug 09 07:22:29 PM PDT 24
Finished Aug 09 07:23:45 PM PDT 24
Peak memory 198740 kb
Host smart-fe0ca438-fb80-427a-b4c9-8f75e81a486b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610545142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.610545142
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2586152899
Short name T295
Test name
Test status
Simulation time 20389475487 ps
CPU time 1182.82 seconds
Started Aug 09 07:22:29 PM PDT 24
Finished Aug 09 07:42:12 PM PDT 24
Peak memory 199944 kb
Host smart-48e58691-086a-4daa-a317-fcb1be51993c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2586152899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2586152899
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2654247419
Short name T424
Test name
Test status
Simulation time 6029302730 ps
CPU time 50.5 seconds
Started Aug 09 07:22:28 PM PDT 24
Finished Aug 09 07:23:18 PM PDT 24
Peak memory 199116 kb
Host smart-2828faaa-5d63-4092-b3e7-f3390ab00e6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2654247419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2654247419
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.801273445
Short name T983
Test name
Test status
Simulation time 194617207952 ps
CPU time 357.43 seconds
Started Aug 09 07:22:31 PM PDT 24
Finished Aug 09 07:28:29 PM PDT 24
Peak memory 199884 kb
Host smart-9a131812-b004-4653-b4b9-a03a9d56e4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801273445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.801273445
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2195888964
Short name T876
Test name
Test status
Simulation time 4100496684 ps
CPU time 6.52 seconds
Started Aug 09 07:22:30 PM PDT 24
Finished Aug 09 07:22:37 PM PDT 24
Peak memory 196484 kb
Host smart-d99cdeae-c49e-429b-9719-fa077f65b27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195888964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2195888964
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3611802445
Short name T951
Test name
Test status
Simulation time 496026328 ps
CPU time 2.23 seconds
Started Aug 09 07:22:29 PM PDT 24
Finished Aug 09 07:22:31 PM PDT 24
Peak memory 199756 kb
Host smart-bd625553-1d14-4c09-a1b9-4ef6569a0d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611802445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3611802445
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.344493585
Short name T1124
Test name
Test status
Simulation time 193374711222 ps
CPU time 282.37 seconds
Started Aug 09 07:22:29 PM PDT 24
Finished Aug 09 07:27:11 PM PDT 24
Peak memory 200048 kb
Host smart-9e5a6525-48c8-44c7-9017-ae53fb778a0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344493585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.344493585
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1947271741
Short name T54
Test name
Test status
Simulation time 295212724803 ps
CPU time 879.58 seconds
Started Aug 09 07:22:29 PM PDT 24
Finished Aug 09 07:37:09 PM PDT 24
Peak memory 224792 kb
Host smart-0d9a3249-bf02-44ba-8bbf-f81f74a9c498
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947271741 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1947271741
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.517144367
Short name T697
Test name
Test status
Simulation time 7275051752 ps
CPU time 11.88 seconds
Started Aug 09 07:22:26 PM PDT 24
Finished Aug 09 07:22:38 PM PDT 24
Peak memory 199824 kb
Host smart-2fe329fa-f4df-46d0-ab92-25d5f212f6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517144367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.517144367
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1923222751
Short name T557
Test name
Test status
Simulation time 75227681129 ps
CPU time 50.6 seconds
Started Aug 09 07:22:29 PM PDT 24
Finished Aug 09 07:23:20 PM PDT 24
Peak memory 199912 kb
Host smart-29ae5785-108f-4e7f-838f-53edefc50465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923222751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1923222751
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.4000628742
Short name T346
Test name
Test status
Simulation time 23929560 ps
CPU time 0.55 seconds
Started Aug 09 07:22:39 PM PDT 24
Finished Aug 09 07:22:39 PM PDT 24
Peak memory 195344 kb
Host smart-3aec5a8c-3e28-4986-b2dc-8b3653c728ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000628742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.4000628742
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2775018387
Short name T258
Test name
Test status
Simulation time 71520908253 ps
CPU time 147.08 seconds
Started Aug 09 07:22:37 PM PDT 24
Finished Aug 09 07:25:05 PM PDT 24
Peak memory 199856 kb
Host smart-529e766c-d754-425d-b2d0-ced02437cdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775018387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2775018387
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1124578336
Short name T155
Test name
Test status
Simulation time 109861539289 ps
CPU time 166.05 seconds
Started Aug 09 07:22:37 PM PDT 24
Finished Aug 09 07:25:23 PM PDT 24
Peak memory 199980 kb
Host smart-3515d5e3-f459-4425-bb64-36c5be5690ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124578336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1124578336
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3514622498
Short name T857
Test name
Test status
Simulation time 166511802934 ps
CPU time 44.97 seconds
Started Aug 09 07:22:36 PM PDT 24
Finished Aug 09 07:23:21 PM PDT 24
Peak memory 199900 kb
Host smart-93773519-a27d-4996-a5aa-0ead60c57102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514622498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3514622498
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.845753693
Short name T928
Test name
Test status
Simulation time 67671475825 ps
CPU time 139.5 seconds
Started Aug 09 07:22:37 PM PDT 24
Finished Aug 09 07:24:56 PM PDT 24
Peak memory 199744 kb
Host smart-ff78f33f-90d2-460e-acd8-358c3f4bc884
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845753693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.845753693
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.1742658267
Short name T497
Test name
Test status
Simulation time 69008122184 ps
CPU time 640.12 seconds
Started Aug 09 07:22:36 PM PDT 24
Finished Aug 09 07:33:16 PM PDT 24
Peak memory 199928 kb
Host smart-6ff55990-439e-4f95-9bf5-1182bdaaaf6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742658267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1742658267
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.285805071
Short name T104
Test name
Test status
Simulation time 7914540502 ps
CPU time 4.28 seconds
Started Aug 09 07:22:38 PM PDT 24
Finished Aug 09 07:22:42 PM PDT 24
Peak memory 198772 kb
Host smart-31bf5198-1d19-4741-82c6-9f582ec9f4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285805071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.285805071
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2807118797
Short name T862
Test name
Test status
Simulation time 237612992100 ps
CPU time 155.14 seconds
Started Aug 09 07:22:37 PM PDT 24
Finished Aug 09 07:25:12 PM PDT 24
Peak memory 208240 kb
Host smart-2c73da52-1149-46f0-8313-d3443c9254f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807118797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2807118797
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.159942564
Short name T1076
Test name
Test status
Simulation time 23892278241 ps
CPU time 333.34 seconds
Started Aug 09 07:22:37 PM PDT 24
Finished Aug 09 07:28:10 PM PDT 24
Peak memory 199968 kb
Host smart-414c96bc-9f44-45f2-97a5-8a905dd26520
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=159942564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.159942564
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1043146611
Short name T409
Test name
Test status
Simulation time 2920259546 ps
CPU time 6.44 seconds
Started Aug 09 07:22:37 PM PDT 24
Finished Aug 09 07:22:43 PM PDT 24
Peak memory 199228 kb
Host smart-fefb3846-9526-49af-8ce0-a057a2778c66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1043146611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1043146611
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.702761558
Short name T953
Test name
Test status
Simulation time 56884138274 ps
CPU time 24.3 seconds
Started Aug 09 07:22:37 PM PDT 24
Finished Aug 09 07:23:01 PM PDT 24
Peak memory 199848 kb
Host smart-23e173e9-54e7-4ad3-859d-7bb2e3a90053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702761558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.702761558
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.220460654
Short name T830
Test name
Test status
Simulation time 2186785202 ps
CPU time 3.85 seconds
Started Aug 09 07:22:37 PM PDT 24
Finished Aug 09 07:22:41 PM PDT 24
Peak memory 195560 kb
Host smart-b154abd0-b38e-4e20-8043-7d0340eac1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220460654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.220460654
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3560770283
Short name T484
Test name
Test status
Simulation time 654735935 ps
CPU time 1.95 seconds
Started Aug 09 07:22:37 PM PDT 24
Finished Aug 09 07:22:40 PM PDT 24
Peak memory 199504 kb
Host smart-d9381520-55cd-4e76-a733-9ae65629681c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560770283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3560770283
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.214373486
Short name T286
Test name
Test status
Simulation time 6473256568 ps
CPU time 21.64 seconds
Started Aug 09 07:22:37 PM PDT 24
Finished Aug 09 07:22:59 PM PDT 24
Peak memory 199844 kb
Host smart-4ec996f0-7934-4c05-b9bc-2611cf194ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214373486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.214373486
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.951935843
Short name T1033
Test name
Test status
Simulation time 13229408666 ps
CPU time 7.88 seconds
Started Aug 09 07:22:38 PM PDT 24
Finished Aug 09 07:22:46 PM PDT 24
Peak memory 199708 kb
Host smart-7f4b0890-826e-4b43-9296-82002c3b03f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951935843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.951935843
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2002128940
Short name T380
Test name
Test status
Simulation time 36002653 ps
CPU time 0.58 seconds
Started Aug 09 07:22:43 PM PDT 24
Finished Aug 09 07:22:44 PM PDT 24
Peak memory 195644 kb
Host smart-e8d68c3a-4238-48b8-80b1-6b974bb390f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002128940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2002128940
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1398642612
Short name T756
Test name
Test status
Simulation time 87855124898 ps
CPU time 133.56 seconds
Started Aug 09 07:22:37 PM PDT 24
Finished Aug 09 07:24:51 PM PDT 24
Peak memory 199944 kb
Host smart-39f6d264-26bf-4007-a7a6-81e992495fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398642612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1398642612
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.3687742987
Short name T251
Test name
Test status
Simulation time 134276588061 ps
CPU time 49.13 seconds
Started Aug 09 07:22:36 PM PDT 24
Finished Aug 09 07:23:25 PM PDT 24
Peak memory 199656 kb
Host smart-9bbe6b81-585c-4929-87a7-5a25a8634fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687742987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.3687742987
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.975516597
Short name T705
Test name
Test status
Simulation time 102667508942 ps
CPU time 146.33 seconds
Started Aug 09 07:22:36 PM PDT 24
Finished Aug 09 07:25:03 PM PDT 24
Peak memory 199900 kb
Host smart-36e9ab94-2599-4d5c-ab3a-7b5f9c461fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975516597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.975516597
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.2524225679
Short name T326
Test name
Test status
Simulation time 41945238769 ps
CPU time 34.06 seconds
Started Aug 09 07:22:36 PM PDT 24
Finished Aug 09 07:23:10 PM PDT 24
Peak memory 200004 kb
Host smart-a4e96e1d-f8ec-4666-b882-8a526aaf5bd4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524225679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2524225679
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2130642649
Short name T1047
Test name
Test status
Simulation time 86189025069 ps
CPU time 97.91 seconds
Started Aug 09 07:22:44 PM PDT 24
Finished Aug 09 07:24:22 PM PDT 24
Peak memory 199980 kb
Host smart-b7c4d019-89fe-473a-814f-2e612dc6fd96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2130642649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2130642649
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1892468453
Short name T1156
Test name
Test status
Simulation time 9419115853 ps
CPU time 5.47 seconds
Started Aug 09 07:22:43 PM PDT 24
Finished Aug 09 07:22:48 PM PDT 24
Peak memory 199944 kb
Host smart-4b4fff75-7c67-4ac5-a41e-f188b74f9db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892468453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1892468453
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1127312315
Short name T915
Test name
Test status
Simulation time 48575703334 ps
CPU time 115.2 seconds
Started Aug 09 07:22:45 PM PDT 24
Finished Aug 09 07:24:40 PM PDT 24
Peak memory 208456 kb
Host smart-8c471123-7be2-4308-a962-f24209f39bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127312315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1127312315
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2210832993
Short name T269
Test name
Test status
Simulation time 17025319249 ps
CPU time 295.99 seconds
Started Aug 09 07:22:43 PM PDT 24
Finished Aug 09 07:27:39 PM PDT 24
Peak memory 199940 kb
Host smart-1ddaebb3-24e7-43ad-aef2-40f55b3a2ed2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2210832993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2210832993
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2775718622
Short name T1074
Test name
Test status
Simulation time 7262400160 ps
CPU time 64.63 seconds
Started Aug 09 07:22:37 PM PDT 24
Finished Aug 09 07:23:42 PM PDT 24
Peak memory 198088 kb
Host smart-09ed4631-3357-4ef5-a7d3-a1d097550bc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2775718622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2775718622
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1652077402
Short name T657
Test name
Test status
Simulation time 20308304025 ps
CPU time 32.6 seconds
Started Aug 09 07:22:44 PM PDT 24
Finished Aug 09 07:23:17 PM PDT 24
Peak memory 199888 kb
Host smart-bab79a45-7d6b-4c04-a950-39095e242fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652077402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1652077402
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.4199381661
Short name T1146
Test name
Test status
Simulation time 4235999120 ps
CPU time 1.34 seconds
Started Aug 09 07:22:44 PM PDT 24
Finished Aug 09 07:22:45 PM PDT 24
Peak memory 196132 kb
Host smart-88f63f86-e8b6-498a-893f-66c514102ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199381661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.4199381661
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.1365865067
Short name T715
Test name
Test status
Simulation time 5846217886 ps
CPU time 18.69 seconds
Started Aug 09 07:22:37 PM PDT 24
Finished Aug 09 07:22:55 PM PDT 24
Peak memory 199964 kb
Host smart-1e46afd0-6fc2-4fed-bbc2-a90e70bb12fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365865067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1365865067
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.4008803166
Short name T746
Test name
Test status
Simulation time 188576067386 ps
CPU time 127.62 seconds
Started Aug 09 07:22:43 PM PDT 24
Finished Aug 09 07:24:51 PM PDT 24
Peak memory 199936 kb
Host smart-63fb05c1-1d70-4a56-b9bb-5177c805b7b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008803166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.4008803166
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.849660585
Short name T600
Test name
Test status
Simulation time 22917476843 ps
CPU time 278.49 seconds
Started Aug 09 07:22:44 PM PDT 24
Finished Aug 09 07:27:23 PM PDT 24
Peak memory 213700 kb
Host smart-bb2001e9-c269-4722-97b4-0a4a414d14f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849660585 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.849660585
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1767360349
Short name T596
Test name
Test status
Simulation time 6888474147 ps
CPU time 19.61 seconds
Started Aug 09 07:22:44 PM PDT 24
Finished Aug 09 07:23:04 PM PDT 24
Peak memory 199740 kb
Host smart-736b05a7-f721-46d6-b7cd-15df40a7af83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767360349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1767360349
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3082411423
Short name T687
Test name
Test status
Simulation time 67057849474 ps
CPU time 30.46 seconds
Started Aug 09 07:22:35 PM PDT 24
Finished Aug 09 07:23:06 PM PDT 24
Peak memory 199976 kb
Host smart-5cd6b4e8-dd9f-4dbf-8ec9-a38d8bc6f073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082411423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3082411423
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.3033622247
Short name T1022
Test name
Test status
Simulation time 11431402 ps
CPU time 0.56 seconds
Started Aug 09 07:22:52 PM PDT 24
Finished Aug 09 07:22:52 PM PDT 24
Peak memory 195348 kb
Host smart-6de60c02-446f-4856-b85a-01814cd3fb08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033622247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.3033622247
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3229207815
Short name T1019
Test name
Test status
Simulation time 18333722567 ps
CPU time 30.39 seconds
Started Aug 09 07:22:50 PM PDT 24
Finished Aug 09 07:23:21 PM PDT 24
Peak memory 199888 kb
Host smart-a20ee2fe-bf02-49b5-97e2-088bcf63b926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229207815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3229207815
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2800598343
Short name T132
Test name
Test status
Simulation time 20711369710 ps
CPU time 20.76 seconds
Started Aug 09 07:22:52 PM PDT 24
Finished Aug 09 07:23:13 PM PDT 24
Peak memory 199956 kb
Host smart-fee36975-d167-48dc-9b48-5792ed14eb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800598343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2800598343
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1467373842
Short name T711
Test name
Test status
Simulation time 159049954030 ps
CPU time 229.71 seconds
Started Aug 09 07:22:52 PM PDT 24
Finished Aug 09 07:26:42 PM PDT 24
Peak memory 199936 kb
Host smart-fe7f91a5-81dd-4e47-b975-d1c1baf9c985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467373842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1467373842
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.2468488129
Short name T1011
Test name
Test status
Simulation time 18091199823 ps
CPU time 17.13 seconds
Started Aug 09 07:22:50 PM PDT 24
Finished Aug 09 07:23:08 PM PDT 24
Peak memory 199444 kb
Host smart-1a975494-365e-475c-bfe3-9cdc2d518e83
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468488129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2468488129
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1685496425
Short name T1066
Test name
Test status
Simulation time 138402871766 ps
CPU time 457.06 seconds
Started Aug 09 07:22:51 PM PDT 24
Finished Aug 09 07:30:28 PM PDT 24
Peak memory 199880 kb
Host smart-1b992515-cffa-4947-bd2f-2bbdad286167
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1685496425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1685496425
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.4096728227
Short name T1171
Test name
Test status
Simulation time 4453860074 ps
CPU time 8.12 seconds
Started Aug 09 07:22:52 PM PDT 24
Finished Aug 09 07:23:00 PM PDT 24
Peak memory 196548 kb
Host smart-e720137a-91c3-406c-9b7e-884c7dedb17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096728227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.4096728227
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1983506752
Short name T985
Test name
Test status
Simulation time 198456699188 ps
CPU time 136.43 seconds
Started Aug 09 07:22:50 PM PDT 24
Finished Aug 09 07:25:07 PM PDT 24
Peak memory 200076 kb
Host smart-240ae4bb-cc59-4557-a87f-d9e7c35095a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983506752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1983506752
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.2546095373
Short name T531
Test name
Test status
Simulation time 19453630979 ps
CPU time 284.87 seconds
Started Aug 09 07:22:51 PM PDT 24
Finished Aug 09 07:27:36 PM PDT 24
Peak memory 199952 kb
Host smart-ed69f0eb-3db3-4f71-9578-d53744ed4f13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2546095373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2546095373
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.2720289838
Short name T740
Test name
Test status
Simulation time 3585866661 ps
CPU time 13.59 seconds
Started Aug 09 07:22:52 PM PDT 24
Finished Aug 09 07:23:05 PM PDT 24
Peak memory 198880 kb
Host smart-64177a29-26b1-4b39-bfc7-063bff119510
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2720289838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2720289838
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2056173263
Short name T538
Test name
Test status
Simulation time 199105276231 ps
CPU time 16.23 seconds
Started Aug 09 07:22:53 PM PDT 24
Finished Aug 09 07:23:09 PM PDT 24
Peak memory 199520 kb
Host smart-e406932d-9783-4ee8-8359-c5d99b4bb59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056173263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2056173263
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3182371486
Short name T559
Test name
Test status
Simulation time 4037457143 ps
CPU time 2.33 seconds
Started Aug 09 07:22:51 PM PDT 24
Finished Aug 09 07:22:53 PM PDT 24
Peak memory 196108 kb
Host smart-3b1f7976-03c8-4f9f-b13d-117cb5672d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182371486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3182371486
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3123149789
Short name T681
Test name
Test status
Simulation time 6168844395 ps
CPU time 22.32 seconds
Started Aug 09 07:22:45 PM PDT 24
Finished Aug 09 07:23:07 PM PDT 24
Peak memory 199908 kb
Host smart-fc802bfa-9d98-4a01-aa39-d46ef9b69094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123149789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3123149789
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.3198708533
Short name T113
Test name
Test status
Simulation time 474075522327 ps
CPU time 911.05 seconds
Started Aug 09 07:22:52 PM PDT 24
Finished Aug 09 07:38:03 PM PDT 24
Peak memory 209420 kb
Host smart-45c2e384-46b0-45e0-8270-ff114ac5664e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198708533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3198708533
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2605567141
Short name T1006
Test name
Test status
Simulation time 21962108349 ps
CPU time 236.98 seconds
Started Aug 09 07:22:52 PM PDT 24
Finished Aug 09 07:26:49 PM PDT 24
Peak memory 216328 kb
Host smart-dea2d29d-d4d9-4b16-9acd-16256c386f4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605567141 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2605567141
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1919241871
Short name T543
Test name
Test status
Simulation time 6693875429 ps
CPU time 28.69 seconds
Started Aug 09 07:22:51 PM PDT 24
Finished Aug 09 07:23:20 PM PDT 24
Peak memory 199900 kb
Host smart-3f0b7d6a-c717-4665-9cf4-f2725d47793a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919241871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1919241871
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.591683916
Short name T1023
Test name
Test status
Simulation time 45184048449 ps
CPU time 42.43 seconds
Started Aug 09 07:22:59 PM PDT 24
Finished Aug 09 07:23:42 PM PDT 24
Peak memory 199928 kb
Host smart-ed12f5d1-826f-4d0a-9233-22e1c7603cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591683916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.591683916
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.991538264
Short name T24
Test name
Test status
Simulation time 47662410 ps
CPU time 0.57 seconds
Started Aug 09 07:18:55 PM PDT 24
Finished Aug 09 07:18:55 PM PDT 24
Peak memory 195328 kb
Host smart-3fd93603-4369-415b-8bfa-22f541131542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991538264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.991538264
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.785431887
Short name T1109
Test name
Test status
Simulation time 97759858207 ps
CPU time 80.65 seconds
Started Aug 09 07:18:54 PM PDT 24
Finished Aug 09 07:20:15 PM PDT 24
Peak memory 199968 kb
Host smart-f54181cc-7319-4939-beba-9954790b7f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785431887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.785431887
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1175926306
Short name T672
Test name
Test status
Simulation time 55358701408 ps
CPU time 15.83 seconds
Started Aug 09 07:18:49 PM PDT 24
Finished Aug 09 07:19:05 PM PDT 24
Peak memory 199968 kb
Host smart-34c9085f-c7a9-4abe-a4c7-9aaa868b437c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175926306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1175926306
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.32861555
Short name T328
Test name
Test status
Simulation time 39379660731 ps
CPU time 18.12 seconds
Started Aug 09 07:18:51 PM PDT 24
Finished Aug 09 07:19:09 PM PDT 24
Peak memory 199956 kb
Host smart-2d392da8-8cea-45a7-af7f-bcbf7dc12151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32861555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.32861555
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.383332438
Short name T911
Test name
Test status
Simulation time 15045677472 ps
CPU time 21.89 seconds
Started Aug 09 07:18:52 PM PDT 24
Finished Aug 09 07:19:14 PM PDT 24
Peak memory 196752 kb
Host smart-7d4cb114-a9f1-47d8-a59e-28eba68df27c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383332438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.383332438
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2726620967
Short name T252
Test name
Test status
Simulation time 96062497485 ps
CPU time 453.42 seconds
Started Aug 09 07:18:51 PM PDT 24
Finished Aug 09 07:26:25 PM PDT 24
Peak memory 199900 kb
Host smart-abda9333-78de-4f95-9ebd-dd601c9d08fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2726620967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2726620967
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.334930115
Short name T923
Test name
Test status
Simulation time 1254478968 ps
CPU time 1.32 seconds
Started Aug 09 07:18:49 PM PDT 24
Finished Aug 09 07:18:51 PM PDT 24
Peak memory 197064 kb
Host smart-a0abe2ef-1bf2-4087-b274-56942c85d6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334930115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.334930115
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.525937083
Short name T1118
Test name
Test status
Simulation time 42938669962 ps
CPU time 34.47 seconds
Started Aug 09 07:18:51 PM PDT 24
Finished Aug 09 07:19:25 PM PDT 24
Peak memory 200088 kb
Host smart-c7445554-3f16-4f47-aa33-9c340fc72672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525937083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.525937083
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2520447187
Short name T599
Test name
Test status
Simulation time 19417460052 ps
CPU time 530.97 seconds
Started Aug 09 07:18:53 PM PDT 24
Finished Aug 09 07:27:44 PM PDT 24
Peak memory 199948 kb
Host smart-6d037c00-561e-4028-803e-7e54da11bcef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2520447187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2520447187
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2349769175
Short name T476
Test name
Test status
Simulation time 3155236435 ps
CPU time 26.74 seconds
Started Aug 09 07:18:49 PM PDT 24
Finished Aug 09 07:19:16 PM PDT 24
Peak memory 199228 kb
Host smart-6545b1ae-5d40-49fa-bbb0-6533af20f149
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2349769175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2349769175
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.2764363695
Short name T739
Test name
Test status
Simulation time 35819157533 ps
CPU time 59.97 seconds
Started Aug 09 07:18:51 PM PDT 24
Finished Aug 09 07:19:51 PM PDT 24
Peak memory 199968 kb
Host smart-c7f80ea9-49b2-4817-bb68-1604b93dbff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764363695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2764363695
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3932040292
Short name T605
Test name
Test status
Simulation time 41010876477 ps
CPU time 63.01 seconds
Started Aug 09 07:18:54 PM PDT 24
Finished Aug 09 07:19:57 PM PDT 24
Peak memory 195744 kb
Host smart-2653e913-c74e-48df-851c-6b30ecad49cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932040292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3932040292
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1352646589
Short name T836
Test name
Test status
Simulation time 5668109777 ps
CPU time 6.88 seconds
Started Aug 09 07:18:57 PM PDT 24
Finished Aug 09 07:19:04 PM PDT 24
Peak memory 199796 kb
Host smart-11711399-a218-4577-a804-afa6e12b5cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352646589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1352646589
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.2372143719
Short name T975
Test name
Test status
Simulation time 131036884169 ps
CPU time 62.34 seconds
Started Aug 09 07:18:57 PM PDT 24
Finished Aug 09 07:19:59 PM PDT 24
Peak memory 216204 kb
Host smart-fa375a98-31ff-4383-9e0a-24582e725ca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372143719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2372143719
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1937528241
Short name T179
Test name
Test status
Simulation time 116611385979 ps
CPU time 195.63 seconds
Started Aug 09 07:18:52 PM PDT 24
Finished Aug 09 07:22:08 PM PDT 24
Peak memory 216732 kb
Host smart-15c5bff0-da13-4c4c-89a9-8e612436acee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937528241 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1937528241
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1146553350
Short name T1177
Test name
Test status
Simulation time 4468492241 ps
CPU time 1.57 seconds
Started Aug 09 07:18:49 PM PDT 24
Finished Aug 09 07:18:51 PM PDT 24
Peak memory 199856 kb
Host smart-67b9b6d7-5a56-4fdb-9492-890eece77ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146553350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1146553350
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1514770756
Short name T513
Test name
Test status
Simulation time 70569687026 ps
CPU time 173.13 seconds
Started Aug 09 07:18:54 PM PDT 24
Finished Aug 09 07:21:47 PM PDT 24
Peak memory 199916 kb
Host smart-ad175aaa-bbc0-4017-a961-a50fa23110b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514770756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1514770756
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.107008896
Short name T754
Test name
Test status
Simulation time 102900864582 ps
CPU time 44.75 seconds
Started Aug 09 07:22:50 PM PDT 24
Finished Aug 09 07:23:35 PM PDT 24
Peak memory 199896 kb
Host smart-87799283-7c6a-4c3a-aee7-25dbb6bdb4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107008896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.107008896
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3998704740
Short name T516
Test name
Test status
Simulation time 425955247332 ps
CPU time 573.3 seconds
Started Aug 09 07:22:51 PM PDT 24
Finished Aug 09 07:32:25 PM PDT 24
Peak memory 216492 kb
Host smart-13196e75-4eb5-41e1-b80c-4803f46231f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998704740 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3998704740
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3193687623
Short name T763
Test name
Test status
Simulation time 32437136270 ps
CPU time 11.62 seconds
Started Aug 09 07:22:52 PM PDT 24
Finished Aug 09 07:23:04 PM PDT 24
Peak memory 199956 kb
Host smart-323cbba9-08ea-40db-9060-839a82dce9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193687623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3193687623
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1970978266
Short name T571
Test name
Test status
Simulation time 43920986429 ps
CPU time 372.13 seconds
Started Aug 09 07:22:52 PM PDT 24
Finished Aug 09 07:29:04 PM PDT 24
Peak memory 224812 kb
Host smart-1f1f80c1-4d10-48bb-a8e1-4e3fbca8bd20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970978266 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1970978266
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2087030954
Short name T414
Test name
Test status
Simulation time 61528297739 ps
CPU time 232.58 seconds
Started Aug 09 07:22:52 PM PDT 24
Finished Aug 09 07:26:45 PM PDT 24
Peak memory 213776 kb
Host smart-e046bfc5-87ec-4e01-9092-03cb6a2e9796
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087030954 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2087030954
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1595819773
Short name T963
Test name
Test status
Simulation time 276117682683 ps
CPU time 26.69 seconds
Started Aug 09 07:22:51 PM PDT 24
Finished Aug 09 07:23:18 PM PDT 24
Peak memory 199912 kb
Host smart-41323efa-6d5c-4809-b1ca-745727635110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595819773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1595819773
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.694603489
Short name T51
Test name
Test status
Simulation time 496787399834 ps
CPU time 1567.26 seconds
Started Aug 09 07:22:50 PM PDT 24
Finished Aug 09 07:48:58 PM PDT 24
Peak memory 226744 kb
Host smart-f5ede2a8-188f-47a5-93b4-00d2fe0530c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694603489 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.694603489
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3467791426
Short name T1064
Test name
Test status
Simulation time 9001156731 ps
CPU time 12.63 seconds
Started Aug 09 07:23:00 PM PDT 24
Finished Aug 09 07:23:13 PM PDT 24
Peak memory 199968 kb
Host smart-15d68f84-0839-4335-9f4b-cb4e72697b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467791426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3467791426
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.38261834
Short name T716
Test name
Test status
Simulation time 67429662952 ps
CPU time 828.28 seconds
Started Aug 09 07:23:01 PM PDT 24
Finished Aug 09 07:36:49 PM PDT 24
Peak memory 216704 kb
Host smart-1936bee2-9a87-40d3-8081-b39db7cdd57f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38261834 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.38261834
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1164246364
Short name T171
Test name
Test status
Simulation time 97052196744 ps
CPU time 26.52 seconds
Started Aug 09 07:23:01 PM PDT 24
Finished Aug 09 07:23:28 PM PDT 24
Peak memory 199904 kb
Host smart-03ec63d5-0825-4e54-8195-d878b9c5fbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164246364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1164246364
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2552259520
Short name T995
Test name
Test status
Simulation time 34696891934 ps
CPU time 493.64 seconds
Started Aug 09 07:22:59 PM PDT 24
Finished Aug 09 07:31:13 PM PDT 24
Peak memory 215648 kb
Host smart-50756f1e-872d-4faf-a6b5-5b1dfa20d75b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552259520 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2552259520
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.691792588
Short name T211
Test name
Test status
Simulation time 147897864967 ps
CPU time 49.92 seconds
Started Aug 09 07:23:00 PM PDT 24
Finished Aug 09 07:23:50 PM PDT 24
Peak memory 199896 kb
Host smart-deef0ede-2d3e-44a6-86a1-d887d26b405d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691792588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.691792588
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1016734469
Short name T50
Test name
Test status
Simulation time 369743595785 ps
CPU time 542.45 seconds
Started Aug 09 07:23:00 PM PDT 24
Finished Aug 09 07:32:02 PM PDT 24
Peak memory 216548 kb
Host smart-d919a779-2af8-423a-95be-4a4561947e12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016734469 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1016734469
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2055822683
Short name T638
Test name
Test status
Simulation time 46102294613 ps
CPU time 291.83 seconds
Started Aug 09 07:23:01 PM PDT 24
Finished Aug 09 07:27:53 PM PDT 24
Peak memory 214432 kb
Host smart-bdd09327-0d97-4898-926b-246c62289af6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055822683 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2055822683
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.4228329797
Short name T218
Test name
Test status
Simulation time 100525569733 ps
CPU time 129.02 seconds
Started Aug 09 07:23:00 PM PDT 24
Finished Aug 09 07:25:09 PM PDT 24
Peak memory 199972 kb
Host smart-8bbe624e-bf8d-4c9f-9f5f-1e766038e3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228329797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.4228329797
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.702862868
Short name T635
Test name
Test status
Simulation time 194568061660 ps
CPU time 842.95 seconds
Started Aug 09 07:22:59 PM PDT 24
Finished Aug 09 07:37:03 PM PDT 24
Peak memory 215804 kb
Host smart-342c6d2b-277b-42af-86a5-0138c4c62798
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702862868 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.702862868
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.564123260
Short name T989
Test name
Test status
Simulation time 29292471261 ps
CPU time 26.18 seconds
Started Aug 09 07:23:00 PM PDT 24
Finished Aug 09 07:23:26 PM PDT 24
Peak memory 199952 kb
Host smart-7f5503c7-2877-410a-97dc-a36102c0b6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564123260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.564123260
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.915262203
Short name T1136
Test name
Test status
Simulation time 64991852267 ps
CPU time 506.89 seconds
Started Aug 09 07:23:00 PM PDT 24
Finished Aug 09 07:31:27 PM PDT 24
Peak memory 225220 kb
Host smart-660eb35a-7e3e-437a-a7c3-911f0b797c0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915262203 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.915262203
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.209059954
Short name T786
Test name
Test status
Simulation time 33329323 ps
CPU time 0.54 seconds
Started Aug 09 07:18:59 PM PDT 24
Finished Aug 09 07:18:59 PM PDT 24
Peak memory 195004 kb
Host smart-c51de1de-9ac9-4f41-830e-b5e902be1eb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209059954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.209059954
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.562137601
Short name T283
Test name
Test status
Simulation time 77506999589 ps
CPU time 122.45 seconds
Started Aug 09 07:18:51 PM PDT 24
Finished Aug 09 07:20:54 PM PDT 24
Peak memory 199872 kb
Host smart-77af9bd7-6ef7-44fd-9b6f-f96393716133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562137601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.562137601
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3024180046
Short name T853
Test name
Test status
Simulation time 39314337372 ps
CPU time 14.66 seconds
Started Aug 09 07:18:51 PM PDT 24
Finished Aug 09 07:19:06 PM PDT 24
Peak memory 199876 kb
Host smart-7c4feaca-6790-4641-9e2d-e2fc70a717e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024180046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3024180046
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1680923147
Short name T864
Test name
Test status
Simulation time 121705512765 ps
CPU time 107.36 seconds
Started Aug 09 07:18:51 PM PDT 24
Finished Aug 09 07:20:39 PM PDT 24
Peak memory 199860 kb
Host smart-d5ae12e2-619a-419d-bb37-6e9ce6323153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680923147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1680923147
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2036413056
Short name T889
Test name
Test status
Simulation time 41566877364 ps
CPU time 72.94 seconds
Started Aug 09 07:18:52 PM PDT 24
Finished Aug 09 07:20:05 PM PDT 24
Peak memory 199892 kb
Host smart-40792e13-ec23-409d-b8eb-5b15496e9cae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036413056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2036413056
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_loopback.817064890
Short name T1106
Test name
Test status
Simulation time 6448560708 ps
CPU time 13.6 seconds
Started Aug 09 07:18:51 PM PDT 24
Finished Aug 09 07:19:05 PM PDT 24
Peak memory 198456 kb
Host smart-3d2a89d0-9469-406c-bd2e-e21d9929ed91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817064890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.817064890
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.232601365
Short name T919
Test name
Test status
Simulation time 453369911240 ps
CPU time 89.36 seconds
Started Aug 09 07:18:51 PM PDT 24
Finished Aug 09 07:20:21 PM PDT 24
Peak memory 208292 kb
Host smart-dc6247f3-ce32-4c13-b918-c7a02819f965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232601365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.232601365
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.2552793410
Short name T1050
Test name
Test status
Simulation time 28564579768 ps
CPU time 241.48 seconds
Started Aug 09 07:18:55 PM PDT 24
Finished Aug 09 07:22:56 PM PDT 24
Peak memory 199960 kb
Host smart-26b00815-a30b-46b4-a7ca-5a8f334ab339
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2552793410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2552793410
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1351932616
Short name T446
Test name
Test status
Simulation time 7083182654 ps
CPU time 33.08 seconds
Started Aug 09 07:18:51 PM PDT 24
Finished Aug 09 07:19:24 PM PDT 24
Peak memory 198224 kb
Host smart-5f893a37-fe89-4c63-bf88-aa4cde6b0ff2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1351932616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1351932616
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2859894406
Short name T440
Test name
Test status
Simulation time 208086310409 ps
CPU time 67.87 seconds
Started Aug 09 07:18:50 PM PDT 24
Finished Aug 09 07:19:58 PM PDT 24
Peak memory 199756 kb
Host smart-a5453120-58ff-4b0d-a697-c932747e42d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859894406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2859894406
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1977450999
Short name T646
Test name
Test status
Simulation time 26504120146 ps
CPU time 11.15 seconds
Started Aug 09 07:18:53 PM PDT 24
Finished Aug 09 07:19:04 PM PDT 24
Peak memory 196100 kb
Host smart-65c97f4c-6184-4af2-8ed7-e42002df55c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977450999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1977450999
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.49817676
Short name T1089
Test name
Test status
Simulation time 287684402 ps
CPU time 1.63 seconds
Started Aug 09 07:18:51 PM PDT 24
Finished Aug 09 07:18:52 PM PDT 24
Peak memory 198908 kb
Host smart-5d7deaa0-064d-45be-8e24-dd2600082f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49817676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.49817676
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1502721324
Short name T842
Test name
Test status
Simulation time 443843505679 ps
CPU time 1172.39 seconds
Started Aug 09 07:18:52 PM PDT 24
Finished Aug 09 07:38:24 PM PDT 24
Peak memory 225852 kb
Host smart-36fae9f8-2839-4515-a89f-3fdecbe70c83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502721324 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1502721324
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3861976122
Short name T1121
Test name
Test status
Simulation time 6698263846 ps
CPU time 17.24 seconds
Started Aug 09 07:18:55 PM PDT 24
Finished Aug 09 07:19:12 PM PDT 24
Peak memory 199756 kb
Host smart-fac3af65-3ba9-4297-987d-ddcbcdb928ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861976122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3861976122
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2751500745
Short name T692
Test name
Test status
Simulation time 84081800052 ps
CPU time 56.25 seconds
Started Aug 09 07:18:51 PM PDT 24
Finished Aug 09 07:19:47 PM PDT 24
Peak memory 199932 kb
Host smart-c20fd416-ab88-47a4-82ac-37e42e1fe8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751500745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2751500745
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.843254985
Short name T442
Test name
Test status
Simulation time 35326310803 ps
CPU time 30.09 seconds
Started Aug 09 07:22:59 PM PDT 24
Finished Aug 09 07:23:30 PM PDT 24
Peak memory 199976 kb
Host smart-d910c2ca-0703-4a0c-8d72-6bc28f2e6482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843254985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.843254985
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2597212099
Short name T877
Test name
Test status
Simulation time 120792485301 ps
CPU time 1224.42 seconds
Started Aug 09 07:23:00 PM PDT 24
Finished Aug 09 07:43:25 PM PDT 24
Peak memory 228496 kb
Host smart-ca8da5a1-b66e-4ca0-90b1-d5fd87cf6706
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597212099 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2597212099
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3297303358
Short name T236
Test name
Test status
Simulation time 160128081804 ps
CPU time 68.23 seconds
Started Aug 09 07:22:59 PM PDT 24
Finished Aug 09 07:24:07 PM PDT 24
Peak memory 199952 kb
Host smart-75c6ea37-d742-4740-8697-4ef7f4f4545c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297303358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3297303358
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.973138430
Short name T57
Test name
Test status
Simulation time 150643103647 ps
CPU time 468.44 seconds
Started Aug 09 07:22:59 PM PDT 24
Finished Aug 09 07:30:47 PM PDT 24
Peak memory 228168 kb
Host smart-6c248a5f-d724-46e4-b565-4ddba6ce27b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973138430 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.973138430
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.745818559
Short name T313
Test name
Test status
Simulation time 134417190810 ps
CPU time 110.12 seconds
Started Aug 09 07:23:07 PM PDT 24
Finished Aug 09 07:24:57 PM PDT 24
Peak memory 199840 kb
Host smart-fb1e487f-3a43-497a-b89a-408c118c9541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745818559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.745818559
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2699296415
Short name T341
Test name
Test status
Simulation time 18255852765 ps
CPU time 10.86 seconds
Started Aug 09 07:23:11 PM PDT 24
Finished Aug 09 07:23:22 PM PDT 24
Peak memory 198884 kb
Host smart-79378a51-ba41-41f8-b387-8c6565649248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699296415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2699296415
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2949366099
Short name T1148
Test name
Test status
Simulation time 146003521267 ps
CPU time 553.68 seconds
Started Aug 09 07:23:06 PM PDT 24
Finished Aug 09 07:32:20 PM PDT 24
Peak memory 216812 kb
Host smart-e10a240b-4f23-4952-a5b8-aeeaac302bae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949366099 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2949366099
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.1351333702
Short name T105
Test name
Test status
Simulation time 15489021783 ps
CPU time 21.33 seconds
Started Aug 09 07:23:07 PM PDT 24
Finished Aug 09 07:23:28 PM PDT 24
Peak memory 199980 kb
Host smart-83b94f4f-cdb8-4b8f-9a08-67de19661ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351333702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1351333702
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3480733715
Short name T553
Test name
Test status
Simulation time 127480884124 ps
CPU time 362.27 seconds
Started Aug 09 07:23:10 PM PDT 24
Finished Aug 09 07:29:12 PM PDT 24
Peak memory 215816 kb
Host smart-4003b1f8-2671-474b-b7c9-0224e2ab44ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480733715 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3480733715
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1439984979
Short name T959
Test name
Test status
Simulation time 32007646626 ps
CPU time 25.7 seconds
Started Aug 09 07:23:08 PM PDT 24
Finished Aug 09 07:23:33 PM PDT 24
Peak memory 199892 kb
Host smart-81cf291e-1b17-4d7c-b122-86d2bc8de07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439984979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1439984979
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.4167580818
Short name T172
Test name
Test status
Simulation time 65313448389 ps
CPU time 183.92 seconds
Started Aug 09 07:23:08 PM PDT 24
Finished Aug 09 07:26:12 PM PDT 24
Peak memory 208468 kb
Host smart-5eb0a8a9-450b-4d99-ba0b-365c5c9045c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167580818 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.4167580818
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1468969171
Short name T617
Test name
Test status
Simulation time 27042506525 ps
CPU time 39.99 seconds
Started Aug 09 07:23:09 PM PDT 24
Finished Aug 09 07:23:49 PM PDT 24
Peak memory 199892 kb
Host smart-6712254c-65f6-477a-8b9e-254005d5a5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468969171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1468969171
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3487088251
Short name T32
Test name
Test status
Simulation time 128501064192 ps
CPU time 581.8 seconds
Started Aug 09 07:23:11 PM PDT 24
Finished Aug 09 07:32:53 PM PDT 24
Peak memory 224836 kb
Host smart-eb5ce7fb-7e18-4b75-a38d-93bc4dcd4f87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487088251 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3487088251
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3780404490
Short name T331
Test name
Test status
Simulation time 60965617040 ps
CPU time 46.19 seconds
Started Aug 09 07:23:08 PM PDT 24
Finished Aug 09 07:23:54 PM PDT 24
Peak memory 200064 kb
Host smart-442c70bf-24a9-4367-988d-fd5d7a2dbf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780404490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3780404490
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.179327460
Short name T683
Test name
Test status
Simulation time 65908478245 ps
CPU time 201.94 seconds
Started Aug 09 07:23:07 PM PDT 24
Finished Aug 09 07:26:29 PM PDT 24
Peak memory 216508 kb
Host smart-e8d0d0c4-daca-48d4-a54b-0397502a35bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179327460 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.179327460
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2120164437
Short name T307
Test name
Test status
Simulation time 28586056590 ps
CPU time 14.19 seconds
Started Aug 09 07:23:08 PM PDT 24
Finished Aug 09 07:23:22 PM PDT 24
Peak memory 199964 kb
Host smart-403330e8-8da3-4726-b2be-80c2eb5b86c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120164437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2120164437
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3119164377
Short name T1058
Test name
Test status
Simulation time 42195624986 ps
CPU time 1026.18 seconds
Started Aug 09 07:23:07 PM PDT 24
Finished Aug 09 07:40:14 PM PDT 24
Peak memory 224836 kb
Host smart-ce604c05-ed1f-4734-9ebe-111c76c59479
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119164377 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3119164377
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1036105435
Short name T291
Test name
Test status
Simulation time 118135285473 ps
CPU time 87.13 seconds
Started Aug 09 07:23:07 PM PDT 24
Finished Aug 09 07:24:34 PM PDT 24
Peak memory 199904 kb
Host smart-7602ec7a-8158-40ed-9310-c619936424e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036105435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1036105435
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.759574485
Short name T1004
Test name
Test status
Simulation time 51150984930 ps
CPU time 691.03 seconds
Started Aug 09 07:23:07 PM PDT 24
Finished Aug 09 07:34:38 PM PDT 24
Peak memory 216432 kb
Host smart-9a3d77bb-f056-4ce8-bce6-e375b872d0ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759574485 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.759574485
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1691025699
Short name T98
Test name
Test status
Simulation time 22374690 ps
CPU time 0.6 seconds
Started Aug 09 07:19:03 PM PDT 24
Finished Aug 09 07:19:04 PM PDT 24
Peak memory 195364 kb
Host smart-096bde3f-744b-43ff-8009-fc266108ba13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691025699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1691025699
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3295510184
Short name T1097
Test name
Test status
Simulation time 91871971841 ps
CPU time 50.57 seconds
Started Aug 09 07:18:59 PM PDT 24
Finished Aug 09 07:19:49 PM PDT 24
Peak memory 199872 kb
Host smart-e6aa745f-9ce6-4514-b669-9092b4c7c5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295510184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3295510184
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2039549522
Short name T522
Test name
Test status
Simulation time 25325022670 ps
CPU time 45.16 seconds
Started Aug 09 07:18:57 PM PDT 24
Finished Aug 09 07:19:43 PM PDT 24
Peak memory 199852 kb
Host smart-a69e76b3-1519-44ea-966b-f65d5ebc5e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039549522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2039549522
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.40183672
Short name T690
Test name
Test status
Simulation time 15037593217 ps
CPU time 26.01 seconds
Started Aug 09 07:18:58 PM PDT 24
Finished Aug 09 07:19:24 PM PDT 24
Peak memory 199464 kb
Host smart-bbc6ad4f-232e-4f90-a378-7875bf4c7c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40183672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.40183672
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.2558238718
Short name T800
Test name
Test status
Simulation time 172113425686 ps
CPU time 129.7 seconds
Started Aug 09 07:18:58 PM PDT 24
Finished Aug 09 07:21:07 PM PDT 24
Peak memory 199536 kb
Host smart-9367ffb5-245d-4a1e-8d08-e025c782caae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558238718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2558238718
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.709118292
Short name T829
Test name
Test status
Simulation time 81473034509 ps
CPU time 203.61 seconds
Started Aug 09 07:18:58 PM PDT 24
Finished Aug 09 07:22:22 PM PDT 24
Peak memory 199972 kb
Host smart-db35bf18-3bab-4922-b893-43f0531009e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=709118292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.709118292
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2020237240
Short name T1003
Test name
Test status
Simulation time 1976409056 ps
CPU time 2.1 seconds
Started Aug 09 07:19:02 PM PDT 24
Finished Aug 09 07:19:04 PM PDT 24
Peak memory 198752 kb
Host smart-13f9aeed-7df5-419a-bc0d-7860cb7a8810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020237240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2020237240
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.4257985761
Short name T534
Test name
Test status
Simulation time 61826191507 ps
CPU time 47.55 seconds
Started Aug 09 07:18:58 PM PDT 24
Finished Aug 09 07:19:45 PM PDT 24
Peak memory 200116 kb
Host smart-3b70eb6d-55c0-473b-8057-d2b45a4d8e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257985761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.4257985761
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.3113870405
Short name T499
Test name
Test status
Simulation time 2652342623 ps
CPU time 153.39 seconds
Started Aug 09 07:18:57 PM PDT 24
Finished Aug 09 07:21:31 PM PDT 24
Peak memory 199912 kb
Host smart-689858a4-32d9-4859-8a1f-e42f5e3dda43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3113870405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3113870405
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.761762512
Short name T445
Test name
Test status
Simulation time 4510004764 ps
CPU time 4.37 seconds
Started Aug 09 07:18:57 PM PDT 24
Finished Aug 09 07:19:02 PM PDT 24
Peak memory 198824 kb
Host smart-42e33865-81ab-4c60-97b7-bdef6c48fa31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=761762512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.761762512
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.4102097372
Short name T178
Test name
Test status
Simulation time 41619860883 ps
CPU time 17.98 seconds
Started Aug 09 07:19:03 PM PDT 24
Finished Aug 09 07:19:21 PM PDT 24
Peak memory 199920 kb
Host smart-f48fe718-bbea-441d-92f0-4925dbf341b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102097372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.4102097372
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.4187877988
Short name T872
Test name
Test status
Simulation time 30752399481 ps
CPU time 11.17 seconds
Started Aug 09 07:18:58 PM PDT 24
Finished Aug 09 07:19:09 PM PDT 24
Peak memory 195800 kb
Host smart-e8c6d3d8-37a1-41a8-b900-86c50592db96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187877988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.4187877988
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1473256432
Short name T529
Test name
Test status
Simulation time 281239247 ps
CPU time 1.44 seconds
Started Aug 09 07:18:58 PM PDT 24
Finished Aug 09 07:19:00 PM PDT 24
Peak memory 198628 kb
Host smart-108fb052-093b-4544-a9b0-9e54d31411de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473256432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1473256432
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2859961830
Short name T1012
Test name
Test status
Simulation time 117054100144 ps
CPU time 349.66 seconds
Started Aug 09 07:18:58 PM PDT 24
Finished Aug 09 07:24:48 PM PDT 24
Peak memory 199884 kb
Host smart-6f068b9b-3581-4d21-963c-9179537accac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859961830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2859961830
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2047654982
Short name T787
Test name
Test status
Simulation time 319747551 ps
CPU time 1.2 seconds
Started Aug 09 07:18:58 PM PDT 24
Finished Aug 09 07:18:59 PM PDT 24
Peak memory 196732 kb
Host smart-674469d8-d885-460d-980f-c60ced7270f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047654982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2047654982
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1736634250
Short name T765
Test name
Test status
Simulation time 43916794726 ps
CPU time 96.13 seconds
Started Aug 09 07:18:58 PM PDT 24
Finished Aug 09 07:20:35 PM PDT 24
Peak memory 199884 kb
Host smart-55770eee-6d34-40b6-93c6-a528f6f7cb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736634250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1736634250
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3909591442
Short name T874
Test name
Test status
Simulation time 132072932122 ps
CPU time 94.75 seconds
Started Aug 09 07:23:11 PM PDT 24
Finished Aug 09 07:24:46 PM PDT 24
Peak memory 199924 kb
Host smart-a3ca6f9d-358d-4310-a6e2-5933045f9aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909591442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3909591442
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1671913349
Short name T890
Test name
Test status
Simulation time 24393538674 ps
CPU time 11.42 seconds
Started Aug 09 07:23:06 PM PDT 24
Finished Aug 09 07:23:18 PM PDT 24
Peak memory 199976 kb
Host smart-30110b0c-67d3-4ec0-934b-0044a64b0edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671913349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1671913349
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2381782308
Short name T102
Test name
Test status
Simulation time 23074957501 ps
CPU time 115.33 seconds
Started Aug 09 07:23:07 PM PDT 24
Finished Aug 09 07:25:02 PM PDT 24
Peak memory 209996 kb
Host smart-29492191-ac36-4758-b30f-3937093864ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381782308 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2381782308
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.338807971
Short name T204
Test name
Test status
Simulation time 130735526742 ps
CPU time 57.7 seconds
Started Aug 09 07:23:08 PM PDT 24
Finished Aug 09 07:24:06 PM PDT 24
Peak memory 199892 kb
Host smart-7d9a944f-310c-4a29-b1e2-831a702c8b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338807971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.338807971
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3699022757
Short name T644
Test name
Test status
Simulation time 49601445671 ps
CPU time 545.82 seconds
Started Aug 09 07:23:08 PM PDT 24
Finished Aug 09 07:32:14 PM PDT 24
Peak memory 216468 kb
Host smart-5e087c7d-c24f-457c-b8db-66f718dbfa4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699022757 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3699022757
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.738628789
Short name T939
Test name
Test status
Simulation time 32996711012 ps
CPU time 52.26 seconds
Started Aug 09 07:23:07 PM PDT 24
Finished Aug 09 07:23:59 PM PDT 24
Peak memory 199884 kb
Host smart-1810ca73-a0af-454b-8516-d911ae366430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738628789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.738628789
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3088824089
Short name T417
Test name
Test status
Simulation time 72313832004 ps
CPU time 418.74 seconds
Started Aug 09 07:23:10 PM PDT 24
Finished Aug 09 07:30:09 PM PDT 24
Peak memory 226604 kb
Host smart-3727d9d3-b493-4fb4-ac75-c691dab8a5c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088824089 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3088824089
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.742036879
Short name T861
Test name
Test status
Simulation time 22586601625 ps
CPU time 192.6 seconds
Started Aug 09 07:23:16 PM PDT 24
Finished Aug 09 07:26:29 PM PDT 24
Peak memory 215784 kb
Host smart-6cab1df9-a50e-435b-b3de-e4f8d7438668
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742036879 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.742036879
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2445173729
Short name T824
Test name
Test status
Simulation time 8098993249 ps
CPU time 13.39 seconds
Started Aug 09 07:23:16 PM PDT 24
Finished Aug 09 07:23:30 PM PDT 24
Peak memory 199736 kb
Host smart-b5641b39-6c61-4789-aac7-7c5fb852dab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445173729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2445173729
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.776487617
Short name T47
Test name
Test status
Simulation time 32164981487 ps
CPU time 312.75 seconds
Started Aug 09 07:23:16 PM PDT 24
Finished Aug 09 07:28:29 PM PDT 24
Peak memory 216040 kb
Host smart-cc01899d-370d-4499-b7a1-cbb414460696
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776487617 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.776487617
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2756720457
Short name T576
Test name
Test status
Simulation time 36132912946 ps
CPU time 17.67 seconds
Started Aug 09 07:23:14 PM PDT 24
Finished Aug 09 07:23:32 PM PDT 24
Peak memory 199896 kb
Host smart-cba455f7-d384-4a8b-9318-7120eaf6c3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756720457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2756720457
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.323103537
Short name T103
Test name
Test status
Simulation time 437661382541 ps
CPU time 335.14 seconds
Started Aug 09 07:23:17 PM PDT 24
Finished Aug 09 07:28:52 PM PDT 24
Peak memory 224788 kb
Host smart-4dc336ec-45ae-476a-83a6-7204889d9c08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323103537 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.323103537
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2827243588
Short name T613
Test name
Test status
Simulation time 330332750703 ps
CPU time 863.38 seconds
Started Aug 09 07:23:15 PM PDT 24
Finished Aug 09 07:37:39 PM PDT 24
Peak memory 225060 kb
Host smart-78f4f055-5abb-4681-924c-33edc4612854
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827243588 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2827243588
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2654115676
Short name T944
Test name
Test status
Simulation time 244967756566 ps
CPU time 36.64 seconds
Started Aug 09 07:23:17 PM PDT 24
Finished Aug 09 07:23:53 PM PDT 24
Peak memory 199900 kb
Host smart-4b1e5616-fbf6-4d6d-a66d-08f88ba59574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654115676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2654115676
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.4065125970
Short name T868
Test name
Test status
Simulation time 79164220947 ps
CPU time 652.81 seconds
Started Aug 09 07:23:19 PM PDT 24
Finished Aug 09 07:34:12 PM PDT 24
Peak memory 216540 kb
Host smart-03abf55e-1e19-4cf2-9a0b-47a1d0b9e3fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065125970 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.4065125970
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1390195129
Short name T1027
Test name
Test status
Simulation time 15454195 ps
CPU time 0.62 seconds
Started Aug 09 07:18:59 PM PDT 24
Finished Aug 09 07:19:00 PM PDT 24
Peak memory 195352 kb
Host smart-006545db-184f-4b29-b88b-20a6f8e28fc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390195129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1390195129
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3477718718
Short name T125
Test name
Test status
Simulation time 181201429372 ps
CPU time 69.96 seconds
Started Aug 09 07:19:02 PM PDT 24
Finished Aug 09 07:20:12 PM PDT 24
Peak memory 199892 kb
Host smart-c86c4da2-91f9-417f-9d5e-0f860b664842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477718718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3477718718
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.807931781
Short name T142
Test name
Test status
Simulation time 30165270723 ps
CPU time 55.57 seconds
Started Aug 09 07:18:57 PM PDT 24
Finished Aug 09 07:19:53 PM PDT 24
Peak memory 198576 kb
Host smart-2dab2414-9979-42b1-a4b1-c6a408af7e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807931781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.807931781
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2899671571
Short name T1095
Test name
Test status
Simulation time 104531686549 ps
CPU time 166.94 seconds
Started Aug 09 07:19:03 PM PDT 24
Finished Aug 09 07:21:50 PM PDT 24
Peak memory 199948 kb
Host smart-d7c9518f-6293-4474-a542-6dd4686f4cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899671571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2899671571
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3525277733
Short name T20
Test name
Test status
Simulation time 4217534917 ps
CPU time 3.28 seconds
Started Aug 09 07:18:59 PM PDT 24
Finished Aug 09 07:19:02 PM PDT 24
Peak memory 199988 kb
Host smart-e43c0161-1ed0-45f3-932b-c6c13e4ffffc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525277733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3525277733
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_loopback.4233315329
Short name T1075
Test name
Test status
Simulation time 4315009656 ps
CPU time 3.63 seconds
Started Aug 09 07:19:03 PM PDT 24
Finished Aug 09 07:19:07 PM PDT 24
Peak memory 199432 kb
Host smart-68e581f2-638a-4b6e-b1d8-d2d5d4737baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233315329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.4233315329
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.3246016254
Short name T456
Test name
Test status
Simulation time 17241327828 ps
CPU time 375.97 seconds
Started Aug 09 07:18:59 PM PDT 24
Finished Aug 09 07:25:15 PM PDT 24
Peak memory 199888 kb
Host smart-38a9f240-9214-4b5f-8456-e1800297222e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3246016254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3246016254
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3591597960
Short name T976
Test name
Test status
Simulation time 2755591240 ps
CPU time 2.29 seconds
Started Aug 09 07:19:02 PM PDT 24
Finished Aug 09 07:19:05 PM PDT 24
Peak memory 198316 kb
Host smart-23de515b-02ef-48bf-9f31-8a4824f1151d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3591597960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3591597960
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.1187121037
Short name T668
Test name
Test status
Simulation time 85891702334 ps
CPU time 245.42 seconds
Started Aug 09 07:18:59 PM PDT 24
Finished Aug 09 07:23:04 PM PDT 24
Peak memory 199876 kb
Host smart-2744be51-9e3e-4580-99ff-ca5ecebb750d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187121037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1187121037
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1544744537
Short name T624
Test name
Test status
Simulation time 4044793012 ps
CPU time 7.03 seconds
Started Aug 09 07:18:59 PM PDT 24
Finished Aug 09 07:19:06 PM PDT 24
Peak memory 196284 kb
Host smart-af6ff83b-9706-45e2-a0c2-06d450945650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544744537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1544744537
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2412049202
Short name T856
Test name
Test status
Simulation time 6267844032 ps
CPU time 21.08 seconds
Started Aug 09 07:18:58 PM PDT 24
Finished Aug 09 07:19:19 PM PDT 24
Peak memory 199788 kb
Host smart-03e2162f-919a-491f-90e3-090f30445820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412049202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2412049202
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.4078116723
Short name T112
Test name
Test status
Simulation time 52633789977 ps
CPU time 55.49 seconds
Started Aug 09 07:18:58 PM PDT 24
Finished Aug 09 07:19:53 PM PDT 24
Peak memory 199992 kb
Host smart-f1ff5ef4-f9af-43cd-96ca-3d26f2271919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078116723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.4078116723
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1652437578
Short name T184
Test name
Test status
Simulation time 625895642618 ps
CPU time 892.49 seconds
Started Aug 09 07:19:00 PM PDT 24
Finished Aug 09 07:33:52 PM PDT 24
Peak memory 216592 kb
Host smart-1b213b2c-9ea3-4027-8b97-f506dbedb3ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652437578 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1652437578
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.4039570934
Short name T506
Test name
Test status
Simulation time 1336863145 ps
CPU time 4.28 seconds
Started Aug 09 07:18:58 PM PDT 24
Finished Aug 09 07:19:02 PM PDT 24
Peak memory 199848 kb
Host smart-bced49e7-a9c4-4d1e-ae29-6b9fcfc3ef15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039570934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.4039570934
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3121271857
Short name T622
Test name
Test status
Simulation time 42463699560 ps
CPU time 13.81 seconds
Started Aug 09 07:18:59 PM PDT 24
Finished Aug 09 07:19:13 PM PDT 24
Peak memory 199868 kb
Host smart-cb7a5df3-3805-42c3-bd56-4419a29fc0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121271857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3121271857
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2316637595
Short name T203
Test name
Test status
Simulation time 105344242624 ps
CPU time 137.95 seconds
Started Aug 09 07:23:16 PM PDT 24
Finished Aug 09 07:25:34 PM PDT 24
Peak memory 199896 kb
Host smart-745dcc6d-efb3-4c42-bfe1-b12880160ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316637595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2316637595
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2424910140
Short name T909
Test name
Test status
Simulation time 120864686720 ps
CPU time 488.29 seconds
Started Aug 09 07:23:19 PM PDT 24
Finished Aug 09 07:31:27 PM PDT 24
Peak memory 216452 kb
Host smart-9a47aed6-f3c7-49be-85a0-2a9d4c737c9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424910140 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2424910140
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.509593092
Short name T621
Test name
Test status
Simulation time 102077235690 ps
CPU time 368.01 seconds
Started Aug 09 07:23:18 PM PDT 24
Finished Aug 09 07:29:26 PM PDT 24
Peak memory 224736 kb
Host smart-e2316292-a6d6-4fff-ae79-027af2010626
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509593092 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.509593092
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2571549558
Short name T551
Test name
Test status
Simulation time 112507294138 ps
CPU time 176.53 seconds
Started Aug 09 07:23:15 PM PDT 24
Finished Aug 09 07:26:12 PM PDT 24
Peak memory 199924 kb
Host smart-0035d1ce-992d-4742-974c-2ea6fc1733d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571549558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2571549558
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.4234866624
Short name T454
Test name
Test status
Simulation time 231748834319 ps
CPU time 1389.11 seconds
Started Aug 09 07:23:17 PM PDT 24
Finished Aug 09 07:46:27 PM PDT 24
Peak memory 224632 kb
Host smart-f557d7fa-37c9-469d-adeb-c379fd4eb45a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234866624 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.4234866624
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1767869162
Short name T232
Test name
Test status
Simulation time 277072158159 ps
CPU time 28.73 seconds
Started Aug 09 07:23:17 PM PDT 24
Finished Aug 09 07:23:46 PM PDT 24
Peak memory 199912 kb
Host smart-3827a2e5-773e-4b86-9f87-f25094ba0549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767869162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1767869162
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.622736181
Short name T314
Test name
Test status
Simulation time 193889285334 ps
CPU time 792.92 seconds
Started Aug 09 07:23:17 PM PDT 24
Finished Aug 09 07:36:30 PM PDT 24
Peak memory 224796 kb
Host smart-ec71b54d-f339-45b2-bca3-7b772369c6e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622736181 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.622736181
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.702462541
Short name T168
Test name
Test status
Simulation time 36534386928 ps
CPU time 51.98 seconds
Started Aug 09 07:23:20 PM PDT 24
Finished Aug 09 07:24:12 PM PDT 24
Peak memory 199912 kb
Host smart-b5790f01-bed1-496c-94ec-45178338842b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702462541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.702462541
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2998839647
Short name T997
Test name
Test status
Simulation time 169071216410 ps
CPU time 562.86 seconds
Started Aug 09 07:23:18 PM PDT 24
Finished Aug 09 07:32:41 PM PDT 24
Peak memory 216556 kb
Host smart-40ea4970-8ea1-4616-b4cf-a2b10e72af9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998839647 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2998839647
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1069956714
Short name T723
Test name
Test status
Simulation time 17330317758 ps
CPU time 13.64 seconds
Started Aug 09 07:23:28 PM PDT 24
Finished Aug 09 07:23:41 PM PDT 24
Peak memory 199544 kb
Host smart-a5aa8b72-f759-4aea-9427-73ed3d8867da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069956714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1069956714
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.549656915
Short name T161
Test name
Test status
Simulation time 70358670384 ps
CPU time 219.62 seconds
Started Aug 09 07:23:28 PM PDT 24
Finished Aug 09 07:27:07 PM PDT 24
Peak memory 216540 kb
Host smart-57ed884b-0d0b-421e-a304-47ab6302785e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549656915 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.549656915
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.53689515
Short name T563
Test name
Test status
Simulation time 56436816669 ps
CPU time 64.25 seconds
Started Aug 09 07:23:26 PM PDT 24
Finished Aug 09 07:24:30 PM PDT 24
Peak memory 199912 kb
Host smart-b1216d99-c733-4222-8fb4-0f98933e911f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53689515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.53689515
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.4250084909
Short name T1152
Test name
Test status
Simulation time 26039180723 ps
CPU time 422.83 seconds
Started Aug 09 07:23:27 PM PDT 24
Finished Aug 09 07:30:31 PM PDT 24
Peak memory 215732 kb
Host smart-5df863d5-a36a-44f2-91e0-98957e6c74f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250084909 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.4250084909
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2203949970
Short name T126
Test name
Test status
Simulation time 43800453903 ps
CPU time 18.21 seconds
Started Aug 09 07:23:26 PM PDT 24
Finished Aug 09 07:23:44 PM PDT 24
Peak memory 199860 kb
Host smart-3e6e41d5-800a-4726-be3b-2f102cdc56a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203949970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2203949970
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1807449028
Short name T609
Test name
Test status
Simulation time 537992586185 ps
CPU time 1717.06 seconds
Started Aug 09 07:23:25 PM PDT 24
Finished Aug 09 07:52:02 PM PDT 24
Peak memory 221488 kb
Host smart-4a07ced7-661e-41bc-9952-943c2be94535
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807449028 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1807449028
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1391255483
Short name T1030
Test name
Test status
Simulation time 64101945389 ps
CPU time 105.26 seconds
Started Aug 09 07:23:25 PM PDT 24
Finished Aug 09 07:25:11 PM PDT 24
Peak memory 199952 kb
Host smart-e73b3571-76aa-4700-a68c-4c924bb0da64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391255483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1391255483
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2535375359
Short name T730
Test name
Test status
Simulation time 716987790546 ps
CPU time 1369.43 seconds
Started Aug 09 07:23:26 PM PDT 24
Finished Aug 09 07:46:15 PM PDT 24
Peak memory 224616 kb
Host smart-f01e8483-bef9-44b2-80ba-ed519a668578
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535375359 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2535375359
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.223943232
Short name T1016
Test name
Test status
Simulation time 15075453274 ps
CPU time 12.76 seconds
Started Aug 09 07:23:27 PM PDT 24
Finished Aug 09 07:23:40 PM PDT 24
Peak memory 199980 kb
Host smart-05cb9b86-b616-4588-bac0-3393c659affe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223943232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.223943232
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.3405772777
Short name T163
Test name
Test status
Simulation time 233985236982 ps
CPU time 651.66 seconds
Started Aug 09 07:23:28 PM PDT 24
Finished Aug 09 07:34:19 PM PDT 24
Peak memory 224744 kb
Host smart-0809fb54-2da1-4d7c-b913-52baa1257cf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405772777 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.3405772777
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1029158285
Short name T677
Test name
Test status
Simulation time 21820080 ps
CPU time 0.58 seconds
Started Aug 09 07:19:15 PM PDT 24
Finished Aug 09 07:19:16 PM PDT 24
Peak memory 195360 kb
Host smart-de27c503-4b74-4b33-8ccd-ebb477c3ad3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029158285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1029158285
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3351785899
Short name T294
Test name
Test status
Simulation time 64715561603 ps
CPU time 109.64 seconds
Started Aug 09 07:18:56 PM PDT 24
Finished Aug 09 07:20:46 PM PDT 24
Peak memory 199932 kb
Host smart-c56134aa-9c13-48c2-a6c5-4b2942f8834c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351785899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3351785899
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1835302368
Short name T141
Test name
Test status
Simulation time 130233148485 ps
CPU time 258.76 seconds
Started Aug 09 07:18:58 PM PDT 24
Finished Aug 09 07:23:17 PM PDT 24
Peak memory 199740 kb
Host smart-40af1408-53f1-4ff1-9e46-11a273b89f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835302368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1835302368
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1722454583
Short name T1043
Test name
Test status
Simulation time 150673975349 ps
CPU time 117.38 seconds
Started Aug 09 07:19:02 PM PDT 24
Finished Aug 09 07:21:00 PM PDT 24
Peak memory 199900 kb
Host smart-0a9cad15-d6b6-4fdb-ac1c-6674ad6bf20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722454583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1722454583
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.3897433768
Short name T952
Test name
Test status
Simulation time 21462289630 ps
CPU time 8.63 seconds
Started Aug 09 07:19:02 PM PDT 24
Finished Aug 09 07:19:11 PM PDT 24
Peak memory 199676 kb
Host smart-696a8dc3-0697-4f67-89d5-f94105fdb23d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897433768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3897433768
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1529439562
Short name T941
Test name
Test status
Simulation time 70681672867 ps
CPU time 379.46 seconds
Started Aug 09 07:19:09 PM PDT 24
Finished Aug 09 07:25:29 PM PDT 24
Peak memory 199972 kb
Host smart-7dcb73d2-5209-49f0-999b-8e0b63c7a8bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1529439562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1529439562
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2212868340
Short name T686
Test name
Test status
Simulation time 5665871361 ps
CPU time 9.91 seconds
Started Aug 09 07:19:11 PM PDT 24
Finished Aug 09 07:19:21 PM PDT 24
Peak memory 199084 kb
Host smart-a8e5d9ec-81dc-43e6-8bbc-1f0eb981563f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212868340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2212868340
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1395848040
Short name T261
Test name
Test status
Simulation time 146000472459 ps
CPU time 66.74 seconds
Started Aug 09 07:18:59 PM PDT 24
Finished Aug 09 07:20:06 PM PDT 24
Peak memory 198404 kb
Host smart-049cab85-0732-40e1-88ad-1a2d401ce354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395848040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1395848040
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.333728693
Short name T569
Test name
Test status
Simulation time 25618908485 ps
CPU time 728.34 seconds
Started Aug 09 07:19:11 PM PDT 24
Finished Aug 09 07:31:19 PM PDT 24
Peak memory 199872 kb
Host smart-cb4406b3-3401-4f5a-9e98-63eceb008711
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=333728693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.333728693
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1979378462
Short name T815
Test name
Test status
Simulation time 6665124753 ps
CPU time 10.92 seconds
Started Aug 09 07:19:03 PM PDT 24
Finished Aug 09 07:19:14 PM PDT 24
Peak memory 198748 kb
Host smart-2b53f3ae-a095-4a5e-a933-1a990eea9d7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1979378462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1979378462
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2311519529
Short name T1137
Test name
Test status
Simulation time 60038664737 ps
CPU time 88.97 seconds
Started Aug 09 07:19:00 PM PDT 24
Finished Aug 09 07:20:29 PM PDT 24
Peak memory 199940 kb
Host smart-7ddeb111-2abf-406d-8fc2-9809b85ab1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311519529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2311519529
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2447282517
Short name T297
Test name
Test status
Simulation time 4656700257 ps
CPU time 7.32 seconds
Started Aug 09 07:19:03 PM PDT 24
Finished Aug 09 07:19:11 PM PDT 24
Peak memory 196520 kb
Host smart-32cab49a-edab-477a-b492-b3330d2a8b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447282517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2447282517
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.4144789204
Short name T1034
Test name
Test status
Simulation time 434659668 ps
CPU time 1.63 seconds
Started Aug 09 07:18:57 PM PDT 24
Finished Aug 09 07:18:59 PM PDT 24
Peak memory 199872 kb
Host smart-e2c711cf-9c16-4354-a164-6f818f0bf353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144789204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.4144789204
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.1454329832
Short name T1017
Test name
Test status
Simulation time 389998756980 ps
CPU time 980.68 seconds
Started Aug 09 07:19:12 PM PDT 24
Finished Aug 09 07:35:33 PM PDT 24
Peak memory 200184 kb
Host smart-ed7506bb-0fcb-41ab-a18b-291f4d4d75f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454329832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1454329832
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.353010182
Short name T651
Test name
Test status
Simulation time 255598841420 ps
CPU time 649.59 seconds
Started Aug 09 07:19:13 PM PDT 24
Finished Aug 09 07:30:03 PM PDT 24
Peak memory 224744 kb
Host smart-d7f88b0a-3b9a-4a48-9b04-c1130f281808
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353010182 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.353010182
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2523251126
Short name T301
Test name
Test status
Simulation time 1330032435 ps
CPU time 3.17 seconds
Started Aug 09 07:19:10 PM PDT 24
Finished Aug 09 07:19:13 PM PDT 24
Peak memory 198348 kb
Host smart-ccd38edd-5464-4f82-85ca-9a164bf94b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523251126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2523251126
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.603042902
Short name T702
Test name
Test status
Simulation time 66855204671 ps
CPU time 40.25 seconds
Started Aug 09 07:19:02 PM PDT 24
Finished Aug 09 07:19:42 PM PDT 24
Peak memory 199952 kb
Host smart-1045299e-75d8-465d-9679-546b251109a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603042902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.603042902
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.437515357
Short name T150
Test name
Test status
Simulation time 157433087061 ps
CPU time 47.94 seconds
Started Aug 09 07:23:27 PM PDT 24
Finished Aug 09 07:24:15 PM PDT 24
Peak memory 199844 kb
Host smart-79b0a34e-a770-4043-9c3d-0d58f4d4ebad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437515357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.437515357
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1762929717
Short name T138
Test name
Test status
Simulation time 93998406174 ps
CPU time 834.82 seconds
Started Aug 09 07:23:27 PM PDT 24
Finished Aug 09 07:37:22 PM PDT 24
Peak memory 224784 kb
Host smart-9b2479c3-8a3f-4cc3-a4cf-4efa8e75f9dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762929717 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1762929717
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2866400380
Short name T192
Test name
Test status
Simulation time 108166658255 ps
CPU time 44.62 seconds
Started Aug 09 07:23:26 PM PDT 24
Finished Aug 09 07:24:11 PM PDT 24
Peak memory 199892 kb
Host smart-d7df788f-a3e0-4831-b2d7-43d5cee15e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866400380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2866400380
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2436953795
Short name T180
Test name
Test status
Simulation time 756657048343 ps
CPU time 386.82 seconds
Started Aug 09 07:23:26 PM PDT 24
Finished Aug 09 07:29:52 PM PDT 24
Peak memory 227944 kb
Host smart-82467f87-dfe1-4ced-b18a-ad0d644a7107
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436953795 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2436953795
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3995457190
Short name T143
Test name
Test status
Simulation time 17907242668 ps
CPU time 31.42 seconds
Started Aug 09 07:23:27 PM PDT 24
Finished Aug 09 07:23:59 PM PDT 24
Peak memory 199816 kb
Host smart-6450e9d1-070b-4422-a13a-c1510968b1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995457190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3995457190
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3115097199
Short name T53
Test name
Test status
Simulation time 63765279963 ps
CPU time 601.02 seconds
Started Aug 09 07:23:27 PM PDT 24
Finished Aug 09 07:33:29 PM PDT 24
Peak memory 216412 kb
Host smart-ab7ba52d-f725-401b-8e40-d37041b7a861
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115097199 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3115097199
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1712032865
Short name T960
Test name
Test status
Simulation time 179283939613 ps
CPU time 156.09 seconds
Started Aug 09 07:23:27 PM PDT 24
Finished Aug 09 07:26:03 PM PDT 24
Peak memory 199888 kb
Host smart-9e3bd9ee-7842-47c7-a118-6c2d95b9cc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712032865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1712032865
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.2065167454
Short name T642
Test name
Test status
Simulation time 991599956042 ps
CPU time 1338.9 seconds
Started Aug 09 07:23:27 PM PDT 24
Finished Aug 09 07:45:46 PM PDT 24
Peak memory 228316 kb
Host smart-212d5148-afa0-42ce-a9fc-046d8b64db12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065167454 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.2065167454
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3310513026
Short name T48
Test name
Test status
Simulation time 372300211173 ps
CPU time 856.11 seconds
Started Aug 09 07:23:26 PM PDT 24
Finished Aug 09 07:37:42 PM PDT 24
Peak memory 224804 kb
Host smart-61bb250b-1646-48e8-a2ed-f99fc36149e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310513026 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3310513026
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3811440027
Short name T837
Test name
Test status
Simulation time 94053524031 ps
CPU time 18.88 seconds
Started Aug 09 07:23:36 PM PDT 24
Finished Aug 09 07:23:55 PM PDT 24
Peak memory 198812 kb
Host smart-13db8f9b-3ffc-4955-9256-5befab2861fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811440027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3811440027
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.164606735
Short name T595
Test name
Test status
Simulation time 53295893587 ps
CPU time 690.95 seconds
Started Aug 09 07:23:38 PM PDT 24
Finished Aug 09 07:35:09 PM PDT 24
Peak memory 226440 kb
Host smart-53272b40-eeaf-4891-aa93-236e25b621b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164606735 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.164606735
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.630822772
Short name T436
Test name
Test status
Simulation time 195597789270 ps
CPU time 266.63 seconds
Started Aug 09 07:23:39 PM PDT 24
Finished Aug 09 07:28:06 PM PDT 24
Peak memory 199968 kb
Host smart-14350281-4436-47c6-a62d-0d00cb078638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630822772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.630822772
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.804135675
Short name T1147
Test name
Test status
Simulation time 230173309964 ps
CPU time 899.49 seconds
Started Aug 09 07:23:37 PM PDT 24
Finished Aug 09 07:38:37 PM PDT 24
Peak memory 224796 kb
Host smart-24696b67-22ae-40e9-bb20-5965b09be3fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804135675 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.804135675
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.822291451
Short name T645
Test name
Test status
Simulation time 149990633622 ps
CPU time 56.73 seconds
Started Aug 09 07:23:39 PM PDT 24
Finished Aug 09 07:24:36 PM PDT 24
Peak memory 199908 kb
Host smart-ff86a653-a4ae-4e3d-a4fd-0a5df99a76de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822291451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.822291451
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3907726909
Short name T949
Test name
Test status
Simulation time 142336974350 ps
CPU time 105.22 seconds
Started Aug 09 07:23:40 PM PDT 24
Finished Aug 09 07:25:26 PM PDT 24
Peak memory 199892 kb
Host smart-fb4b735f-a350-485c-9da9-585ef1d16bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907726909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3907726909
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.2434648556
Short name T920
Test name
Test status
Simulation time 97109850446 ps
CPU time 2357.87 seconds
Started Aug 09 07:23:39 PM PDT 24
Finished Aug 09 08:02:57 PM PDT 24
Peak memory 224696 kb
Host smart-9bd54735-7402-420a-b5c2-dd98b4c5ab5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434648556 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.2434648556
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1002069673
Short name T214
Test name
Test status
Simulation time 144293571359 ps
CPU time 97.97 seconds
Started Aug 09 07:23:37 PM PDT 24
Finished Aug 09 07:25:15 PM PDT 24
Peak memory 199916 kb
Host smart-c9377769-e12e-429e-a2fe-a905707c0ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002069673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1002069673
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1741025206
Short name T101
Test name
Test status
Simulation time 179637461576 ps
CPU time 588.29 seconds
Started Aug 09 07:23:40 PM PDT 24
Finished Aug 09 07:33:29 PM PDT 24
Peak memory 216624 kb
Host smart-c854fffc-77d6-445e-98fe-13377e365021
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741025206 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1741025206
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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