Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	106612	1			T1	155		T2	94		T3	76
all_values[1]	106612	1			T1	155		T2	94		T3	76
all_values[2]	106612	1			T1	155		T2	94		T3	76
all_values[3]	106612	1			T1	155		T2	94		T3	76
all_values[4]	106612	1			T1	155		T2	94		T3	76
all_values[5]	106612	1			T1	155		T2	94		T3	76
all_values[6]	106612	1			T1	155		T2	94		T3	76
all_values[7]	106612	1			T1	155		T2	94		T3	76
all_values[8]	106612	1			T1	155		T2	94		T3	76

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

480067

1

T1

499

T2

452

T3

449

auto[1]

479441

1

T1

896

T2

394

T3

235

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

867661

1

T1

1239

T2

674

T3

618

auto[1]

91847

1

T1

156

T2

172

T3

66

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	30337	1			T1	43		T2	4		T3	37
all_values[0]	auto[0]	auto[1]	25311	1			T1	31		T2	34		T3	20
all_values[0]	auto[1]	auto[0]	29893	1			T2	9		T3	6		T6	5
all_values[0]	auto[1]	auto[1]	21071	1			T1	81		T2	47		T3	13
all_values[1]	auto[0]	auto[0]	55143	1			T1	29		T3	32		T4	2
all_values[1]	auto[0]	auto[1]	1814	1			T1	11		T10	26		T81	4
all_values[1]	auto[1]	auto[0]	47679	1			T1	115		T2	92		T3	44
all_values[1]	auto[1]	auto[1]	1976	1			T2	2		T39	10		T12	3
all_values[2]	auto[0]	auto[0]	48163	1			T1	29		T2	16		T3	66
all_values[2]	auto[0]	auto[1]	2698	1			T1	1		T3	6		T5	2
all_values[2]	auto[1]	auto[0]	53266	1			T1	118		T2	78		T3	1
all_values[2]	auto[1]	auto[1]	2485	1			T1	7		T3	3		T4	3
all_values[3]	auto[0]	auto[0]	53914	1			T1	145		T2	78		T3	22
all_values[3]	auto[0]	auto[1]	284	1			T10	2		T12	2		T20	9
all_values[3]	auto[1]	auto[0]	52096	1			T1	10		T2	15		T3	54
all_values[3]	auto[1]	auto[1]	318	1			T2	1		T10	1		T12	3
all_values[4]	auto[0]	auto[0]	54211	1			T1	20		T2	78		T3	67
all_values[4]	auto[0]	auto[1]	524	1			T10	1		T12	4		T20	6
all_values[4]	auto[1]	auto[0]	51288	1			T1	135		T2	12		T3	9
all_values[4]	auto[1]	auto[1]	589	1			T2	4		T10	2		T12	1
all_values[5]	auto[0]	auto[0]	51095	1			T1	65		T2	54		T3	64
all_values[5]	auto[0]	auto[1]	167	1			T20	5		T28	6		T29	1
all_values[5]	auto[1]	auto[0]	55170	1			T1	90		T2	40		T3	12
all_values[5]	auto[1]	auto[1]	180	1			T20	3		T18	4		T28	1
all_values[6]	auto[0]	auto[0]	53633	1			T1	40		T2	56		T3	55
all_values[6]	auto[0]	auto[1]	153	1			T12	1		T20	4		T28	1
all_values[6]	auto[1]	auto[0]	52632	1			T1	115		T2	38		T3	21
all_values[6]	auto[1]	auto[1]	194	1			T12	2		T20	1		T18	3
all_values[7]	auto[0]	auto[0]	51897	1			T1	10		T2	49		T3	11
all_values[7]	auto[0]	auto[1]	345	1			T2	5		T12	4		T20	2
all_values[7]	auto[1]	auto[0]	54061	1			T1	145		T2	40		T3	65
all_values[7]	auto[1]	auto[1]	309	1			T14	4		T82	1		T20	6
all_values[8]	auto[0]	auto[0]	33418	1			T1	55		T2	15		T3	49
all_values[8]	auto[0]	auto[1]	16960	1			T1	20		T2	63		T3	20
all_values[8]	auto[1]	auto[0]	39765	1			T1	75		T3	3		T6	103
all_values[8]	auto[1]	auto[1]	16469	1			T1	5		T2	16		T3	4