Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2437	1			T1	2		T3	4		T9	1
auto[BaudRate115200]	2020	1			T1	3		T2	1		T3	1
auto[BaudRate230400]	2167	1			T1	1		T2	2		T3	2
auto[BaudRate128Kbps]	1974	1			T2	1		T3	5		T5	2
auto[BaudRate256Kbps]	2271	1			T1	1		T3	3		T4	2
auto[BaudRate1Mbps]	1879	1			T3	3		T4	2		T5	1
auto[BaudRate1p5Mbps]	1405	1			T3	1		T6	1		T8	3

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1448	1			T9	2		T134	6		T133	5
freqs[25]	1279	1			T4	6		T275	10		T41	10
freqs[48]	812	1			T51	57		T121	4		T294	2
freqs[50]	650	1			T43	46		T49	2		T281	14
freqs[100]	1369	1			T2	4		T17	39		T35	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	223	1			T9	1		T263	5		T32	15
auto[BaudRate9600]	freqs[25]	212	1			T41	2		T308	1		T342	3
auto[BaudRate9600]	freqs[48]	156	1			T51	9		T175	3		T142	14
auto[BaudRate9600]	freqs[50]	85	1			T43	3		T49	1		T281	1
auto[BaudRate9600]	freqs[100]	255	1			T17	7		T20	7		T29	4
auto[BaudRate115200]	freqs[24]	212	1			T134	2		T263	1		T32	8
auto[BaudRate115200]	freqs[25]	166	1			T275	5		T259	1		T342	6
auto[BaudRate115200]	freqs[48]	124	1			T51	6		T121	1		T294	2
auto[BaudRate115200]	freqs[50]	88	1			T43	9		T281	1		T276	1
auto[BaudRate115200]	freqs[100]	153	1			T2	1		T17	2		T20	3
auto[BaudRate230400]	freqs[24]	234	1			T134	1		T133	2		T263	3
auto[BaudRate230400]	freqs[25]	187	1			T4	2		T275	2		T41	5
auto[BaudRate230400]	freqs[48]	109	1			T51	15		T121	1		T175	2
auto[BaudRate230400]	freqs[50]	98	1			T43	7		T49	1		T281	4
auto[BaudRate230400]	freqs[100]	179	1			T2	2		T17	7		T35	1
auto[BaudRate128Kbps]	freqs[24]	209	1			T134	2		T263	2		T32	17
auto[BaudRate128Kbps]	freqs[25]	174	1			T275	1		T41	2		T342	9
auto[BaudRate128Kbps]	freqs[48]	99	1			T121	2		T142	21		T343	1
auto[BaudRate128Kbps]	freqs[50]	96	1			T43	8		T276	2		T330	1
auto[BaudRate128Kbps]	freqs[100]	165	1			T2	1		T17	9		T35	1
auto[BaudRate256Kbps]	freqs[24]	240	1			T134	1		T133	1		T263	2
auto[BaudRate256Kbps]	freqs[25]	218	1			T4	2		T275	1		T41	1
auto[BaudRate256Kbps]	freqs[48]	125	1			T51	6		T175	2		T142	25
auto[BaudRate256Kbps]	freqs[50]	88	1			T43	7		T281	3		T276	1
auto[BaudRate256Kbps]	freqs[100]	220	1			T17	3		T20	2		T29	9
auto[BaudRate1Mbps]	freqs[24]	232	1			T9	1		T133	2		T263	5
auto[BaudRate1Mbps]	freqs[25]	191	1			T4	2		T259	1		T260	5
auto[BaudRate1Mbps]	freqs[48]	99	1			T51	12		T175	1		T142	12
auto[BaudRate1Mbps]	freqs[50]	80	1			T43	5		T330	2		T335	1
auto[BaudRate1Mbps]	freqs[100]	219	1			T17	8		T20	6		T29	8
auto[BaudRate1p5Mbps]	freqs[25]	131	1			T275	1		T259	1		T260	3
auto[BaudRate1p5Mbps]	freqs[48]	100	1			T51	9		T175	1		T142	14
auto[BaudRate1p5Mbps]	freqs[50]	115	1			T43	7		T281	5		T276	1
auto[BaudRate1p5Mbps]	freqs[100]	178	1			T17	3		T20	2		T29	6

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded