Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	8	122	93.85

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	8	122	93.85	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	28589609	1			T1	157		T2	14360		T3	685
all_levels[1]	197757	1			T1	65		T3	29		T4	1
all_levels[2]	2768	1			T1	12		T3	8		T4	1
all_levels[3]	1139	1			T1	7		T3	3		T5	1
all_levels[4]	716	1			T1	4		T3	2		T11	3
all_levels[5]	576	1			T1	2		T3	2		T11	2
all_levels[6]	420	1			T1	3		T3	1		T5	1
all_levels[7]	367	1			T5	2		T8	2		T33	2
all_levels[8]	296	1			T1	1		T5	1		T11	1
all_levels[9]	242	1			T1	1		T3	1		T11	1
all_levels[10]	223	1			T33	2		T12	1		T14	2
all_levels[11]	203	1			T1	1		T5	3		T14	1
all_levels[12]	189	1			T8	1		T39	1		T14	2
all_levels[13]	133	1			T11	1		T130	1		T131	1
all_levels[14]	135	1			T5	2		T11	1		T14	1
all_levels[15]	133	1			T1	3		T11	1		T37	1
all_levels[16]	102	1			T132	1		T133	1		T130	1
all_levels[17]	113	1			T1	1		T14	1		T38	1
all_levels[18]	94	1			T4	1		T8	1		T12	2
all_levels[19]	94	1			T1	2		T37	1		T29	1
all_levels[20]	90	1			T1	1		T14	1		T134	1
all_levels[21]	68	1			T1	3		T12	1		T34	2
all_levels[22]	60	1			T12	2		T41	3		T43	3
all_levels[23]	57	1			T37	1		T132	1		T43	2
all_levels[24]	62	1			T8	1		T43	1		T18	1
all_levels[25]	53	1			T1	1		T43	1		T30	1
all_levels[26]	48	1			T37	1		T131	2		T135	2
all_levels[27]	41	1			T37	1		T43	1		T131	1
all_levels[28]	51	1			T38	1		T40	1		T43	1
all_levels[29]	47	1			T1	1		T12	2		T20	1
all_levels[30]	47	1			T132	2		T136	1		T48	1
all_levels[31]	36	1			T20	1		T131	1		T136	1
all_levels[32]	46	1			T1	1		T134	1		T32	1
all_levels[33]	33	1			T28	3		T32	1		T137	1
all_levels[34]	29	1			T20	1		T138	1		T57	1
all_levels[35]	22	1			T20	2		T29	1		T139	2
all_levels[36]	30	1			T53	2		T140	1		T54	1
all_levels[37]	23	1			T32	1		T141	1		T142	1
all_levels[38]	21	1			T136	1		T45	1		T119	1
all_levels[39]	10	1			T39	1		T34	1		T143	3
all_levels[40]	29	1			T39	1		T144	1		T120	1
all_levels[41]	17	1			T30	1		T141	2		T145	1
all_levels[42]	11	1			T12	1		T119	1		T146	1
all_levels[43]	16	1			T142	1		T147	1		T148	1
all_levels[44]	14	1			T39	1		T28	1		T29	1
all_levels[45]	15	1			T149	1		T150	1		T151	1
all_levels[46]	16	1			T41	3		T130	1		T148	1
all_levels[47]	22	1			T152	3		T153	1		T154	2
all_levels[48]	18	1			T28	1		T32	1		T155	1
all_levels[49]	11	1			T156	1		T145	1		T157	1
all_levels[50]	9	1			T136	2		T144	1		T158	1
all_levels[51]	15	1			T39	1		T149	1		T159	1
all_levels[52]	6	1			T28	1		T160	1		T161	1
all_levels[53]	12	1			T151	1		T148	1		T162	1
all_levels[54]	6	1			T150	1		T145	1		T163	1
all_levels[55]	14	1			T130	2		T45	1		T144	1
all_levels[56]	7	1			T164	1		T165	1		T166	1
all_levels[57]	11	1			T161	1		T57	1		T167	1
all_levels[58]	10	1			T168	1		T169	1		T170	3
all_levels[59]	1	1			T171	1		-	-		-	-
all_levels[60]	5	1			T172	1		T173	1		T174	1
all_levels[61]	8	1			T53	2		T175	1		T176	1
all_levels[62]	10	1			T144	1		T156	1		T177	1
all_levels[63]	4	1			T140	1		T178	1		T62	2
all_levels[64]	130	1			T8	1		T12	1		T134	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28791652

1

T1

266

T2

14319

T3

731

auto[1]

4948

1

T2

41

T5

6

T8

8

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	8	122	93.85	8

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[35]]	[auto[1]]	0	1	1
[all_levels[44]]	[auto[1]]	0	1	1
[all_levels[52] , all_levels[53]]	[auto[1]]	--	--	2
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[59] , all_levels[60] , all_levels[61]]	[auto[1]]	--	--	3

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	28585094	1			T1	157		T2	14319		T3	685
all_levels[0]	auto[1]	4515	1			T2	41		T5	4		T8	8
all_levels[1]	auto[0]	197702	1			T1	65		T3	29		T4	1
all_levels[1]	auto[1]	55	1			T37	1		T42	1		T131	2
all_levels[2]	auto[0]	2742	1			T1	12		T3	8		T4	1
all_levels[2]	auto[1]	26	1			T150	1		T179	1		T180	1
all_levels[3]	auto[0]	1120	1			T1	7		T3	3		T5	1
all_levels[3]	auto[1]	19	1			T181	1		T136	1		T182	1
all_levels[4]	auto[0]	696	1			T1	4		T3	2		T11	3
all_levels[4]	auto[1]	20	1			T183	1		T184	1		T185	2
all_levels[5]	auto[0]	560	1			T1	2		T3	2		T11	2
all_levels[5]	auto[1]	16	1			T133	1		T136	1		T186	1
all_levels[6]	auto[0]	409	1			T1	3		T3	1		T5	1
all_levels[6]	auto[1]	11	1			T48	1		T143	1		T187	1
all_levels[7]	auto[0]	347	1			T5	2		T8	2		T33	1
all_levels[7]	auto[1]	20	1			T33	1		T136	1		T112	4
all_levels[8]	auto[0]	288	1			T1	1		T5	1		T11	1
all_levels[8]	auto[1]	8	1			T188	2		T179	1		T189	1
all_levels[9]	auto[0]	232	1			T1	1		T3	1		T11	1
all_levels[9]	auto[1]	10	1			T37	1		T190	1		T191	1
all_levels[10]	auto[0]	206	1			T33	1		T12	1		T14	2
all_levels[10]	auto[1]	17	1			T33	1		T192	2		T193	1
all_levels[11]	auto[0]	189	1			T1	1		T5	2		T14	1
all_levels[11]	auto[1]	14	1			T5	1		T175	1		T194	2
all_levels[12]	auto[0]	184	1			T8	1		T39	1		T14	2
all_levels[12]	auto[1]	5	1			T106	1		T195	1		T196	2
all_levels[13]	auto[0]	127	1			T11	1		T130	1		T131	1
all_levels[13]	auto[1]	6	1			T197	1		T140	1		T198	1
all_levels[14]	auto[0]	125	1			T5	1		T11	1		T14	1
all_levels[14]	auto[1]	10	1			T5	1		T190	1		T183	1
all_levels[15]	auto[0]	117	1			T1	3		T11	1		T37	1
all_levels[15]	auto[1]	16	1			T197	1		T199	1		T200	1
all_levels[16]	auto[0]	93	1			T132	1		T133	1		T130	1
all_levels[16]	auto[1]	9	1			T32	1		T201	2		T202	1
all_levels[17]	auto[0]	108	1			T1	1		T14	1		T38	1
all_levels[17]	auto[1]	5	1			T192	1		T203	1		T204	1
all_levels[18]	auto[0]	89	1			T4	1		T8	1		T12	2
all_levels[18]	auto[1]	5	1			T205	2		T113	1		T206	2
all_levels[19]	auto[0]	88	1			T1	2		T37	1		T29	1
all_levels[19]	auto[1]	6	1			T207	1		T208	1		T209	1
all_levels[20]	auto[0]	76	1			T1	1		T14	1		T134	1
all_levels[20]	auto[1]	14	1			T210	1		T99	1		T211	4
all_levels[21]	auto[0]	65	1			T1	3		T12	1		T34	2
all_levels[21]	auto[1]	3	1			T212	1		T213	1		T214	1
all_levels[22]	auto[0]	52	1			T12	2		T41	1		T43	3
all_levels[22]	auto[1]	8	1			T41	2		T99	2		T215	2
all_levels[23]	auto[0]	48	1			T37	1		T132	1		T43	2
all_levels[23]	auto[1]	9	1			T160	3		T170	1		T216	2
all_levels[24]	auto[0]	54	1			T8	1		T43	1		T18	1
all_levels[24]	auto[1]	8	1			T217	1		T218	3		T219	1
all_levels[25]	auto[0]	46	1			T1	1		T43	1		T30	1
all_levels[25]	auto[1]	7	1			T220	2		T221	1		T208	1
all_levels[26]	auto[0]	46	1			T37	1		T131	2		T135	2
all_levels[26]	auto[1]	2	1			T185	1		T222	1		-	-
all_levels[27]	auto[0]	35	1			T37	1		T43	1		T131	1
all_levels[27]	auto[1]	6	1			T223	1		T224	1		T225	1
all_levels[28]	auto[0]	44	1			T38	1		T40	1		T43	1
all_levels[28]	auto[1]	7	1			T226	1		T227	2		T228	3
all_levels[29]	auto[0]	42	1			T1	1		T12	1		T20	1
all_levels[29]	auto[1]	5	1			T12	1		T229	1		T219	1
all_levels[30]	auto[0]	45	1			T132	2		T136	1		T48	1
all_levels[30]	auto[1]	2	1			T230	1		T231	1		-	-
all_levels[31]	auto[0]	35	1			T20	1		T131	1		T136	1
all_levels[31]	auto[1]	1	1			T232	1		-	-		-	-
all_levels[32]	auto[0]	38	1			T1	1		T134	1		T32	1
all_levels[32]	auto[1]	8	1			T233	1		T234	3		T235	1
all_levels[33]	auto[0]	30	1			T28	2		T32	1		T137	1
all_levels[33]	auto[1]	3	1			T28	1		T236	1		T237	1
all_levels[34]	auto[0]	28	1			T20	1		T138	1		T57	1
all_levels[34]	auto[1]	1	1			T238	1		-	-		-	-
all_levels[35]	auto[0]	22	1			T20	2		T29	1		T139	2
all_levels[36]	auto[0]	27	1			T53	2		T140	1		T54	1
all_levels[36]	auto[1]	3	1			T239	1		T240	1		T241	1
all_levels[37]	auto[0]	22	1			T32	1		T141	1		T142	1
all_levels[37]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[38]	auto[0]	20	1			T136	1		T45	1		T119	1
all_levels[38]	auto[1]	1	1			T239	1		-	-		-	-
all_levels[39]	auto[0]	9	1			T39	1		T34	1		T143	2
all_levels[39]	auto[1]	1	1			T143	1		-	-		-	-
all_levels[40]	auto[0]	25	1			T39	1		T144	1		T120	1
all_levels[40]	auto[1]	4	1			T200	3		T243	1		-	-
all_levels[41]	auto[0]	16	1			T30	1		T141	2		T145	1
all_levels[41]	auto[1]	1	1			T244	1		-	-		-	-
all_levels[42]	auto[0]	10	1			T12	1		T119	1		T146	1
all_levels[42]	auto[1]	1	1			T245	1		-	-		-	-
all_levels[43]	auto[0]	15	1			T142	1		T147	1		T148	1
all_levels[43]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[44]	auto[0]	14	1			T39	1		T28	1		T29	1
all_levels[45]	auto[0]	14	1			T149	1		T150	1		T151	1
all_levels[45]	auto[1]	1	1			T246	1		-	-		-	-
all_levels[46]	auto[0]	13	1			T41	1		T130	1		T148	1
all_levels[46]	auto[1]	3	1			T41	2		T211	1		-	-
all_levels[47]	auto[0]	18	1			T152	1		T153	1		T154	1
all_levels[47]	auto[1]	4	1			T152	2		T154	1		T247	1
all_levels[48]	auto[0]	15	1			T28	1		T32	1		T155	1
all_levels[48]	auto[1]	3	1			T246	1		T248	2		-	-
all_levels[49]	auto[0]	10	1			T156	1		T145	1		T157	1
all_levels[49]	auto[1]	1	1			T196	1		-	-		-	-
all_levels[50]	auto[0]	8	1			T136	1		T144	1		T158	1
all_levels[50]	auto[1]	1	1			T136	1		-	-		-	-
all_levels[51]	auto[0]	13	1			T39	1		T149	1		T159	1
all_levels[51]	auto[1]	2	1			T239	1		T249	1		-	-
all_levels[52]	auto[0]	6	1			T28	1		T160	1		T161	1
all_levels[53]	auto[0]	12	1			T151	1		T148	1		T162	1
all_levels[54]	auto[0]	5	1			T150	1		T145	1		T163	1
all_levels[54]	auto[1]	1	1			T250	1		-	-		-	-
all_levels[55]	auto[0]	12	1			T130	1		T45	1		T144	1
all_levels[55]	auto[1]	2	1			T130	1		T251	1		-	-
all_levels[56]	auto[0]	7	1			T164	1		T165	1		T166	1
all_levels[57]	auto[0]	8	1			T161	1		T57	1		T167	1
all_levels[57]	auto[1]	3	1			T234	1		T252	2		-	-
all_levels[58]	auto[0]	7	1			T168	1		T169	1		T170	1
all_levels[58]	auto[1]	3	1			T170	2		T247	1		-	-
all_levels[59]	auto[0]	1	1			T171	1		-	-		-	-
all_levels[60]	auto[0]	5	1			T172	1		T173	1		T174	1
all_levels[61]	auto[0]	8	1			T53	2		T175	1		T176	1
all_levels[62]	auto[0]	8	1			T144	1		T156	1		T177	1
all_levels[62]	auto[1]	2	1			T253	2		-	-		-	-
all_levels[63]	auto[0]	3	1			T140	1		T178	1		T62	1
all_levels[63]	auto[1]	1	1			T62	1		-	-		-	-
all_levels[64]	auto[0]	99	1			T8	1		T12	1		T134	1
all_levels[64]	auto[1]	31	1			T254	2		T175	3		T168	1