Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	106612	1			T1	155		T2	94		T3	76
all_pins[1]	106612	1			T1	155		T2	94		T3	76
all_pins[2]	106612	1			T1	155		T2	94		T3	76
all_pins[3]	106612	1			T1	155		T2	94		T3	76
all_pins[4]	106612	1			T1	155		T2	94		T3	76
all_pins[5]	106612	1			T1	155		T2	94		T3	76
all_pins[6]	106612	1			T1	155		T2	94		T3	76
all_pins[7]	106612	1			T1	155		T2	94		T3	76
all_pins[8]	106612	1			T1	155		T2	94		T3	76

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	914807	1			T1	1291		T2	772		T3	664
values[0x1]	44701	1			T1	104		T2	74		T3	20
transitions[0x0=>0x1]	36316	1			T1	104		T2	71		T3	17
transitions[0x1=>0x0]	36093	1			T1	104		T2	71		T3	17

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	85443	1			T1	74		T2	44		T3	63
all_pins[0]	values[0x1]	21169	1			T1	81		T2	50		T3	13
all_pins[0]	transitions[0x0=>0x1]	20530	1			T1	81		T2	48		T3	13
all_pins[0]	transitions[0x1=>0x0]	1339	1			T39	10		T12	1		T14	3
all_pins[1]	values[0x0]	104634	1			T1	155		T2	92		T3	76
all_pins[1]	values[0x1]	1978	1			T2	2		T39	10		T12	3
all_pins[1]	transitions[0x0=>0x1]	1842	1			T2	2		T39	8		T12	1
all_pins[1]	transitions[0x1=>0x0]	2419	1			T1	7		T2	1		T3	3
all_pins[2]	values[0x0]	104057	1			T1	148		T2	93		T3	73
all_pins[2]	values[0x1]	2555	1			T1	7		T2	1		T3	3
all_pins[2]	transitions[0x0=>0x1]	2475	1			T1	7		T2	1		T3	3
all_pins[2]	transitions[0x1=>0x0]	238	1			T2	1		T10	1		T12	1
all_pins[3]	values[0x0]	106294	1			T1	155		T2	93		T3	76
all_pins[3]	values[0x1]	318	1			T2	1		T10	1		T12	3
all_pins[3]	transitions[0x0=>0x1]	281	1			T2	1		T10	1		T12	3
all_pins[3]	transitions[0x1=>0x0]	552	1			T2	4		T10	2		T12	1
all_pins[4]	values[0x0]	106023	1			T1	155		T2	90		T3	76
all_pins[4]	values[0x1]	589	1			T2	4		T10	2		T12	1
all_pins[4]	transitions[0x0=>0x1]	501	1			T2	4		T10	2		T12	1
all_pins[4]	transitions[0x1=>0x0]	157	1			T20	3		T18	4		T29	2
all_pins[5]	values[0x0]	106367	1			T1	155		T2	94		T3	76
all_pins[5]	values[0x1]	245	1			T13	2		T20	3		T15	3
all_pins[5]	transitions[0x0=>0x1]	184	1			T13	2		T20	3		T15	3
all_pins[5]	transitions[0x1=>0x0]	925	1			T1	11		T8	4		T12	4
all_pins[6]	values[0x0]	105626	1			T1	144		T2	94		T3	76
all_pins[6]	values[0x1]	986	1			T1	11		T8	4		T12	4
all_pins[6]	transitions[0x0=>0x1]	930	1			T1	11		T8	4		T12	4
all_pins[6]	transitions[0x1=>0x0]	253	1			T14	4		T82	1		T20	6
all_pins[7]	values[0x0]	106303	1			T1	155		T2	94		T3	76
all_pins[7]	values[0x1]	309	1			T14	4		T82	1		T20	6
all_pins[7]	transitions[0x0=>0x1]	207	1			T14	4		T82	1		T20	2
all_pins[7]	transitions[0x1=>0x0]	16450	1			T1	5		T2	16		T3	4
all_pins[8]	values[0x0]	90060	1			T1	150		T2	78		T3	72
all_pins[8]	values[0x1]	16552	1			T1	5		T2	16		T3	4
all_pins[8]	transitions[0x0=>0x1]	9366	1			T1	5		T2	15		T3	1
all_pins[8]	transitions[0x1=>0x0]	13760	1			T1	81		T2	49		T3	10